Heterojunction solar cell structure and preparation method thereof

Abstract

The invention relates to the technical field of crystalline silicon solar cells, particularly provides a heterojunction solar cell structure and a preparation method, and aims to solve the problems that in the preparation process of a heterojunction solar cell in the prior art, non-uniform winding plating exists on the side face of a silicon substrate, the cell performance is affected, even short circuit occurs, and the side face is exposed, and the cell reliability is reduced. Therefore, the heterojunction solar cell structure comprises a silicon substrate, an intrinsic amorphous silicon layer, a first doping layer, a first conducting layer, a second doping layer and a second conducting layer, and the silicon substrate is provided with a first main surface, a second main surface and a side surface; an intrinsic amorphous silicon layer, a first doped layer and a first conductive layer are stacked on the basis of the first main surface, and an intrinsic amorphous silicon layer, a second doped layer and a second conductive layer are stacked on the basis of the second main surface; an intrinsic amorphous silicon layer is at least arranged based on the side surface; the first doped layer and the second doped layer are not in contact, and the first conductive layer and the second conductive layer are not in contact. Therefore, the battery is more stable and reliable.

Description

Technical Field

[0001] The present invention relates to the technical field of crystalline silicon solar cells, and specifically provides a heterojunction solar cell structure and a preparation method thereof. Background Art

[0002] Heterojunction solar cells have the advantages of simple structure, low process temperature, good passivation effect, high open circuit voltage, good temperature characteristics, and double-sided power generation. They are one of the hot spots for high conversion efficiency silicon-based solar cells. Their performance is greatly affected by the passivation effect and TCO conductivity. The preparation process of heterojunction solar cells is mainly divided into four steps: cleaning and texturing → deposition of silicon film on the front and back → deposition of transparent conductive oxide film (TCO) on the front and back → preparation of metal electrodes on the front and back. In the process of preparing batteries, more attention is usually paid to the performance on the front and back sides of the battery, and less attention is paid to the side of the battery. When coating on the front and back sides, there is often a certain amount of wrapping on the side of the battery, but the wrapping is extremely uneven. Not only can the photogenerated carriers not be extracted, which limits the efficiency of the battery, but the exposure of amorphous silicon will have a significant impact on the long-term reliability of the solar cell.

[0003] Accordingly, the art needs a new battery structure and preparation method to solve the above problems. Summary of the invention

[0004] The present invention aims to solve the above technical problems, that is, to solve the problem in the prior art that in the process of preparing heterojunction solar cells, there is uneven plating on the side of the silicon substrate, which affects the battery performance or even short circuits, and there is exposure on the side, which reduces the reliability of the battery.

[0005] In a first aspect, the present invention provides a heterojunction solar cell structure, the cell structure comprising:

[0006] A silicon substrate, wherein the silicon substrate is provided with a first main surface, a second main surface opposite to the first main surface, and a side surface;

[0007] The intrinsic amorphous silicon layer comprises a first intrinsic amorphous silicon portion located on the first main surface, a second intrinsic amorphous silicon portion located on the second main surface, and a third intrinsic amorphous silicon portion located on the side surface;

[0008] A first doped layer, comprising at least a first doped portion located on the first intrinsic amorphous silicon portion;

[0009] A first conductive layer, comprising at least a first conductive portion located on the first doped portion;

[0010] a second doped layer, comprising at least a second doped portion located on the second intrinsic amorphous silicon portion;

[0011] a second conductive layer, comprising at least a second conductive portion located on the second doped portion,

[0012] There is a gap between the first doped layer and the second doped layer and between the first conductive layer and the second conductive layer, so that the intrinsic amorphous silicon layer is exposed.

[0013] In a specific embodiment having the above heterojunction solar cell structure, the first doped layer further includes a third doped portion located on the third intrinsic amorphous silicon portion, and the first conductive layer further includes a third conductive portion located on the third doped portion;

[0014] The second doped layer includes only the second doped portion and the second conductive layer includes only the second conductive portion,

[0015] The gap exists between the third doped portion and the second doped portion and between the third conductive portion and the second conductive portion.

[0016] In a specific embodiment of the heterojunction solar cell structure, the cell structure includes:

[0017] The first passivation layer is located on a surface of the second conductive portion away from the silicon substrate and extends onto the exposed intrinsic amorphous silicon layer.

[0018] In a specific embodiment of the heterojunction solar cell structure, the second doped layer further includes a fourth doped portion located on the third intrinsic amorphous silicon portion, and the second conductive layer further includes a fourth conductive portion located on the fourth doped portion;

[0019] The first doped layer includes only the first doped portion and the first conductive layer includes only the first conductive portion,

[0020] The gap exists between the fourth doped portion and the first doped portion and between the fourth conductive portion and the first conductive portion.

[0021] In a specific embodiment of the heterojunction solar cell structure, the cell structure includes:

[0022] The second passivation layer is located on a surface of the first conductive portion away from the silicon substrate and extends onto the exposed intrinsic amorphous silicon layer.

[0023] In a specific embodiment of the heterojunction solar cell structure, the first doped layer has an N-type conductivity; and the second doped layer has a P-type conductivity.

[0024] In a specific embodiment of the heterojunction solar cell structure, the materials of the first doping layer and the second doping layer are respectively at least one of amorphous silicon, microcrystalline silicon and nanocrystalline silicon.

[0025] In a specific embodiment having the above heterojunction solar cell structure, the first conductive layer and the second conductive layer are configured as TCO layers.

[0026] In a specific embodiment of the heterojunction solar cell structure, the TCO layer includes at least one of an ITO layer, an IWO layer, an ICO layer, an IMO layer, a GZO layer, and a VTTO layer.

[0027] In a specific embodiment of the heterojunction solar cell structure, the cell structure further includes:

[0028] A first gate line electrode and a second gate line electrode, wherein the first gate line electrode and the second gate line electrode are connected to the first conductive part and the second conductive part respectively.

[0029] In a specific embodiment of the heterojunction solar cell structure, the first grid line electrode and the second grid line electrode are configured as one of a silver electrode, a silver-clad copper electrode or a silver alloy paste electrode.

[0030] The present invention also provides a method for preparing a heterojunction solar cell structure, the method comprising the following steps:

[0031] forming an intrinsic amorphous silicon layer, comprising a first intrinsic amorphous silicon portion located on a first main surface of a silicon substrate, a second intrinsic amorphous silicon portion located on a second main surface of the silicon substrate opposite to the first main surface, and a third intrinsic amorphous silicon portion located on a side surface of the silicon substrate;

[0032] forming a first doped layer, the first doped layer at least comprising a first doped portion located on the first intrinsic amorphous silicon portion;

[0033] forming a first conductive layer, wherein the first conductive layer at least includes a first conductive portion located on the first doped portion;

[0034] forming a second doped layer, the second doped layer at least comprising a second doped portion located on the second intrinsic amorphous silicon portion;

[0035] forming a second conductive layer, wherein the second conductive layer at least includes a second conductive portion located on the second doped portion;

[0036] A gap is formed between the first doped layer and the second doped layer and between the first conductive layer and the second conductive layer, thereby exposing the intrinsic amorphous silicon layer.

[0037] In the case of adopting the above technical scheme, the heterojunction solar cell structure disclosed in the present invention optimizes the cell structure and designs the side film deposition of the silicon substrate so that at least an intrinsic amorphous silicon layer is deposited on the side of the silicon substrate, thereby avoiding exposure of the side of the cell and improving the long-term reliability of the cell. At the same time, it can also have a passivation effect and avoid the formation of a large number of composite centers generated by plating, thereby increasing the open circuit voltage of the cell. The cell is designed with a non-contact disconnection position to avoid short circuits and improve the safety and stability of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings, in which:

[0039] Figure 1 is a cross-sectional schematic diagram of one embodiment of a heterojunction solar cell structure in the present invention, wherein only an intrinsic amorphous silicon layer is deposited on the side surface;

[0040] Figure 2 is a cross-sectional schematic diagram of one embodiment of a heterojunction solar cell structure in the present invention, wherein a side-deposited intrinsic amorphous silicon layer, a first doping layer and a first conductive layer are shown;

[0041] Figure 3 is a cross-sectional schematic diagram of one embodiment of a heterojunction solar cell structure in the present invention, wherein a side-deposited intrinsic amorphous silicon layer, a second doping layer and a second conductive layer are shown;

[0042] Figure 4 It is a flow chart of the main steps of the method for preparing a heterojunction solar cell structure in the present invention;

[0043] Figure 5 The present invention is a specific flow chart of one embodiment of the method for preparing a heterojunction solar cell structure.

[0044] Among them, 1. silicon substrate, 2. first main surface, 3. second main surface, 4. side surface, 5. intrinsic amorphous silicon layer, 5-1. first intrinsic amorphous silicon portion, 5-2. second intrinsic amorphous silicon portion, 5-3. third intrinsic amorphous silicon portion, 6. first doped layer, 6-1. first doped portion, 6-2. third doped portion, 7. first conductive layer, 7-1. first conductive portion, 7-2. third conductive portion, 8. second doped layer, 8-1. second doped portion, 8-2. fourth doped portion, 9. second conductive layer, 9-1. second conductive portion, 9-2. fourth conductive portion, 10-1. first passivation layer, 10-2. second passivation layer, 11. first gate line electrode, 12. second gate line electrode. DETAILED DESCRIPTION

[0045] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0046] In the description of the present invention, the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", etc. may explicitly or implicitly include at least one of the features. In addition, in the present invention, unless otherwise clearly specified and defined, the terms "connected", "connected", etc. should be understood in a broad sense. For example, it can be directly connected or indirectly connected through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0047] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0048] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0049] In the process of preparing heterojunction solar cells, more attention is usually paid to the performance on the front and back sides of the cell, and less attention is paid to the sides of the cell. When coating on the front and back sides, there is often a certain amount of wrapping on the sides of the cell, but the wrapping is extremely uneven, which not only limits the efficiency of the cell because the photogenerated carriers cannot be extracted, but also the exposure of amorphous silicon will have a significant impact on the long-term reliability of the solar cell.

[0050] Based on the above problems, the study found that the exposed crystalline silicon / amorphous silicon on the side of the battery will form a large number of recombination centers, causing carrier recombination, which not only affects the open circuit voltage of the battery, but also challenges the long-term reliability of the battery. Due to a certain degree of wrapping plating in the film layer during preparation, the conductive layer of the battery may be connected to cause a short circuit problem. Therefore, structural optimization of the side film layer of the battery can improve the performance of the battery.

[0051] Specifically, see Figures 1 to 3 The present invention proposes a heterojunction solar cell structure, which includes a silicon substrate 1, an intrinsic amorphous silicon layer 5, a first doped layer 6, a first conductive layer 7, a second doped layer 8 and a second conductive layer 9. It can be seen that the silicon substrate 1 is provided with a first main surface 2, a second main surface 3 and a side surface 4 connecting the first main surface 2 and the second main surface 3, and the first main surface 2 and the second main surface 3 are arranged opposite to each other.

[0052] In a specific implementation process, the silicon substrate 1 can be an N-type crystalline silicon substrate, and its first main surface 2 serves as a light-facing surface to absorb light. The second main surface 3 serves as a backlight surface. An intrinsic amorphous silicon layer 5, a first doped layer 6, and a first conductive layer 7 are sequentially deposited on the first main surface 2, and an intrinsic amorphous silicon layer 5, a second doped layer 8, and a second conductive layer 9 are sequentially deposited on the second main surface 3.

[0053] Among them, the first doping layer 6 is set as an N-type doping layer; the second doping layer 8 is set as a P-type doping layer; the N-type doping layer and the P-type doping layer include at least one of an amorphous silicon layer, a microcrystalline silicon layer or a nanocrystalline silicon layer. It should be noted that the N-type doping layer and the P-type doping layer can be one of the above examples or a combination of multiple ones, and this is not restrictive. The N-type doping layer and the P-type doping layer can also adopt other crystal structures that can achieve similar functions.

[0054] In addition, the first conductive layer 7 and the second conductive layer 9 can be configured as TCO layers (transparent conductive oxides), and the TCO layers include at least one of ITO layers (aluminum-doped zinc oxide), IWO layers (tungsten-doped indium oxide), ICO layers (cerium-doped indium oxide), IMO layers (molybdenum-doped indium oxide), GZO layers (gallium-doped zinc oxide), and VTTO layers (mixed layers deposited by VTTO target materials). It should be noted that the first conductive layer 7 and the second conductive layer 9 can be made of different conductive materials according to the performance requirements of the battery.

[0055] Furthermore, a non-contact gap is provided between the first doped layer 6 and the second doped layer 8, and between the first conductive layer 7 and the second conductive layer 9, that is, they are separated to form a circuit break. According to the distribution of film layer deposition, the non-contact circuit break position can be configured at the edge of the first main surface 2 or the edge of the second main surface 3 according to the situation. By setting the non-contact circuit break position, short circuit of the battery can be avoided and the battery safety can be improved.

[0056] See also Figure 1 , at least one layer of intrinsic amorphous silicon layer 5 is provided on the side 4 of the silicon substrate 1, then the intrinsic amorphous silicon layer 5 can completely cover the silicon substrate 1, passivate the N-type silicon substrate, prevent the epitaxial growth of single crystal silicon, reduce the recombination of carriers, and improve the open circuit voltage of the battery. It should be noted here that at least one layer of intrinsic amorphous silicon layer 5 is provided on the side 4 of the silicon substrate 1, which means that a film layer of the same type as the first main surface 2 or the second main surface 3 can also be provided on the side 4 of the silicon substrate 1. Therefore, it is a possible embodiment to provide a layer of intrinsic amorphous silicon layer 5 on the side 4 of the silicon substrate 1. At the same time, the first intrinsic amorphous silicon portion 5-1 is deposited on the first main surface 2 of the silicon substrate 1, the second intrinsic amorphous silicon portion 5-2 is deposited on the second main surface 3 of the silicon substrate 1, and the third intrinsic amorphous silicon portion 5-3 is deposited on the side 4.

[0057] See also Figure 2 In other possible embodiments, the side surface 4 of the silicon substrate 1 is provided with a film layer of the same type as the first main surface 2. Specifically, the first doped layer 6 includes a first doped portion 6-1 provided on the first intrinsic amorphous silicon portion 5-1, and also includes a third doped portion 6-2 extending to the side surface 4; the first conductive layer 7 includes a first conductive portion 7-1 provided on the first doped portion 6-1, and also includes a third conductive portion 7-2 extending to the side surface 4, that is, the third intrinsic amorphous silicon portion 5-3, the third doped portion 6-2 and the third conductive portion 7-2 are deposited on the side surface 4 of the silicon substrate 1, and the non-contact disconnection position is at the edge of the second main surface 3. The above structure is adopted to increase the heterojunction contact area, collect and utilize the generated photogenerated carriers, and improve the current and efficiency of the battery.

[0058] See also Figure 3 , and a film layer of the same type as the second main surface 3 can also be set for the side surface 4 of the silicon substrate 1. Specifically, the second doped layer 8 includes a second doped portion 8-1 set on the second intrinsic amorphous silicon portion 5-2, and also includes a fourth doped portion 8-2 extending to the side surface 4; the second conductive layer 9 includes a second conductive portion 9-1 set on the second doped portion 8-1, and also includes a fourth conductive portion 9-2 extending to the side surface 4, that is, the third intrinsic amorphous silicon portion 5-3, the fourth doped portion 8-2 and the fourth conductive portion 9-2 are deposited on the side surface 4 of the silicon substrate 1, and the non-contact disconnection position is at the edge of the first main surface 2. The above structure can also improve the current and efficiency of the battery to a certain extent.

[0059] Furthermore, the battery structure is also provided with a passivation layer, and the position of the passivation layer is selected according to the position of the non-contact disconnection position. In some specific implementation processes, when the side surface 4 of the silicon substrate 1 only covers the third intrinsic amorphous silicon portion 5-3, the passivation layer can be selectively arranged on the first conductive portion 7-1 or the second conductive portion 9-1; in some specific implementation processes, when the non-contact disconnection position is located at the edge of the second main surface 3, the passivation layer is arranged on the surface of the second conductive portion 9-1 to form a first passivation layer 10-1. The first passivation layer 10-1 is arranged on the surface of the second conductive layer 9 to reduce reflection on the back of the battery and to passivate and protect the amorphous / microcrystalline layer not covered with the doped layer and TCO. In the non-contact disconnection position, the first doped layer 6 and the second doped layer 8 are disconnected, and the first conductive layer 7 and the second conductive layer 9 are also disconnected, and the intrinsic amorphous silicon layer 5 is exposed. The first passivation layer 10-1 extends to the surface of the intrinsic amorphous silicon layer 5 at the non-contact disconnection position, and is located between the first doped layer 6 and the second doped layer 8 and between the first conductive layer 7 and the second conductive layer 9, which can further prevent the battery from short-circuiting and avoid the connection of conductive layers on different main surfaces. In another possible implementation process, when the non-contact disconnection position is located at the edge of the first main surface 2, the passivation layer is arranged on the surface of the first conductive portion 7-1 to form a second passivation layer 10-2, and the second passivation layer 10-2 is arranged on the surface of the first conductive portion 7-1. As in the above embodiment, the second passivation layer 10-2 extends from the surface of the first conductive portion 7-1 to the non-contact disconnection position. In summary, the passivation layer can protect the amorphous / microcrystalline layer.

[0060] It should be noted that the passivation layer includes at least one layer of a SiO layer or a SiO2 layer, or may be a combination of the two, as long as it can play a passivation and protection role.

[0061] Further, based on the above embodiment, the battery structure is further provided with a first gate electrode 11 and a second gate electrode 12, which are respectively connected to the first conductive part 7-1 and the second conductive part 9-1. The first gate electrode 11 and the second gate electrode 12 are configured as a silver electrode, a silver-clad copper electrode or a silver alloy paste electrode.

[0062] See also Figure 4 The present invention also provides a method for preparing a heterojunction solar cell structure, the method comprising the following steps:

[0063] S100: forming an intrinsic amorphous silicon layer 5, including a first intrinsic amorphous silicon portion 5-1 located on a first main surface 2 of a silicon substrate 1, a second intrinsic amorphous silicon portion 5-2 located on a second main surface 3 of the silicon substrate 1 opposite to the first main surface 2, and a third intrinsic amorphous silicon portion 5-3 located on a side surface 4 of the silicon substrate 1;

[0064] S200: forming a first doped layer 6, wherein the first doped layer 6 at least includes a first doped portion 6-1 located on the first intrinsic amorphous silicon portion 5-1;

[0065] S300: forming a first conductive layer 7, wherein the first conductive layer 7 at least includes a first conductive portion 7-1 located on the first doped portion 6-1;

[0066] S400: forming a second doped layer 8, wherein the second doped layer 8 at least includes a second doped portion 8-1 located on the second intrinsic amorphous silicon portion 5-2;

[0067] S500: forming a second conductive layer 9, wherein the second conductive layer 9 at least includes a second conductive portion 9-1 located on the second doped portion 8-1;

[0068] S600: A gap is formed between the first doping layer 6 and the second doping layer 8 and between the first conductive layer 7 and the second conductive layer 9, so as to expose the intrinsic amorphous silicon layer.

[0069] See also Figure 5 , taking one embodiment as an example for specific description, the following steps are included:

[0070] S100: cleaning and texturing, cleaning, gettering and texturing the silicon substrate 1 to form a pyramid light trapping structure on the surface of the silicon substrate 1;

[0071] Specifically, the N-type silicon substrate is first pre-cleaned by a tank cleaning machine, and then the silicon substrate is treated with impurities using a chain-type impurity gettering device. The silicon substrate is then cleaned and textured by a tank cleaning machine to form a pyramid light-trapping structure.

[0072] S200: depositing an intrinsic amorphous silicon layer 5, depositing the intrinsic amorphous silicon layer 5 to a first target thickness on the first main surface 2 of the silicon substrate 1, and then depositing the intrinsic amorphous silicon layer 5 to a second target thickness on the second main surface 3 of the silicon substrate 1;

[0073] Specifically, an intrinsic amorphous silicon layer 5 of a first target thickness is deposited on the first main surface 2 by an RF-PECVD device. The first target thickness can be 5-8 nm in this embodiment. During this process, a 2-4 nm intrinsic amorphous silicon layer 5 is simultaneously formed on the battery side 4; then an intrinsic amorphous silicon layer 5 of a second target thickness is deposited on the second main surface 3. The second target thickness can be 8-10 nm in this embodiment. During this process, a 3-5 nm intrinsic amorphous silicon layer 5 is simultaneously formed on the battery side. Therefore, a 5-9 nm intrinsic amorphous silicon layer 5 is formed on the battery side 4 through two depositions. The intrinsic amorphous silicon layer 5 can prevent the epitaxial growth of crystalline silicon and form a good passivation effect on the N-type silicon substrate.

[0074] S300: doping layer deposition, depositing the second doping layer 8 on the surface of the intrinsic amorphous silicon layer 5 corresponding to the second main surface 3, performing mask protection on the side surface 4 of the silicon substrate 1, and depositing the first doping layer 6 on the surface of the intrinsic amorphous silicon layer 5 corresponding to the first main surface 2 and the side surface 4;

[0075] Specifically, a 15-20 nm thick second doping layer 8 is deposited on the outer surface of the intrinsic amorphous silicon layer 5 of the second main surface 3 by RF-PECVD equipment. The second doping layer 8 is a P-type doping layer, which is amorphous, microcrystalline or nanocrystalline silicon. In this step, a mask is used to protect the edges around the second main surface 3 to prevent the second doping layer 8 from spreading to the edge or side 4. Then, a 10-15 nm thick first doping layer 6 is deposited on the outer surface of the intrinsic amorphous silicon layer 5 of the first main surface 2. The first doping layer 6 is an N-type doping layer, which is amorphous, microcrystalline or nanocrystalline silicon. In this step, a 5-10 nm second doping layer 8 is simultaneously formed on the side of the battery. The doping layer can form a heterojunction structure with the crystalline silicon substrate to achieve selective carrier transmission.

[0076] S400: depositing a conductive layer, depositing the second conductive layer 9 on the surface of the second doped layer 8, performing mask protection on the surface of the first doped layer 6 corresponding to the side surface 4, and depositing the first conductive layer 7 on the surface of the first doped layer 6;

[0077] Specifically, a PVD device is used to deposit a second conductive layer 9 with a thickness of 80-100 nm on the outer surface of the second doped layer 8 of the second main surface 3. The second conductive layer 9 is a TCO layer. TCO can be a combination of one or more of ITO, IWO, ICO, IMO, GZO, and VTTO. In this step, a mask is used to protect the edges around the second main surface 3 to prevent the second conductive layer 9 of the second main surface 3 from spreading to the edge or side 4. The second conductive layer 9 can achieve the functions of conductivity and reflection reduction, which is conducive to the generation and collection of carriers. In addition, the TCO layer is relatively hard and can protect other internal film layers. A 60-80 nm thick first conductive layer 7 is deposited on the outer surface of the first doped layer 6 of the first main surface 2 through an RPD device. The first conductive layer 7 is a TCO layer. TCO is a high-mobility ICO material. In this step, a 40-60 nm ICO layer is simultaneously formed on the side of the battery. Due to the high mobility of ICO and the good lateral conductivity, the carriers generated on the side 4 of the battery can be transferred to the gate line of the first main surface 2 for collection.

[0078] S500: electrode preparation, preparing the first gate line electrode 11 and the second gate line electrode 12 based on the first conductive layer 7 and the second conductive layer 9 respectively;

[0079] Specifically, a first gate electrode 11 and a second gate electrode 12 are respectively prepared on the first main surface 2 and the second main surface 3 of the battery by screen printing or laser transfer equipment. The first gate electrode 11 and the second gate electrode 12 are metal electrodes and are respectively connected to the first conductive layer 7 and the second conductive layer 9; the material of the metal electrode can be silver, silver-coated copper or silver alloy paste. The metal electrode can collect carriers transmitted by TCO to generate current.

[0080] S600: Depositing the passivation layer 10 . The passivation layer 10 is deposited on the surface of the second conductive layer 9 and extends between the first doped portion 6 - 1 and the second doped portion 8 - 1 and between the first conductive portion 7 - 1 and the second conductive portion 9 - 1 , so as to perform mask protection on the second gate line electrode 12 .

[0081] Specifically, a passivation layer 10 of 80-100 nm is deposited on the outer surface of the second conductive layer 9 of the second main surface 3 by PECVD / evaporation / ALD equipment, and the passivation layer 10 at the edge of the second main surface 3 is directly deposited on the outer surface of the intrinsic amorphous silicon layer 5, which strengthens the passivation effect and protects it, that is, the passivation layer 10 extends between the first doped part 6-1 and the second doped part 8-1, between the first conductive part 7-1 and the second conductive part 9-1, and can also be understood as the non-contact part between the first doped layer 6 and the second doped layer 8, and the first conductive layer 7 and the second conductive layer 9 is filled with the passivation layer 10. In this process, the second gate line electrode 12 of the metal electrode of the second main surface 3 needs to be masked to prevent the passivation layer 10 from covering the second gate line electrode 12 and causing the loss of conductive performance. The passivation layer 10 also has an anti-reflection effect.

[0082] The above structure is taken as Example 1, and different comparative examples are set up below to compare battery performance indicators.

[0083] Comparative Example 1: No treatment was done on the side of the battery, standard heterojunction battery;

[0084] Comparative Example 2: Only an intrinsic hydrogenated amorphous silicon layer is deposited on the side of the cell;

[0085] Comparative Example 3: An intrinsic hydrogenated amorphous silicon layer and a first doping layer are sequentially deposited on the side of the battery;

[0086] Comparative Example 4: An intrinsic hydrogenated amorphous silicon layer, a first doping layer and a first conductive layer are sequentially deposited on the side of the battery; Isc(A) Voc(V) FF(%) Eta(%) Rsh(ohm) Rs(ohm) Example 1 8.864 0.751 85.65 25.59 1333.5 0.00106 Comparative Example 1 8.815 0.707 85.16 25.31 1587.2 0.00153 Comparative Example 2 8.806 0.742 85.48 25.45 1378.5 0.00166 Comparative Example 3 8.797 0.742 85.41 25.39 1383.9 0.00161 Comparative Example 4 8.863 0.749 85.58 25.52 1358.3 0.00092

[0087] From the above table, we can see that Example 1 has optimized performance in Isc (open circuit current), Voc (open circuit voltage), FF (fill factor), Eta (rated capacity), Rsh (bypass resistance), and Rs (series resistance), thereby improving battery-related performance.

[0088] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A heterojunction solar cell structure, characterized in that: The battery structure comprises: A silicon substrate (1), the silicon substrate (1) being provided with a first main surface (2), a second main surface (3) opposite to the first main surface (2), and a side surface (4); An intrinsic amorphous silicon layer (5), comprising a first intrinsic amorphous silicon portion (5-1) located on the first main surface (1), a second intrinsic amorphous silicon portion (5-2) located on the second main surface (2), and a third intrinsic amorphous silicon portion (5-3) located on the side surface (4); A first doped layer (6), comprising at least a first doped portion (6-1) located on the first intrinsic amorphous silicon portion (5-1); A first conductive layer (7), comprising at least a first conductive portion (7-1) located on the first doped portion (6-1); A second doped layer (8), comprising at least a second doped portion (8-1) located on the second intrinsic amorphous silicon portion (5-2); The second conductive layer (9) at least comprises a second conductive portion (9-1) located on the second doped portion (8-1), There is a gap between the first doped layer (6) and the second doped layer (8) and between the first conductive layer (7) and the second conductive layer (9), thereby exposing the intrinsic amorphous silicon layer (5).

2. The heterojunction solar cell structure according to claim 1, characterized in that: The first doped layer (6) further comprises a third doped portion (6-2) located on the third intrinsic amorphous silicon portion (5-3), and the first conductive layer (7) further comprises a third conductive portion (7-2) located on the third doped portion (6-2); The second doped layer (8) includes only the second doped portion (8-1) and the second conductive layer (9) includes only the second conductive portion (9-1), The gap exists between the third doped portion (6-2) and the second doped portion (8-1) and between the third conductive portion (7-2) and the second conductive portion (9-1).

3. The heterojunction solar cell structure according to claim 2, characterized in that: The battery structure comprises: A first passivation layer (10-1) is located on a surface of the second conductive portion (9-1) away from the silicon substrate (1) and extends onto the exposed intrinsic amorphous silicon layer (5).

4. The heterojunction solar cell structure according to claim 1, characterized in that: The second doped layer (8) further comprises a fourth doped portion (8-2) located on the third intrinsic amorphous silicon portion (5-3), and the second conductive layer (9) further comprises a fourth conductive portion (9-2) located on the fourth doped portion (8-2); The first doping layer (6) includes only the first doping portion (6-1) and the first conductive layer (7) includes only the first conductive portion (7-1), The gap exists between the fourth doped portion (8-2) and the first doped portion (6-1) and between the fourth conductive portion (9-2) and the first conductive portion (7-1).

5. The heterojunction solar cell structure according to claim 4, characterized in that: The battery structure comprises: A second passivation layer (10-2) is located on a surface of the first conductive portion (7-1) away from the silicon substrate (1) and extends onto the exposed intrinsic amorphous silicon layer (5).

6. The heterojunction solar cell structure according to any one of claims 1 to 5, characterized in that: The conductivity type of the first doped layer (6) is N-type; the conductivity type of the second doped layer (8) is P-type.

7. The heterojunction solar cell structure according to any one of claims 1 to 5, characterized in that: The first conductive layer (7) and the second conductive layer (9) are TCO layers.

8. The heterojunction solar cell structure according to claim 1, characterized in that: The battery structure further comprises: A first gate line electrode (11) and a second gate line electrode (12), wherein the first gate line electrode (11) and the second gate line electrode (12) are respectively connected to the first conductive part (7-1) and the second conductive part (9-1).

9. The heterojunction solar cell structure according to claim 8, characterized in that: The first gate line electrode (11) and the second gate line electrode (12) are one of silver electrodes, silver-clad copper electrodes or silver alloy paste electrodes.

10. A method for preparing a heterojunction solar cell structure, characterized in that: The following steps are involved: Forming an intrinsic amorphous silicon layer (5), comprising a first intrinsic amorphous silicon portion (5-1) located on a first main surface (2) of a silicon substrate (1), a second intrinsic amorphous silicon portion (5-2) located on a second main surface (3) of the silicon substrate (1) opposite to the first main surface (2), and a third intrinsic amorphous silicon portion (5-3) located on a side surface (4) of the silicon substrate (1); forming a first doped layer (6), the first doped layer (6) comprising at least a first doped portion (6-1) located on the first intrinsic amorphous silicon portion (5-1); forming a first conductive layer (7), wherein the first conductive layer (7) at least comprises a first conductive portion (7-1) located on the first doped portion (6-1); forming a second doped layer (8), the second doped layer (8) comprising at least a second doped portion (8-1) located on the second intrinsic amorphous silicon portion (5-2); forming a second conductive layer (9), wherein the second conductive layer (9) at least comprises a second conductive portion (9-1) located on the second doped portion (8-1), A gap is formed between the first doped layer (6) and the second doped layer (8) and between the first conductive layer (7) and the second conductive layer (9), thereby exposing the intrinsic amorphous silicon layer.

Images