Wireless communication device and method of controlling activation of radio frequency transmit signal generation circuitry

Abstract

The present disclosure provides a wireless communication device and method for controlling activation of a radio frequency (RF) transmit signal generation circuit. The wireless communication equipment comprises a communication processor and a transceiver; the transceiver is controlled by the communication processor and performs wireless communication. Wherein the transceiver comprises: a phase locked loop (PLL) circuit for generating a first oscillation signal based on a clock frequency signal; an RF transmission signal generation circuit for generating an RF transmission signal based on the first oscillation signal received from the PLL circuit and a baseband transmission signal received from the communication processor; and a first decision circuit for receiving a first phase comparison signal from a first phase comparator of the PLL circuit and controlling activation of at least one component of the RF transmit signal generation circuit based on the first phase comparison signal, where the first phase comparison signal indicates whether a phase of the first oscillation signal is fixed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a technique for controlling activation of a radio frequency (RF) transmission signal generating circuit and a wireless communication device for performing the technique. Background Art

[0002] In wireless communication devices, communication processors can perform communication-related controls. Signals generated by communication processors can be used to control transceivers and radio frequency (RF) components. A transceiver is a device configured to send and receive wireless communication signals, which can implement the functions of a transmitter and a receiver as a single module. RF components may include an RF front end. Generally, the RF front end refers to all components between the antenna and the transceiver, and can perform functions such as networking, file transfer, communication, card swiping and / or positioning. Summary of the invention

[0003] Technical goals

[0004] When a communication processor has control problems in the process of controlling the transceiver, such as software code errors or timing alignment errors, wireless communication may fail. When such problems occur in the control process related to the radio frequency (RF) transmission signal, the RF components may be damaged.

[0005] According to the wireless communication device and method for controlling activation of an RF transmission signal generating circuit of the embodiment, a hardware control method for a transceiver may be adopted, thereby reducing damage to RF components caused by problems occurring in a control process related to the RF transmission signal.

[0006] Technical Solution

[0007] According to an embodiment, a wireless communication device is provided, comprising: a communication processor; and a transceiver, the transceiver being configured to be controlled by the communication processor to perform wireless communication. The transceiver comprises: a phase-locked loop (PLL) circuit configured to generate a first oscillation signal based on a clock frequency signal; a radio frequency (RF) transmission signal generation circuit configured to generate an RF transmission signal based on the first oscillation signal received from the PLL circuit and a baseband transmission signal received from the communication processor; and a first determination circuit configured to receive a first phase comparison signal from a first phase comparator in the PLL circuit, the first phase comparison signal indicating whether the phase of the first oscillation signal is locked, and controlling activation of at least one component in the RF transmission signal generation circuit based on the first phase comparison signal.

[0008] According to an embodiment, a method for controlling activation of an RF transmission signal generation circuit included in a transceiver in a wireless communication device is provided, the transceiver being configured to perform wireless communication. The method includes: a first phase comparator of a PLL circuit in the transceiver compares the phase of a clock frequency signal with the phase of a first oscillation signal and generates a first phase comparison signal, the first oscillation signal being an output signal of the PLL circuit, the first phase comparison signal indicating whether the phase of the first oscillation signal is locked; the first phase comparator sends the first phase comparison signal to a first determination circuit of the transceiver; the first determination circuit controls activation of at least one component in the RF transmission signal generation circuit based on whether the phase of the first oscillation signal indicated in the first phase comparison signal is locked; in response to the at least one component being activated, the RF transmission signal generation circuit generates an RF transmission signal according to the first oscillation signal and a baseband transmission signal generated by a communication processor of the wireless communication device; and the RF transmission signal generation circuit outputs the generated RF transmission signal.

[0009] According to the embodiments, a wireless communication device and method for controlling activation of an RF transmission signal generation circuit can control activation of the RF transmission signal generation circuit when a transmission signal having a frequency outside a normal range is generated due to an error generated by a control process related to the RF transmission signal, thereby reducing damage to components of the RF transmission signal generation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 shows the configuration of a wireless communication device;

[0011] Figure 2 showing a first determination circuit configured to control activation of an RF transmit signal generating circuit;

[0012] Figure 3 Components of an RF transmit signal generating circuit whose activation is controlled by a first decision circuit are shown;

[0013] Figure 4 shows the input and output of the first determination circuit;

[0014] Figure 5 A first determination circuit is shown;

[0015] Figure 6 shows the input and output of the first determination circuit;

[0016] Figure 7 A first determination circuit and a second determination circuit are shown;

[0017] Figure 8An example is shown in which the frequency of the baseband signal exceeds the normal range after being acted upon by the first frequency shifter and the second frequency shifter;

[0018] Fig. 9 shows the input and output of the first determination circuit;

[0019] Fig.10 A flow chart illustrating a method of controlling activation of an RF transmit signal generating circuit;

[0020] Fig.11 A block diagram of an electronic device including a wireless communication device is shown. DETAILED DESCRIPTION

[0021] Hereinafter, examples / embodiments will be described in detail with reference to the accompanying drawings. When describing the embodiments with reference to the accompanying drawings, the same reference numerals denote the same elements, and repeated description thereof will be omitted.

[0022] Those skilled in the art will appreciate that the features described above and / or below may be combined in any manner deemed useful. The drawings of the present disclosure illustrate examples / embodiments of the present invention, which will be described in detail below. It should be understood that, unless mechanical or other limitations prevent such implementation, one or more elements / components shown and / or described in one or more examples / embodiments (and not shown and / or described in other examples / embodiments) may also be used in other examples / embodiments. In addition, describing the features of different examples / embodiments in a single paragraph does not mean that these features are inseparably linked together. They can be applied independently of each other.

[0023] Figure 1 A configuration of a wireless communication device is shown.

[0024] Reference Figure 1 , the wireless communication device 100 may include a communication processor 105, a transceiver 110, a radio frequency (RF) front-end circuit 120, a power modulator 115, and an antenna 125. The transceiver 110 is configured to be controlled by the communication processor 105 to perform wireless communication, the RF front-end circuit 120 is configured to amplify RF transmission signals and RF reception signals, the power modulator 115 is configured to supply power to an amplifier 130 of the RF front-end circuit 120, and the antenna 125 is configured to transmit and receive RF signals. The RF front-end circuit 120 may include, for example, an amplifier 130, a duplexer 135, and / or a coupler 140.

[0025] The transceiver 110 may include a phase locked loop (PLL) circuit configured to generate an oscillation signal based on a clock frequency signal and an RF transmission signal generating circuit configured to generate a radio frequency transmission signal Tx based on the oscillation signal received from the PLL circuit and the baseband transmission signal received from the communication processor 105. Figures 1 to 11 These components and / or functions are described / illustrated in more detail.

[0026] In the wireless communication device 100, the transceiver 110 may be controlled by the communication processor 105 based on software. However, when such software-based control is performed, the transceiver 110 may operate abnormally due to software inaccuracies caused by, for example, human errors. For example, if the control of the transceiver 110 is not performed correctly when sending an RF transmit signal, an RF transmit signal with a frequency outside the normal range may be generated. For example, there may be a situation where the transceiver 110 may use the oscillation signal to generate an RF signal before the phase of the oscillation signal is locked, in which case an RF transmit signal with an unexpected frequency may be generated. According to the circuit characteristics of the wireless communication device 100, the RF front-end circuit 120 is able to normally amplify RF transmit signals within a certain frequency range. When the RF front-end circuit 120 amplifies an RF transmit signal with an abnormal frequency that exceeds its normal amplification range, damage may be caused to the components included in the RF front-end circuit 120.

[0027] For example, the PLL circuit of the wireless communication device 100 can determine whether the phase of the oscillation signal has been locked by comparing the clock frequency signal and the oscillation signal as the output signal of the PLL circuit. Generally, the PLL circuit can be configured to adjust the frequency of the oscillation signal to match the frequency of the clock frequency signal. In this sense, the clock frequency signal can be referred to as a reference signal having a reference frequency, for example, which can be generated by the wireless communication device 100 or received by the wireless communication device 100. The wireless communication device 100 may include a determination circuit configured to control the activation (or enablement) of at least one component in the RF transmission signal generation circuit based on whether the phase of the oscillation signal is locked. When the phase of the oscillation signal is locked, the determination circuit can activate at least one component in the RF transmission signal generation circuit, and when the phase of the oscillation signal is not locked, the determination circuit can deactivate at least one component in the RF transmission signal generation circuit. At least one component included in the RF transmission signal generation circuit can be an active component such as an amplifier, a voltage converter, and a mixer. When at least one component in the RF transmission signal generation circuit is deactivated, the RF transmission signal generation circuit may not generate an RF transmission signal. The wireless communication device 100 may be configured to activate the RF transmission signal generation circuit only when the phase of the oscillation signal is locked, thereby preventing the generation of an RF transmission signal of an abnormal frequency based on the oscillation signal whose phase is not locked.

[0028] Figure 2 A first decision circuit configured to control activation of an RF transmit signal generating circuit is shown. One or more of these components may be associated with Figure 1 and 3 -11 and / or the same as the components described with reference to these figures, and / or may be used with Figure 1 and 3 -11 and / or the components described with reference to these figures are implemented together.

[0029] Reference Figure 2 , Figure 2An exemplary block diagram of the transceiver 110 is shown. The transceiver 110 of the wireless communication device 100 may include a PLL circuit 210 configured to generate an oscillation signal based on a clock frequency signal. The PLL circuit 210 may include: a first buffer 287 configured to amplify the clock frequency signal and send it to a first phase comparator 285; a first phase comparator 285 configured to compare the phases of the clock frequency signal and the first oscillation signal 220; a first oscillator 225 configured to generate a first oscillation signal 220 based on an output signal of the first phase comparator 285; a first frequency divider 289 configured to reduce the frequency of the first oscillation signal 220 and send it (the first oscillation signal 220 after the frequency reduction) to the first phase comparator 285; and / or a first loop filter 283 configured to remove noise contained in the output signal of the first phase comparator 285.

[0030] The PLL circuit 210 may also include: a second buffer 297, configured to amplify the clock frequency signal and send it to a second phase comparator 295; a second phase comparator 295, configured to compare the phases of the clock frequency signal and the second oscillation signal 235; a second oscillator 230, configured to generate a second oscillation signal 235 based on the output signal of the second phase comparator 295; a second divider 299, configured to reduce the frequency of the second oscillation signal 235 and send it to the second phase comparator 295; and / or a second loop filter 293, configured to remove noise contained in the output signal of the second phase comparator 295.

[0031] The transceiver 110 may further include an RF transmit signal generating circuit 205 configured to generate an RF transmit signal Tx based on a first oscillation signal 220 received from the PLL circuit 210 and a baseband transmit signal received from the communication processor 105. The transceiver 110 may further include an RF receive signal processing circuit 215 configured to generate a baseband receive signal based on a second oscillation signal 235 received from the PLL circuit 210 and a radio frequency receive signal Rx received from the outside.

[0032] The RF reception signal Rx received from the outside through the antenna 125 can be combined with the second oscillation signal 235 in the mixer 275. The combined signal can be converted into a baseband reception signal through a transimpedance amplifier (TIA) 270, a low pass filter (LPF) / variable gain amplifier (VGA) 265, and a voltage analog-to-digital converter (ADC) 263. The baseband reception signal can be sent to the communication processor 105. Both the baseband transmission signal and the baseband reception signal can be complex signals including an in-phase component I signal and an orthogonal component Q signal.

[0033] The communication processor 105 may send a baseband transmission signal containing data to be sent to the outside to the transceiver 110. The transmission signal generated by the communication processor 105 may be a digital signal. The baseband transmission signal input to the transceiver 110 may be converted into an analog signal by a voltage digital-to-analog converter (DAC) 240 in the RF transmission signal generating circuit 205, and filtered into a signal of a set bandwidth by an LPF 245. After the filtered signal passes through a voltage-current (V2I) amplifier 250, it may be combined with the first oscillation signal 220 in a mixer 255. The RF transmission signal generated by the combination in the mixer 255 may be a voltage signal. The RF transmission signal may be amplified by an RF signal amplifier 260 and then output. The RF signal amplifier 260 may include, for example, a VGA and a driver amplifier (DA).

[0034] The RF transmit signal Tx can be generated by combining the baseband transmit signal with the first oscillation signal 220, so when the frequency and phase of the first oscillation signal 220 are unstable, the frequency and phase of the RF transmit signal Tx may also become unstable. The wireless communication device 100 can first determine whether the phase of the oscillation signal output by the PLL circuit 210 has been locked to ensure that the RF transmit signal Tx can be stably transmitted, and then activate the RF transmit signal generation circuit 205 after the phase of the oscillation signal is locked.

[0035] The first phase comparator 285 in the PLL circuit 210 may compare the clock frequency signal and the first oscillation signal 220 and generate the first oscillation signal 220 indicating whether the phase of the first oscillation signal 220 is locked. The second phase comparator 295 in the PLL circuit 210 may compare the clock frequency signal and the second oscillator signal 235 and generate the second oscillation signal 235 indicating whether the phase of the second oscillation signal 235 is locked.

[0036] The transceiver 110 may further include a first determination circuit 280 configured to control activation of at least one component in the RF transmit signal generation circuit 205 according to at least one of the first oscillating signal 220 or the second oscillating signal 235. The first determination circuit 280 may receive a first phase comparison signal 286 from the first phase comparator 285. The first determination circuit 280 may also receive a second phase comparison signal 296 from the second phase comparator 295. Based on at least one of the first phase comparison signal 286 or the second phase comparison signal 296, when the phase of the first oscillating signal 220 and the phase of the second oscillating signal 235 are both locked, the first determination circuit 280 may activate at least one component in the RF transmit signal generation circuit 205; and when at least one of the phase of the first oscillating signal 220 or the phase of the second oscillating signal 235 is not locked, the first determination circuit 280 may deactivate at least one component in the RF transmit signal generation circuit 205. For example, if only the first phase comparator 285 for generating the first oscillating signal 220 is implemented, then when the phase of the first oscillating signal 220 is locked, the first determination circuit 280 may activate at least one component in the RF transmission signal generating circuit 205. Similarly, if only the second phase comparator 295 is implemented, the situation is similar.

[0037] In wireless communication operation, when sending an RF transmission signal using a communication network, the wireless communication device 100 may need to receive a signal for establishing a communication channel with a base station, and in order to receive this corresponding signal, the phase of the second oscillation signal 235 provided to the RF reception signal processing circuit 215 may need to be locked prior to the phase of the first oscillation signal 220 provided to the RF transmission signal generating circuit 205. In this case, if the RF transmission signal is generated without the phase of the second oscillation signal 235 being locked, then this signal may be unnecessary. For example, in order to stably generate the RF transmission signal, the wireless communication device 100 may control the activation of the RF transmission signal generating circuit 205 based on whether the phase of the second oscillation signal 235 is locked and whether the phase of the first oscillation signal 220 is locked.

[0038] Figure 3 Components of the RF transmission signal generating circuit whose activation / deactivation is controlled by the first decision circuit are shown. One or more of these components may be connected to Figure 1 , 2 and / or components that are the same as those shown in and / or described with reference to Figures 4-11, and / or can be used with Figure 1 , 2 Implemented together with the components shown and / or described in 4-11.

[0039] Reference Figure 3, components of the RF transmit signal generation circuit 205 controlled by the first decision circuit 280 are shown.

[0040] The first determination circuit 280 may activate at least one component included in the RF transmit signal generation circuit 205 based on, for example, the first phase comparison signal 286 and the second phase comparison signal 296. The component controlled by the first determination circuit 280 may be, for example, an active component included in the RF transmit circuit. For example, the first determination circuit 280 may control activation of one or more of an amplifier, a voltage converter, a mixer, etc. based on the first phase comparison signal 286 and the second phase comparison signal 296.

[0041] For example, when the phase of the first oscillation signal 220 and the phase of the second oscillation signal 235 are both locked, the first determination circuit 280 may activate at least one component included in the RF transmission signal generation circuit 205. According to another example, when the phase of the first oscillation signal 220 and the phase of the second oscillation signal 235 are both not locked, the first determination circuit 280 may deactivate at least one component included in the RF transmission signal generation circuit 205. According to yet another example, when at least one of the phase of the first oscillation signal 220 and the phase of the second oscillation signal 235 is not locked, the first determination circuit 280 may deactivate at least one component included in the RF transmission signal generation circuit 205.

[0042] When at least one component included in the RF transmission signal generation circuit 205 is disabled, the RF transmission signal generation circuit 205 may not generate an RF transmission signal. When at least one of the phase of the first oscillation signal 220 and the phase of the second oscillation signal 235 is not locked, the first determination circuit 280 may disable the RF transmission signal generation circuit 205, thereby preventing the generation of an abnormal frequency RF transmission signal based on the phase-unlocked oscillator signal.

[0043] The first determination circuit 280 may control at least one component in the RF transmission signal generation circuit 205 , for example, by controlling the power provided to the at least one component, or controlling the bias voltage or bias current provided to the at least one component.

[0044] Figure 4 The input and output of the first decision circuit are shown. Figure 4 shown in and / or with reference to Figure 4 One or more of the components described may be used with Figure 1-3 The same as the components shown in 5-11 and / or described with reference to these figures, and / or can be implemented together with these components.

[0045] Reference Figure 4 , an exemplary logic circuit of the first determination circuit 280 is shown.

[0046] As an example, one or more of the power signal, the ground (or GND) signal, the first phase comparison signal 286, and the second phase comparison signal 296 may be input to the first determination circuit 280. For example, the logic circuit of the first determination circuit 280 may include a multiplexer 405 and an AND gate 410, the power signal and the ground signal are input to the multiplexer 405, and the first phase comparison signal 286 and the second phase comparison signal 296 are input to the AND gate 410.

[0047] The first determination circuit 280 may output the input power or ground signal according to at least one of the first phase comparison signal 286 and the second phase comparison signal 296. The output of the first determination circuit 280 may be connected to at least one component of the RF transmit signal generation circuit 205 to activate or deactivate the corresponding component.

[0048] When the phase of the first oscillation signal 220 and the phase of the second oscillation signal 235 are both locked, the first determination circuit 280 can activate at least one component included in the RF transmission signal generation circuit 205; and when at least one of the phase of the first oscillation signal 220 or the phase of the second oscillation signal 235 is not locked, the first determination circuit 280 can deactivate at least one component included in the RF transmission signal generation circuit 205.

[0049] For example, when the phase difference between the clock frequency signal and the first oscillation signal 220 remains within a set range within a set time, the first phase comparator 285 of the PLL circuit 210 can output a first phase comparison signal 286 having a first value; and when the phase difference between the clock frequency signal and the first oscillation signal 220 does not remain within the set range within the set time, it can output a first phase comparison signal 286 having a second value. A phase comparison signal having a certain value can mean that the phase comparison signal corresponds to the value, or can be measured and / or identified by the value. When the phase difference between the clock frequency signal and the second oscillation signal 235 remains within a set range within a set time, the second phase comparator 295 of the PLL circuit 210 can output a second phase comparison signal 296 having a first value; and when the phase difference between the clock frequency signal and the second oscillation signal 235 does not remain within the set range within the set time, it can output a second phase comparison signal 296 having a second value. For the first and second phase comparators, their setting ranges and setting times can be configured to be different, similar or the same, respectively. These parameters can be preset, configurable and / or predetermined. The setting range may refer to an interval or a set of value ranges of the phase difference. The setting time may refer to a time interval having a predetermined, preset and / or configurable length. For the convenience of description, the following will use expressions such as "setting range", "setting time" and the like.

[0050] The phase comparator (e.g., the first phase comparator 285 and / or the second phase comparator 295) may include an analog circuit or a digital circuit. For example, if the phase comparator includes an analog circuit, the phase difference between the clock frequency signal and the oscillation signal (e.g., the first oscillation signal 220 or the second oscillation signal 235) may be represented as an analog voltage. In this case, when the analog voltage representing the phase difference remains within a set voltage range within a set time, the phase comparator may determine that the phase of the oscillation signal is locked and generate a phase comparison signal having a first value (e.g., the first phase comparison signal 286 or the second phase comparison signal 296). For another example, if the phase comparator is a digital circuit, the phase difference between the clock frequency signal and the oscillation signal (e.g., the first oscillation signal 220 or the second oscillation signal 235) may be represented as a digital bit. In this case, when the value of the digital bit remains within a set value range within a set time, the phase comparator may determine that the phase of the oscillation signal is locked and generate a phase comparison signal having a first value.

[0051] For example, when the value of the first phase comparison signal 286 is a first value and the value of the second phase comparison signal 296 is a first value, the first determination circuit 280 can output the input power supply signal; and when at least one of the value of the first phase comparison signal 286 or the value of the second phase comparison signal 296 is a second value, the first determination circuit 280 can output the input ground signal.

[0052] Figure 5 A first decision circuit is shown. Figure 5 shown in and / or with reference to Figure 5 One or more of the components described may be used with Figure 1-4 and 6-11 shown and / or referenced Figure 1-4 The same as the components described in 6-11, and / or can be implemented together with these components.

[0053] From a circuit design perspective, it may be difficult to Figure 2 The circuit of the transceiver 110 shown includes (or adds) a conductor for sending the second phase comparison signal 296 to the first decision circuit 280. Figure 5 , which shows an example of a first decision circuit 280 configured to control activation of the RF transmit signal generation circuit 205 based on a first phase comparison signal 286.

[0054] The first phase comparator 285 in the PLL circuit 210 can compare the clock frequency signal and the first oscillation signal 220 to generate a first phase comparison signal 286, which indicates whether the phase of the first oscillation signal 220 is locked. The transceiver 110 may include a first determination circuit 280, which is configured to control the activation of at least one component in the RF transmission signal generation circuit 205 based on the first oscillation signal 220. For example, the first determination circuit 280 can receive the first phase comparison signal 286 from the first phase comparator 285. Based on the first phase comparison signal 286, when the phase of the first oscillation signal 220 is locked, the first determination circuit 280 can activate at least one component in the RF transmission signal generation circuit 205; and when the phase of the first oscillation signal 220 is not locked, the at least one component in the RF transmission signal generation circuit 205 can be deactivated. Basically, the above reference Figure 3 The description of the first determination circuit 280 is also applicable to the description of the components in the RF transmission signal generation circuit 205 that are controlled by the first determination circuit 280 .

[0055] Figure 6 is a schematic diagram of the input and output of the first determination circuit. Figure 6 shown in and / or with reference to Figure 6 One or more of the components described may be used with Figure 1-5 and 7-11 shown and / or referenced Figure 1-5 The same as components described in 7-11, and / or can be implemented together with these components.

[0056] Reference Figure 6 , which shows a first determination circuit 505 (eg, Figure 2 and Figure 5 An exemplary logic circuit of the first decision circuit 280 in FIG.

[0057] As an example, one or more of the power signal, the ground (or GND) signal, and the first phase comparison signal 286 may be input to the first determination circuit 505. For example, the logic circuit of the first determination circuit 505 may include a multiplexer 605, and the power signal and the ground signal are input to the multiplexer 605.

[0058] The first determination circuit 505 may output the input power signal or ground signal according to the first phase comparison signal 286. The output of the first determination circuit 505 may be connected to at least one component of the RF transmission signal generation circuit 205 to activate or deactivate the corresponding component.

[0059] When the phase of the first oscillation signal 220 is locked, the first determination circuit 505 may activate at least one component included in the RF transmission signal generation circuit 205; and when the phase of the first oscillation signal 220 is not locked, the first determination circuit 505 may deactivate at least one component included in the RF transmission signal generation circuit 205.

[0060] For example, when the phase difference between the clock frequency signal and the first oscillation signal 220 remains within a set range within a set time, the first phase comparator 285 of the PLL circuit 210 can output a first phase comparison signal 286 having a first value; and when the phase difference between the clock frequency signal and the first oscillation signal 220 does not remain within a set range within a set time, a first phase comparison signal 286 having a second value is output.

[0061] For example, when the value of the first phase comparison signal 286 is a first value, the first determination circuit 505 may output the input power signal; and when the value of the first phase comparison signal 286 is a second value, the first determination circuit 505 may output the input ground signal.

[0062] Figure 7 Schematic diagram of a first determination circuit and a second determination circuit.

[0063] Reference Figure 7 , which illustrates examples of the communication processor 105 and the transceiver 110 in block diagram form. Figure 7 shown in and / or referenced in Figure 7 One or more of the components described may be used with Figure 1-6 and 8-11 shown and / or referenced Figure 1-6 The same as the components described in 8-11, and / or can be implemented together with these components.

[0064] The transceiver 110 may include a first determination circuit 705 configured to control activation of the RF transmit signal generation circuit 205 based on the first phase comparison signal 286 received from the first phase comparator 285, the second phase comparison signal 296 received from the second phase comparator 295, and a signal received from the second determination circuit 710.

[0065] The communication processor 105 may include at least one of the following components: a complex signal generator 725, a first frequency shifter 730, a modulator 735, a second frequency shifter 740 and / or a second determination circuit 710; wherein the complex signal generator 725 is configured to generate a complex signal, the first frequency shifter 730 is configured to frequency shift the frequency of the complex signal to generate a baseband transmission signal, the modulator 735 is configured to modulate the complex signal, the second frequency shifter 740 is configured to frequency shift the frequency of the complex signal modulated by the modulator 735 to generate a baseband transmission signal, and the second determination circuit 710 is configured to detect whether the first frequency shifter 730 and the second frequency shifter 740 are working, and send the detection result signal 750 to the first determination circuit 705.

[0066] The communication processor 105 may use any one of the first frequency shifter 730 or the second frequency shifter 740 to generate a baseband transmission signal according to the complex signal. The communication processor 105 may use a frequency shifter (e.g., the first frequency shifter 730 and the second frequency shifter 740) to select a frequency resource block for RF signal transmission. The communication processor 105 may select to use one of the first frequency shifter 730 or the second frequency shifter 740 according to the communication protocol used in the transmission of the RF transmission signal. For example, when transmitting a physical random access channel (PRACH) protocol signal, the communication processor 105 may use a complex signal of a Zadoff-chu sequence and the first frequency shifter 730 to generate a baseband transmission signal. When transmitting data such as a physical uplink shared channel (PUSCH), the communication processor 105 may use a modulator 735 and a second frequency shifter 740 to generate a baseband transmission signal.

[0067] As described above, one of the first frequency shifter 730 and the second frequency shifter 740 may be selected for use as needed. However, when the first frequency shifter 730 and the second frequency shifter 740 are used simultaneously, the frequency of the baseband transmission signal may be changed to an unintended frequency.

[0068] For example, refer to Figure 8 , which shows an example case where the frequency of the baseband signal obtained by the first frequency shifter 730 and the second frequency shifter 740 exceeds the normal range.

[0069] For example, when the communication processor 105 generates a baseband transmission signal using the first frequency shifter 730, the generated baseband transmission signal may be a first frequency baseband transmission signal 805. When the first frequency shifter 730 and the second frequency shifter 740 work simultaneously to generate a baseband transmission signal, the generated baseband transmission signal may be a second frequency baseband transmission signal 810. In this example, the second frequency may be a frequency that exceeds a normal frequency range 815 according to a circuit design of a wireless communication device, and the baseband transmission signal of this frequency may damage the RF front-end circuit 120 during signal processing.

[0070] The second determination circuit 710 can detect whether the first frequency shifter 730 and the second frequency shifter 740 are working, and send the detection result signal 750 to the first determination circuit 705. For example, the detection result signal 750 can be converted into a digital signal in the communication processor controller 715 that controls the operation performed by the communication processor 105, and the digital signal can be sent to the transceiver controller 720 through the digital interface 745 connecting the communication processor 105 and the transceiver 110. The transmitted signal can be sent to the first determination circuit 705 through the transceiver controller 720 that controls the operation performed by the transceiver 110. The detection result signal 750 can also be sent to the first determination circuit 705 through an interface formed separately from the digital interface 745 and dedicated to sending the detection result signal 750.

[0071] The first determination circuit 705 can control the activation of at least one component in the RF transmission signal generation circuit 205 according to the detection result signal 750, the first phase comparison signal 286 and the second phase comparison signal 296, and the detection result signal 750 is received from the second determination circuit 710. When the first determination circuit 705 controls the activation of at least one component in the RF transmission signal generation circuit 205, in addition to using the first phase comparison signal 286 and the second phase comparison signal 296, the detection result of the second determination circuit 710 is further used, so that damage that may be caused by the baseband transmission signal beyond the normal frequency range can be avoided. Basically, the above reference Figure 3 The description of the first determination circuit 280 may be applied to the description of the components of the RF transmission signal generation circuit 205 controlled by the first determination circuit 705.

[0072] When any one of the first frequency shifter 730 and the second frequency shifter 740 is working and the phase of the first oscillation signal 220 and the phase of the second oscillation signal 235 are locked, the first determination circuit 705 can activate at least one component in the RF transmission signal generation circuit 205 based on the detection result signal 750, the first phase comparison signal 286 and the second phase comparison signal 296. When both the first frequency shifter 730 and the second frequency shifter 740 are working, or at least one of the phase of the first oscillation signal 220 and the phase of the second oscillation signal 235 is not locked, the first determination circuit 705 can deactivate at least one component in the RF transmission signal generation circuit 205 based on the detection result signal 750, the first phase comparison signal 286 and the second phase comparison signal 296.

[0073] Fig. 9 is a schematic diagram of the input and output of the first determination circuit. Fig. 9 shown in and / or with reference to Fig. 9 One or more of the components described may be used with Figure 1-8 The same as the components shown in Figures 10-11 and / or described with reference to these figures, and / or can be implemented together with these components.

[0074] Reference Fig. 9 , which shows an example of a logic circuit of the first determination circuit.

[0075] For example, the power signal, the ground (or GND) signal, the first phase comparison signal 286, the second phase comparison signal 296, and the detection result signal 750 sent from the second determination circuit 710 may be input into the first determination circuit 705. For example, the logic circuit of the first determination circuit 705 may include a multiplexer 905, a first AND gate 910, and a second AND gate 915; wherein the power signal and the ground signal are input into the multiplexer 905, the first phase comparison signal 286 and the detection result signal 750 are input into the first AND gate 910, and the second phase comparison signal 296 and the output of the first AND gate 910 are input into the second AND gate 915.

[0076] The first determination circuit 705 may output the input power signal or ground signal based on the detection result signal 750, the first phase comparison signal 286, and the second phase comparison signal 296. The output of the first determination circuit 705 may be connected to at least one component in the RF transmission signal generation circuit 205 to activate or deactivate the corresponding component.

[0077] When any one of the first frequency shifter 730 and the second frequency shifter 740 is operating and the phase of the first oscillation signal 220 and the phase of the second oscillation signal 235 are locked, the first determination circuit 705 can activate at least one component in the RF transmission signal generation circuit 205. When the first frequency shifter 730 and the second frequency shifter 740 are operating at the same time, or at least one of the phase of the first oscillation signal 220 and the phase of the second oscillation signal 235 is not locked, the first determination circuit 705 can deactivate at least one component in the RF transmission signal generation circuit 205.

[0078] For example, when the phase difference between the clock frequency signal and the first oscillation signal 220 remains within a set range within a set time, the first phase comparator 285 of the PLL circuit 210 may output a first phase comparison signal 286 having a first value; when the phase difference between the clock frequency signal and the first oscillation signal 220 remains within a set range within a set time, the first phase comparator 285 may output a first phase comparison signal 286 having a second value. When the phase difference between the clock frequency signal and the second oscillation signal 235 remains within a set range within a set time, the second phase comparator 295 of the PLL circuit 210 may output a second phase comparison signal 296 having a first value; when the phase difference between the clock frequency signal and the second oscillation signal 235 does not remain within the set range within a set time, the second phase comparator 295 may output a second phase comparison signal 296 having a second value. When any one of the first frequency shifter 730 and the second frequency shifter 740 is working, the second determination circuit 710 can output a detection result signal 750 with a first value; when the first frequency shifter 730 and the second frequency shifter 740 are working simultaneously, the second determination circuit 710 can output a detection result signal 750 with a second value.

[0079] For example, when the value of the detection result signal 750 is a first value, the value of the first phase comparison signal 286 is a first value, and the value of the second phase comparison signal 296 is a first value, the first determination circuit 705 can output the input power supply signal; and when at least one of the value of the detection result signal 750, the value of the first phase comparison signal 286 or the value of the second phase comparison signal 296 is a second value, the first determination circuit 705 can output the input ground signal.

[0080] Fig.10 A flow chart illustrating a method of controlling activation of an RF transmit signal generating circuit is shown. Fig.10 shown in and / or with reference to Fig.10 One or more of the components described may be used with Figure 1-9 and 11 shown and / or referenced Figure 1-9 The same as the components described in 11, and / or can be implemented together with them.

[0081] Reference Fig.10 In operation 1005, the first phase comparator 285 may generate a first phase comparison signal 286 indicating whether the phase of the first oscillation signal 220 is locked by comparing the phase of the clock frequency signal and the phase of the first oscillation signal 220 as the output signal of the PLL circuit 210.

[0082] For example, when the value of the first phase comparison signal 286 remains within a set range within a set time, the first phase comparator 285 can generate a first oscillation signal 220 having a first value; when the value of the first phase comparison signal 286 does not remain within the set range within the set time, the first phase comparator 285 can generate a first oscillator signal 220 having a second value.

[0083] The oscillator (e.g., the first oscillator 225 or the second oscillator 230) in the PLL circuit 210 can generate an oscillation signal (e.g., the first oscillation signal 220 or the second oscillation signal 235) based on the output signal of the phase comparator (e.g., the first phase comparator 285 or the second phase comparator 295). The frequency divider (e.g., the first frequency divider 289 or the second frequency divider 299) in the PLL circuit 210 can reduce the frequency of the oscillation signal (e.g., the first oscillation signal 220 or the second oscillation signal 235) and send it to the phase comparator (e.g., the first phase comparator 285 or the second phase comparator 295). The loop filter (e.g., the first loop filter 283 or the second loop filter 293) in the PLL circuit 210 can remove noise contained in the output signal of the phase comparator (e.g., the first phase comparator 285).

[0084] In operation 1010 , the first phase comparator 285 may send the generated first phase comparison signal 286 to a first determination circuit (eg, the first determination circuit 280 , the first determination circuit 505 , or the first determination circuit 705 ).

[0085] In operation 1015 , the first determination circuit (eg, the first determination circuit 280 ) may control activation of at least one component included in the RF transmit signal generation circuit 205 based on whether the phase of the first oscillation signal 220 indicated in the first phase comparison signal 286 is locked.

[0086] For example, when the phase of the first oscillator signal 220 is locked, the first determination circuit (e.g., the first determination circuit 280) may activate at least one component included in the RF transmit signal generation circuit 205, and when the phase of the first oscillator signal 220 is not locked, at least one component included in the RF transmit signal generation circuit 205 may be deactivated. The component in the RF transmit signal generation circuit 205 whose activation can be controlled by the first determination circuit (e.g., the first determination circuit 280) may be an active component. For example, when the phase of the first oscillator signal 220 is locked, the first determination circuit (e.g., the first determination circuit 280) may activate at least one of an amplifier, a voltage converter, or a mixer included in the RF transmit signal generation circuit 205, and when the phase of the first oscillator signal 220 is not locked, at least one of the amplifier, a voltage converter, or a mixer included in the RF transmit signal generation circuit 205 may be deactivated.

[0087] The second phase comparator 295 in the PLL circuit 210 can generate a second phase comparison signal 296 indicating whether the phase of the second oscillation signal 235 is locked by comparing the phase of the clock frequency signal with the phase of the second oscillation signal 235 as the output signal of the PLL circuit 210. Then, the second phase comparator 295 can send the second phase comparison signal 296 to the first determination circuit (e.g., the first determination circuit 505) of the transceiver 110.

[0088] When the phase of the first oscillating signal 220 is locked and the second phase comparison signal 296 indicates that the phase of the second oscillating signal 235 is locked, the first determination circuit (e.g., the first determination circuit 505) may activate at least one component included in the RF transmit signal generation circuit 205. When at least one of the phase of the first oscillating signal 220 or the phase of the second oscillating signal 235 is not locked, the first determination circuit may deactivate at least one component included in the RF transmit signal generation circuit 205.

[0089] The second determination circuit 710 included in the communication processor 105 can detect whether the first frequency shifter 730 is running, and the first frequency shifter is configured to frequency shift the frequency of the complex signal generated in the communication processor 105 to generate a baseband transmission signal; the second determination circuit 710 can also detect whether the second frequency shifter 740 is running, and the second frequency shifter is configured to frequency shift the frequency of the modulated complex signal in the communication processor 105 to generate a baseband transmission signal. The second determination circuit 710 can send a detection result signal to the first determination circuit (e.g., the first determination circuit 705), and the detection result signal indicates whether the first frequency shifter 730 and / or the second frequency shifter 740 are running. The detection result signal can be sent through a digital interface between the communication processor 105 and the transceiver 110.

[0090] When it is detected that either the first frequency shifter 730 or the second frequency shifter 740 is operating, and the phase of the first oscillation signal 220 and the phase of the second oscillation signal 235 are both locked, the first determination circuit (e.g., the first determination circuit 705) may activate at least one component included in the RF transmission signal generation circuit 205 based on the detection result signal, the first phase comparison signal 286, and the second phase comparison signal 296. When both the first frequency shifter 730 and the second frequency shifter 740 are operating, or the phase of the first oscillation signal 220 is not locked, or the phase of the second oscillation signal 235 is not locked, the first determination circuit (e.g., the first determination circuit 705) may deactivate at least one component included in the RF transmission signal generation circuit 205 based on the detection result signal, the first phase comparison signal 286, and the second phase comparison signal 296.

[0091] The first determination circuit (eg, the first determination circuit 705 ) may control activation of at least one component in the RF transmit signal generation circuit 205 by controlling power supplied to the at least one component, or by controlling a bias voltage or a bias current of the at least one component.

[0092] In operation 1020, when at least one component in the RF transmit signal generation circuit 205 is activated in operation 1015, the RF transmit signal generation circuit 205 may generate an RF transmit signal according to the first oscillation signal 220 and the baseband transmit signal generated by the communication processor 105 of the wireless communication device 100. In operation 1025, the RF transmit signal generation circuit 205 may output the generated RF transmit signal.

[0093] The wireless communication device 100 may include a communication processor 105 and a transceiver 110 controlled by the communication processor 105 to perform wireless communication. The transceiver 110 may include at least one of the following components: a PLL circuit 210, an RF transmission signal generation circuit 205, and a first determination circuit (e.g., a first determination circuit 280); wherein the PLL circuit 210 is configured to generate a first oscillation signal 220 based on a clock frequency signal; the RF transmission signal generation circuit 205 is configured to generate an RF transmission signal based on the first oscillation signal 220 received from the PLL circuit 210 and a baseband transmission signal received from the communication processor 105; the first determination circuit is configured to receive a first phase comparison signal 286 from a first phase comparator 285 in the PLL circuit 210, and control activation of at least one component included in the RF transmission signal generation circuit 205 based on the first phase comparison signal 286, the first phase comparison signal 286 indicating whether the phase of the first oscillation signal 220 is locked.

[0094] The first phase comparator 285 can generate a first phase comparison signal 286 indicating whether the phase of the first oscillator signal 220 is locked by comparing the phase of the clock frequency signal with the phase of the first oscillator signal 220 , where the first oscillator signal 220 is the output signal of the PLL circuit 210 .

[0095] For example, when the value of the first phase comparison signal 286 remains within a set range within a set time, the first phase comparator 285 can generate a first oscillator signal 220 having a first value; and when the value of the first phase comparison signal 286 does not remain within the set range within the set time, a first oscillator signal 22 having a second value can be generated.

[0096] The oscillator (e.g., the first oscillator 225 or the second oscillator 230) in the PLL circuit 210 can generate an oscillation signal (e.g., the first oscillation signal 220 or the second oscillation signal 235) according to the output signal of the phase comparator (e.g., the first phase comparator 285 or the second phase comparator 295). The frequency divider (e.g., the first frequency divider 289 or the second frequency divider 299) in the PLL circuit 210 can reduce the frequency of the oscillation signal (e.g., the frequency of the first oscillation signal 220 or the second oscillation signal 235) and send it to the phase comparator (e.g., the first phase comparator 285 or the second phase comparator 295). The loop filter (e.g., the first loop filter 283 or the second loop filter 293) in the PLL circuit 210 can remove the noise contained in the output signal of the phase comparator (e.g., the first phase comparator 285).

[0097] The first phase comparator 285 may send the generated first phase comparison signal 286 to a first determination circuit (eg, the first determination circuit 280 , the first determination circuit 505 , or the first determination circuit 705 ).

[0098] The first determination circuit (eg, the first determination circuit 280 ) may control activation of at least one component in the RF transmit signal generation circuit 205 based on whether the phase of the first oscillation signal 220 indicated in the first phase comparison signal 286 is locked.

[0099] For example, when the phase of the first oscillating signal 220 is locked, the first determination circuit (e.g., the first determination circuit 280) may activate at least one component in the RF transmission signal generation circuit 205; and when the phase of the first oscillating signal 220 is not locked, at least one component in the RF transmission signal generation circuit 205 may be deactivated. At least one component in the RF transmission signal generation circuit 205 that can be controlled to be activated by the first determination circuit (e.g., the first determination circuit 280) may be an active component. For example, when the phase of the first oscillating signal 220 is locked, the first determination circuit (e.g., the first determination circuit 280) may activate at least one of an amplifier, a voltage converter, or a mixer included in the RF transmission signal generation circuit 205; and when the phase of the first oscillating signal 220 is not locked, at least one of the amplifier, a voltage converter, or a mixer included in the RF transmission signal generation circuit 205 may be deactivated.

[0100] The second phase comparator 295 in the PLL circuit 210 can generate a second phase comparison signal 296 by comparing the phase of the clock frequency signal with the phase of the second oscillation signal 235, and send the second phase comparison signal 296 to the first determination circuit (e.g., the first determination circuit 505) in the transceiver 110. The second oscillation signal 235 is the output signal of the PLL circuit 210, and the second phase comparison signal 296 indicates whether the phase of the second oscillation signal 235 is locked.

[0101] When the phase of the first oscillation signal 220 is locked and the second phase comparison signal 296 indicates that the phase of the second oscillation signal 235 is also locked, the first determination circuit (e.g., the first determination circuit 505) can activate at least one component in the RF transmission signal generation circuit 205; and when at least one of the phase of the first oscillation signal 220 or the phase of the second oscillation signal 235 is not locked, at least one component in the RF transmission signal generation circuit 205 can be deactivated.

[0102] The second determination circuit 710 included in the communication processor 105 can detect whether the first frequency shifter 730 is working and detect whether the second frequency shifter 740 is working, wherein the first frequency shifter 730 is configured to frequency shift the frequency of the complex signal generated in the communication processor 105 to generate a baseband transmission signal, and the second frequency shifter 740 is configured to frequency shift the frequency of the complex signal modulated in the communication processor 105 to generate a baseband transmission signal. The second determination circuit 710 can send a detection result signal to the first determination circuit (e.g., the first determination circuit 705), and the detection result signal indicates the result of detecting whether the first frequency shifter 730 and the second frequency shifter 740 are working. The detection result signal can be sent through a digital interface between the communication processor 105 and the transceiver 110.

[0103] When it is detected that any one of the first frequency shifter 730 or the second frequency shifter 730 is operating and the phase of the first oscillation signal 220 and the phase of the second oscillation signal 235 are both locked, the first determination circuit (e.g., the first determination circuit 705) may activate at least one component in the RF transmission signal generation circuit 205 based on the detection result signal, the first phase comparison signal 286 and the second phase comparison signal 296. When both the first frequency shifter 730 and the second frequency shifter 740 are operating, the phase of the first oscillation signal 220 is not locked, or the phase of the second oscillation signal 220 is not locked, the first determination circuit (e.g., the first determination circuit 705) may deactivate at least one component in the RF transmission signal generation circuit 205 based on the detection result signal, the first phase comparison signal 286 and the second phase comparison signal 296.

[0104] The first determination circuit (eg, the first determination circuit 705 ) may control activation of at least one component in the RF transmit signal generation circuit 205 by controlling power supplied to the at least one component or controlling a bias voltage or a bias current of the at least one component.

[0105] When at least one component in the RF transmit signal generation circuit 205 is activated, the RF transmit signal generation circuit 205 may generate an RF transmit signal according to the first oscillation signal 220 and a baseband transmit signal, wherein the baseband transmit signal is generated by the communication processor 105 of the wireless communication device 100. Then, the RF transmit signal generation circuit 205 may output the generated RF transmit signal in operation 1025.

[0106] Fig.11 A block diagram of an exemplary electronic device including a wireless communication device is shown. Fig.11 shown in and / or with reference to Fig.11 One or more of the components described may be used with Figure 1-10 The components shown in and / or described with reference to these figures are the same as, or can be implemented together with, these components.

[0107] Reference Fig.11, the electronic device 1101 in the network environment 1100 can communicate with the electronic device 1102 through the first network 1198 (e.g., a short-range wireless communication network), or communicate with at least one of the electronic device 1104 and the server 1108 through the second network 1199 (e.g., a long-range wireless communication network). According to an embodiment, the electronic device 1101 can communicate with the electronic device 1104 through the server 1108. According to one embodiment, the electronic device 1101 may include a processor 1120, a memory 1130, an input module 1150, a sound output module 1155, a display module 1160, an audio module 1170, a sensor module 1176, an interface 1177, a connection terminal 1178, a tactile module 1179, a camera module 1180, a power management module 1188, a battery 1189, a communication module 1190, a user identification module (SIM) 1196, or an antenna module 1197. In various embodiments, at least one of the above components (e.g., connection terminal 1178) may be omitted from electronic device 1101, or one or more other components may be added to electronic device 1101. In various embodiments, some of the components (e.g., sensor module 1176, camera module 1180, or antenna module 1197) may be integrated into one component (e.g., display module 1160).

[0108] The processor 1120 may execute, for example, software (e.g., program 1140) to control at least one other component (e.g., hardware or software component) of the electronic device 1101 connected to the processor 1120, and may perform various data processing or calculations. According to an embodiment, as at least part of the data processing or calculation, the processor 1120 may store a command or data received from another component (e.g., sensor module 1176 or communication module 1190) in the volatile memory 1132, process the command or data stored in the volatile memory 1132, and store the resultant data in the non-volatile memory 1134. According to an embodiment, the processor 1120 may include a main processor 1121 (e.g., a central processing unit (CPU) or an application processor (AP)) or an auxiliary processor 1123 (e.g., a graphics processing unit (GPU), a neural processing unit (NPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)), and the auxiliary processor 1123 may operate independently of the main processor 1121 or in conjunction with the main processor 1121. For example, when the electronic device 1101 includes a main processor 1121 and an auxiliary processor 1123, the auxiliary processor 1123 may be designed to consume less power or be dedicated to a specific function than the main processor 1121. The auxiliary processor 1123 may be implemented independently of the main processor 1121 or as part of the main processor 1121.

[0109] When the main processor 1121 is in an inactive state (e.g., a sleep state), the auxiliary processor 1123 may control the relevant functions or states of at least one of the components of the electronic device 1101 (e.g., the display device 1160, the sensor module 1176, or the communication module 1190) instead of the main processor 1121; or when the main processor 1121 is in an active state (e.g., executing an application), the auxiliary processor 1123 may control these functions or states together with the main processor 1121. According to an embodiment, the auxiliary processor 1123 (e.g., ISP or CP) may be implemented as part of another component (e.g., camera module 1180 or communication module 1190) functionally related to the auxiliary processor 1123. According to an embodiment, the auxiliary processor 1123 (e.g., NPU) may include a hardware structure specifically for artificial intelligence (AI) model processing. The AI ​​model may be generated by machine learning. Machine learning may be performed by, for example, the electronic device 1101 that executes the AI ​​model, or by a separate server (e.g., server 1108). The learning algorithm may include, but is not limited to, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning. The AI ​​model may include multiple artificial neural network layers. The artificial neural network may include, for example, a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q network, or a combination of two or more thereof, but is not limited thereto. The AI ​​model may also alternatively or additionally include a software structure in addition to a hardware structure.

[0110] The memory 1130 may store various data used by at least one component of the electronic device 1101 (e.g., the processor 1120 or the sensor module 1176). These data may include, for example, software (e.g., program 1140) and input data or output data related to related commands. The memory 1130 may include a volatile memory 1132 or a non-volatile memory 1134. The non-volatile memory 1134 may include an internal memory 1136 and / or an external memory 1138.

[0111] The program 1140 may be stored as software in the memory 1130 , and may include, for example, an operating system (OS) 1142 , middleware 1144 , or an application program 1146 .

[0112] The input module 1150 may receive a command or data to be used by another component (e.g., the processor 1120) of the electronic device 1101 from outside (e.g., a user) of the electronic device 1101. The input module 1150 may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus).

[0113] The sound output module 1155 can output sound signals to the outside of the electronic device 1101. The sound output module 1155 may include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as playing multimedia or playing recordings. The receiver can be used to answer calls. According to an embodiment, the receiver can be implemented separately from the speaker, or as a part of the speaker.

[0114] The display module 1160 can visually provide information to the outside of the electronic device 1101 (e.g., a user). The display module 1160 may include, for example, a display, a holographic device, or a projector, and a corresponding control circuit for controlling one of the display, the holographic device, and the projector. According to an embodiment, the display module 1160 may include a touch sensor for sensing a touch or a pressure sensor for measuring a touch force.

[0115] The audio module 1170 can convert sound into an electrical signal, or convert an electrical signal into sound. According to an embodiment, the audio module 1170 can obtain sound through the input module 1150, or output sound through the sound output module 1155, or output sound through an external electronic device (e.g., electronic device 1102, such as a speaker or earphone) directly connected to the electronic device 1101 or wirelessly connected.

[0116] The sensor module 1176 can detect an operating state (e.g., power supply or temperature) of the electronic device 1101 or an external environment state (e.g., a user's state) of the electronic device 1101, and generate an electrical signal or data value corresponding to the detected state. According to an embodiment, the sensor module 1176 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, an illumination sensor, or a fingerprint sensor.

[0117] The interface 1177 may support one or more specified protocols used by the electronic device 1101 to couple with an external electronic device (e.g., the electronic device 1102) directly (e.g., by wire) or wirelessly. According to an embodiment, the interface 1177 may include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0118] The connection terminal 1178 may include a connector through which the electronic device 1101 can be physically connected to an external electronic device (e.g., the electronic device 1102). According to an embodiment, the connection terminal 1178 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0119] The haptic module 1179 may convert electrical signals into mechanical stimulation (eg, vibration or motion) or electrical stimulation, which the user may sense through their sense of touch or kinesthetic sense. According to an embodiment, the haptic module 1179 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0120] The camera module 1180 may capture still images and dynamic images. According to an embodiment, the camera module 1180 may include a lens, an image sensor, an image signal processor (ISP), and a flash, and they may be one or more.

[0121] The power management module 1188 may manage power supplied to the electronic device 1101. According to an embodiment, the power management module 1188 may be implemented as, for example, at least a portion of a power management integrated circuit (PMIC).

[0122] The battery 1189 may provide power to at least one component of the electronic device 1101. According to an embodiment, the battery 1189 may include, for example, a non-rechargeable disposable battery, a rechargeable energy storage battery, or a fuel cell.

[0123] The communication module 1190 may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 1101 and an external electronic device (e.g., electronic device 1102, electronic device 1104, or server 1108), and communicate through the established communication channel. The communication module 1190 may include one or more CPs that can operate independently of the processor 1120 (e.g., AP) and support direct (e.g., wired) communication or wireless communication. According to an embodiment, the communication module 1190 may include a wireless communication module 1192 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 1194 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules can communicate with an external electronic device (e.g., electronic device 1104) via a first network 1198 (e.g., a short-range communication network such as Bluetooth technology, Wireless Fidelity (Wi-Fi) Direct, or Infrared Data Association (IrDA)) or a second network 1199 (e.g., a long-range communication network such as a traditional cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN))). These different types of communication modules can be implemented as a single component (e.g., a single chip) or as multiple components separated from each other (e.g., multiple chips). The wireless communication module 1192 can identify and authenticate the electronic device 1101 in a communication network (e.g., first network 1198 or second network 1199) using subscriber information (e.g., International Mobile Subscriber Identity (IMSI)) stored in the SIM 1196.

[0124] After supporting 4G networks, the wireless communication module 1192 can also support 5G networks and next-generation communication technologies (e.g., new radio (NR) access technology). NR access technology can support enhanced mobile broadband (eMBB), massive machine type communication (mMTC), or ultra-reliable low-latency communication (URLLC). The wireless communication module 1192 can support high frequency bands (e.g., millimeter wave bands) to achieve, for example, high data transmission rates. The wireless communication module 1192 can support a variety of technologies to ensure performance in high frequency bands, such as beamforming, massive multiple-input multiple-output (MIMO), full-dimensional MIMO (FD-MIMO), antenna arrays, analog beamforming, or massive antennas. The wireless communication module 1192 can support various requirements specified in the electronic device 1101, an external electronic device (e.g., electronic device 1104), or a network system (e.g., a second network 1199). According to an embodiment, the wireless communication module 1192 may support the peak data rate of eMBB (e.g., 20 Gbps or higher), support the loss coverage of mMTC (e.g., 164 dB or lower), or support the U-plane latency of URLLC (e.g., 0.5 ms or less for downlink (DL) and uplink (UL) respectively, or 1 ms or less for round trip).

[0125] The antenna module 1197 may transmit a signal or power to the outside of the electronic device 1101 (e.g., an external electronic device), or receive a signal or power from the outside of the electronic device 1101. According to an embodiment, the antenna module 1197 may include an antenna having a radiating element including a conductive material or a conductive pattern formed in or on a substrate (e.g., a printed circuit board (PCB)). According to an embodiment, the antenna module 1197 may include a plurality of antennas (e.g., an antenna array). In this case, for example, the communication module 1190 may select at least one antenna suitable for a communication scheme used in a communication network from a plurality of antennas, and the communication network may be, for example, a first network 1198 or a second network 1199. A signal or power may be transmitted or received between the communication module 1190 and the external electronic device through at least one selected antenna. According to an embodiment, in addition to the radiating element, other components (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed in the antenna module 1197 as a part.

[0126] According to various embodiments, the antenna module 1197 may be formed with a millimeter wave antenna module. According to an embodiment, the millimeter wave antenna module may include a PCB, an RFIC capable of supporting a specified high frequency band (e.g., a millimeter wave band), and a plurality of antennas (e.g., an antenna array) capable of sending or receiving signals within the specified high frequency band, wherein the RFIC is located on a first surface (e.g., bottom surface) of the PCB or adjacent to the first surface of the PCB, and the plurality of antennas are arranged on a second surface of the PCB or adjacent to the second surface of the PCB.

[0127] At least some of the above components can be interconnected and exchange signals (e.g., commands and data) with each other through an inter-peripheral communication scheme (e.g., a bus, general purpose input and output (GPIO), a serial peripheral interface (SPI), or a mobile industry processor interface (MIPI)).

[0128] According to an embodiment, commands and data may be sent and received between the electronic device 1101 and an external electronic device (e.g., the electronic device 1104) via the server 1108 connected through the second network 1199. Each external electronic device (e.g., the electronic devices 1102 and 1104) may be a device of the same type as the electronic device 1101, or may be a device of a different type from the electronic device 1101. According to an embodiment, all or part of the operations to be performed by the electronic device 1101 may be performed by one or more external electronic devices (e.g., the electronic devices 1102 and 1104, and the server 1108). For example, if the electronic device 1101 needs to automatically perform a function or service, or respond to a request from a user or another device, the electronic device 1101 may request one or more external electronic devices to perform at least a part of the function or service instead of performing the function or service, or the electronic device 1101 may request one or more external electronic devices to perform at least a part of the function or service in addition to performing the function or service. One or more external electronic devices that receive the request may perform at least part of the requested function or service, or perform additional functions or additional services related to the request, and may send the execution result to the electronic device 1101. The electronic device 1101 may further process the result or not process it, and then use the result as at least a partial response to the request. To this end, technologies such as cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device 1101 may use technologies such as distributed computing or MEC to provide ultra-low latency services. In an embodiment, the external electronic device (e.g., electronic device 1104) may include an Internet of Things (IoT) device. The server 1108 may be an intelligent server using machine learning and / or a neural network. According to an embodiment, the external electronic device (e.g., electronic device 1104) or the server 1108 may be included in the second network 1199. The electronic device 1101 may be applied to intelligent services (e.g., smart homes, smart cities, smart cars, or healthcare) based on 5G communication technology or IoT-related technologies.

[0129] According to various embodiments described in the present disclosure, the electronic device may be any of a variety of types. As non-limiting examples, the electronic device may include, but is not limited to: portable communication devices (such as smart phones, etc.), computing devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and household appliances, etc. However, the electronic device is not limited to the above examples.

[0130] It should be understood that the various embodiments of the present disclosure and the terms used therein are not intended to limit the technical features described in the present disclosure to specific embodiments, but include various variations, equivalent embodiments or alternative embodiments for the corresponding embodiments. When describing in conjunction with the accompanying drawings, the same reference numerals may be used for similar or related components. It should be understood that, unless otherwise clearly indicated by the relevant context, the singular form of a word corresponding to a certain item may include one or more styles of the item. In the phrases of "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C" and "A, B or C" used herein, each may include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as "first", "second", "initial" or "next" or "subsequent" are used only to distinguish a component from other components discussed, and do not limit the component in other aspects (such as importance or order). It should be understood that if an element (e.g., a first element) is mentioned as being "coupled to," "coupled to," "connected to," or "connected to" another element (e.g., a second element) without the terms "operably" or "communicatively," the element may be coupled to the other element directly (e.g., via a wire), wirelessly, or through a third element.

[0131] When describing various embodiments of the present disclosure, the term "module" may include units implemented in hardware, software, firmware, or any combination thereof, and may be used interchangeably with other terms (e.g., "logic," "logic block," "portion," or "circuit"). A module may be a single integral component, or the smallest unit or part thereof, for performing one or more functions. For example, according to an embodiment, a module may be implemented in the form of an application specific integrated circuit (ASIC).

[0132] The various embodiments provided by the present disclosure may be implemented as software (e.g., program 1140), which includes one or more instructions stored in a storage medium (e.g., internal memory 1136 or external memory 1138) that can be read by a machine (e.g., electronic device 1101). For example, a processor (e.g., processor 1120) of a machine (e.g., electronic device 1101) may call and execute at least one of the one or more instructions stored in the storage medium. This enables the machine to perform at least one function according to at least one of the called instructions. One or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The machine-readable storage medium may be a non-volatile storage medium. Here, a "non-volatile" storage medium is a tangible device that does not include signals (e.g., electromagnetic waves), but this term does not distinguish whether data is semi-permanently stored or temporarily stored in a storage medium.

[0133] According to various embodiments, the method provided by the embodiments of the present disclosure may be included in and provided in a computer program product. The computer program product can be traded as a commodity between a seller and a buyer. The computer program product can be distributed (e.g., downloaded or uploaded) in the form of a machine-readable storage medium (e.g., a read-only compact disk memory (CD-ROM)), or distributed online through an application store (e.g., PlayStore) or directly between two user devices (e.g., smartphones). If distributed online, at least a portion of the computer program product may be temporarily generated or at least temporarily stored in a machine-readable storage medium, such as a memory of a manufacturer's server, a server of an application store, or a relay server.

[0134] According to various embodiments, each component (e.g., module or program) in the above-mentioned components may include a single entity or multiple entities, and some entities in the multiple entities may be respectively arranged in different components. According to various embodiments, one or more of the above-mentioned components or operations may be omitted, or one or more other components or operations may be added. In addition or as an alternative, multiple components (e.g., module or program) may be integrated into a single component. In this case, according to various embodiments, the integrated component may still be used in the same or similar manner as the manner in which these functions are performed by the corresponding components before the integration when performing one or more functions of each of the multiple components. According to various embodiments, the operations performed by modules, programs or other components may be performed sequentially, in parallel, repeatedly or heuristically, or one or more of these operations may be performed or omitted in different orders, or one or more other operations may be added.

Claims

1. A wireless communication device (100), comprising: Communications processor (105); as well as a transceiver (110) configured to be controlled by the communication processor (105) to perform wireless communication, Wherein, the transceiver (110) comprises: A phase locked loop (PLL) circuit (210) configured to generate a first oscillation signal based on a clock frequency signal; A radio frequency (RF) transmission signal generating circuit (205) configured to generate an RF transmission signal based on the first oscillation signal (220) received from the PLL circuit (210) and a baseband transmission signal received from the communication processor (105); and A first determination circuit (280) is configured to receive a first phase comparison signal (286) from a first phase comparator (285) included in the PLL circuit (210), and to control activation of at least one component included in the RF transmission signal generation circuit (205) based on the first phase comparison signal (286), wherein the first phase comparison signal (286) indicates whether the phase of the first oscillation signal (220) is locked.

2. The wireless communication device (100) according to claim 1, wherein: The first determination circuit (280) is further configured to: In response to the phase of the first oscillation signal (220) being locked, activating at least one component included in the RF transmission signal generating circuit (205); as well as In response to the phase of the first oscillating signal (220) not being locked, at least one component included in the RF transmit signal generating circuit (205) is deactivated.

3. The wireless communication device (100) according to claim 1 or 2, wherein: The first phase comparator (285) is configured as: In response to the phase difference between the clock frequency signal and the first oscillation signal (220) being maintained within a set range within a set time, outputting the first phase comparison signal having a first value; In response to the phase difference between the clock frequency signal and the first oscillation signal (220) not being maintained within a set range within a set time, the first phase comparison signal having a second value is output.

4. The wireless communication device (100) according to any one of claims 1 to 3, wherein: The first determination circuit (280) is further configured to: In response to the phase of the first oscillation signal (220) being locked, activating at least one of an amplifier, a voltage converter or a mixer included in the RF transmission signal generating circuit (205); as well as In response to the phase of the first oscillation signal (220) not being locked, at least one of an amplifier, a voltage converter or a mixer included in the RF transmission signal generation circuit (205) is deactivated.

5. The wireless communication device (100) according to any one of claims 1 to 4, wherein: The PLL circuit (210) is further configured as: generating a second oscillation signal (235) based on the clock frequency signal, Wherein, the wireless communication device (100) further comprises: an RF reception signal processing circuit (215) configured to generate a baseband reception signal based on the second oscillation signal (235) received from the PLL circuit (210) and an RF signal received from the outside; Wherein, the first determination circuit (280) is further configured as follows: receiving a second phase comparison signal from a second phase comparator (295) included in the PLL circuit (210), the second phase comparison signal indicating whether the phase of the second oscillation signal (235) is locked; and Based on the first phase comparison signal (286) and the second phase comparison signal (296), activation of at least one component included in the RF transmit signal generation circuit (205) is controlled.

6. The wireless communication device (100) according to claim 5, wherein: The first determination circuit (280) is further configured to: In response to the first oscillation signal (220) and the second oscillation signal (235) being phase locked, activating at least one component included in the RF transmission signal generating circuit (205); and In response to at least one of the first oscillating signal (220) and the second oscillating signal (235) being out of phase, at least one component included in the RF transmit signal generating circuit (205) is deactivated.

7. The wireless communication device (100) according to claim 5, wherein: The communication processor (105) further comprises: a complex signal generator (725) configured to generate a complex signal; A first frequency shifter (730) configured to frequency shift the frequency of the complex signal to generate the baseband transmission signal; a modulator (735) configured to modulate the complex signal; a second frequency shifter (740) configured to frequency shift the frequency of the modulated complex signal to generate the baseband transmission signal; and a second determination circuit (710) configured to detect whether the first frequency shifter is working and whether the second frequency shifter is working, and to send a detection result signal indicating the detection result to the first determination circuit (705), Wherein, the first determination circuit (280) is further configured as follows: In response to either one of the first frequency shifter (730) and the second frequency shifter (740) operating and the phases of the first oscillation signal (220) and the second oscillation signal (235) being locked, at least one component included in the RF transmission signal generating circuit (205) is activated.

8. The wireless communication device (100) according to claim 7, wherein: The detection result signal is sent to the first determination circuit (705) via a digital interface (745) for connecting the communication processor (105) and the transceiver (110).

9. The wireless communication device (100) according to any one of claims 1 to 8, wherein: The PLL circuit (210) further comprises: an oscillator (225) configured to generate the first oscillation signal (220) based on the output signal of the first phase comparator (285); A frequency divider (289) configured to reduce the frequency of the first oscillation signal (220) and send the first oscillation signal (220) with the reduced frequency to the first phase comparator (285); and A loop filter (283) is configured to remove noise contained in the output signal of the first phase comparator (285).

10. The wireless communication device (100) according to any one of claims 1 to 9, wherein: The first determination circuit (280) is further configured to: controlling power supplied to the at least one component; or The activation of the at least one component is controlled by controlling a bias voltage or a bias current provided to the at least one component.

11. A method of controlling activation of a radio frequency (RF) transmission signal generating circuit included in a transceiver (110) for performing wireless communication of a wireless communication device (100), the method comprising: A first phase comparator (285) in a phase-locked loop (PLL) circuit (210) in the transceiver (110) compares the phase of a clock frequency signal with the phase of a first oscillation signal (220), and generates a first phase comparison signal, wherein the first oscillation signal (220) is an output signal of the PLL circuit (210), and the first phase comparison signal indicates whether the phase of the first oscillation signal (220) is locked; The first phase comparator (285) sends the first phase comparison signal to a first determination circuit (280) of the transceiver (110); controlling, by the first determination circuit (280), activation of at least one component included in the RF transmission signal generation circuit (205) based on whether the phase of the first oscillation signal (220) indicated by the first phase comparison signal is locked; In response to the at least one component being activated, the RF transmit signal generation circuit (205) generates an RF transmit signal based on the first oscillation signal (220) and a baseband transmit signal generated by a communication processor (105) of the wireless communication device (100); and The generated RF transmission signal is outputted by the RF transmission signal generating circuit (205).

12. The method according to claim 11, wherein: Controlling activation of the at least one component comprises: In response to the phase of the first oscillation signal (220) being locked, activating at least one component included in the RF transmission signal generation circuit (205) by the first determination circuit (280); and In response to the phase of the first oscillating signal (220) not being locked, at least one component included in the RF transmit signal generating circuit (205) is deactivated.

13. The method according to claim 11 or 12, wherein: Generating the first phase comparison signal comprises: generating the first oscillation signal (220) having a first value in response to the value of the first phase comparison signal being maintained within a set range within a set time; and In response to the value of the first phase comparison signal not being maintained within a set range within a set time, the first oscillation signal having a second value is generated (220).

14. The method according to claim 11 or 12, wherein: Controlling activation of the at least one component comprises: In response to the phase of the first oscillation signal (220) being locked, at least one of an amplifier, a voltage converter or a mixer included in the RF transmission signal generating circuit (205) is activated by the first determination circuit (280); and In response to the phase of the first oscillation signal (220) not being locked, at least one of an amplifier, a voltage converter or a mixer included in the RF transmission signal generation circuit (205) is deactivated.

15. A non-volatile computer-readable storage medium, used for storing instructions, which, when executed by a processor, causes the processor to execute the method according to any one of claims 11 to 14.

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