Core particle testing method and device and chip

Abstract

The embodiment of the invention discloses a core particle testing method and device and a chip, relates to the technical field of semiconductor testing, and can improve the testing efficiency of core particles to a certain extent. The method comprises the following steps: determining a critical path in a current to-be-detected core particle; the key path is a part of paths in all paths formed by a circuit between an input port and an output port of the core particle, and the key path is used for testing an item to be tested; and testing the to-be-tested item based on the key path. The core particle comprises at least one critical path which is arranged on the packaging substrate, the critical path is a part of paths in all paths formed by a circuit between an input port and an output port of the core particle, and the critical path is configured to be used for testing a test item required in a core particle test standard specification in a test stage. The method and the device are suitable for various test scenes of the core particles and the chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing technology, and in particular to a core particle testing method, device and chip. Background Art

[0002] In modern semiconductor technology, the chip modularization (Chiplets, it should be noted that the meaning is different in different contexts, and when used as a noun, it is generally translated as small chips or core particles) technology, which is a continuation of Moore's Law, is increasingly widely used, especially in high-performance computing, artificial intelligence, and data centers. This technology breaks through the limitations of traditional monolithic integration by integrating multiple dies (dies, also translated as grains in Chinese) of different process nodes and materials, thereby achieving higher performance and lower costs. However, with the increasing complexity of modular system-on-a-chip (SOC) products, the testing process faces unprecedented challenges.

[0003] Specifically, because chiplets (sometimes also called chips) involve the integration of multiple bare dies, their testing process is more complicated than that of traditional single chips. In addition to conventional pin testing and final testing, multiple testing links such as dielectric layer testing, mid-stage testing, and system-level testing are also required. In relevant test methods or test specifications, it is often necessary to traverse and scan each pin, which takes a long time to test. Therefore, the problem of chiplet testing efficiency needs to be solved urgently, and the existing test process is difficult to meet the needs of efficient testing. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a core particle testing method, a core particle and a chip, which can improve the testing efficiency of the core particle to a certain extent.

[0005] In a first aspect, an embodiment of the present invention provides a chip testing method, the method comprising: determining a critical path in the current chip to be tested; the critical path is a partial path among all paths formed by the circuit from the input port to the output port of the chip, and the critical path is used to test the item to be tested; and testing the item to be tested based on the critical path.

[0006] According to an embodiment of the present invention, determining the critical path in the current core particle to be tested includes: determining a path preset inside the core particle for testing the item to be tested as the critical path.

[0007] According to an embodiment of the present invention, determining the critical path in the current chiplet to be tested includes: determining a partial path in an existing circuit between an input port and an output port of the chiplet as the critical path.

[0008] According to an embodiment of the present invention, determining a partial path in an existing circuit from an input port to an output port of the core particle as the critical path includes: Screening out the critical path according to the location of the conductive bumps in the existing circuit and the distance of the package pins; or, Find the weak points in the existing circuit according to the retrospective design, and determine the critical path based on the weak points; or, All paths formed by the circuit between the input port and the output port of the current chip to be tested are tested, and the critical path is determined according to the test result.

[0009] According to an embodiment of the present invention, the step of testing the item to be tested based on the critical path includes: Based on the critical path, executing a test item test on the current chip to be tested; and / or Based on the critical path, the remaining core particles of the same batch as the current core particle to be tested are tested for the items to be tested.

[0010] According to one embodiment of the present invention, the testing of the item to be tested based on the critical path includes: testing based on the worst path in the critical path to verify whether the worst path meets the design standard specifications; wherein the worst path is the path with the longest physical distance or the worst performance.

[0011] According to one embodiment of the present invention, the testing of the item to be tested based on the critical path includes: testing based on the best path in the critical path to verify whether the best path meets the design standard specifications; wherein the best path is the path with the shortest physical distance or the best performance.

[0012] According to one embodiment of the present invention, the testing of the item to be tested based on the critical path includes: testing based on a typical path in the critical path to verify whether the typical path meets the design standard specifications; wherein the typical path is a path whose physical distance or performance is between the worst path and the best path, the worst path is the path with the longest physical distance or the worst performance, and the best path is the path with the shortest physical distance or the best performance.

[0013] According to an embodiment of the present invention, after verifying whether the worst path meets the design standard specification, it also includes: if the worst path meets the design standard specification, determining whether the typical path or the best path in the critical path meets the design standard specification.

[0014] In a second aspect, an embodiment of the present invention also provides a chip, comprising: at least one critical path, arranged on a packaging substrate, and the critical path is a partial path of all paths formed by the circuit from the input port to the output port of the chip, and the critical path is configured to be used for testing test items required in the chip test standard specification during the testing phase.

[0015] According to an embodiment of the present invention, the critical path is a path preset inside the core particle for testing the item to be tested; or, the critical path is a partial path determined in an existing circuit between an input port and an output port of the core particle.

[0016] According to one embodiment of the present invention, the critical path includes a worst path, an optimal path, and a typical path between the worst path and the best path; wherein the worst path is a path with the longest physical distance or the worst performance, the best path is a path with the shortest physical distance or the best performance, and the physical distance or performance of the typical path is between the worst path and the best path.

[0017] According to an embodiment of the present invention, the critical path configuration is used for testing any one of the test items of protocol layer testing, data path layer testing and physical layer testing during the testing phase.

[0018] According to an embodiment of the present invention, the critical path is arranged between logic circuits of the core particle; and / or, The critical path is between the circuit and the register; and / or, The critical path is arranged between different functional module circuits of the packaged die; wherein the different functional module circuits include: one or more of an analog circuit, a storage circuit, a radio frequency circuit, an interface circuit and a protection circuit.

[0019] In a third aspect, the present invention also provides a chip in an embodiment, comprising: at least two interconnected core particles as described in any one of the second aspects.

[0020] The core particle testing method, core particle and chip provided by the embodiment of the present invention determine the critical path in the current core particle to be tested during the testing phase, and test the project to be tested on the crystal particle in a targeted manner based on the critical path, replacing the traditional pin-by-pin scanning test scheme. Since the critical path is a partial path among all the paths formed by the circuit from the input port to the output port of the core particle, testing the crystal particle based on the critical path greatly reduces the test time and can improve the test efficiency of the core particle to a certain extent. Furthermore, for the entire chip, testing based on the determined critical path can replace the traditional pin-by-pin scanning test scheme, which can improve the test efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a schematic block diagram of the structure of a conventional chiplet embodiment; Figure 2 A schematic diagram of a flow chart of an embodiment of a core particle testing method provided by the present invention; Figure 3 A schematic flow chart of another embodiment of the core particle testing method provided by the present invention; Figure 4 A schematic flow chart of another embodiment of the core particle testing method provided by the present invention; Figure 5 A schematic flow chart of another embodiment of the core particle testing method provided by the present invention; Figure 6 A schematic block diagram of the structure of a core particle according to an embodiment of the present invention; Figure 7 A schematic block diagram of the structure of another embodiment of the core particle provided by the present invention; Figures 8 to 10 A schematic diagram comparing the test results of a core particle test method according to an embodiment of the present invention with those of a traditional test method; Fig.11 A schematic block diagram of the structure of a 3D chip according to an embodiment of the present invention; Fig.12 The structure and test schematic diagram of a conventional core particle test method based on a scan chain are shown in FIG. Fig.13 A schematic diagram of a key path structure and a test in an embodiment of a core particle testing method provided in an embodiment of the present invention; Fig.14 A key path structure and test schematic diagram of another embodiment of the core particle testing method provided in an embodiment of the present invention; Fig.15 A critical path structure and test schematic diagram of another embodiment of the core particle testing method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] See also Figure 1 As shown in the figure, in the relevant chiplet test specifications or technologies, it is often necessary to traverse and scan each pin of the chiplet to complete the reliability, electromagnetic compatibility and system testing of the product. In addition, when testing chips based on chiplets technology, it is necessary to test, verify and confirm multiple chiplets (also called small chips, sometimes directly referred to as chips in the industry). This traditional solution of scanning and testing pin by pin or scan chain by scan chain not only has low test efficiency, but also increases test costs.

[0026] To this end, the chip testing method provided in the embodiment of the present application determines the critical path in the current chip to be tested, at least for reliability, electromagnetic compatibility and system testing. During the testing phase, only the test items in the chip testing standard specification are executed for the critical path, replacing the traditional pin-by-pin or scan chain-by-scan testing solution, thereby improving the testing efficiency of the chip and the chip.

[0027] See also Figures 2 to 4 As shown, the core particle testing method provided in the embodiment of the present application includes: S110, determining a critical path in the current chip to be tested; the critical path is a partial path among all paths formed by the circuit from the input port to the output port of the chip 100, and the critical path is used to test the item to be tested.

[0028] It should be noted that in chip design and testing, the critical path refers to the most critical signal transmission path that affects chip performance and power consumption during chip operation. For chiplets (i.e., modular chips composed of multiple small chips), the testing and verification of the critical path is particularly important.

[0029] Among them, the determination of the critical path in this application needs to consider at least the following aspects: reliability testing, ensuring that the setting of the critical path can reflect the stability of the chip under various operating conditions. Electromagnetic compatibility testing, the setting of the critical path should include paths that may be subject to external electromagnetic interference, so that it can be used to detect the anti-interference ability of the chip during the testing phase. System testing, the critical path should cover the main functional modules of the chip to ensure that the test results can represent or reflect the performance of the entire chip.

[0030] S120: Testing the item to be tested based on the critical path.

[0031] Among them, the items to be tested include test items in the chip test standard specifications, such as some of the test items listed in Table 1 below. It should be noted that the examples here are mainly to help understanding and are not intended to limit specific items to be tested.

[0032]

[0033] In step S120, the test equipment can be connected, and according to the item to be tested, a specific signal can be injected into the critical path through the input port to simulate the actual working state, and the signal response can be monitored at the output port and the output result can be recorded to evaluate the function and performance of the item to be tested.

[0034] The core particle testing method provided by the embodiment of the present invention determines the critical path in the core particle to be tested during the testing phase, and tests the project to be tested on the crystal particle in a targeted manner based on the critical path, replacing the traditional pin-by-pin scanning test solution. Since the critical path is a partial path among all the paths formed by the circuit from the input port to the output port of the core particle, testing the crystal particle based on the critical path greatly reduces the testing time and can improve the testing efficiency of the core particle to a certain extent. Furthermore, for the entire chip, testing based on the determined critical path can replace the traditional pin-by-pin or scan chain-by-scan testing solution, optimize the core particle testing process, and improve the chip testing efficiency.

[0035] Specifically, the critical path is a path preset inside the core particle for testing the item to be tested; therefore, in some embodiments, determining the critical path in the current core particle to be tested includes: determining the path preset inside the core particle for testing the item to be tested as the critical path. The critical path is specifically a preset path corresponding to the item to be tested of the core particle in the test phase during the core particle design phase; the preset path can be an additional path specifically used for testing, such as Fig.15 As shown, it can also be formed by modifying part of the internal circuit in the path formed by the existing circuit, such as Fig.13 Or as shown in 14, please see below for more detailed description.

[0036] In the case where a critical path is preset in a core particle during the design phase, determining the critical path in the core particle to be tested currently includes: determining the path preset in the core particle for testing the item to be tested as the critical path.

[0037] In the case where no critical path is reserved in the design stage, in some embodiments, the critical path is a partial path determined in the existing circuit between the input port and the output port of the chip. That is, the determination of the critical path in the current chip to be tested includes: determining the partial path in the existing circuit between the input port and the output port of the chip as the critical path. Specifically, the critical path can be specifically selected according to the location of the conductive bumps in the existing circuit and the distance of the package pins in the post-silicon stage; or, according to the retrospective design, the weak points in the existing circuit are found and the critical path is determined based on the weak points; or, in the chip testing stage, all paths formed by the circuit between the input port and the output port of the current chip to be tested are tested, and the critical path is determined according to the test results.

[0038] Specifically, the critical path can be reserved and set in the chip design stage. The critical path can be pre-designed according to the test items and the technical design concept of the shortest or longest path and the best or worst performance. Fig.12 As shown in the figure, in a typical chip test method, the chip is tested by scanning the traditional scan chain line by line. Fig.13 As shown, in some embodiments of the present invention, the critical path is pre-designed based on the technical design concept of the shortest or longest path, the best or worst performance, and the high or low workload. It can be achieved by adjusting the local circuit inside the core particle. The adjustment is determined according to the test purpose or test item. For example, for reliability tests such as ESD, LU, and aging, the parameters of an original internal circuit are changed, such as reducing the device parameters, etc., to form a critical path. Such a critical path can be regarded as the worst path. After adjusting the internal local circuit, for example, the replaced internal circuit is Fig.13 If the internal circuit 2 in the circuit is internal, then the path (RX2-TX2) with the internal circuit 2 is the critical path. Then, in the test phase, the test can be performed based on this critical path, and the remaining links can be tested as needed. Of course, additional tests can be performed as needed, replacing the traditional scan chain scan test solution and optimizing the test process, thereby improving test efficiency and reducing test costs.

[0039] See also Fig.14 In some embodiments of the present invention, the critical path can be realized by changing the length of the logic path or the length of the routing. The specific adjustment is also determined according to the test purpose or test item. For example, for reliability tests such as ESD, LU, and aging, the original logic is lengthened, and the length of the physical routing can be extended to form a critical path. Such a critical path can be regarded as the worst path. After adjusting the length of the internal logic path, for example, replacing Fig.12The internal circuit shown is Fig.14 If it is realized by the three internal circuits in, then the path with the three internal circuits is the critical path (RX2-TX2). Then, in the test phase, the test is based on this critical path, and the remaining links can be untested as needed. Of course, additional tests can be performed as needed, thereby improving test efficiency and reducing test costs.

[0040] See also Fig.15 In some embodiments of the present invention, the critical path can be implemented by adding a physical link structure that was not originally in the core particle as a special critical path. For example, a physical link (RXCritical Path-TXCritical Path) that adapts to the test requirements is arranged, and the internal circuits and physical routing in the link are specifically set with parameters for testing in the subsequent test phase. The specific adjustment is also determined according to the test purpose or test item. Then, in the test phase, the test can be carried out based on this critical path, and the remaining links can be tested as needed. Of course, additional tests can be carried out as needed, thereby improving the test efficiency and reducing the test cost.

[0041] If the critical path is not considered in the chip design phase, the critical path can be found by testing at least one chip in the test phase. Then, based on the found critical path, the remaining chips are tested for corresponding test items.

[0042] In this embodiment, by testing the test items based on the critical path, the workload of the core particle or chip testing can be reduced, thereby saving the testing time and improving the testing efficiency.

[0043] For the testing of each item to be tested, the testing sequence can be executed as needed without specific limitation.

[0044] The critical path includes: a worst path, an optimal path, and a typical path between the worst path and the optimal path.

[0045] Traditional chiplet testing methods usually rely on pin-by-pin scanning testing, which is not only inefficient, but also significantly increases testing costs when testing multiple chips. Especially in chips based on chiplet technology, as the number of chips increases, the pin-by-pin scanning method leads to extended testing time and waste of resources. Although the traditional scan chain line-by-line scanning test method has improved, it also leads to extended side test time and low efficiency.

[0046] To this end, the present application optimizes the test process based on the proposed critical path, specifically: the test of the item to be tested based on the critical path includes: A test is performed based on the worst path in the critical path to verify whether the worst path meets the design standard specification.

[0047] In this embodiment, after determining the critical path, the function and performance test of the project to be tested is performed based on the path. Specifically, the test is performed based on the worst path in the critical path to verify whether the worst path meets the design standard specifications. If the test results verify that the core can still work normally and meet the expected functions and performance even under the most unfavorable conditions, the performance of other paths can be derived, thereby reducing the need to test all paths one by one and improving the overall test efficiency.

[0048] Of course, during the test process, after the worst path test is completed, other paths can be selected for targeted testing. For example, after completing the verification of the worst path, the best path can be tested next. The best path can also be tested according to test needs, for example, to verify the performance of the chip under ideal conditions.

[0049] In some other embodiments, the testing of the items to be tested based on the critical path includes: testing based on the best path in the critical path to verify whether the best path meets the design standard specification. The best path includes the key functional modules of the core particle, such as the critical path composed of the processor, memory, input and output interface, etc., which is the path with the best performance for the signal from one input end to the output end of the chip, or from one trigger to another trigger.

[0050] For example, see again Figures 13 to 15 For the worst path, as shown in the figure, the physical path can be extended or the internal circuit performance can be deteriorated. For the formation of the best path, the physical path can be shortened, the number of logic units can be reduced, or the drive can be strengthened or the parasitics can be reduced, thereby improving the transmission speed and other performance, so as to understand the process characteristics, accelerate DTCO (design process co-optimization) and product performance, and thus accelerate the iteration speed of chip reliability improvement.

[0051] In this embodiment, a performance test is performed based on the best path in the critical path. The performance test includes key performance indicators of the core particles, such as power consumption, speed, stability, etc. For example, the power consumption of the core particles under different workloads, the maximum operating speed of the processor, the stability of the system, etc. are tested to ensure that all performance indicators meet the design standards and specifications. If the test results show that the best path meets the design standards and specifications, it can be confirmed that the design of the core particles meets the expected requirements. The remaining core particles can also be tested in a targeted manner according to the best path to reduce the testing cost caused by scanning pins one by one.

[0052] In other embodiments, the testing of the item to be tested based on the critical path includes: testing based on a typical path in the critical path to verify whether the typical path meets the design standard specification.

[0053] In addition, it should be noted that the test order of the best path, the worst path, and the typical path is not limited in this embodiment, and the test can be performed as needed.

[0054] Of course, in some embodiments, the typical path can be tested after the worst path, specifically, after verifying whether the worst path meets the design standard specifications, it also includes: if the worst path meets the design standard specifications, then determining that the typical path meets the design standard specifications; the critical path includes: a typical path (Normal path).

[0055] Specifically, the critical path refers to the signal transmission path that has the greatest impact on chip performance and power consumption during chip operation. These paths usually include clock signal paths, data transmission paths, etc.

[0056] Specifically, the worst path refers to the path with the worst performance or the longest distance among all possible signal transmission paths. This path is usually caused by factors such as circuit delay, load characteristics, and parasitic effects. When looking for the worst path, you can use simulation tools or actual test equipment to verify based on the worst path in the critical path, check the signal transmission time, signal integrity, power consumption and other parameters of the path, and ensure that it meets the design standard specifications.

[0057] In some embodiments, by testing the worst path, it can be determined whether the core particle performance meets the requirements. Of course, by testing the best path and the worst path, the process characteristics can also be understood.

[0058] The typical path is the path with average performance among all possible signal transmission paths. This path is usually the common path in the design and does not include extreme cases.

[0059] In this application, if the worst path has met the design standard specifications, it can be inferred that the typical path also meets the design standard specifications. This is because the performance of the typical path is usually better than or equal to the worst path. In this way, during the chip test, after the test item is tested for the worst path, the test can be ended, thereby reducing the test time and improving the test efficiency.

[0060] When all critical paths meet the design standard specifications after testing, it can be basically determined whether the chip is good. In this way, by determining the critical path, it is possible to effectively verify whether the critical path in the chiplets meets the design standard specifications, saving testing time and cost.

[0061] As mentioned above, there are two situations when testing a chip. One is that a critical path is reserved in the chip structure during the chip design phase to form a critical path. Figure 6 ,Considering the setting of critical paths in the design stage, various critical paths can be considered according to the actual situation in the chip, such as Figure 6 The worst path between the two red pins can be path a indicated by the green line or path b indicated by the brown line. Figure 7 , a stricter worst-case path can be designed, for example, Figure 7 The path c between the red pin in the lower right corner and the purple pin in the lower right corner. For the best path, you can choose the path d formed by several pins similar to the one above Die5. You can see that the two paths that make up d are relatively short. According to product requirements, you can conduct a preliminary test on the best performance.

[0062] Another is that during the chip design phase, critical paths are not reserved in its structure for subsequent testing.

[0063] For the second case, it is necessary to find an equivalent critical path during testing. Specifically, the critical path is a partial path determined in the existing circuit from the input port to the output port of the chip, including: in the post-silicon validation stage, according to the location of the conductive bumps and the distance of the package pins, screen out the expected critical path.

[0064] In general, the worst paths are usually those with the longest path delay, close to the edge, and prone to interference.

[0065] In the post-silicon stage, the critical path is screened out according to the location of the conductive bumps and the distance of the package pins, including: determining the location of all conductive bumps on the core particle; the conductive bumps are the connection points between the core particle and the package pins.

[0066] Get the distance from each conductive bump to the package pin; select the path with the longest distance from the conductive bump to the package pin as the worst path in the critical path. Of course, the longer the path, the longer the corresponding signal transmission delay. Select the path with the shortest distance from the conductive bump to the package pin as the best path in the critical path. The best path usually refers to the path with the shortest signal transmission delay or the shortest path. Select the path between the shortest path and the best path as the typical path.

[0067] Since the location of the conductive bumps and the distance of the package pins will affect the quality and delay of signal transmission, specifically, in the post-silicon stage, according to the location of the conductive bumps and the distance of the package pins, the key paths that meet the expectations are screened out, including: post-silicon processing of the chip, including conductive bump detection and package pin inspection. According to the location of the conductive bumps and the distance of the package pins, a candidate path set is generated. The candidate path set is analyzed and evaluated to select the key path that meets the expectations. The selected key path is used for chip (general) testing to verify the performance and reliability of the chip.

[0068] Specifically, the step of searching for weak points in the existing circuit according to the traceable design and determining the critical path based on the weak points may include: reverse engineering the design drawings of the chip to find the die and connection points where the weak points may exist. Based on the reverse engineering results, the die and connection points where the weak points may exist are determined to generate a candidate path set. The candidate path set is analyzed and evaluated to select the critical path determined based on the weak points. The selected critical path is used for chip testing to verify the performance and reliability of the chip.

[0069] Among them, weak points may be potential risk points in the design, such as excessive current density, heat concentration, signal interference, power supply noise, etc. Through retrospective design, these weak points can be accurately located and the critical paths can be determined based on these weak points. For example, if path A passes through an area with excessively high current density and path B passes through an area with concentrated heat, then path A and path B are determined as critical paths.

[0070] Of course, you can also combine the post-silicon stage and trace the design to find weak points to determine the critical test path. You can also use static timing analysis (STA) tools to evaluate the delay and performance of each logic path and determine the optimal path (best path) and the worst path.

[0071] In this embodiment, through the above method, in the case where no critical path is reserved in the chip, the critical path can be effectively determined, and then the test items tested based on the critical path can reduce the number of test cores and improve test efficiency.

[0072] When testing, you can choose the most complex software application scenario, that is, test the chip under high load conditions, or you can comprehensively consider various key conditions and test the critical path.

[0073] The current chiplet testing faces problems such as long testing time and high cost. The traditional full-chip testing method requires comprehensive testing of each chiplet, which is not only time-consuming and labor-intensive, but also increases the testing cost due to the large number of chiplets.

[0074] For core particle testing, such as Figure 3 As shown, in some embodiments, the test of the item to be tested based on the critical path includes: based on the critical path, performing the test of the item to be tested on the current chip to be tested. In this embodiment, since the critical path is the critical path of all key logic units from the input port to the output port of the chip, based on the critical path, a chip is tested, and the test results of other chip can be judged based on the test results of the critical path, so that the test of each chip can be omitted, thereby improving the test efficiency.

[0075] Therefore, for chip testing, the test results of one chip are inferred based on the test results of the critical path test to infer the test results of the remaining chips. In this way, only one chip needs to be tested during testing, which greatly reduces the test time and improves the test efficiency.

[0076] Of course, based on the critical path, the remaining core particles interconnected with the current core particle to be tested can also be tested for the items to be tested. Specifically, the testing of the items to be tested based on the critical path includes: based on the critical path, the testing of the items to be tested of the remaining core particles of the same batch as the current core particle to be tested can be performed.

[0077] For example, see Figure 5 As shown, in other embodiments, for example, in the case where no critical path is reserved, one of the core particles can be scan tested by a traditional scan test method. During the test, the test results of each path are recorded, including indicators such as test time, power consumption, and yield of the test results. According to the test results, the critical path is determined. Then, the remaining core particles are tested based on the critical path in a targeted manner. In this way, compared with the traditional scan test method, the test time can also be reduced and the test efficiency can be improved. Specifically, the determination of the critical path in the current core particle to be tested includes: traversing and scanning all paths of the current core particle to be tested, and finding the critical path according to the test results; the testing of the items to be tested based on the critical path includes: based on the critical path, the remaining crystal particles are targeted to perform the items to be tested on the critical path.

[0078] Specifically, the critical path is determined based on the test results. The judgment can be made based on multiple indicators, such as test coverage, and the path with the highest coverage is selected as the critical path, wherein the coverage can be calculated by analyzing the number of logic units or functional modules covered by the path.

[0079] Fault sensitivity, select the path that is most sensitive to potential faults as the critical path. This can be determined by analyzing the path's ability to detect different types of faults.

[0080] Test time: Under the premise of meeting certain coverage and fault sensitivity, the path with the shortest test time is selected as the critical path. Among them, coverage and fault sensitivity can be determined in combination with specific test items.

[0081] To verify the test results, see Figures 8 to 10 As shown, it can be seen from multiple groups of comparison results that in the present application, whether it is a scheme of directly testing based on the critical path (the critical path in the figure) or a scheme of first obtaining the critical path through testing and then testing based on the critical path (the local critical path in the figure), both can greatly reduce the test time and improve the test efficiency compared to the traditional scan test scheme.

[0082] In addition, in this embodiment, by testing various critical paths, the chip process characteristics can be determined, and the design can be fed back for optimization, thereby accelerating the iteration speed of DTCO (design process collaborative optimization).

[0083] Embodiment 2 Existing chiplet packaging technology faces the challenge of low testing efficiency. Traditional testing methods require comprehensive testing of each chip, which is not only time-consuming but also costly. Especially in multi-chip packaging, the testing time is long. Because the traditional packaging structure design fails to adapt to the subsequent testing requirements in some aspects, the chip testing time is long and the efficiency is low.

[0084] Based on the core particle testing method provided in Example 1, see Figure 6 and Figure 7 As shown, the present invention also provides a chiplet 100 according to an embodiment, and the chiplet 100 facilitates efficient chiplet testing by pre-designing a critical path.

[0085] The chip includes: at least one critical path, which is arranged on a packaging substrate, and the critical path is a partial path of all paths formed by the circuit between the input port and the output port of the chip, and the critical path is configured to be used for testing the test items required in the chip test standard specification during the testing phase.

[0086] In some embodiments, the critical path is a path preset inside the core particle for testing the item to be tested.

[0087] In some other embodiments, the critical path is a partial path determined in an existing circuit from an input port to an output port of the chiplet.

[0088] In some embodiments, the core comprises a plurality of dies, and at least one critical path is pre-designed on the substrate of the core as a subsequent critical path, which connects the input and output ports of the plurality of cores and is for all critical circuits. The critical path is made of metal wires with low resistance and low capacitance characteristics to ensure signal integrity and reduce test time.

[0089] Among them, the design of the critical path can select the shortest and most reliable path as the critical path according to the location of the conductive bumps and the distance of the package pins. Or, ensure that it is for the possible weak points in the core particle. In short, the setting of the critical path in this embodiment is the test items required by the core particle test standard specification, such as functional testing, timing testing, power consumption testing, electromagnetic compatibility testing, reliability testing, etc. In this embodiment, by reserving a critical path in the core particle, it is convenient to optimize the subsequent core particle test process and improve the core particle test efficiency, so that efficient core particle testing can be achieved.

[0090] The setting of the critical path is applicable to various packaged products such as 2D, 2.5D, 3D, etc. Some routing in the core grain needs to be realized through packaging, while for 2D products with a single die, the routing can be realized directly in the chip.

[0091] In some embodiments, the critical path includes a worst path, an optimal path, and a typical path between the worst path and the optimal path.

[0092] In some embodiments, the worst path is the path with the longest physical distance or the worst performance, the best path is the path with the shortest physical distance or the best performance, and the physical distance or performance of the typical path is between the worst path and the best path.

[0093] In some embodiments, the critical path is configured to test any one of the test items in the protocol layer test, data path layer test and physical layer test during the test phase. Among them, the protocol layer test is used to test the service interoperability between the protocol layer buses of two interconnected grains. The data path layer test is used to test the correctness of the data content interacting between the physical layer and the data path layer, the accuracy of data packet parsability and identification, and the interoperability of power consumption state management. The physical layer test is used to test the electrical characteristics of the transmitter and receiver. The specific test items are listed in the requirements of T / HiPi 001-2023 "Chip Grain Interconnection Interface Specification", so I will not go into details.

[0094] In some embodiments, the critical path is arranged between all logic units of the core particle; and / or, The critical path is between all circuits and registers; and / or, The critical path is arranged between different functional module circuits of the packaged die, wherein the different functional module circuits include: one or more of an analog circuit, a storage circuit, a radio frequency circuit, an interface circuit and a protection circuit.

[0095] According to the same technical concept as above, the present application also provides a chip in an embodiment, comprising: at least two interconnected core particles as described in any of the above embodiments.

[0096] Specifically, the core particles are interconnected based on Chiplets technology to form the chip.

[0097] See also Fig.11 As shown, a schematic diagram of the structure of a 3D packaged chip is shown. Applying the technical concept of the present application, the 3D packaged chip 200 includes at least two core particles 100 described in any of the above embodiments stacked and interconnected in the vertical direction. By optimizing its structure in the design stage, the subsequent test efficiency can be improved and the test cost can be reduced.

[0098] It should be noted that the scheme of this embodiment has corresponding specific technical features as the first embodiment, and its specific technical scheme and technical effects are similar. The difference is that the core particles and chips of the embodiment of the present invention can be applied to the test method described in the first embodiment to perform chip testing, forming a set of standard specifications for chiplets chip testing, thereby improving test efficiency.

[0099] For each embodiment provided by the present invention, the technical solutions and technical effects are basically the same, and the relevant parts can be referenced to each other.

[0100] In summary, the core particle testing method, core particles and chips provided in the embodiments of the present invention are applicable to various tests of core particles and chips, or systems with multiple chips, and are not limited to reliability testing (ESD, LUP, aging), system testing, and electromagnetic compatibility testing. The critical path selected in the test phase, or the critical path reserved in the design phase, is applicable to chip-level testing as well as system-level testing. By testing the items to be tested based on the critical path, instead of the traditional pin-by-pin scanning test scheme, the chip testing efficiency can be improved and the testing cost can be reduced.

[0101] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0102] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0103] For the convenience of description, the above chip internal clock period jitter measurement device is described as being divided into various functional units / circuits / modules by function. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0104] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A core particle testing method, characterized in that: The method comprises: Determine a critical path in the current chip to be tested; the critical path is a partial path among all paths formed by the circuit from the input port to the output port of the chip, and the critical path is used to test the item to be tested; The project to be tested is tested based on the critical path.

2. The core particle testing method according to claim 1, characterized in that: The determining of the critical path in the current core particle to be tested includes: determining a path preset in the core particle for testing the item to be tested as the critical path.

3. The core particle testing method according to claim 1, characterized in that: The determining of the critical path in the current chiplet to be tested includes: determining a partial path in an existing circuit between an input port and an output port of the chiplet as the critical path.

4. The core particle testing method according to claim 3, characterized in that: The determining of a portion of the path in the existing circuit from the input port to the output port of the chiplet as the critical path includes: Screening out the critical path according to the location of the conductive bumps in the existing circuit and the distance of the package pins; or, Find the weak points in the existing circuit according to the retrospective design, and determine the critical path based on the weak points; or, All paths formed by the circuit between the input port and the output port of the current chip to be tested are tested, and the critical path is determined according to the test result.

5. The core particle testing method according to claim 1, characterized in that: The testing of the item to be tested based on the critical path includes: Based on the critical path, executing a test item test on the current chip to be tested; and / or Based on the critical path, the remaining core particles of the same batch as the current core particle to be tested are tested for the items to be tested.

6. The core particle testing method according to claim 1, characterized in that: The testing of the item to be tested based on the critical path includes: testing based on the worst path in the critical path to verify whether the worst path meets the design standard specification; wherein the worst path is the path with the longest physical distance or the worst performance.

7. The core particle testing method according to claim 1 or 5, characterized in that: The testing of the item to be tested based on the critical path includes: testing based on the best path in the critical path to verify whether the best path meets the design standard specification; wherein the best path is the path with the shortest physical distance or the best performance.

8. The core particle testing method according to claim 1 or 5, characterized in that: The testing of the item to be tested based on the critical path includes: testing based on a typical path in the critical path to verify whether the typical path meets the design standard specifications; wherein the typical path is a path whose physical distance or performance is between the worst path and the best path, the worst path is the path with the longest physical distance or the worst performance, and the best path is the path with the shortest physical distance or the best performance.

9. The core particle testing method according to claim 6, characterized in that: After verifying whether the worst path meets the design standard specification, the method further includes: if the worst path meets the design standard specification, determining whether the typical path or the best path in the critical path meets the design standard specification.

10. A core particle, characterized in that: The core particle comprises: At least one critical path is arranged on the packaging substrate, and the critical path is a partial path of all paths formed by the circuit between the input port and the output port of the chip, and the critical path is configured to test the test items required in the chip test standard specification.

11. The core particle according to claim 10, characterized in that: The critical path is a path preset inside the core particle for testing the item to be tested; or, The critical path is a partial path determined in an existing circuit from an input port to an output port of the core particle.

12. The core particle according to claim 10 or 11, characterized in that: The critical path includes a worst path, an optimal path, and a typical path between the worst path and the optimal path; The worst path is the path with the longest physical distance or the worst performance, the best path is the path with the shortest physical distance or the best performance, and the physical distance or performance of the typical path is between the worst path and the best path.

13. The core particle according to claim 10, characterized in that The critical path configuration is used for testing any one of the test items of protocol layer testing, data path layer testing and physical layer testing during the testing phase.

14. The core particle according to claim 10, characterized in that The critical path is arranged between the logic circuits of the core particles; and / or, The critical path is between the circuit and the register; and / or, The critical path is arranged between different functional module circuits of the packaged die; wherein the different functional module circuits include: one or more of an analog circuit, a storage circuit, a radio frequency circuit, an interface circuit and a protection circuit.

15. A chip, characterized in that: include: At least two interconnected core particles according to any one of claims 10 to 14.

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