Battery voltage sampling circuit for battery management system

Abstract

The invention relates to battery voltage sampling, in particular to a battery voltage sampling circuit for a battery management system, which comprises a level conversion circuit for receiving a sampling clock signal CLK for controlling the starting of the battery voltage sampling circuit, converting the sampling clock signal CLK into a level signal conforming to battery voltage and outputting the level signal to a latch; the latch is used for latching the level signal output by the level conversion circuit and outputting the level signal to the sampling switch control circuit; the sampling switch control circuit is used for generating a control signal required by a sampling switch according to the converted level signal output by the latch and outputting the control signal to the sampling switch; the sampling switch is used for changing the conduction state of an internal switch according to the control signal output by the sampling switch control circuit and outputting a battery voltage sampling value; according to the technical scheme, the defect that in the prior art, the chip manufacturing cost is high due to the fact that the area of a battery voltage sampling circuit is large can be effectively overcome.

Description

Technical Field

[0001] The invention relates to battery voltage sampling, and in particular to a battery voltage sampling circuit for a battery management system. Background Art

[0002] In the field of new energy vehicles, since a single battery cannot meet the voltage requirements, dozens of batteries are usually required to be used in series or in parallel. A battery pack is composed of multiple battery cells connected in series, and multiple battery packs are connected in series to form a battery pack. The voltage of each battery pack can reach tens of volts, and the voltage of the battery pack is as high as 400V. In practical applications, a battery pack is generally equipped with a battery information acquisition board, which requires a battery management analog front-end (AFE) chip. When collecting battery voltage signals, the terminal voltage of the battery cell ranges from a few volts to tens of volts.

[0003] In order to meet the voltage sampling requirements of the above-mentioned power batteries, the commonly used battery voltage sampling circuits are basically solutions that use a mixture of high-voltage DMOS tubes and CMOS tubes, such as nuvoTon's KA49517. For a battery pack consisting of more than a dozen battery cells, more than a dozen corresponding sampling circuits are required in the battery management analog front-end chip to complete the collection of battery voltage information. The high-voltage tubes in such chips are generally implemented using high-voltage DMOS tubes in the high-voltage BCD process. However, the high-voltage DMOS tube has a large area, and in order to ensure the isolation of the high-voltage DMOS tube from the CMOS tube, a large-area isolation ring is required. Therefore, the area of ​​the existing battery voltage sampling circuit is generally relatively large. For battery management analog front-end chips that require more than a dozen sampling circuits, the area occupied by the entire sampling module has a great impact on its overall area, resulting in a high chip manufacturing cost. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides a battery voltage sampling circuit for a battery management system, which can effectively overcome the defect of the prior art that the chip manufacturing cost is high due to the large area of ​​the battery voltage sampling circuit.

[0006] (II) Technical solution

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0008] A battery voltage sampling circuit for a battery management system, comprising a level conversion circuit, a latch, a sampling switch control circuit, a sampling switch connected in sequence, and a charge pump;

[0009] The level conversion circuit receives the sampling clock signal CLK for controlling the start of the battery voltage sampling circuit, converts the sampling clock signal CLK into a level signal that conforms to the battery voltage, and outputs it to the latch;

[0010] A latch latches the level signal output by the level conversion circuit and outputs it to the sampling switch control circuit;

[0011] The sampling switch control circuit generates a control signal required by the sampling switch according to the converted level signal output by the latch, and outputs the control signal to the sampling switch;

[0012] The sampling switch changes the conduction state of the internal switch according to the control signal output by the sampling switch control circuit, and outputs the battery voltage sampling value;

[0013] The charge pump receives a logic low level V representing the positive terminal voltage of the battery. cp and the logic high level V representing the negative terminal voltage of the battery cn , boost the positive terminal voltage of the battery to get a logic high level V cp_up , the negative terminal voltage of the battery is stepped down to obtain a logic low level V cn_down and the logic high level V cp_up and logic low V cn_down The signals are output to the level conversion circuit and the sampling switch control circuit respectively.

[0014] Preferably, the level conversion circuit includes a first level conversion circuit and a second level conversion circuit, the first level conversion circuit includes a first cross-coupled amplifier, a first inverter in the first level conversion circuit receives a sampling clock signal CLK, a gate of an NMOS tube M1 in the first cross-coupled amplifier is connected to the first inverter through a capacitor C1, and receives a logic low level V through a first resistor. cp ;

[0015] The gate of the NMOS transistor M2 in the first cross-coupled amplifier receives the sampling clock signal CLK through the capacitor C2 and receives the logic low level V through the second resistor. cp , the source of the NMOS tube M1 and the NMOS tube M2 receives the logic low level V cp , the first cross-coupled amplifier receives a logic high level V cp_up , the first cross-coupled amplifier outputs V to the latch M1_d and V M2_d .

[0016] Preferably, the second level conversion circuit includes a second cross-coupled amplifier, a second inverter in the second level conversion circuit receives a sampling clock signal CLK, a gate of a PMOS tube M3 in the second cross-coupled amplifier is connected to the first inverter through a capacitor C3, and receives a logic high level V through a third resistor. cn ;

[0017] The gate of the PMOS transistor M4 in the second cross-coupled amplifier receives the sampling clock signal CLK through the capacitor C4 and receives the logic high level V through the fourth resistor. cn , the source of the PMOS tube M3 and the PMOS tube M4 receives the logic high level V cn , the second cross-coupled amplifier receives a logic low level V cn_down , the second cross-coupled amplifier outputs V to the latch M3_d and V M4_d .

[0018] Preferably, the latch comprises a first latch circuit and a second latch circuit, wherein the first latch circuit and the second latch circuit are both composed of a plurality of OR gates and a plurality of inverters, and the first latch circuit receives the V output by the first level conversion circuit. M1_d and V M2_d and outputs V to the sampling switch control circuit lp 、V lpz 、V ctrp 、V ctrpz ;

[0019] Among them, V lp and V ctrp In phase with the sampling clock signal CLK, V lpz and V ctrpz The sampling clock signal CLK is in opposite phase, V lp 、V lpz 、V ctrp 、V ctrpz The high level and low level are respectively the logic high level V cp_up , logic low level V cp .

[0020] Preferably, the second latch circuit receives the V output by the second level conversion circuit. M3_d and V M4_d and outputs V to the sampling switch control circuit ln 、V lnz 、V ctrn 、V ctrnz ;

[0021] Among them, V ln and V ctrnIn phase with the sampling clock signal CLK, V lnz and V ctrnz The sampling clock signal CLK is in opposite phase, V ln 、V lnz 、V ctrn 、V ctrnz The high level and low level are respectively the logic high level V cn , logic low level V cn_down .

[0022] Preferably, the sampling switch control circuit includes a first sampling switch control circuit and a second sampling switch control circuit, the first sampling switch control circuit includes a third cross-coupled amplifier and a first reset circuit, the third cross-coupled amplifier receives V output by the first latch circuit through capacitors C6 and C5 respectively. lp 、V lpz , the third cross-coupled amplifier receives a logic low level V cp ;

[0023] The third cross-coupled amplifier outputs V to the source of the NMOS transistor M6 and the NMOS transistor M5 respectively. C6_R 、V C5_R The gates of the NMOS tubes M6 and M5 receive a logic low level V cp The drains of the NMOS tubes M6 and M5 are connected to a first reset circuit, and the first reset circuit receives V output by the first latch circuit. ctrp and V ctrpz , and a logic high level V cp_up and outputs V to the sampling switch sp and V spz .

[0024] Preferably, the second sampling switch control circuit includes a fourth cross-coupled amplifier and a second reset circuit, and the fourth cross-coupled amplifier receives V output by the second latch circuit through capacitors C7 and C8 respectively. ln 、V lnz , the fourth cross-coupled amplifier receives a logic high level V cn ;

[0025] The fourth cross-coupled amplifier outputs V to the source of the PMOS tube M7 and the PMOS tube M8 respectively. C7_R 、V C8_R The gates of the PMOS tubes M7 and M8 receive a logic high level V cn The drains of the PMOS tubes M7 and M8 are connected to a second reset circuit, and the second reset circuit receives V output by the second latch circuit. ctrn and V ctrnz, and a logic low level V cn_down and outputs V to the sampling switch sn and V snz .

[0026] Preferably, the sampling switch includes a first sampling switch circuit and a second sampling switch circuit, the first sampling switch circuit includes a PMOS tube M9 and a PMOS tube M10, the second sampling switch circuit includes an NMOS tube M11 and an NMOS tube M12, and the gates of the PMOS tube M9 and the PMOS tube M10 receive V output by the first sampling switch control circuit respectively. spz 、V sp , the source of the PMOS tube M9 and the PMOS tube M10 receives the logic low level V cp , the drains of the PMOS tube M9 and the PMOS tube M10 are connected to the drains of the NMOS tube M11 and the NMOS tube M12 respectively;

[0027] The gates of the NMOS transistors M11 and M12 receive the V output by the second sampling switch control circuit. snz 、V sn , the source of the NMOS tube M11 and the NMOS tube M12 receives the logic high level V cn The drains of the NMOS tubes M11 and M12 output V ocp 、V ocn .

[0028] Preferably, when V sp >V cp , V spz <V cp , V sn <V cn , V snz >V cn When V ocp Output represents the logic low level V of the battery positive terminal voltage cp , V ocn Output represents the logic high level V of the negative terminal voltage of the battery cn ;

[0029] When V sp <V cp , V spz >V cp , V sn >V cn , V snz <V cn When V ocp Output represents the logic high level V of the negative terminal voltage of the battery cn , V ocn Output represents the logic low level V of the battery positive terminal voltagecp .

[0030] (III) Beneficial effects

[0031] Compared with the prior art, the battery voltage sampling circuit for a battery management system provided by the present invention generates the control signal required by the sampling switch through capacitor bootstrapping to meet the battery voltage sampling requirements of the high-voltage battery pack. Only CMOS tubes are needed in the sampling circuit, and high-voltage DMOS tubes in the existing battery voltage sampling circuits are not needed. The area of ​​the battery voltage sampling circuit can be effectively reduced, which helps to reduce the area of ​​the battery management analog front-end chip in new energy vehicles, thereby reducing the chip manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 It is a hardware structure diagram of the present invention;

[0034] Figure 2 A circuit diagram of a level conversion circuit and a latch in the present invention;

[0035] Figure 3 It is a circuit diagram of the sampling switch control circuit and the sampling switch in the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] A battery voltage sampling circuit for a battery management system, such as Figure 1 As shown, it includes a level conversion circuit 101, a latch 102, a sampling switch control circuit 103, a sampling switch 104 connected in sequence, and also includes a charge pump 105;

[0038] The level conversion circuit 101 receives the sampling clock signal CLK for controlling the start of the battery voltage sampling circuit, converts the sampling clock signal CLK into a level signal that conforms to the battery voltage, and outputs it to the latch 102;

[0039] The latch 102 latches the level signal output by the level conversion circuit 101 and outputs it to the sampling switch control circuit 103;

[0040] The sampling switch control circuit 103 generates a control signal required by the sampling switch 104 according to the converted level signal output by the latch 102, and outputs the control signal to the sampling switch 104;

[0041] The sampling switch 104 changes the conduction state of the internal switch according to the control signal output by the sampling switch control circuit 103, and outputs the battery voltage sampling value;

[0042] The charge pump 105 receives a logic low level V representing the positive terminal voltage of the battery. cp and the logic high level V representing the negative terminal voltage of the battery cn , boost the positive terminal voltage of the battery to get a logic high level V cp_up , the negative terminal voltage of the battery is stepped down to obtain a logic low level V cn_down and the logic high level V cp_up and logic low V cn_down The signals are output to the level conversion circuit 101 and the sampling switch control circuit 103 respectively.

[0043] like Figure 2 As shown, the level conversion circuit 101 includes a first level conversion circuit and a second level conversion circuit. The first level conversion circuit includes a first cross-coupled amplifier. The first inverter in the first level conversion circuit receives the sampling clock signal CLK. The gate of the NMOS tube M1 in the first cross-coupled amplifier is connected to the first inverter through the capacitor C1, and receives the logic low level V through the first resistor. cp ;

[0044] The gate of the NMOS transistor M2 in the first cross-coupled amplifier receives the sampling clock signal CLK through the capacitor C2 and receives the logic low level V through the second resistor. cp , the source of NMOS tube M1 and NMOS tube M2 receives the logic low level V cp , the first cross-coupled amplifier receives a logic high level V cp_up , the first cross-coupled amplifier outputs V to the latch 102 M1_d and V M2_d .

[0045] The second level conversion circuit includes a second cross-coupled amplifier. The second inverter in the second level conversion circuit receives the sampling clock signal CLK. The gate of the PMOS tube M3 in the second cross-coupled amplifier is connected to the first inverter through the capacitor C3. At the same time, the gate receives the logic high level V through the third resistor. cn ;

[0046] The gate of the PMOS tube M4 in the second cross-coupled amplifier receives the sampling clock signal CLK through the capacitor C4 and receives the logic high level V through the fourth resistor. cn , the source of PMOS tube M3 and PMOS tube M4 receives the logic high level V cn , the second cross-coupled amplifier receives the logic low level V cn_down , the second cross-coupled amplifier outputs V to latch 102 M3_d and V M4_d .

[0047] like Figure 2 As shown, the latch 102 includes a first latch circuit and a second latch circuit. The first latch circuit and the second latch circuit are both composed of a plurality of OR gates and a plurality of inverters. The first latch circuit receives the V output by the first level conversion circuit. M1_d and V M2_d and outputs V to the sampling switch control circuit 103 lp 、V lpz 、V ctrp 、V ctrpz ;

[0048] Among them, V lp and V ctrp In phase with the sampling clock signal CLK, V lpz and V ctrpz The sampling clock signal CLK is in opposite phase, V lp 、V lpz 、V ctrp 、V ctrpz The high level and low level are respectively the logic high level V cp_up , logic low level V cp .

[0049] The second latch circuit receives the V output by the second level conversion circuit. M3_d and V M4_d and outputs V to the sampling switch control circuit 103 ln 、V lnz 、V ctrn 、V ctrnz ;

[0050] Among them, V ln and V ctrn In phase with the sampling clock signal CLK, V lnz and V ctrnz The sampling clock signal CLK is in opposite phase, V ln 、V lnz 、V ctrn 、V ctrnz The high level and low level are respectively the logic high level Vcn , logic low level V cn_down .

[0051] like Figure 3 As shown, the sampling switch control circuit 103 includes a first sampling switch control circuit and a second sampling switch control circuit. The first sampling switch control circuit includes a third cross-coupled amplifier and a first reset circuit. The third cross-coupled amplifier receives V output by the first latch circuit through capacitors C6 and C5 respectively. lp 、V lpz , the third cross-coupled amplifier receives a logic low level V cp ;

[0052] The third cross-coupled amplifier outputs V to the source of NMOS tube M6 and NMOS tube M5 respectively. C6_R 、V C5_R , the gates of NMOS tubes M6 and M5 receive the logic low level V cp The drains of the NMOS tubes M6 and M5 are connected to the first reset circuit, which receives the V output by the first latch circuit. ctrp and V ctrpz , and a logic high level V cp_up and outputs V to the sampling switch 104 sp and V spz .

[0053] The second sampling switch control circuit includes a fourth cross-coupled amplifier and a second reset circuit. The fourth cross-coupled amplifier receives V output by the second latch circuit through capacitors C7 and C8 respectively. ln 、V lnz , the fourth cross-coupled amplifier receives a logic high level V cn ;

[0054] The fourth cross-coupled amplifier outputs V to the source of the PMOS tube M7 and the PMOS tube M8 respectively. C7_R 、V C8_R , the gates of PMOS tubes M7 and M8 receive the logic high level V cn The drains of the PMOS tubes M7 and M8 are connected to the second reset circuit, and the second reset circuit receives the V output by the second latch circuit. ctrn and V ctrnz , and a logic low level V cn_down and outputs V to the sampling switch 104 sn and V snz .

[0055] like Figure 3As shown, the sampling switch 104 includes a first sampling switch circuit and a second sampling switch circuit. The first sampling switch circuit includes a PMOS tube M9 and a PMOS tube M10, and the second sampling switch circuit includes an NMOS tube M11 and an NMOS tube M12. The gates of the PMOS tube M9 and the PMOS tube M10 receive the V output by the first sampling switch control circuit respectively. spz 、V sp , the source of PMOS tube M9 and PMOS tube M10 receives the logic low level V cp , the drains of the PMOS tube M9 and the PMOS tube M10 are connected to the drains of the NMOS tube M11 and the NMOS tube M12 respectively;

[0056] The gates of the NMOS tubes M11 and M12 receive the V output by the second sampling switch control circuit. snz 、V sn , the source of NMOS tube M11 and NMOS tube M12 receives the logic high level V cn , the drains of NMOS tube M11 and NMOS tube M12 output V ocp 、V ocn .

[0057] When V sp >V cp , V spz <V cp , V sn <V cn , V snz >V cn When V ocp Output represents the logic low level V of the battery positive terminal voltage cp , V ocn Output represents the logic high level V of the negative terminal voltage of the battery cn ;

[0058] When V sp <V cp , V spz >V cp , V sn >V cn , V snz <V cn When V ocp Output represents the logic high level V of the negative terminal voltage of the battery cn , V ocn Output represents the logic low level V of the battery positive terminal voltage cp .

[0059] like Figure 2 As shown, there are the following two situations for the level conversion circuit 101 and the latch 102:

[0060] 1) After power-on, when the rising edge of the sampling clock signal CLK arrives, the left end of the capacitor C1 of the first level conversion circuit becomes a CMOS low level, and the right end of the capacitor C1 will be at V cp A falling pulse signal is generated on the voltage, and then it returns to V cp ; The left end of capacitor C2 becomes CMOS high level, and the right end of capacitor C2 will be at V cp A rising pulse signal is generated on the voltage, and then it returns to V cp The right end of capacitor C1 is connected to the gate of NMOS tube M1, and the right end of capacitor C2 is connected to the gate of NMOS tube M2. After the pulse voltage difference between the two gates is amplified by the positive feedback latch amplifier, V M1_D Output logic high level V cp_up , V M2_D Output logic low level V cp . V M1_D and V M2_D Input to the first latch circuit, V lp and V ctrp The output is logic high level V cp_up , V lpz and V ctrpz Output is logic low V cp ;

[0061] Similarly, the left end of the capacitor C3 of the second level conversion circuit becomes a CMOS low level, and the right end of the capacitor C3 will be at V cn A falling pulse signal is generated on the voltage, and then it returns to V cn ; The left end of capacitor C4 becomes CMOS high level, and the right end of capacitor C4 will be at V cn A rising pulse signal is generated on the voltage, and then it returns to V cn The right end of capacitor C3 is connected to the gate of PMOS tube M3, and the right end of capacitor C4 is connected to the gate of PMOS tube M4. After the pulse voltage difference between the two gates is amplified by the positive feedback latch amplifier, V M3_D Output logic high level V cn , V M4_D Output logic low level V cn_down . V M3_D and V M4_D Input to the second latch circuit, V ln and V ctrn The output is logic high level V cn , V lnz and V ctrnz Output is logic low V cn down ;

[0062] 2) When the falling edge of the sampling clock signal CLK arrives, the left end of the capacitor C1 of the first level conversion circuit becomes a CMOS high level, and the right end of the capacitor C1 is at V cp A rising pulse signal is generated on the voltage, and then it returns to V cp ; The left end of capacitor C2 becomes CMOS low level, and the right end of capacitor C2 will be at V cp A falling pulse signal is generated on the voltage, and then it returns to V cp The pulse voltage difference between the gates of NMOS tube M1 and NMOS tube M2 is amplified by the positive feedback latch amplifier, V M1_D Output logic low level V cp , V M2_D Output logic high level V cp_up . V M1_D and V M2_D Input to the first latch circuit, V lp and V ctrp Output is logic low V cp , V lpz and V ctrpz The output is logic high level V cp_up ;

[0063] Similarly, the left end of the capacitor C3 of the second level conversion circuit becomes a CMOS high level, and the right end of the capacitor C3 will be at V cn A rising pulse signal is generated on the voltage, and then it returns to V cn ; The left end of capacitor C4 becomes CMOS low level, and the right end of capacitor C4 will be at V cn A falling pulse signal is generated on the voltage, and then it returns to V cn The pulse voltage difference between the gates of PMOS tube M3 and PMOS tube M4 is amplified by the positive feedback latch amplifier, V M3_D Output logic low level V cn_down , V M4_D Output logic high level V cn . V M3_D and V M4_D Input to the second latch circuit, V ln and V ctrn Output is logic low V cn_down , V lnz and V ctrnz The output is logic high level V cn .

[0064] like Figure 3 As shown, there are the following two situations for the sampling switch control circuit 103 and the sampling switch 104:

[0065] 1) When the sampling clock signal CLK is at a high level, after passing through the first level conversion circuit and the first latch circuit, V lp and V ctrp Output logic high level V cp_up , while V lpz and V ctrpz Output logic low level V cp At this time, the right end V of the capacitor C5 of the first sampling switch control circuit C5_R Output V cp , the right end of capacitor C6 V C6_R Output is below V cp , NMOS tube M5 is disconnected, NMOS tube M6 is turned on, making V spz Output is below V cp , Vsp output resets to V cp_up , so that the PMOS tube M9 of the first sampling switch circuit is turned on and the PMOS tube M10 is turned off, V ocp Output the sampling value of the battery positive terminal voltage;

[0066] Similarly, when the sampling clock signal CLK is high, V ln and V ctrn Output logic high level V cn , while V lnz and V ctrnz Output logic low level V cn_down At this time, the right end V of the capacitor C7 of the second sampling switch control circuit C7_R Output higher than V cn , the right end of capacitor C8 V C8_R Output V cn , PMOS tube M7 is turned on and PMOS tube M8 is turned off, making V sn Output higher than V cn , V snz Output reset to V cn_down , so that the NMOS tube M11 of the second sampling switch circuit is disconnected and the NMOS tube M12 is turned on, V ocn Output the sampled value of the negative terminal voltage of the battery;

[0067] 2) When the sampling clock signal CLK is at a low level, after passing through the first level conversion circuit and the first latch circuit, V lp and V ctrp Output logic low level V cp , while V lpz and V ctrpz Output logic high level V cp_up At this time, the right end V of the capacitor C5 of the first sampling switch control circuit C5_R Output is below V cp , the right end of capacitor C6 V C6_ROutput V cp , NMOS tube M5 is turned on and NMOS tube M6 is turned off, making V spz Output reset to V cp_up , V sp Output is below V cp , so that the PMOS tube M9 of the first sampling switch circuit is disconnected and the PMOS tube M10 is turned on, V ocn Output the sampling value of the battery positive terminal voltage;

[0068] Similarly, when the sampling clock signal CLK is low, V ln and V ctrn Output logic low level V cn_down , while V lnz and V ctrnz Output logic high level V cn At this time, the right end V of the capacitor C7 of the second sampling switch control circuit C7_R Output V cn , the right end of capacitor C8 V C8_R Output higher than V cn , PMOS tube M7 is disconnected and PMOS tube M8 is turned on, making V sn Output reset to V cn_down , V snz Output higher than V cn , so that the NMOS tube M11 of the second sampling switch circuit is turned on and the NMOS tube M12 is turned off, V ocp Output the sampled value of the negative terminal voltage of the battery.

[0069] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A battery voltage sampling circuit for a battery management system, characterized in that: It includes a level conversion circuit 101, a latch 102, a sampling switch control circuit 103, a sampling switch 104 connected in sequence, and also includes a charge pump 105; The level conversion circuit 101 receives the sampling clock signal CLK for controlling the start of the battery voltage sampling circuit, converts the sampling clock signal CLK into a level signal that conforms to the battery voltage, and outputs it to the latch 102; The latch 102 latches the level signal output by the level conversion circuit 101 and outputs it to the sampling switch control circuit 103; The sampling switch control circuit 103 generates a control signal required by the sampling switch 104 according to the converted level signal output by the latch 102, and outputs the control signal to the sampling switch 104; The sampling switch 104 changes the conduction state of the internal switch according to the control signal output by the sampling switch control circuit 103, and outputs the battery voltage sampling value; The charge pump 105 receives a logic low level V representing the positive terminal voltage of the battery. cp and the logic high level V representing the negative terminal voltage of the battery cn , boost the positive terminal voltage of the battery to get a logic high level V cp_up , the negative terminal voltage of the battery is stepped down to obtain a logic low level V cn_down and the logic high level V cp_up and logic low V cn_down The signals are output to the level conversion circuit 101 and the sampling switch control circuit 103 respectively.

2. The battery voltage sampling circuit for a battery management system according to claim 1, characterized in that: The level conversion circuit 101 includes a first level conversion circuit and a second level conversion circuit. The first level conversion circuit includes a first cross-coupled amplifier. A first inverter in the first level conversion circuit receives a sampling clock signal CLK. The gate of the NMOS tube M1 in the first cross-coupled amplifier is connected to the first inverter through a capacitor C1 and receives a logic low level V through a first resistor. cp ; The gate of the NMOS transistor M2 in the first cross-coupled amplifier receives the sampling clock signal CLK through the capacitor C2 and receives the logic low level V through the second resistor. cp , the source of the NMOS tube M1 and the NMOS tube M2 receives the logic low level V cp , the first cross-coupled amplifier receives a logic high level V cp_up , the first cross-coupled amplifier outputs V to the latch 102 M1_d and V M2_d .

3. The battery voltage sampling circuit for a battery management system according to claim 2, characterized in that: The second level conversion circuit includes a second cross-coupled amplifier. The second inverter in the second level conversion circuit receives the sampling clock signal CLK. The gate of the PMOS tube M3 in the second cross-coupled amplifier is connected to the first inverter through the capacitor C3. At the same time, the gate receives the logic high level V through the third resistor. cn ; The gate of the PMOS transistor M4 in the second cross-coupled amplifier receives the sampling clock signal CLK through the capacitor C4 and receives the logic high level V through the fourth resistor. cn , the source of the PMOS tube M3 and the PMOS tube M4 receives the logic high level V cn , the second cross-coupled amplifier receives a logic low level V cn_down , the second cross-coupled amplifier outputs V to the latch 102 M3_d and V M4_d .

4. The battery voltage sampling circuit for a battery management system according to claim 3, characterized in that: The latch 102 includes a first latch circuit and a second latch circuit. The first latch circuit and the second latch circuit are both composed of a plurality of OR gates and a plurality of inverters. The first latch circuit receives the V output by the first level conversion circuit. M1_d and V M2_d and outputs V to the sampling switch control circuit 103 lp 、V lpz 、V ctrp 、V ctrpz ; Among them, V lp and V ctrp In phase with the sampling clock signal CLK, V lpz and V ctrpz The sampling clock signal CLK is in opposite phase, V lp 、V lpz 、V ctrp 、V ctrpz The high level and low level are respectively the logic high level V cp_up , logic low level V cp .

5. The battery voltage sampling circuit for a battery management system according to claim 4, characterized in that: The second latch circuit receives the V output by the second level conversion circuit. M3_d and V M4_d and outputs V to the sampling switch control circuit 103 ln 、V lnz 、V ctrn 、V ctrnz ; Among them, V ln and V ctrn In phase with the sampling clock signal CLK, V lnz and V ctrnz The sampling clock signal CLK is in opposite phase, V ln 、V lnz 、V ctrn 、V ctrnz The high level and low level are respectively the logic high level V cn , logic low level V cn_down .

6. The battery voltage sampling circuit for a battery management system according to claim 5, characterized in that: The sampling switch control circuit 103 includes a first sampling switch control circuit and a second sampling switch control circuit. The first sampling switch control circuit includes a third cross-coupled amplifier and a first reset circuit. The third cross-coupled amplifier receives V output by the first latch circuit through capacitors C6 and C5 respectively. lp 、V lpz , the third cross-coupled amplifier receives a logic low level V cp ; The third cross-coupled amplifier outputs V to the source of the NMOS transistor M6 and the NMOS transistor M5 respectively. C6_R 、V C5_R The gates of the NMOS tubes M6 and M5 receive a logic low level V cp The drains of the NMOS tubes M6 and M5 are connected to a first reset circuit, and the first reset circuit receives V output by the first latch circuit. ctrp and V ctrpz , and a logic high level V cp_up and outputs V to the sampling switch 104 sp and V spz .

7. The battery voltage sampling circuit for a battery management system according to claim 6, characterized in that: The second sampling switch control circuit includes a fourth cross-coupled amplifier and a second reset circuit. The fourth cross-coupled amplifier receives V output by the second latch circuit through capacitors C7 and C8 respectively. ln 、V lnz , the fourth cross-coupled amplifier receives a logic high level V cn ; The fourth cross-coupled amplifier outputs V to the source of the PMOS tube M7 and the PMOS tube M8 respectively. C7_R 、V C8_R The gates of the PMOS tubes M7 and M8 receive a logic high level V cn The drains of the PMOS tubes M7 and M8 are connected to a second reset circuit, and the second reset circuit receives V output by the second latch circuit. ctrn and V ctrnz , and a logic low level V cn_down and outputs V to the sampling switch 104 sn and V snz .

8. The battery voltage sampling circuit for a battery management system according to claim 7, characterized in that: The sampling switch 104 includes a first sampling switch circuit and a second sampling switch circuit. The first sampling switch circuit includes a PMOS transistor M9 and a PMOS transistor M10. The second sampling switch circuit includes an NMOS transistor M11 and an NMOS transistor M12. The gates of the PMOS transistor M9 and the PMOS transistor M10 receive the V output by the first sampling switch control circuit. spz 、V sp , the source of the PMOS tube M9 and the PMOS tube M10 receives the logic low level V cp , the drains of the PMOS tube M9 and the PMOS tube M10 are connected to the drains of the NMOS tube M11 and the NMOS tube M12 respectively; The gates of the NMOS transistors M11 and M12 receive the V output by the second sampling switch control circuit. snz 、V sn , the source of the NMOS tube M11 and the NMOS tube M12 receives the logic high level V cn The drains of the NMOS tubes M11 and M12 output V ocp 、V ocn .

9. The battery voltage sampling circuit for a battery management system according to claim 8, characterized in that: When V sp >V cp , V spz <V cp , V sn <V cn , V snz >V cn When V ocp Output represents the logic low level V of the battery positive terminal voltage cp , V ocn Output represents the logic high level V of the negative terminal voltage of the battery cn ; When V sp <V cp , V spz >V cp , V sn >V cn , V snz <V cn When V ocp Output represents the logic high level V of the negative terminal voltage of the battery cn , V ocn Output represents the logic low level V of the battery positive terminal voltage cp .

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