Bias circuit for reducing read crosstalk

Abstract

The invention provides a bias circuit capable of reducing read crosstalk, in the read operation of a selected storage unit, a control device is used for controlling the control gate voltage and the word line voltage of an unselected storage bit according to a read enable signal, and the bias circuit comprises the following steps: when the read enable signal is at a high level, the word line voltage of the unselected storage bit is controlled; setting a control gate voltage of an unselected storage bit in a first time period of high level duration as a first high voltage and setting a word line voltage as a second high voltage, the first high voltage ensures that the region section of the channel region controlled by the first gate structure of the unselected storage bit is conducted, and the second high voltage ensures that the region section of the channel region controlled by the second gate structure is conducted; and when the read enable signal is at a low level, the first high voltage and the second high voltage are adjusted to be medium voltage within a second time period in which the low level continues, and the range of the medium voltage is between the first high voltage and the second high voltage, so that read interference is prevented from being generated within the second time period. According to the invention, the influence on speed and power consumption can be reduced while read crosstalk is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a bias circuit for reducing read crosstalk. Background Art

[0002] like Figure 1 As shown, it is a schematic diagram of the circuit structure of the storage unit 101 of the existing flash memory; Figure 2 , which is a schematic diagram of the cross-sectional structure of a storage unit 101 of an existing flash memory; each of the storage units 101 adopts a split-gate floating-gate device.

[0003] like Figure 2 As shown, the separated gate floating gate device includes: a first source and drain region 205 and a second source and drain region 206, a plurality of separated first gate structures with floating gates 104 located between the first source and drain region 205 and the second source and drain region 206, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.

[0004] The split-gate floating-gate device is a double split-gate floating-gate device, and the number of the first gate structures is two, which are respectively indicated by marks 102a and 102b.

[0005] The split-gate floating-gate device is an N-type device, and the first source and drain regions 205 and the second source and drain regions 206 are both composed of N+ regions.

[0006] The P-type doped channel region is located between the first source and drain region 205 and the second source and drain region 206 and is covered by the first gate structure and the second gate structure 103. The first source and drain region 205 and the second source and drain region 206 are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer side surfaces of the corresponding two first gate structures, and the channel region is composed of the P-type semiconductor substrate 201 between the first source and drain region 205 and the second source and drain region 206 or is further formed by doping on the P-type semiconductor substrate 201.

[0007] The second source and drain region 206 of the memory cell 101 is connected to the bit line BL1 .

[0008] The first source and drain regions 205 of the memory cell 101 are connected to the bit line BL0 .

[0009] Each of the first gate structures is formed by stacking a tunnel dielectric layer 202 , the floating gate 104 , a control gate dielectric layer 203 and the control gate 105 .

[0010] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106 .

[0011] Figure 2 In the embodiment, the two control gates 105 can be controlled separately and connected to control gate lines CG0 and CG1 respectively, and the word line gate 106 is connected to the word line WL.

[0012] When the storage unit 101 of the storage unit 101 is read, taking the storage bit 'a' corresponding to the first source and drain region 205 as an example:

[0013] The control gate line CG0 is connected to 0V;

[0014] The word line WL is connected to 3.5V;

[0015] The control gate line CG1 is connected to 5.4V;

[0016] like Figure 3 , which is a read voltage curve of a read circuit of a memory cell of a conventional flash memory during a read operation; Figure 3 In the embodiment, the read voltage includes the control gate voltage of the unselected storage bit and the word line voltage, the word line voltage is also represented by WL, and the control gate voltage of the unselected storage bit is represented by CG. Figure 3 In the reading voltage curve, only the high and low levels of WL or CG are indicated, and the actual voltage is not indicated. Therefore, the voltage change of WL or CG adopts the same curve, and the corresponding curve is the WL / CG curve.

[0017] It can be seen that in the WL / CG curve, the read voltage switches between a high voltage, i.e., a high level 'H', and a low voltage, i.e., a low level 'L'. When WL / CG is at a high level 'H', if the read enable signal SEB is at a low level, read crosstalk will be generated.

[0018] In order to solve the above problems, it is necessary to propose a new bias circuit for reducing read crosstalk. Summary of the invention

[0019] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a bias circuit for reducing read crosstalk, so as to solve the problem of read crosstalk existing in flash memory in the prior art.

[0020] To achieve the above objectives and other related objectives, the present invention provides a bias circuit for reducing read crosstalk, comprising:

[0021] A flash memory comprising a plurality of storage cells, each of which uses a split-gate floating-gate device;

[0022] The split-gate floating-gate device comprises: a first source-drain region and a second source-drain region, a plurality of separated first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate;

[0023] The channel region is located between the first source and drain region and the second source and drain region and is covered by the first gate structure and the second gate structure, and each of the first gate structure and the second gate structure controls a region segment of the channel region;

[0024] The floating gate of each of the first gate structures serves as a storage bit;

[0025] The control gate of each of the first gate structures is connected to a corresponding control gate line;

[0026] Each of the second gate structures is connected to a corresponding word line;

[0027] The read circuit is used for providing a control gate voltage for each of the control gate lines and a word line voltage for the word line during a read operation;

[0028] In a read operation on the selected storage unit, the control device is used to control the control gate voltage and the word line voltage of the unselected storage bit according to the read enable signal, including:

[0029] When the read enable signal is at a high level, the control gate voltage of the unselected storage bit in the first time period during which the high level lasts is set to a first high voltage and the word line voltage is set to a second high voltage, wherein the first high voltage ensures that the region segment of the channel region controlled by the first gate structure of the unselected storage bit is turned on and the second high voltage ensures that the region segment of the channel region controlled by the second gate structure is turned on;

[0030] When the read enable signal is at a low level, during the second time period when the low level continues, the first and second high voltages are adjusted to a medium voltage, and the range of the medium voltage is between the first and second high voltages, so as to prevent read interference from occurring during the second time period.

[0031] Preferably, the read enable signal is a pulse signal.

[0032] Preferably, the control device further comprises setting: a chip enable signal, wherein the chip enable signal sets a chip enable time period of the flash memory.

[0033] Preferably, in the chip enable time period, the first time period and the second time period form a cycle unit and cycle more than once; when the chip enable time period ends, the control gate voltage and the word line voltage of the unselected storage bit are both set to the low voltage.

[0034] Preferably, the low voltage is a ground voltage.

[0035] Preferably, the control device includes: a predecoder, which is used to convert a binary code with a specific meaning into a corresponding output signal; a first and a second level converter and a first and a second drive circuit; the first high voltage is connected to the control gate line through the first level converter and the first drive circuit, and the first medium voltage is connected to the control gate line through the drive circuit; the second high voltage is connected to the control gate line through the second level converter and the second drive circuit, and the second medium voltage is connected to the control gate line through the drive circuit.

[0036] Preferably, the control device further comprises a plurality of charge pumps, and the first and second high voltages and the medium voltage are outputted by corresponding charge pumps respectively.

[0037] Preferably, the control device includes two charge pumps; the first charge pump includes multiple output terminals, respectively outputting the second high voltage and the medium voltage; the second charge pump includes multiple output terminals, respectively outputting the first high voltage and the medium voltage.

[0038] Preferably, the control device also includes first to third switch circuits; the output end of the first charge pump is connected to the first switch circuit, the output end of the second charge pump is connected to the second switch circuit, the selection end of the third switch circuit is connected to the read enable signal, and the third switch is also connected to the first and second switch circuits respectively; when the read enable signal is at a low level, the third switch circuit is turned on, the first and second switch circuits are turned off, and the control gate voltage and the word line voltage are the medium voltage; when the read enable signal is at a high level, the third switch circuit is turned off, the first and second switch circuits are turned on, the control gate voltage is the first high voltage, and the word line voltage is the second high voltage.

[0039] Preferably, the third switch circuit includes: a first PMOS tube and a second PMOS tube, the gate of the first PMOS tube and the gate of the second PMOS tube are connected together and serve as a selection end; the drain of the first PMOS tube and the drain of the second PMOS tube are connected together.

[0040] As described above, the bias circuit for reducing read crosstalk of the present invention has the following beneficial effects:

[0041] The present invention can reduce the read crosstalk and the influence on the speed and power consumption by balancing the CG / WL voltage during the non-sensing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram showing the circuit structure of a storage unit of a flash memory in the prior art;

[0043] Figure 2 Shown is a schematic diagram of a split-gate floating-gate device of the prior art;

[0044] Figure 3 A schematic diagram showing a read voltage curve of a read circuit of a memory cell of a flash memory in the prior art during a read operation;

[0045] Figure 4 Shown is a schematic diagram of a bias circuit for reducing read crosstalk according to the present invention;

[0046] Figure 5 Shown is a schematic diagram of a circuit for generating a medium voltage according to the present invention;

[0047] Figure 6 It is a schematic diagram showing a read voltage curve of a read circuit of a memory cell of a flash memory of the present invention during a read operation. DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] See also Figure 4 , the present invention provides a bias circuit for reducing read crosstalk, comprising;

[0050] A flash memory comprising a plurality of storage cells, each of which uses a split-gate floating-gate device;

[0051] The split-gate floating-gate device comprises: a first source-drain region and a second source-drain region, a plurality of separated first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate;

[0052] The channel region is located between the first source and drain regions and the second source and drain regions and is covered by the first gate structures and the second gate structures, and each of the first gate structures and the second gate structures controls a region segment of the channel region;

[0053] The floating gate of each first gate structure serves as a storage bit;

[0054] The control gate of each first gate structure is connected to the corresponding control gate line;

[0055] Each second gate structure is connected to a corresponding word line;

[0056] The read circuit is used to provide a control gate voltage to each control gate line and a word line voltage to the word line during a read operation;

[0057] See also Figure 6 In a read operation on a selected storage cell, the control device is used to control a control gate voltage and a word line voltage of an unselected storage bit according to a read enable signal SEN, including:

[0058] When the read enable signal SEN is at a high level, the control gate voltage of the unselected storage bit in the first time period of the high level is set to the first high voltage ZVDD_CG and the word line voltage is set to the second high voltage ZVDD_WL, the first high voltage ZVDD_CG ensures that the region section of the channel region controlled by the first gate structure of the unselected storage bit is turned on and the second high voltage ZVDD_WL ensures that the region section of the channel region controlled by the second gate structure is turned on;

[0059] When the read enable signal SEN is at a low level, the first and second high voltages are adjusted to a medium voltage (ZVDDL_WL, ZVDDL_CG) during the second time period in which the low level is maintained. The range of the medium voltage (ZVDDL_WL, ZVDDL_CG) is between the first and second high voltages to prevent read interference during the second time period.

[0060] By balancing the CG / WL voltage during non-sensing time, the read crosstalk can be reduced while reducing the impact on speed and power consumption.

[0061] In some embodiments, the read enable signal SEN is a pulse signal.

[0062] In some embodiments, the control device further includes setting: a chip enable signal, the chip enable signal sets a chip enable time period of the flash memory.

[0063] In some embodiments, in the chip enable time period, the first time period and the second time period form a cycle unit and cycle more than once; at the end of the chip enable time period, the control gate voltage and word line voltage of the unselected storage bit are both set to a low voltage.

[0064] In some embodiments, the low voltage is a ground voltage.

[0065] In some embodiments, the control device includes: a predecoder, which is used to convert a binary code with a specific meaning into a corresponding output signal; a first and a second level converter and a first and a second drive circuit; the first high voltage ZVDD_CG is connected to the control gate line through the first level converter and the first drive circuit, and the first medium voltage (ZVDDL_WL, ZVDDL_CG) is connected to the control gate line through the drive circuit; the second high voltage ZVDD_WL is connected to the control gate line through the second level converter and the second drive circuit, and the second medium voltage (ZVDDL_WL, ZVDDL_CG) is connected to the control gate line through the drive circuit.

[0066] In some embodiments, the control device further includes a plurality of charge pumps, and the first and second high voltages and the middle voltage (ZVDDL_WL, ZVDDL_CG) are output by corresponding charge pumps respectively.

[0067] In some embodiments, see Figure 5 The control device includes two charge pumps; the first charge pump includes multiple output terminals, which respectively output the second high voltage ZVDD_WL and the medium voltage (ZVDDL_WL, ZVDDL_CG); the second charge pump includes multiple output terminals, which respectively output the first high voltage ZVDD_CG and the medium voltage (ZVDDL_WL, ZVDDL_CG).

[0068] In some embodiments, the control device also includes first to third switch circuits; the output end of the first charge pump is connected to the first switch circuit, the output end of the second charge pump is connected to the second switch circuit, the selection end of the third switch circuit is connected to the read enable signal SEN, and the third switch is also connected to the first and second switch circuits respectively; when the read enable signal SEN is at a low level, the third switch circuit is turned on, the first and second switch circuits are turned off, and the control gate voltage and the word line voltage are medium voltages (ZVDDL_WL, ZVDDL_CG); when the read enable signal SEN is at a high level, the third switch circuit is turned off, the first and second switch circuits are turned on, the control gate voltage is the first high voltage ZVDD_CG, and the word line voltage is the second high voltage ZVDD_WL.

[0069] In some embodiments, the third switch circuit includes: a first PMOS tube and a second PMOS tube, the gate of the first PMOS tube and the gate of the second PMOS tube are connected together and serve as a selection end; the drain of the first PMOS tube and the drain of the second PMOS tube are connected together.

[0070] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0071] In summary, the present invention can reduce read crosstalk and reduce the impact on speed and power consumption by balancing the CG / WL voltage during the non-sensing time. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A bias circuit for reducing read crosstalk, characterized in that: include; A flash memory comprising a plurality of storage cells, each of which uses a split-gate floating-gate device; The split-gate floating-gate device comprises: a first source-drain region and a second source-drain region, a plurality of separated first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate; The channel region is located between the first source and drain region and the second source and drain region and is covered by the first gate structure and the second gate structure, and each of the first gate structure and the second gate structure controls a region segment of the channel region; The floating gate of each of the first gate structures serves as a storage bit; The control gate of each of the first gate structures is connected to a corresponding control gate line; Each of the second gate structures is connected to a corresponding word line; The read circuit is used for providing a control gate voltage for each of the control gate lines and a word line voltage for the word line during a read operation; In a read operation on the selected storage unit, the control device is used to control the control gate voltage and the word line voltage of the unselected storage bit according to the read enable signal, including: When the read enable signal is at a high level, the control gate voltage of the unselected storage bit in the first time period during which the high level lasts is set to a first high voltage and the word line voltage is set to a second high voltage, wherein the first high voltage ensures that the region segment of the channel region controlled by the first gate structure of the unselected storage bit is turned on and the second high voltage ensures that the region segment of the channel region controlled by the second gate structure is turned on; When the read enable signal is at a low level, during the second time period when the low level continues, the first and second high voltages are adjusted to a medium voltage, and the range of the medium voltage is between the first and second high voltages, so as to prevent read interference from occurring during the second time period.

2. The bias circuit for reducing read crosstalk according to claim 1, characterized in that: The read enable signal is a pulse signal.

3. The bias circuit for reducing read crosstalk according to claim 1, characterized in that: The control device further includes setting: a chip enable signal, wherein the chip enable signal sets a chip enable time period of the flash memory.

4. The bias circuit for reducing read crosstalk according to claim 3, characterized in that: In the chip enable time period, the first time period and the second time period form a cycle unit and cycle more than once; when the chip enable time period ends, the control gate voltage and the word line voltage of the unselected storage bit are both set to the low voltage.

5. The bias circuit for reducing read crosstalk according to claim 4, characterized in that: The low voltage is a ground voltage.

6. The bias circuit for reducing read crosstalk according to claim 1, characterized in that: The control device includes: a predecoder, which is used to convert a binary code with a specific meaning into a corresponding output signal; a first and a second level converter and a first and a second drive circuit; the first high voltage is connected to the control gate line through the first level converter and the first drive circuit, and the first medium voltage is connected to the control gate line through the drive circuit; the second high voltage is connected to the control gate line through the second level converter and the second drive circuit, and the second medium voltage is connected to the control gate line through the drive circuit.

7. The bias circuit for reducing read crosstalk according to claim 1 or 7, characterized in that: The control device further includes a plurality of charge pumps, and the first and second high voltages and the medium voltage are outputted by the corresponding charge pumps respectively.

8. The bias circuit for reducing read crosstalk according to claim 8, characterized in that: The control device includes two charge pumps; the first charge pump includes multiple output terminals, respectively outputting the second high voltage and the medium voltage; the second charge pump includes multiple output terminals, respectively outputting the first high voltage and the medium voltage.

9. The bias circuit for reducing read crosstalk according to claim 9, characterized in that: The control device also includes first to third switch circuits; the output end of the first charge pump is connected to the first switch circuit, the output end of the second charge pump is connected to the second switch circuit, the selection end of the third switch circuit is connected to the read enable signal, and the third switch is also connected to the first and second switch circuits respectively; when the read enable signal is at a low level, the third switch circuit is turned on, the first and second switch circuits are turned off, and the control gate voltage and the word line voltage are the medium voltage; when the read enable signal is at a high level, the third switch circuit is turned off, the first and second switch circuits are turned on, the control gate voltage is the first high voltage, and the word line voltage is the second high voltage.

10. The bias circuit for reducing read crosstalk according to claim 10, characterized in that: The third switch circuit includes: a first PMOS tube and a second PMOS tube, wherein the gate of the first PMOS tube and the gate of the second PMOS tube are connected together and serve as a selection end; and the drain of the first PMOS tube and the drain of the second PMOS tube are connected together.

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