Testing device and testing method for limit signal computer memory board
By designing a test device for the extreme signal computer memory board, the core control module and other modules are used to achieve rapid testing and fault location of the memory board, the problems of low test coverage and cumbersome operation in the existing test methods are solved, and the problem of high-quality test coverage and complicated operation is improved. Test efficiency and accuracy of fault location.
Patent Information
- Application Number
- CN202411417309.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-02-11
AI Technical Summary
The existing testing methods have limited test coverage of the extreme signal computer memory board, are cumbersome and time-consuming, and cannot directly test and locate fault points.
A testing device is designed, including a core control module, a power module, an input detection module and an output display module. Through address traversal, the address full coverage test of read-only memory and random memory is achieved, and the fault points are quickly located.
It realizes fast and simple testing of the extreme signal computer memory board, reduces testing time, improves testing efficiency, and can directly locate faulty devices.
Smart Images
Figure CN119418748A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of circuit board testing, in particular to a testing device and a testing method for a limit signal computer memory board. Background Art
[0002] The extreme signal computer memory board mainly includes a read-only memory part and a random access memory part. The read-only memory part is mainly composed of six PROMs to store programs. Its address is formed by the signal coming from the port through the logic gate circuit. The enable end and power supply end of each memory are controlled by related circuits. The data signal coming out of the memory reaches the port through the inverter; the random access memory part is mainly composed of four random access memories, counters, logic gates, etc. The data and address of the random access memory are controlled by related discrete devices, which can realize the data writing and reading functions.
[0003] The existing testing method relies on the entire product for system testing, using product testing equipment. For a single memory board, not only is the test coverage limited, but the operation is also cumbersome and time-consuming. Once a fault occurs, the signal cannot be directly tested because the board is inside the product, and the fault point cannot be directly located. Summary of the invention
[0004] In order to solve the above technical problems, the present invention proposes a test device and a test method for a computer memory board of an extreme signal. By building a core control module, the control signal, data signal and address signal of the memory board can be controlled automatically, and the address full coverage test of the read-only memory and random access memory can be realized by address traversal, so as to realize single board testing and rapid fault location.
[0005] The technical problem to be solved by the present invention is achieved by adopting the following technical solutions:
[0006] A test device for a limit signal computer memory board, comprising:
[0007] The core control module is connected to the board under test and is used to generate the signals required for the test;
[0008] A power module is connected to the board under test and is used to generate the voltage required by the board under test;
[0009] The input detection module is connected to the board under test and is used to monitor the input signal in real time;
[0010] The output display module is connected to the board under test and is used to display each bit of data read from the board under test.
[0011] As a further improvement of the present invention, the core control module includes an industrial computer and a single-chip microcomputer, and the industrial computer communicates with the single-chip microcomputer via a serial port.
[0012] As a further improvement of the present invention, the input detection module monitors the input signal status in real time through a light emitting diode.
[0013] As a further improvement of the present invention, the input detection module and the output display module have the functions of reducing the fault range and locating the fault point.
[0014] A method for testing a limit signal computer memory board, using the above-mentioned test device for a limit signal computer memory board, includes a read-only memory test and a random access memory test, and the steps of the read-only memory test are as follows:
[0015] Step 1: The corresponding I / O port of the MCU in the core control module is fixed to high or low according to the signal analysis table of the read-only memory address part, and the clock signal is added to the ports X5 / B12 to X11 / B13 on the board to be tested, and the signal is increased from the minimum cycle t by two times to 1024t, combined with the selection result of the power supply part;
[0016] Step 2: The single-chip microcomputer in the core control module reads the output signals of the data terminals X5 / B3, X5 / A3, X5 / B4, X5 / A2, X5 / B2, X5 / A1, X5 / B6, X5 / B7, X5 / B9, X5 / A9, X5 / B10, X5 / A8, X5 / B8, X5 / A7, X5 / A6, and X5 / A5 on the board under test and compares the read results with the theoretical values to make a judgment.
[0017] As a further improvement of the present invention, the random access memory test steps are as follows:
[0018] Step 1: The core control module adds a signal of 0 to the ports X12 / B16, X6 / B15, X12 / A15, and X12 / A14 on the board under test through the single-chip microcomputer. At this time, the common input end of the data input part D12, D11, D10, and D13 is 1. When the other input end of D12, D11, D10, and D13 is 1, the data output is 1, and when the other input end is 0, the data output is 0. Therefore, the data end of the random access memory can be controlled to be 1 or 0. The address input of the random access memory is directly controlled by the single-chip microcomputer in the core control module through the circuit board port;
[0019] Step 2: Write data 0000, 1111, 1010, 0101 in each address space respectively, and then read the data in each storage address to see if it is the same as written.
[0020] The beneficial effects of the present invention are:
[0021] Compared with the existing method that must rely on the entire product to test the board, the present invention is not only simple and fast to operate, greatly reducing the test time and improving the test efficiency, but also can realize direct power-on testing of the single board. The test covers all devices on the board. The input detection module and the output display module can intuitively display the fault branch, and locate the faulty device quickly and effectively. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The present invention is further described below in conjunction with the accompanying drawings and embodiments:
[0023] Figure 1 It is the structural block diagram of the test device;
[0024] Figure 2 A flow chart for testing read-only memory;
[0025] Figure 3 Test flow chart for random access memory test.
[0026] In the figure: 1. Core control module; 2. Power module; 3. Input detection module; 4. Output display module. DETAILED DESCRIPTION
[0027] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further described below with reference to the accompanying drawings and embodiments.
[0028] like Figure 1 As shown, a test device for a limit signal computer memory board includes a core control module 1, a power module 2, an input detection module 3, and an output display module 4. The core control module 1 is connected to the board under test, and is mainly composed of an industrial computer and a single-chip microcomputer. The industrial computer communicates with the single-chip microcomputer through a serial port and controls the I / O port of the single-chip microcomputer to generate the required signal. The power module 2 is connected to the board under test and is used to generate the voltage required by the board under test. The input detection module 3 is connected to the board under test and is used to monitor the input signal in real time using a light-emitting diode. The output display module 4 is connected to the board under test and is used to display each bit of data read from the board under test. When a fault occurs in the board under test, the input detection module 3 and the output display module 4 can be directly used to narrow the fault range and locate the fault point.
[0029] A test method for a limit signal computer memory board, using the above-mentioned test device for a limit signal computer memory board, includes a read-only memory test and a random access memory test, such as Figure 2 As shown, the steps for testing the read-only memory are as follows:
[0030] The corresponding I / O ports of the single-chip microcomputer in the core control module 1 are fixed to high or low according to Table 1, and the clock signal is added to the ports X5 / B12 to X11 / B13 on the board to be tested, and the signal is increased by two times from the minimum period t to 1024t, combined with the selection result of the power supply part; the single-chip microcomputer in the core control module 1 reads the output signals of the data terminals X5 / B3, X5 / A3, X5 / B4, X5 / A2, X5 / B2, X5 / A1, X5 / B6, X5 / B7, X5 / B9, X5 / A9, X5 / B10, X5 / A8, X5 / B8, X5 / A7, X5 / A6, and X5 / A5 on the board to be tested, and compares the read results with the theoretical values to make a result judgment.
[0031] Table 1 Read-only memory address part signal analysis table
[0032]
[0033] like Figure 3 As shown, the random access memory test steps are as follows:
[0034] The core control module 1 adds a signal of 0 to the ports X12 / B16, X6 / B15, X12 / A15, and X12 / A14 on the board under test through the single-chip microcomputer. At this time, the common input end of the data input part D12, D11, D10, and D13 is 1. When the other input end of D12, D11, D10, and D13 is 1, the data output is 1, and when the other input end is 0, the data output is 0. Therefore, the data end of the random access memory can be controlled to be 1 or 0. The address input of the random access memory is directly controlled by the single-chip microcomputer in the core control module 1 through the circuit board port; write data 0000, 1111, 1010, and 0101 in each address space respectively, and then read out the data in each storage address to see if it is the same as the written data.
[0035] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions only describe the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.
Claims
1. A test device for a limit signal computer memory board, characterized in that: include, The core control module (1) is connected to the board under test and is used to generate the signals required for the test; A power module (2), connected to the board under test, and used to generate a voltage required by the board under test; An input detection module (3), connected to the board under test, for real-time monitoring of input signal conditions; The output display module (4) is connected to the board under test and is used to display each bit of data read from the board under test.
2. The device for testing a computer memory board of a limit signal according to claim 1, characterized in that: The core control module (1) comprises an industrial computer and a single-chip microcomputer, and the industrial computer communicates with the single-chip microcomputer via a serial port.
3. The device for testing a computer memory board of a limit signal according to claim 1, characterized in that: The input detection module (3) monitors the input signal status in real time through a light emitting diode.
4. The device for testing a computer memory board of a limit signal according to claim 1, characterized in that: The input detection module (3) and the output display module (4) have the functions of reducing the fault range and locating the fault point.
5. A method for testing a limit signal computer memory board, characterized in that: The test device for a computer memory board of an extreme signal according to claims 1 to 4 includes a read-only memory test and a random access memory test, and the steps of the read-only memory test are as follows: Step 1: The corresponding I / O port of the single-chip microcomputer in the core control module (1) is fixed to high or low according to the signal analysis table of the read-only memory address part, and the clock signal is added to the ports X5 / B12 to X11 / B13 on the board to be tested, and the signal is increased from the minimum cycle t by two times to 1024t, combined with the selection result of the power supply part; Step 2: The single-chip microcomputer in the core control module (1) reads the output signals of the data terminals X5 / B3, X5 / A3, X5 / B4, X5 / A2, X5 / B2, X5 / A1, X5 / B6, X5 / B7, X5 / B9, X5 / A9, X5 / B10, X5 / A8, X5 / B8, X5 / A7, X5 / A6 and X5 / A5 on the board under test and compares the read results with the theoretical values to make a result judgment.
6. The method for testing a limit signal computer memory board according to claim 5, characterized in that: The steps for random access memory testing are as follows: Step 1: The core control module (1) adds a signal of 0 to the ports X12 / B16, X6 / B15, X12 / A15, and X12 / A14 on the board under test through the single-chip microcomputer. At this time, the common input end of the data input part D12, D11, D10, and D13 is 1. When the other input end of D12, D11, D10, and D13 is 1, the data output is 1. When the other input end is 0, the data output is 0. Therefore, the data end of the random access memory can be controlled to be 1 or 0. The address input of the random access memory is directly controlled by the single-chip microcomputer in the core control module (1) through the circuit board port; Step 2: Write data 0000, 1111, 1010, and 0101 into each address space respectively, and then read the data in each storage address to see if it is the same as what was written.