Power amplification circuit and radio frequency module

Abstract

The invention discloses a power amplification circuit and a radio frequency module. The power amplification circuit comprises a power amplification module and a bias module. The power amplification module comprises M first power amplifiers and M second power amplifiers, the M first power amplifiers are correspondingly connected to the M first signal ends, and the M second power amplifiers are correspondingly connected to the M second signal ends. The bias module comprises a first bias unit and a second bias unit, the first bias unit is connected to the M first signal ends, and the second bias unit is connected to the M second signal ends. The phases of M paths of radio frequency signals input by the M first power amplifiers are roughly the same, and the phases of M paths of radio frequency signals input by the M second power amplifiers are roughly the same, so that bias signals can be provided for the M first power amplifiers and the M second power amplifiers by arranging the first bias unit and the second bias unit; the circuit structure of the power amplification circuit is simplified, and the layout area is reduced.

Description

Technical Field

[0001] The present application relates to the field of radio frequency technology, and more specifically, to a power amplifier circuit and a radio frequency module. Background Art

[0002] Existing RF modules have been widely used in wireless communications, Internet of Things, smart homes and other fields. Among them, the RF power amplifier is the core unit of the RF module, and its performance has a great impact on the signal output indicators of the RF module.

[0003] In the prior art, in order to improve the signal amplification power of the RF module, researchers usually adopt a power amplifier architecture that synthesizes multiple signals. Specifically, multiple power amplifier units are set in the RF power amplifier to amplify the RF signals separately, and then the multiple RF signals after power amplification are synthesized into one RF signal for output.

[0004] However, in the above-mentioned RF power amplifier, a corresponding bias unit needs to be provided for each power amplification unit, thereby increasing the layout area of ​​the RF module. Summary of the invention

[0005] The embodiments of the present application provide a power amplifier circuit and a radio frequency module.

[0006] According to the first aspect of the present application, an embodiment of the present application provides a power amplifier circuit, which includes a power amplifier module and a bias module. The power amplifier module includes M first power amplifiers and M second power amplifiers; the M first power amplifiers are correspondingly connected to the M first signal terminals, and the M second power amplifiers are correspondingly connected to the M second signal terminals; the absolute value of the phase difference between the two RF signals output by any two of the M first signal terminals is less than the first specified value, and the absolute value of the phase difference between the two RF signals output by any two of the M second signal terminals is less than the second specified value, and M is an integer greater than 1. The bias module includes a first bias unit and a second bias unit; the first bias unit is respectively connected to the M first signal terminals, and the second bias unit is respectively connected to the M second signal terminals.

[0007] According to the second aspect of the present application, an embodiment of the present application also provides a radio frequency module, which includes the above-mentioned power amplifier circuit.

[0008] The present application provides a power amplifier circuit and a radio frequency module, and the filter circuit includes a power amplifier module and a bias module. Among them, the M first power amplifiers in the power amplifier module are connected to the M first signal terminals, and the M second power amplifiers in the power amplifier module are connected to the M second signal terminals, wherein the absolute value of the phase difference between the two radio frequency signals output by any two first signal terminals among the M first signal terminals is less than the first specified value, and the absolute value of the phase difference between the two radio frequency signals output by any two second signal terminals among the M second signal terminals is less than the second specified value. Therefore, the phases of the M radio frequency signals input by the M first power amplifiers in the present application are roughly the same, and the phases of the M radio frequency signals input by the M second power amplifiers are roughly the same.

[0009] Therefore, when the first bias unit is connected to the M first signal terminals respectively, it can provide the first bias signal to the M first power amplifiers at the same time, thereby realizing the multiplexing of the bias units corresponding to the M first power amplifiers. Similarly, when the second bias unit is connected to the M second signal terminals respectively, it can provide the second bias signal to the M second power amplifiers at the same time, thereby realizing the multiplexing of the bias units corresponding to the M second power amplifiers.

[0010] On the one hand, since the phases of the M RF signals input by the M first power amplifiers are substantially the same, and the phases of the M RF signals input by the M second power amplifiers are substantially the same, when the structure multiplexing of the first bias unit and the second bias unit is realized, the output performance of the power amplifier circuit is hardly affected. On the other hand, only two bias units (that is, the first bias unit and the second bias unit) are required in the power amplifier circuit of the present application to provide bias signals for multiple power amplifiers in the power amplifier module, thereby simplifying the circuit structure of the power amplifier circuit, reducing the layout area and improving the balance performance of the power amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 It is a structural diagram of the radio frequency module provided in an embodiment of the present application.

[0013] Figure 2 yes Figure 1 Schematic diagram of the structure of the medium power amplifier circuit.

[0014] Figure 3 yes Figure 2Schematic diagram of the structure of the first bias unit.

[0015] Figure 4 yes Figure 2 Schematic diagram of the structure of the second bias unit.

[0016] Figure 5 yes Figure 2 Another structural schematic diagram of the power amplifier circuit shown.

[0017] Figure 6 yes Figure 2 Another structural schematic diagram of the power amplifier circuit shown.

[0018] Figure 7 yes Figure 2 Another structural schematic diagram of the power amplifier circuit shown. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0020] See also Figure 1 and Figure 2 , the embodiment of the present application provides a power amplifier circuit 100 and a radio frequency module 200 equipped with the power amplifier circuit 100. Among them, the radio frequency module 200 is a component that integrates two or more discrete devices such as a radio frequency switch, a low noise amplifier, a filter, a duplexer, a power amplifier, etc. into an independent module, thereby improving the integration and hardware performance, and miniaturizing the volume. Specifically, the radio frequency module 200 can be applied to 4G and 5G communication devices such as smart phones, tablet computers, and smart watches.

[0021] In this embodiment, the RF module 200 includes a power amplifier circuit 100, and the power amplifier circuit 100 may include a power amplifier module 10 and a bias module 30. Among them, the power amplifier module 10 may include M first power amplifiers 110 and M second power amplifiers 120. The M first power amplifiers 110 are correspondingly connected to the M first signal terminals 12, and the M second power amplifiers 120 are correspondingly connected to the M second signal terminals 14. Among them, M is an integer greater than 1. It can be understood that the RF module 200 in this embodiment is mainly aimed at the RF front-end module.

[0022] Specifically, the absolute value of the phase difference between the two RF signals output by any two of the M first signal terminals 12 is less than the first specified value. The first specified value may be greater than or equal to 0 degrees and less than or equal to 10 degrees. For example, the first specified value may be 10 degrees, in which case the absolute value of the phase difference between the two RF signals output by any two of the M first signal terminals 12 is less than 10 degrees, that is, the phases of the M RF signals output by the M first signal terminals 12 in this embodiment are substantially the same.

[0023] Similarly, the absolute value of the phase difference between the two RF signals output by any two of the M second signal terminals 14 is less than the second specified value. The second specified value may be greater than or equal to 0 degrees and less than or equal to 10 degrees. For example, the second specified value may be 10 degrees. In this case, the absolute value of the phase difference between the two RF signals output by any two of the M second signal terminals 14 is less than 10 degrees, that is, the phases of the M RF signals output by the M second signal terminals 14 in this embodiment are substantially the same.

[0024] Therefore, the phases of the M RF signals input by the M first power amplifiers 110 in this embodiment are substantially the same, and the phases of the M RF signals input by the M second power amplifiers 120 are substantially the same. In an ideal state, the phases of the M RF signals input by the M first power amplifiers 110 in this embodiment are substantially the same, and the phases of the M RF signals input by the M second power amplifiers 120 are substantially the same, but the phases of the M RF signals input by the M first power amplifiers 110 and the M RF signals input by the M second power amplifiers 120 are different. For example, the phases of the M RF signals input by the M first power amplifiers 110 and the phases of the M RF signals input by the M second power amplifiers 120 differ by 180 degrees, that is, the phases of the M RF signals input by the M first power amplifiers 110 are 0 degrees, and the phases of the M RF signals input by the M second power amplifiers 120 are 180 degrees.

[0025] The bias module 30 may include a first bias unit 320 and a second bias unit 340, wherein the first bias unit 320 is respectively connected to the M first signal terminals 12, and the second bias unit 340 is respectively connected to the M second signal terminals 14. Therefore, when the first bias unit 320 is respectively connected to the M first signal terminals 12, it can provide the first bias signal to the M first power amplifiers 110 at the same time, thereby realizing the multiplexing of the bias units corresponding to the M first power amplifiers 110. Similarly, when the second bias unit 340 is respectively connected to the M second signal terminals 14, it can provide the second bias signal to the M second power amplifiers 120 at the same time, thereby realizing the multiplexing of the bias units corresponding to the M second power amplifiers 120.

[0026] On the one hand, since the phases of the M RF signals input by the M first power amplifiers 110 are substantially the same, and the phases of the M RF signals input by the M second power amplifiers 120 are substantially the same, when the structure multiplexing of the first bias unit 320 and the second bias unit 340 is realized, the output performance of the power amplifier circuit 100 is hardly affected. On the other hand, only two bias units (that is, the first bias unit 320 and the second bias unit 340) are required to be provided in the power amplifier circuit 100 of the present application to provide bias signals for multiple power amplifiers in the power amplifier module 10, thereby simplifying the circuit structure of the power amplifier circuit 100, reducing the layout area, and improving the balance performance of the power amplifier circuit 100.

[0027] The various modules in the power amplifier circuit 100 are introduced below.

[0028] The power amplifier module 10 is used to power amplify the input RF signal. In this embodiment, the power amplifier module 10 may include M first power amplifiers 110 and M second power amplifiers 120, where M is an integer greater than 1. The M first power amplifiers 110 are correspondingly connected to the M first signal terminals 12, and the M second power amplifiers 120 are correspondingly connected to the M second signal terminals 14. That is, the M first power amplifiers 110 are used to power amplify the M RF signals input from the M first signal terminals 12, and the M second power amplifiers 120 are used to power amplify the M RF signals input from the M second signal terminals 14.

[0029] In some possible embodiments, M first signal terminals 12 and M second signal terminals 14 may output M pairs of RF signals. Specifically, the M pairs of RF signals may include differential signals, that is, the absolute value of the difference between the phase difference between the RF signal output by the first signal terminal 12 and the RF signal output by the second signal terminal 14 and 180 degrees is less than a specified difference. The specified difference may be greater than or equal to 0 degrees and less than or equal to 10 degrees. For example, the specified difference may be 10 degrees, in which case the phase difference between the RF signal output by the first signal terminal 12 and the RF signal output by the second signal terminal 14 may be between 170 degrees and 190 degrees.

[0030] In this embodiment, M first power amplifiers 110 and M second power amplifiers 120 may form M pairs of power amplification units to respectively power amplify the input M pairs of RF signals. In some possible embodiments, the first power amplifier 110 and the second power amplifier 120 included in the same pair of power amplification units may be the same, in which case the first power amplifier 110 and the second power amplifier 120 may form a differential power amplifier circuit to power amplify the same pair of RF signals. In other possible embodiments, the first power amplifier 110 and the second power amplifier 120 included in the same pair of power amplification units may be different, in which case the first power amplifier 110 and the second power amplifier 120 may form a push-pull power amplifier circuit to power amplify the same pair of RF signals.

[0031] Exemplarily, the first power amplifier 110 and the second power amplifier 120 may be implemented by transistors, for example, the first power amplifier 110 and the second power amplifier 120 may be bipolar junction transistors (Bipolar Junction Transistor, BJT), or the first power amplifier 110 and the second power amplifier 120 may be metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). Specifically, the first power amplifier 110 and the second power amplifier 120 used to constitute the same pair of power amplification units may be BJT tubes of the same model, for example, the first power amplifier 110 and the second power amplifier 120 are both P-type BJT tubes, or both are N-type BJT tubes. In this case, the first power amplifier 110 and the second power amplifier 120 constitute a differential power amplifier circuit. In some other possible embodiments, the first power amplifier 110 and the second power amplifier 120 used to constitute the same pair of power amplification units may be BJT tubes of different models. For example, the first power amplifier 110 may be a P-type BJT tube, and the second power amplifier 120 may be an N-type BJT tube. In this case, the first power amplifier 110 and the second power amplifier 120 constitute a push-pull power amplifier circuit. This embodiment does not limit the specific implementation of the first power amplifier 110 and the second power amplifier 120.

[0032] The bias module 30 is used to provide a bias signal for the power amplifier module 10. In this embodiment, the bias module 30 may include a first bias unit 320 and a second bias unit 340, wherein the first bias unit 320 is respectively connected to the M first signal terminals 12, and is used to provide a first bias signal for the M first power amplifiers 110, so that the M first power amplifiers 110 can be in a normal working state. The first bias signal can be a bias voltage or a bias current. The second bias unit 340 is respectively connected to the M second signal terminals 14, and is used to provide a first bias signal for the M second power amplifiers 120, so that the M second power amplifiers 120 can be in a normal working state. The second bias signal can be a bias voltage or a bias current.

[0033] Since the phases of the M-channel RF signals input by the M first power amplifiers 110 in this embodiment are substantially the same, and the phases of the M-channel RF signals input by the M second power amplifiers 120 are substantially the same, when the structure multiplexing of the first bias unit 320 and the second bias unit 340 is realized, the output performance of the power amplifier circuit 100 is hardly affected. Furthermore, only two bias units (that is, the first bias unit 320 and the second bias unit 340) are required to be provided in the power amplifier circuit 100 of the present application to provide bias signals for multiple power amplifiers in the power amplifier module 10, thereby simplifying the circuit structure of the power amplifier circuit 100, reducing the layout area, and improving the balance performance of the power amplifier circuit 100.

[0034] See also Figure 3 , the first bias unit 320 may include a first transistor 3200, and the first transistor 3200 is used to power amplify the input first bias signal, so that the first bias signal after power amplification can match the M first power amplifiers 110. Among them, the input terminal 3201 of the first transistor 3200 is configured to input the first bias signal, the output terminal 3203 of the first transistor 3200 is respectively connected to the M first signal terminals 12, and the power supply terminal 3205 of the first transistor 3200 is configured to input the first power supply signal. Specifically, the first power supply signal can be a power supply voltage or a power supply current, and the specific parameters of the first power supply signal can be determined based on the hardware parameters of the first transistor 3200, which is not specifically limited in this embodiment.

[0035] In some possible embodiments, as Figure 3As shown, the first transistor 3200 may be a bipolar junction transistor (Bipolar Junction Transistor, BJT). Wherein, the base of the BTJ tube is the input terminal 3201 of the first transistor 3200, the emitter of the BTJ tube is the output terminal 3203 of the first transistor 3200, and the collector of the BTJ tube is the power supply terminal 3205 of the first transistor 3200. In other possible embodiments, the first transistor 3200 may be a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). Wherein, the gate of the MOSFET tube is the input terminal 3201 of the first transistor 3200, the drain of the MOSFET tube is the output terminal 3203 of the first transistor 3200, and the source of the MOSFET tube is the power supply terminal 3205 of the first transistor 3200. This embodiment does not limit the specific implementation method of the first transistor 3200.

[0036] In some possible embodiments, the first bias unit 320 may further include M first resistors 3210. Among them, the M first terminals 3212 of the M first resistors 3210 are connected to the output terminal 3203 of the first transistor 3200, and the M second terminals 3214 of the M first resistors 3210 are respectively connected to the M first signal terminals 12. In this embodiment, by setting the M first resistors 3210, the magnitude of the first bias signal output to the M first power amplifiers 110 can be adjusted respectively, so that the M first power amplifiers 110 can be more stable when working. Specifically, the resistance values ​​of the M first resistors 3210 can be the same, or the resistance values ​​of the M first resistors 3210 can be adjusted based on the actual working conditions of the M first power amplifiers 110, which is not limited in this embodiment.

[0037] In some possible embodiments, the first bias unit 320 may further include a first voltage stabilizing subunit 3220. The first voltage stabilizing subunit 3220 may stabilize the first bias signal input to the first transistor 3200, so that the first transistor 3200 can be more stable during operation. Specifically, one end of the first voltage stabilizing subunit 3220 is connected to the input end 3201 of the first transistor 3200, and the other end of the first voltage stabilizing subunit 3220 is grounded.

[0038] As an implementation manner, the first voltage stabilizing subunit 3220 may include a first diode 3221, wherein the anode of the first diode 3221 is connected to the input terminal 3201 of the first transistor 3200, and the cathode of the first diode 3221 is grounded. On the one hand, the first diode 3221 can stabilize the first bias signal input to the first transistor 3200; on the other hand, the first diode 3221 can also improve the signal output linearity of the power amplifier circuit 100. Specifically, there may be multiple first diodes 3221, wherein the anode formed by connecting multiple first diodes 3221 in series is connected to the input terminal 3201 connected to the first transistor 3200, and the cathode formed by connecting multiple first diodes 3221 in series is grounded. Figure 3 As shown, there are two first diodes 3221, and the two first diodes 3221 are connected in series to form a first voltage stabilizing subunit 3220. In this embodiment, by providing a plurality of first diodes 3221, the overall voltage stabilizing effect of the first bias signal input to the first transistor 3200 can be improved, so that the first transistor 3200 can be more stable during operation.

[0039] As another implementation, the first voltage stabilizing subunit 3220 may include a first capacitor 3223, one end of the first capacitor 3223 is connected to the input end 3201 of the first transistor 3200, and the other end is grounded. Therefore, by connecting a first capacitor 3223 to the input end 3201 of the first transistor 3200, the first capacitor 3223 can stabilize the first bias signal input to the first transistor 3200, so that the first transistor 3200 can be more stable when working. Specifically, the first capacitor 3223 can be a chip capacitor or a plug-in capacitor, which is not specifically limited in this embodiment.

[0040] See also Figure 4 , the second bias unit 340 may include a second transistor 3400, and the second transistor 3400 is used to power amplify the input second bias signal so that the power-amplified second bias signal can match the M second power amplifiers 120. Among them, the input terminal 3401 of the second transistor 3400 is configured to input the second bias signal, the output terminal 3403 of the second transistor 3400 is respectively connected to the M second signal terminals 14, and the power supply terminal 3405 of the second transistor 3400 is configured to input the second power supply signal. Specifically, the second power supply signal can be a power supply voltage or a power supply current, and the specific parameters of the second power supply signal can be determined based on the hardware parameters of the second transistor 3400, which is not specifically limited in this embodiment.

[0041] In some possible embodiments, the magnitude of the first bias signal is different from the magnitude of the second bias signal. Exemplarily, the input terminal 3201 of the first transistor 3200 can be connected to a first power supply terminal (not shown in the figure), and the first power supply terminal provides a first bias signal (for example, a bias current Iref1) for the first transistor 3200; the input terminal 3401 of the second transistor 3400 can be connected to a second power supply terminal (not shown in the figure), and the second power supply terminal provides a second bias signal (for example, a bias current Iref2) for the second transistor 3400. In this embodiment, the magnitude of the bias signal input to the first transistor 3200 and the second transistor 3400 is different by providing bias signals respectively through two different power supply terminals. Specifically, the R&D personnel can flexibly adjust the bias signals outputted from the first power supply terminal and the second power supply terminal respectively according to the actual working conditions of the M first power amplifiers 110 and the M second power amplifiers 120, thereby improving the stability and balance of the M first power amplifiers 110 and the M second power amplifiers 120 during operation.

[0042] In some possible embodiments, as Figure 4 As shown, the second transistor 3400 may be a bipolar junction transistor (Bipolar Junction Transistor, BJT). Wherein, the base of the BTJ tube is the input terminal 3401 of the second transistor 3400, the emitter of the BTJ tube is the output terminal 3403 of the second transistor 3400, and the collector of the BTJ tube is the power supply terminal 3405 of the second transistor 3400. In some other possible embodiments, the second transistor 3400 may be a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). Wherein, the gate of the MOSFET tube is the input terminal 3401 of the second transistor 3400, the drain of the MOSFET tube is the output terminal 3403 of the second transistor 3400, and the source of the MOSFET tube is the power supply terminal 3405 of the second transistor 3400. This embodiment does not limit the specific implementation method of the second transistor 3400.

[0043] In some possible embodiments, the second bias unit 340 may further include M second resistors 3410. Among them, the M first ends 3412 of the M second resistors 3410 are connected to the output end 3403 of the second transistor 3400, and the M second ends 3414 of the M second resistors 3410 are respectively connected to the M second signal ends 14. In this embodiment, by setting the M second resistors 3410, the magnitude of the second bias signal output to the M second power amplifiers 120 can be adjusted respectively, so that the M second power amplifiers 120 can be more stable when working. Specifically, the resistance values ​​of the M second resistors 3410 can be the same, or the resistance values ​​of the M second resistors 3410 can be adjusted based on the actual working conditions of the M second power amplifiers 120, which is not limited in this embodiment.

[0044] In some possible embodiments, the second bias unit 340 may further include a second voltage stabilizing subunit 3420. The second voltage stabilizing subunit 3420 may stabilize the second bias signal input to the second transistor 3400, so that the second transistor 3400 can be more stable during operation. Specifically, one end of the second voltage stabilizing subunit 3420 is connected to the input end 3401 of the second transistor 3400, and the other end of the second voltage stabilizing subunit 3420 is grounded.

[0045] As an implementation manner, the second voltage stabilizing subunit 3420 may include a second diode 3421, wherein the anode of the second diode 3421 is connected to the input terminal 3401 of the second transistor 3400, and the cathode of the second diode 3421 is grounded. On the one hand, the second diode 3421 can stabilize the second bias signal input to the second transistor 3400; on the other hand, the second diode 3421 can also improve the signal output linearity of the power amplifier circuit 100. Specifically, the number of the second diodes 3421 may be multiple, and the anode formed by the multiple second diodes 3421 connected in series is connected to the input terminal 3401 connected to the second transistor 3400, and the cathode formed by the multiple second diodes 3421 connected in series is grounded. Figure 4 As shown, there are two second diodes 3421, and the two second diodes 3421 are connected in series to form a second voltage stabilizing subunit 3420. In this embodiment, by providing a plurality of second diodes 3421, the overall voltage stabilizing effect of the second bias signal input to the second transistor 3400 can be improved, so that the second transistor 3400 can be more stable during operation.

[0046] As another implementation, the second voltage stabilizing subunit 3420 may include a second capacitor 3423, one end of the second capacitor 3423 is connected to the input end 3401 of the second transistor 3400, and the other end is grounded. Therefore, by connecting a second capacitor 3423 to the input end 3201 of the second transistor 3400, the second capacitor 3423 can stabilize the second bias signal input to the second transistor 3400, so that the second transistor 3400 can be more stable during operation. Specifically, the second capacitor 3423 can be a chip capacitor or a plug-in capacitor, which is not specifically limited in this embodiment.

[0047] See also Figure 5 , the power amplifier circuit 100 may further include a balun module 50, which may convert an input RF signal into multiple RF signals for output. The balun module 50 may include M baluns 500, the M first primary terminals 510 of the M baluns 500 are connected to form a signal input terminal 16, the M second primary terminals 520 of the M baluns 500 are grounded, or the M second primary terminals 520 of the M baluns 500 are connected to a power supply terminal VCC (not shown in the figure). The M first secondary terminals 530 of the M baluns 500 form M first signal terminals 12, and the M second secondary terminals 540 of the M baluns 500 form M second signal terminals 14. Therefore, the M baluns 500 in this embodiment are used to convert a RF signal of the input signal input terminal 16 into 2M RF signals for output to the M first power amplifiers 110 and the M second power amplifiers 120. Specifically, the implementation methods of the M baluns 500 may be the same or different, and this embodiment does not limit the specific implementation method of the M baluns 500.

[0048] In some other possible embodiments, the power amplifier circuit 100 may also adopt a circuit structure of M combiners combined with M phase shifters to convert an input RF signal into M pairs of RF signals for output. Exemplarily, the combiner may be a 90-degree combiner, and the phase shifter may be a 90-degree phase shifter. When the RF signal passes through the 90-degree combiner and the 90-degree phase shifter in sequence, a pair of differential signals may be output. Therefore, when the M combiners all input the same RF signal, the M combiners and the M phase shifters may convert the RF signal into M pairs of differential signals for output. Specifically, this embodiment does not limit the specific implementation of the combiner and the phase shifter.

[0049] In this embodiment, the power amplifier circuit 100 may also include a signal synthesis module 70, which is connected to the signal output ends of the M first power amplifiers 110 and the M second power amplifiers 120, and is used to synthesize 2M RF signals after power amplification by the M first power amplifiers 110 and the M second power amplifiers 120, and finally synthesize one RF signal for output.

[0050] Specifically, the signal synthesis module 70 may be an output balun 700, which may include M-segment primary side parts 710 and secondary side parts 720. One end of each of the M-segment primary side parts 710 is connected to the signal output end of the first power amplifier 110, and the other end is connected to the signal output end of the second power amplifier 120. The first power amplifier 110 and the second power amplifier 120 connected to the same segment of the primary side part 710 output the same pair of RF signals (for example, the same pair of differential signals). The secondary side parts 720 are coupled to the M-segment primary side parts 710, one end of the secondary side part 720 is used to output the synthesized RF signal, and the other end is grounded.

[0051] The following takes M equal to 2 as an example to introduce the specific structure of the power amplifier circuit 100 provided in this embodiment.

[0052] See also Figure 6 , the balun module 50 may include a first balun 5100 and a second balun 5200. The first primary terminal 5110 of the first balun 5100 is connected to the first primary terminal 5210 of the second balun 5200 to form a signal input terminal 16, and the second primary terminal 5120 of the first balun 5100 and the second primary terminal 5220 of the second balun 5200 are grounded, or the second primary terminal 5120 of the first balun 5100 and the second primary terminal 5220 of the second balun 5200 are connected to the power supply terminal VCC (not shown in the figure).

[0053] The power amplifier module 10 may include a first sub-power amplifier 1100, a second sub-power amplifier 1200, a third sub-power amplifier 1300, and a fourth sub-power amplifier 1400. The first sub-power amplifier 1100 is connected to the first secondary side terminal 5130 of the first balun 5100, and the second sub-power amplifier 1200 is connected to the first secondary side terminal 5230 of the second balun 5200, that is, the first sub-power amplifier 1100 and the second sub-power amplifier 1200 are the first power amplifier 110 in the above embodiment. The third sub-power amplifier 1300 is connected to the second secondary side terminal 5140 of the first balun 5100, and the fourth sub-power amplifier 1400 is connected to the second secondary side terminal 5240 of the second balun 5200, that is, the third sub-power amplifier 1300 and the fourth sub-power amplifier 1400 are the second power amplifier 120 in the above embodiment.

[0054] In this embodiment, the first sub-power amplifier 1100 and the third sub-power amplifier 1300 are used to power amplify a pair of RF signals output by the first balun 5100, and the second sub-power amplifier 1200 and the fourth sub-power amplifier 1400 are used to power amplify a pair of RF signals output by the second balun 5200.

[0055] The first bias unit 320 is connected to the first secondary end 5130 of the first balun 5100 and the first secondary end 5230 of the second balun 5200 , respectively. The second bias unit 340 is connected to the second secondary end 5140 of the first balun 5100 and the second secondary end 5240 of the second balun 5200 , respectively.

[0056] In some possible embodiments, the first secondary end 5130 of the first balun 5100 , the second secondary end 5140 of the first balun 5100 , the first secondary end 5230 of the second balun 5200 , and the second secondary end 5240 of the second balun 5200 are sequentially spaced along the first preset direction X.

[0057] Specifically, the first secondary side terminal 5130 of the first balun 5100 is used to output a first RF signal, and the second secondary side terminal 5140 of the first balun 5100 is used to output a second RF signal, and the first RF signal and the second RF signal have different phases. In some possible embodiments, the first RF signal and the second RF signal may be a pair of differential signals.

[0058] Specifically, the first primary terminal 5110 of the first balun 5100 and the first secondary terminal 5130 of the first balun 5100 can be the same-name terminals, that is, the phase of the RF signal of the input signal input terminal 16 is the same as the phase of the first RF signal output by the first secondary terminal 5130 of the first balun 5100. For example, the phase of the RF signal of the input signal input terminal 16 can be P (for example, P is 0 degrees), and the phase of the first RF signal output by the first secondary terminal 5130 of the first balun 5100 is also P. Since the first RF signal and the second RF signal can be a pair of differential signals, the phase of the second RF signal output by the second secondary terminal 5140 of the first balun 5100 can be N (for example, N is 180 degrees).

[0059] The first secondary end 5230 of the second balun 5200 is used to output a third RF signal. The first secondary end 5230 of the second balun 5200 and the first primary end 5210 of the second balun 5200 can be the same-named ends. Therefore, the phase of the third RF signal output by the first secondary end 5230 of the second balun 5200 is also P, that is, the third RF signal and the first RF signal have the same phase.

[0060] The second secondary side end 5240 of the second balun 5200 is used to output a fourth RF signal. The fourth RF signal and the third RF signal can be a pair of differential signals. Therefore, the phase of the fourth RF signal output by the second secondary side end 5240 of the second balun 5200 is N, that is, the fourth RF signal and the second RF signal have the same phase.

[0061] therefore, Figure 6 The first sub-power amplifier 1100, the third sub-power amplifier 1300, the second sub-power amplifier 1200 and the fourth sub-power amplifier 1400 in the power amplifier circuit 100 shown constitute a PNPN type multiplexing power amplifier structure.

[0062] In some possible embodiments, see Figure 7 The first secondary end 5130 of the first balun 5100 , the second secondary end 5140 of the first balun 5100 , the second secondary end 5240 of the second balun 5200 , and the first secondary end 5230 of the second balun 5200 are sequentially spaced along the second preset direction Y.

[0063] Specifically, the first secondary side terminal 5130 of the first balun 5100 is used to output the fifth RF signal, and the second secondary side terminal 5140 of the first balun 5100 is used to output the sixth RF signal, and the phases of the fifth RF signal and the sixth RF signal are different. In some possible embodiments, the fifth RF signal and the sixth RF signal can be a pair of differential signals.

[0064] Specifically, the first primary terminal 5110 of the first balun 5100 and the first secondary terminal 5130 of the first balun 5100 can be the same-name terminals, that is, the phase of the RF signal of the input signal input terminal 16 is the same as the phase of the first RF signal output by the first secondary terminal 5130 of the first balun 5100. For example, the phase of the RF signal of the input signal input terminal 16 can be P (for example, P is 0 degrees), and the phase of the fifth RF signal output by the first secondary terminal 5130 of the first balun 5100 is also P. Since the fifth RF signal and the sixth RF signal can be a pair of differential signals, the phase of the sixth RF signal output by the second secondary terminal 5140 of the first balun 5100 can be N (for example, N is 180 degrees).

[0065] The second secondary end 5240 of the second balun 5200 is used to output the seventh RF signal. The second secondary end 5240 of the second balun 5200 and the second primary end 5220 of the second balun 5200 can be the same-named ends. Therefore, the phase of the seventh RF signal output by the second secondary end 5240 of the second balun 5200 is N, that is, the seventh RF signal and the sixth RF signal have the same phase.

[0066] The first secondary side end 5230 of the second balun 5200 is used to output the eighth RF signal. The eighth RF signal and the seventh RF signal can be a pair of differential signals. Therefore, the phase of the eighth RF signal output by the first secondary side end 5230 of the second balun 5200 is P, that is, the eighth RF signal and the fifth RF signal have the same phase.

[0067] therefore, Figure 7 The first sub-power amplifier 1100, the third sub-power amplifier 1300, the fourth sub-power amplifier 1400 and the second sub-power amplifier 1200 in the power amplifier circuit 100 shown constitute a PNNP type multiplexing power amplifier structure.

[0068] In this embodiment, the distance between the second secondary end 5140 of the first balun 5100 and the second secondary end 5240 of the second balun 5200 is smaller than the distance between the first secondary end 5130 of the first balun 5100 and the first secondary end 5230 of the second balun 5200. Specifically, the second secondary end 5140 of the first balun 5100 and the second secondary end 5240 of the second balun 5200 are arranged adjacent to each other, so when the second bias unit 340 is laid out in the power amplifier circuit 100, it can be placed in the gap between the second secondary end 5140 of the first balun 5100 and the second secondary end 5240 of the second balun 5200, so that the overall structure of the power amplifier circuit 100 is more compact, and the layout area of ​​the power amplifier circuit 100 is further reduced.

[0069] The embodiment of the present application provides a power amplifier circuit 100 and a radio frequency module 200 configured with the power amplifier circuit 100. The radio frequency module 200 includes the power amplifier circuit 100, and the power amplifier circuit 100 may include a power amplifier module 10 and a bias module 30. Among them, the power amplifier module 10 may include M first power amplifiers 110 and M second power amplifiers 120. The M first power amplifiers 110 are correspondingly connected to the M first signal terminals 12, and the M second power amplifiers 120 are correspondingly connected to the M second signal terminals 14. Among them, M is an integer greater than 1. Specifically, the absolute value of the phase difference between the two radio frequency signals output by any two first signal terminals 12 among the M first signal terminals 12 is less than the first specified value, and the absolute value of the phase difference between the two radio frequency signals output by any two second signal terminals 14 among the M second signal terminals 14 is less than the second specified value. Therefore, the phases of the M radio frequency signals input by the M first power amplifiers 110 in this embodiment are substantially the same, and the phases of the M radio frequency signals input by the M second power amplifiers 120 are substantially the same.

[0070] The bias module 30 may include a first bias unit 320 and a second bias unit 340, wherein the first bias unit 320 is respectively connected to the M first signal terminals 12, and the second bias unit 340 is respectively connected to the M second signal terminals 14. Therefore, when the first bias unit 320 is respectively connected to the M first signal terminals 12, it can provide the first bias signal to the M first power amplifiers 110 at the same time, thereby realizing the multiplexing of the bias units corresponding to the M first power amplifiers 110. Similarly, when the second bias unit 340 is respectively connected to the M second signal terminals 14, it can provide the second bias signal to the M second power amplifiers 120 at the same time, thereby realizing the multiplexing of the bias units corresponding to the M second power amplifiers 120.

[0071] On the one hand, since the phases of the M RF signals input by the M first power amplifiers 110 are substantially the same, and the phases of the M RF signals input by the M second power amplifiers 120 are substantially the same, when the structure multiplexing of the first bias unit 320 and the second bias unit 340 is realized, the output performance of the power amplifier circuit 100 is hardly affected. On the other hand, only two bias units (that is, the first bias unit 320 and the second bias unit 340) are required to be provided in the power amplifier circuit 100 of the present application to provide bias signals for multiple power amplifiers in the power amplifier module 10, thereby simplifying the circuit structure of the power amplifier circuit 100, reducing the layout area, and improving the balance performance of the power amplifier circuit 100.

[0072] In the specification of this application, certain words are used to refer to specific components in the specification and claims. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. The specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the criterion for distinction. For example, "including" mentioned throughout the specification and claims is an open term, so it should be interpreted as "including but not limited to"; "substantially" means that those skilled in the art can solve technical problems within a certain error range and basically achieve technical effects.

[0073] In the description of the present application, it should be understood that terms such as "upper", "lower", "front", "back", "left", "right", and "inside" indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are merely simplified descriptions for the convenience of describing the present application. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0074] In this application, unless otherwise clearly specified or limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can be internal communication between two elements, or it can be only surface contact. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0075] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0076] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A power amplifier circuit, characterized in that: include: A power amplification module, comprising M first power amplifiers and M second power amplifiers; the M first power amplifiers are correspondingly connected to the M first signal terminals, and the M second power amplifiers are correspondingly connected to the M second signal terminals; wherein the absolute value of the phase difference between two RF signals output by any two of the M first signal terminals is less than a first specified value, and the absolute value of the phase difference between two RF signals output by any two of the M second signal terminals is less than a second specified value, and M is an integer greater than 1; as well as The bias module comprises a first bias unit and a second bias unit; the first bias unit is respectively connected to the M first signal terminals, and the second bias unit is respectively connected to the M second signal terminals.

2. The power amplifier circuit according to claim 1, characterized in that: The M first power amplifiers include a first sub-power amplifier and a second sub-power amplifier, and the M second power amplifiers include a third sub-power amplifier and a fourth sub-power amplifier. The first sub-power amplifier and the second sub-power amplifier are respectively connected to a corresponding first signal terminal, and the third sub-power amplifier and the fourth sub-power amplifier are respectively connected to a corresponding second signal terminal. The absolute value of the phase difference between the RF signal output by the first signal terminal corresponding to the first sub-power amplifier and the RF signal output by the first signal terminal corresponding to the second sub-power amplifier is less than a first specified value, and the absolute value of the phase difference between the RF signal output by the second signal terminal corresponding to the third sub-power amplifier and the RF signal output by the second signal terminal corresponding to the fourth sub-power amplifier is less than a second specified value.

3. The power amplifier circuit according to claim 1, characterized in that: The power amplifier circuit also includes a balun module; the balun module includes M baluns; the M first primary ends of the M baluns are connected to form a signal input end, and the M second primary ends of the M baluns are grounded or the M second primary ends of the M baluns are connected to a power supply end; The M first secondary ends of the M baluns form the M first signal ends; the M second secondary ends of the M baluns form the M second signal ends.

4. The power amplifier circuit according to claim 3, characterized in that: The M is equal to 2, the balun module includes a first balun and a second balun, the first primary end of the first balun is connected to the first primary end of the second balun to form the signal input end, the second primary end of the first balun and the second primary end of the second balun are grounded or the second primary end of the first balun and the second primary end of the second balun are connected to the power supply end; The power amplification module includes a first sub-power amplifier, a second sub-power amplifier, a third sub-power amplifier and a fourth sub-power amplifier, wherein the first sub-power amplifier is connected to the first secondary side end of the first balun, the second sub-power amplifier is connected to the first secondary side end of the second balun, the third sub-power amplifier is connected to the second secondary side end of the first balun, and the fourth sub-power amplifier is connected to the second secondary side end of the second balun; The first bias unit is connected to the first secondary end of the first balun and the first secondary end of the second balun respectively, and the second bias unit is connected to the second secondary end of the first balun and the second secondary end of the second balun respectively.

5. The power amplifier circuit according to claim 4, characterized in that: The first secondary end of the first balun, the second secondary end of the first balun, the first secondary end of the second balun and the second secondary end of the second balun are sequentially spaced along a first preset direction; The first secondary end of the first balun is used to output a first RF signal, and the second secondary end of the first balun is used to output a second RF signal, and the phases of the first RF signal and the second RF signal are different; the first secondary end of the second balun is used to output a third RF signal, and the phases of the third RF signal and the first RF signal are the same; the second secondary end of the second balun is used to output a fourth RF signal, and the phases of the fourth RF signal and the second RF signal are the same.

6. The power amplifier circuit according to claim 4, characterized in that: The first secondary end of the first balun, the second secondary end of the first balun, the second secondary end of the second balun and the first secondary end of the second balun are sequentially arranged at intervals along a second preset direction; The first secondary end of the first balun is used to output a fifth RF signal, and the second secondary end of the first balun is used to output a sixth RF signal, and the phases of the fifth RF signal and the sixth RF signal are different; the second secondary end of the second balun is used to output a seventh RF signal, and the phases of the seventh RF signal and the sixth RF signal are the same; the first secondary end of the second balun is used to output an eighth RF signal, and the phases of the eighth RF signal and the fifth RF signal are the same.

7. The power amplifier circuit according to claim 6, characterized in that: A distance between the second secondary end of the first balun and the second secondary end of the second balun is smaller than a distance between the first secondary end of the first balun and the first secondary end of the second balun.

8. The power amplifier circuit according to claim 1, characterized in that: The first bias unit includes a first transistor, an input terminal of the first transistor is configured to input a first bias signal, an output terminal of the first transistor is respectively connected to M first signal terminals, and a power supply terminal of the first transistor is configured to input a first power supply signal; The second bias unit includes a second transistor, an input terminal of the second transistor is configured to input a second bias signal, an output terminal of the second transistor is respectively connected to M second signal terminals, and a power supply terminal of the second transistor is configured to input a second power supply signal.

9. The power amplifier circuit according to claim 8, characterized in that: The first bias unit includes M first resistors, M first ends of the M first resistors are connected to the output end of the first transistor, and M second ends of the M first resistors are respectively connected to the M first signal ends; The second bias unit includes M second resistors, M first ends of the M second resistors are connected to the output end of the second transistor, and M second ends of the M second resistors are respectively connected to the M second signal ends.

10. The power amplifier circuit according to claim 8, characterized in that: The first bias unit comprises a first voltage stabilizing subunit, one end of the first voltage stabilizing subunit is connected to the input end of the first transistor, and the other end of the first voltage stabilizing subunit is grounded; The second bias unit includes a second voltage stabilizing subunit, one end of the second voltage stabilizing subunit is connected to the input end of the second transistor, and the other end of the second voltage stabilizing subunit is grounded.

11. The power amplifier circuit according to claim 10, characterized in that: The first voltage stabilizing subunit comprises a first diode, an anode of the first diode is connected to the input end of the first transistor, and a cathode of the first diode is grounded; The second voltage stabilizing subunit includes a second diode, an anode of the second diode is connected to the input end of the second transistor, and a cathode of the second diode is grounded.

12. The power amplifier circuit according to claim 11, characterized in that: There are multiple first diodes, an anode formed by connecting multiple first diodes in series is connected to the input end of the first transistor, and a cathode formed by connecting multiple first diodes in series is grounded; There are multiple second diodes, an anode formed by connecting multiple second diodes in series is connected to the input end of the second transistor, and a cathode formed by connecting multiple second diodes in series is grounded.

13. The power amplifier circuit according to claim 10, characterized in that: The first voltage stabilizing subunit comprises a first capacitor, one end of the first capacitor is connected to the input end of the first transistor, and the other end is grounded; The second voltage stabilizing subunit includes a second capacitor, one end of the second capacitor is connected to the input end of the second transistor, and the other end is grounded.

14. The power amplifier circuit according to claim 8, characterized in that: The magnitude of the first bias signal is different from the magnitude of the second bias signal.

15. The power amplifier circuit according to claim 1, characterized in that: An absolute value of a difference between a phase difference between the radio frequency signal output by the first signal terminal and the radio frequency signal output by the second signal terminal and 180 degrees is smaller than a specified difference.

16. The power amplifier circuit according to claim 1, characterized in that: The first designated value is less than or equal to 10 degrees, and the second designated value is less than or equal to 10 degrees.

17. The power amplifier circuit according to claim 1, characterized in that: The phase difference between the radio frequency signal output by the first signal terminal and the radio frequency signal output by the second signal terminal is in the range of [170°, 190°].

18. A radio frequency module, characterized in that: Comprising the power amplifier circuit as claimed in any one of claims 1 to 17.

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