Pulse generation circuit, driving chip and electronic equipment

Abstract

The invention discloses a pulse generation circuit, a driving chip and electronic equipment, and belongs to the technical field of electronic equipment. The pulse generation circuit comprises a square wave input end, a first pulse unit and a second pulse unit. The first pulse unit comprises a first delay module and a first logic processing module; the first delay module is used for performing delay processing on the falling edge of the square wave signal to generate a first delay signal; the first logic processing module is used for outputting a first pulse signal according to the first delay signal; the second pulse unit comprises a second delay module and a second logic processing module; the second delay module is used for performing delay processing on the rising edge of the square wave signal to generate a second delay signal; the second logic processing module is used for outputting a second pulse signal according to the second delay signal. The pulse width of the first pulse signal and the pulse width of the second pulse signal are narrower than the pulse width of the square wave signal, and conversion from the square wave signal to the pulse signal with the narrower pulse width is achieved.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic equipment, and specifically relates to a pulse generating circuit, a driving chip and an electronic device. Background Art

[0002] As insulated gate bipolar transistors (IGBTs) are widely used in various industries, their corresponding driver chips, also known as driver integrated circuits (ICs), have also received widespread attention.

[0003] Among them, the driver IC needs to convert the lower voltage square wave signal into a higher voltage square wave signal to generate the driving current of the IGBT. However, the current driver IC usually uses a level conversion circuit to directly convert the lower voltage square wave signal into a higher voltage square wave signal, which causes the driver IC to be in a high current state for a long time, resulting in high device loss and reduced reliability of the driver IC. Obviously, if the signal pulse width during the level conversion process can be reduced, the purpose of reducing device loss during the level conversion process can be achieved, and the reliability of the driver IC can be improved. Therefore, there is an urgent need for a circuit that can convert a square wave signal into a pulse signal with a narrow pulse width to achieve the conversion of the square wave signal. Summary of the invention

[0004] A pulse generating circuit, a driving chip and an electronic device provided in the embodiments of the present application can realize the conversion from a square wave signal to a pulse signal with a narrow pulse width.

[0005] In a first aspect, a pulse generating circuit is provided, the pulse generating circuit comprising: a square wave input terminal, a first pulse unit and a second pulse unit, the square wave input terminal being used to receive a square wave signal;

[0006] The first pulse unit comprises a first delay module and a first logic processing module, wherein the first delay module is connected to the square wave input terminal and the first logic processing module;

[0007] The first delay module is used to delay the falling edge of the square wave signal, generate and transmit a first delay signal to the first logic processing module;

[0008] The first logic processing module is used to output a first pulse signal according to the first delay signal, and the high level duration of the first pulse signal is the falling edge duration of the first delay signal;

[0009] The second pulse unit comprises a second delay module and a second logic processing module, and the second delay module is connected to the square wave input terminal and the second logic processing module;

[0010] The second delay module is used to delay the rising edge of the square wave signal, generate and transmit a second delay signal to the second logic processing module;

[0011] The second logic processing module is used to output a second pulse signal according to the second delay signal, and the high level duration of the second pulse signal is the rising edge duration of the first delay signal.

[0012] Optionally, the first delay module includes: a first inverter and a first capacitor; the first inverter is connected to the square wave input terminal, the first terminal of the first capacitor and the first logic processing module, and the second terminal of the first capacitor is grounded;

[0013] The first inverter and the first capacitor are used to cooperate in delaying the rising edge and the falling edge of the square wave signal to generate and transmit the first delayed signal to the first logic processing module.

[0014] Optionally, the first logic processing module is used to output a high-level signal during the rising edge duration period of the first delay signal, and output a low-level signal during the remaining period of the first delay signal to obtain the first pulse signal, and the remaining period is the period of the first delay signal excluding the rising edge duration period.

[0015] Optionally, the first logic processing module includes: a second inverter, a third inverter and a first AND gate; the second inverter is connected to the square wave input terminal and the first AND gate, and the third inverter is connected to the first inverter and the first AND gate.

[0016] Optionally, the second delay module is used to delay the falling edge of the inverted signal of the square wave signal to generate and transmit a second delayed signal to the second logic processing module.

[0017] Optionally, the second delay module includes: a fourth inverter, a fifth inverter and a second capacitor; the fourth inverter is connected to the square wave input terminal and the fifth inverter, the fifth inverter is also connected to the first terminal of the second capacitor and the second logic processing module, and the second terminal of the second capacitor is grounded;

[0018] The fifth inverter and the second capacitor are used to cooperate in delaying the rising edge and the falling edge of the inverted signal to generate and transmit a second delayed signal to the second logic processing module.

[0019] Optionally, the first logic processing module includes a second inverter, a third inverter and a first AND gate; the second inverter is connected to the square wave input terminal and the first AND gate, and the third inverter is connected to the first inverter and the first AND gate; the second delay module includes: a sixth inverter and a third capacitor; the sixth inverter is connected to the second inverter, the first end of the third capacitor and the second logic processing module, and the second end of the third capacitor is grounded;

[0020] The sixth inverter and the third capacitor are used to cooperate in delaying the rising edge and the falling edge of the inverted signal to generate and transmit a second delayed signal to the second logic processing module.

[0021] Optionally, the second logic processing module is used to output a high-level signal during the rising edge duration period of the second delay signal, and output a low-level signal during the remaining period of the second delay signal to obtain the second pulse signal, and the remaining period of the second delay signal is the period of the second delay signal excluding the rising edge duration period.

[0022] Optionally, the second logic processing module includes: an eighth inverter, a seventh inverter and a second AND gate; the eighth inverter is connected to the second AND gate to receive an inverted signal of the square wave signal, and the seventh inverter is connected to the fifth inverter and the second AND gate.

[0023] Optionally, the second delay module includes a fourth inverter, a fifth inverter and a second capacitor, and the eighth inverter is connected to the fourth inverter;

[0024] Alternatively, the second delay module includes: a sixth inverter and a third capacitor, and the eighth inverter is connected to the second inverter.

[0025] In a second aspect, a driving chip is provided, wherein the driving chip comprises the pulse generating circuit described in any one of the first aspects.

[0026] In a third aspect, an electronic device is provided, wherein the electronic device includes any pulse generating circuit described in the first aspect, or the electronic device includes the driving chip described in the second aspect.

[0027] In the pulse generating circuit, driving chip and electronic device provided by the embodiment of the present application, the first delay module in the first pulse unit in the pulse generating circuit can delay the falling edge of the square wave signal, generate and transmit the first delay signal to the first logic processing module, so that the first logic processing module can output the first pulse signal according to the first delay signal, and the high level duration of the first pulse signal is the falling edge duration of the first delay signal. The second delay module in the second pulse unit can delay the rising edge of the square wave signal, generate and transmit the second delay signal to the second logic processing module, so that the second logic processing module can output the second pulse signal according to the second delay signal, and the high level duration of the second pulse signal is the rising edge duration of the first delay signal. In this technical solution, the pulse generating circuit can delay the rising edge and falling edge of the input square wave signal to output a first pulse signal whose high level duration is equal to the duration of the falling edge, and a second pulse signal whose high level duration is equal to the duration of the rising edge. The pulse widths of the first pulse signal and the second pulse signal are narrower than the pulse width of the square wave signal, thereby realizing the conversion from a square wave signal to a pulse signal with a narrower pulse width. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is one of the schematic diagrams of the pulse generating circuit provided in the embodiment of the present application;

[0029] Figure 2 This is the second schematic diagram of the pulse generating circuit provided in the embodiment of the present application;

[0030] Figure 3 It is one of the timing diagrams of the pulse generating circuit provided in the embodiment of the present application;

[0031] Figure 4 This is the third schematic diagram of the pulse generating circuit provided in the embodiment of the present application;

[0032] Figure 5 This is the second timing diagram of the pulse generating circuit provided in the embodiment of the present application;

[0033] Figure 6 This is the fourth schematic diagram of the pulse generating circuit provided in the embodiment of the present application;

[0034] Figure 7 This is the third timing diagram of the pulse generating circuit provided in the embodiment of the present application;

[0035] Figure 8 This is the fifth schematic diagram of the pulse generating circuit provided in the embodiment of the present application;

[0036] Fig. 9 This is the fourth timing diagram of the pulse generating circuit provided in the embodiment of the present application;

[0037] Fig.10 This is the sixth schematic diagram of the pulse generating circuit provided in the embodiment of the present application;

[0038] Fig.11 This is the fifth timing diagram of the pulse generating circuit provided in the embodiment of the present application;

[0039] Fig.12 This is the seventh schematic diagram of the pulse generating circuit provided in the embodiment of the present application;

[0040] Fig.13 This is the sixth timing diagram of the pulse generating circuit provided in the embodiment of the present application;

[0041] Fig.14 This is the seventh timing diagram of the pulse generating circuit provided in the embodiment of the present application;

[0042] Fig.15 This is one of the structural schematic diagrams of the driver chip provided in the embodiment of the present application;

[0043] Fig.16 This is one of the operating principle diagrams of the driver chip provided in the embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] As IGBT is widely used in various industries, its corresponding driver IC has also received extensive attention. Among them, the driver IC can receive a 3.3V (V) pulse width modulation (PWM) square wave drive signal provided by an external signal generating unit such as a microcontroller unit (MCU) and a controller, and convert the 3.3V square wave drive signal into a 15V square wave drive signal through a level conversion circuit, and then convert the 15V square wave drive signal into a 615V square wave drive signal through a level conversion circuit to generate the drive current of the IGBT.

[0046] However, current driver ICs usually use level conversion circuits to directly convert lower voltage square wave signals into higher voltage square wave signals, which causes the driver IC to be in a high current state for a long time, resulting in high device loss and reduced reliability of the driver IC. Obviously, if the signal pulse width during the level conversion process can be reduced, the device loss during the level conversion process can be reduced and the reliability of the driver IC can be improved. Therefore, there is an urgent need for a circuit that can convert a square wave signal into a pulse signal with a narrow pulse width to achieve the conversion of the square wave signal.

[0047] Please refer to Figure 1 , which shows a schematic diagram of a pulse generating circuit provided by an embodiment of the present application. The pulse generating circuit converts a square wave signal into a pulse signal with a narrow pulse width. Figure 1 As shown, the pulse generating circuit 1 comprises: a square wave input terminal IN, a first pulse unit 11 and a second pulse unit 12. The square wave input terminal IN is used to receive a square wave signal.

[0048] The first pulse unit 11 includes a first delay module 111 and a first logic processing module 112. The first delay module 111 is connected to the square wave input terminal IN and the first logic processing module 112. The first delay module 111 is used to delay the falling edge of the square wave signal, generate and transmit a first delay signal to the first logic processing module 112. The first logic processing module 112 is used to output a first pulse signal Out1 according to the first delay signal. The high level duration of the first pulse signal Out1 is the duration of the falling edge of the first delay signal.

[0049] The second pulse unit 12 includes a second delay module 121 and a second logic processing module 122. The second delay module 121 is connected to the square wave input terminal IN and the second logic processing module 122. The second delay module 121 is used to delay the rising edge of the square wave signal, generate and transmit a second delay signal to the second logic processing module 122. The second logic processing module 122 is used to output a second pulse signal Out2 according to the second delay signal. The high level duration of the second pulse signal Out2 is the duration of the rising edge of the first delay signal.

[0050] In the embodiment of the present application, the first delay module 111 and the second delay module 121 can both receive the square wave signal output from the square wave input terminal IN. The first delay module 111 can perform delay processing on the falling edge of the received square wave signal to delay the change time of the square wave signal from a high level to a low level, and output the first pulse signal obtained by the delay processing to the first logic processing module 112. The first logic processing module 112 can output a first pulse signal according to the received first delay signal. The high level duration of the first pulse signal is the falling edge duration of the first delay signal, and the pulse width of the first pulse signal is narrower than the pulse width of the square wave signal received by the pulse generating circuit 1, and the first pulse signal can be called a narrow pulse width signal.

[0051] Similarly, the second delay module 121 can delay the rising edge of the received square wave signal to delay the change time of the square wave signal from a low level to a high level, and output the second pulse signal obtained by the delay processing to the second logic processing module 122. The second logic processing module 122 can output a second pulse signal according to the received second delay signal. The duration of the high level of the second pulse signal is the duration of the rising edge of the second delay signal, and the pulse width of the second pulse signal is narrower than the pulse width of the square wave signal received by the pulse generating circuit 1. It is not difficult to understand that the smaller the delay of the first delay module 111 to the falling edge of the square wave signal, the narrower the pulse width of the first pulse signal output by the first logic processing module 112. The smaller the delay of the second delay module 121 to the rising edge of the square wave signal, the narrower the pulse width of the second pulse signal output by the second logic processing module 122, and the second pulse signal can be called a narrow pulse width signal.

[0052] In summary, in the pulse generating circuit provided by the embodiment of the present application, the first delay module in the first pulse unit can delay the falling edge of the square wave signal, generate and transmit the first delay signal to the first logic processing module, so that the first logic processing module can output the first pulse signal according to the first delay signal, and the high level duration of the first pulse signal is the falling edge duration of the first delay signal. The second delay module in the second pulse unit can delay the rising edge of the square wave signal, generate and transmit the second delay signal to the second logic processing module, so that the second logic processing module can output the second pulse signal according to the second delay signal, and the high level duration of the second pulse signal is the rising edge duration of the first delay signal. In this technical solution, the pulse generating circuit can delay the rising and falling edges of the input square wave signal to output a first pulse signal whose high level duration is the falling edge duration, and a second pulse signal whose high level duration is the rising edge duration, and the pulse width of the first pulse signal and the second pulse signal is narrower than the pulse width of the square wave signal, realizing the conversion from the square wave signal to the pulse signal with a narrow pulse width.

[0053] Alternatively, if Figure 2 As shown, the first delay module 111 includes: a first inverter G1 and a first capacitor C1. The first inverter G1 is connected to the square wave input terminal IN, the first end of the first capacitor C1 and the first logic processing module 112. The second end of the first capacitor C1 is grounded.

[0054] The first inverter G1 and the first capacitor C1 are used to coordinate the rising edge and the falling edge of the square wave signal for delay processing, generate and transmit the first delayed signal to the first logic processing module 112. The first inverter G1 is used to invert the square wave signal. The first capacitor C1 and the first inverter G1 coordinate the rising edge and the falling edge of the inverted signal of the square wave signal for delay processing, generate and transmit the first delayed signal to the first logic processing module 112.

[0055] It should be noted that the first capacitor C1 can form a resistor-capacitor circuit (i.e., an RC circuit) with the internal resistor of the first inverter G1, which is used to delay the rising edge and the falling edge of the square wave signal. It should also be noted that the delay time of the rising edge and the falling edge of the square wave signal is positively correlated with the resistance value of the internal resistor of the first inverter G1 and the capacitance value of the first capacitor C1. In some embodiments, the first delay module 111 can also be a delay chain unit, which is used to delay the rising edge and the falling edge of the square wave signal.

[0056] Correspondingly, optionally, the first logic processing module 112 is used to output a high level signal during the rising edge duration period of the first delay signal, and output a low level signal during the remaining period of the first delay signal, so as to obtain a first pulse signal. The remaining period is the period of the first delay signal except the rising edge duration period. For example, please refer to Figure 3 , which shows that the embodiment of the present application provides Figure 2 Partial timing diagram of the pulse generating circuit shown in Figure 1. Figure 3 In represents the square wave signal received by the square wave input terminal. A represents the output signal of the first inverter G1. B represents the output signal of the first delay module 111, that is, the signal of the path node between the first capacitor C1 and the first logic processing module 112, that is, the first delay signal. Out1 represents the output signal of the first logic processing module 112, that is, the first pulse signal. Figure 3 It can be seen that the first pulse signal Out1 output by the first logic processing module 112 is at a high level during the rising edge duration of the signal B (ie, the first delayed signal), and is at a low level during the remaining duration of the signal B.

[0057] In a further alternative case, if Figure 4As shown, the first logic processing module 112 may include: a second inverter G2, a third inverter G3 and a first AND gate L1. The second inverter G2 is connected to the square wave input terminal IN and the first AND gate L1. The third inverter G3 is connected to the first inverter G1 and the first AND gate L1.

[0058] The second inverter G2 is used to invert the square wave signal output from the square wave input terminal IN, and output the inverse signal of the square wave signal to the first AND gate L1. The third inverter G3 is used to receive the first delayed signal output from the first inverter G1, invert the first delayed signal, and output the inverse signal of the first delayed signal to the first AND gate L1. The first AND gate L1 is used to perform a logical AND process on the inverse signal of the square wave signal and the inverse signal of the first delayed signal to obtain the first pulse signal Out1, and output the first pulse signal Out1. Figure 4 In the case shown, the first AND gate L1 performs logical AND processing on the inverse signal of the square wave signal and the inverse signal of the first delayed signal to output a high level signal during the period of the falling edge of the inverse signal of the first delayed signal, and outputs a low level signal during the remaining period of the inverse signal of the first delayed signal to output the first pulse signal Out1.

[0059] For example, see Figure 5 , which shows that the embodiment of the present application provides Figure 4 Partial timing diagram of the pulse generating circuit shown in Figure 1. Figure 4 In represents the square wave signal received by the square wave input terminal. A represents the output signal of the first inverter G1. B represents the output signal of the first delay module 111, that is, the signal of the path node between the first capacitor C1 and the first logic processing module 112, that is, the first delay signal. C represents the output signal of the third inverter G3. D represents the output signal of the second inverter G2. Out1 represents the output signal of the first AND gate L1, that is, the first pulse signal. Figure 5 It can be seen that the first pulse signal Out1 output by the first AND gate L1 is at a high level during the falling edge duration of the signal C (ie, the inverted signal of the first delayed signal), and is at a low level during the remaining duration of the signal C.

[0060] In some embodiments of the present application, the second delay module 121 can be used to delay the falling edge of the inverted signal of the square wave signal, generate and transmit a second delayed signal to the second logic processing module 122 .

[0061] In an optional implementation, Figure 6As shown, the second delay module 121 may include: a fourth inverter G4, a fifth inverter G5, and a second capacitor C2. The fourth inverter G4 is connected to the square wave input terminal IN and the fifth inverter G5. The fifth inverter G5 is also connected to the first end of the second capacitor C2 and the second logic processing module 122. The second end of the second capacitor C2 is grounded.

[0062] The fifth inverter G5 and the second capacitor C2 are used to coordinate the rising edge and the falling edge of the inverted signal of the square wave signal to delay processing, generate and transmit the second delayed signal to the second logic processing module 122. Among them, the fourth inverter G4 is used to invert the square wave signal and output the inverted signal of the square wave signal to the fifth inverter G5. The fifth inverter G5 is used to invert the inverted signal of the square wave signal and output the square wave signal. The second capacitor C2 and the fifth inverter G5 coordinate the rising edge and the falling edge of the inverted signal of the square wave signal (i.e., the input signal of the fifth inverter G5) to delay processing, generate and transmit the second delayed signal to the second logic processing module 122.

[0063] It should be noted that the second capacitor C2 can form a resistor-capacitor circuit (i.e., an RC circuit) with the internal resistance of the fifth inverter G5, which is used to delay the rising edge and falling edge of the inverted signal of the square wave signal. It should also be noted that the delay duration of the rising edge and falling edge of the inverted signal of the square wave signal is positively correlated with the resistance value of the internal resistance of the fifth inverter G5 and the capacitance value of the second capacitor C2. In some embodiments, the second delay module 121 may also include a fourth inverter G4 and a delay chain unit. The fourth inverter G4 is connected to the square wave input terminal IN and the delay chain unit. The fourth inverter G4 is used to invert the square wave signal and output the inverted signal of the square wave signal to the delay chain unit. The delay chain unit is used to delay the rising edge and falling edge of the inverted signal of the square wave signal.

[0064] Correspondingly, optionally, the second logic processing module 122 is used to output a high level signal during the rising edge duration period of the second delay signal, and output a low level signal during the remaining period of the second delay signal, so as to obtain a second pulse signal. The remaining period of the second delay signal is the period of the second delay signal except the rising edge duration period. For example, please refer to Figure 7 , which shows that the embodiment of the present application provides Figure 6 Partial timing diagram of the pulse generating circuit shown in Figure 1. Figure 7In represents the square wave signal received by the square wave input terminal. E represents the output signal of the fourth inverter G4. F represents the output signal of the fifth inverter G5. H represents the output signal of the second delay module 121, that is, the signal of the path node between the second capacitor C2 and the second logic processing module 122, that is, the second delay signal. Out2 represents the output signal of the second logic processing module 122, that is, the second pulse signal. Figure 7 It can be seen that the second pulse signal Out2 output by the second logic processing module 122 is at a high level during the rising edge duration of the signal H (ie, the second delayed signal), and is at a low level during the remaining duration of the signal H.

[0065] Further optionally, if Figure 8 As shown, the second logic processing module 122 includes: an eighth inverter G8, a seventh inverter G7 and a second AND gate L2. The eighth inverter G8 is connected to the second AND gate L2 to receive the inverted signal of the square wave signal. The seventh inverter G7 is connected to the fifth inverter G5 and the second AND gate L2.

[0066] Among them, when the second delay module 121 includes a fourth inverter G4, a fifth inverter G5 and a second capacitor C, the eighth inverter G8 is connected to the fourth inverter G4. The eighth inverter G8 is used to receive the inverted signal of the square wave signal output by the fourth inverter G4. The eighth inverter G8 is used to invert the inverted signal of the square wave signal and output the square wave signal to the second AND gate L2. The seventh inverter G7 is used to receive the second delayed signal output by the fifth inverter G5, invert the second delayed signal, and output the inverted signal of the second delayed signal to the second AND gate L2. The second AND gate L2 is used to perform logical AND processing on the inverted signal of the second delayed signal and the square wave signal to obtain the second pulse signal Out2, and output the second pulse signal Out2. Figure 8 In the case shown, the second AND gate L2 performs logical AND processing on the square wave signal and the inverse signal of the second delayed signal to output a high level signal during the period of the rising edge of the inverse signal of the second delayed signal, and outputs a low level signal during the remaining period of the inverse signal of the second delayed signal to output the second pulse signal Out2.

[0067] For example, see Fig. 9 , which shows that the embodiment of the present application provides Figure 8 Partial timing diagram of the pulse generating circuit shown in Figure 1. Figure 8In represents the square wave signal received by the square wave input terminal. E represents the output signal of the fourth inverter G4. F represents the output signal of the fifth inverter G5. H represents the output signal of the second delay module 121, that is, the signal of the path node between the second capacitor C2 and the second logic processing module 122, that is, the second delay signal. I represents the output signal of the seventh inverter G7. J represents the output signal of the eighth inverter G8. Out2 represents the output signal of the second AND gate L2, that is, the second pulse signal. Fig. 9 It can be seen that the second pulse signal Out2 output by the second AND gate L2 is at a high level during the falling edge duration of the signal I (ie, the inverted signal of the second delayed signal), and is at a low level during the remaining duration of the signal I.

[0068] In another optional implementation, in the first logic processing module 112: Figure 4 In the case of the first logic processing module 112 shown in the figure, that is, if the first logic processing module 112 includes a second inverter G2, a third inverter G3 and a first AND gate L1. The second inverter G2 is connected to the square wave input terminal IN and the first AND gate L1. The third inverter G3 is connected to the first inverter G1 and the first AND gate L1. Then Fig.10 As shown, the second delay module 121 includes: a sixth inverter G6 and a third capacitor C3.

[0069] The sixth inverter G6 is connected to the second inverter G2, the first end of the third capacitor C3, and the second logic processing module 122. The second end of the third capacitor C3 is grounded. The sixth inverter G6 and the third capacitor C3 are used to coordinate the rising edge and the falling edge of the inverted signal of the square wave signal to delay processing, generate and transmit the second delayed signal to the second logic processing module 122. The sixth inverter G6 is used to receive the inverted signal of the square wave signal output by the second inverter G2, and perform inversion processing on the inverted signal of the square wave signal. The third capacitor C3 and the sixth inverter G6 coordinate the rising edge and the falling edge of the inverted signal of the square wave signal to delay processing, generate and transmit the second delayed signal to the second logic processing module 122.

[0070] It should be noted that the third capacitor C3 can form a resistor-capacitor circuit (i.e., an RC circuit) with the internal resistor of the sixth inverter G6, which is used to delay the rising edge and falling edge of the inverted signal of the square wave signal. It should also be noted that the delay time of the rising edge and falling edge of the inverted signal of the square wave signal is positively correlated with the resistance value of the internal resistor of the sixth inverter G6 and the capacitance value of the third capacitor C3. In some embodiments, the second delay module 121 can also be a delay chain unit, which is used to delay the rising edge and falling edge of the inverted signal of the square wave signal.

[0071] Correspondingly, optionally, the second logic processing module 122 is used to output a high level signal during the rising edge duration period of the second delay signal, and output a low level signal during the remaining period of the second delay signal, so as to obtain a second pulse signal. The remaining period of the second delay signal is the period of the second delay signal except the rising edge duration period. For example, please refer to Fig.11 , which shows that the embodiment of the present application provides Fig.10 Partial timing diagram of the pulse generating circuit shown in Figure 1. Fig.11 In represents the square wave signal received by the square wave input terminal. D represents the output signal of the second inverter G2. F represents the output signal of the fifth inverter G5. H represents the output signal of the second delay module 121, that is, the signal of the path node between the second capacitor C2 and the second logic processing module 122, that is, the second delay signal. Out2 represents the output signal of the second logic processing module 122, that is, the second pulse signal. Fig.11 It can be seen that the second pulse signal Out2 output by the second logic processing module 122 is at a high level during the rising edge duration of the signal H (ie, the second delayed signal), and is at a low level during the remaining duration of the signal H.

[0072] Further optionally, if Fig.12 As shown, the second logic processing module 122 includes: an eighth inverter G8, a seventh inverter G7 and a second AND gate L2. The eighth inverter G8 is connected to the second AND gate L2 to receive the inverted signal of the square wave signal. The seventh inverter G7 is connected to the fifth inverter G5 and the second AND gate L2.

[0073] Among them, when the second delay module 121 includes the sixth inverter G6 and the third capacitor C3, the eighth inverter G8 is connected to the sixth inverter G6. The eighth inverter G8 is used to receive the inverted signal of the square wave signal output by the sixth inverter G6. The eighth inverter G8 is used to invert the inverted signal of the square wave signal and output the square wave signal to the second AND gate L2. The seventh inverter G7 is used to receive the second delayed signal output by the fifth inverter G5, invert the second delayed signal, and output the inverted signal of the second delayed signal to the second AND gate L2. The second AND gate L2 is used to perform logical AND processing on the inverted signal of the second delayed signal and the square wave signal to obtain the second pulse signal Out2, and output the second pulse signal Out2. Fig.12 In the case shown, the second AND gate L2 performs logical AND processing on the square wave signal and the inverse signal of the second delayed signal to output a high level signal during the period of the rising edge of the inverse signal of the second delayed signal, and outputs a low level signal during the remaining period of the inverse signal of the second delayed signal to output the second pulse signal Out2.

[0074] For example, see Fig.13 , which shows that the embodiment of the present application provides Fig.12 Partial timing diagram of the pulse generating circuit shown in Figure 1. Fig.13 In represents the square wave signal received by the square wave input terminal. D represents the output signal of the second inverter G2. F represents the output signal of the fifth inverter G5. H represents the output signal of the second delay module 121, that is, the signal of the passage node between the second capacitor C2 and the second logic processing module 122, that is, the second delay signal. I represents the output signal of the seventh inverter G7. J represents the output signal of the eighth inverter G8. Out2 represents the output signal of the second AND gate L2, that is, the second pulse signal. Fig.13 It can be seen that the second pulse signal Out2 output by the second AND gate L2 is at a high level during the falling edge duration of the signal I (ie, the inverted signal of the second delayed signal), and is at a low level during the remaining duration of the signal I.

[0075] In order to facilitate understanding of the pulse generating circuit 1 provided by the present application, the pulse generating circuit 1 of the technical solution of the present application is schematically illustrated by the following example. Fig.12 As shown, the pulse generating circuit 1 comprises: a square wave input terminal IN, a first pulse unit 11 and a second pulse unit 12. The square wave input terminal IN is used to receive a square wave signal.

[0076] Wherein, the first pulse unit 11 includes a first delay module 111 and a first logic processing module 112. The first delay module 111 includes: a first inverter G1 and a first capacitor C1. The first inverter G1 is connected to the square wave input terminal IN, the first end of the first capacitor C1 and the first logic processing module 112. The second end of the first capacitor C1 is grounded. The first logic processing module 112 may include: a second inverter G2, a third inverter G3 and a first AND gate L1. The second inverter G2 is connected to the square wave input terminal IN and the first AND gate L1. The third inverter G3 is connected to the first inverter G1 and the first AND gate L1.

[0077] The second pulse unit 12 includes a second delay module 121 and a second logic processing module 122. The second delay module 121 includes: a sixth inverter G6 and a third capacitor C3. The sixth inverter G6 is connected to the second inverter G2, the first end of the third capacitor C3 and the second logic processing module 122. The second end of the third capacitor C3 is grounded. The second logic processing module 122 includes: an eighth inverter G8, a seventh inverter G7 and a second AND gate L2. The eighth inverter G8 is connected to the second AND gate L2. The eighth inverter G8 is connected to the sixth inverter G6. The seventh inverter G7 is connected to the fifth inverter G5 and the second AND gate L2.

[0078] Please refer to Fig.14 , which shows that the embodiment of the present application provides Fig.12 Partial timing diagram of the pulse generating circuit shown in Figure 1. Fig.14 In represents the square wave signal received by the square wave input terminal. A represents the output signal of the first inverter G1. B represents the output signal of the first delay module 111, that is, the signal of the path node between the first capacitor C1 and the first logic processing module 112, that is, the first delay signal. C represents the output signal of the third inverter G3. D represents the output signal of the second inverter G2. F represents the output signal of the fifth inverter G5. H represents the output signal of the second delay module 121, that is, the signal of the path node between the second capacitor C2 and the second logic processing module 122, that is, the second delay signal. I represents the output signal of the seventh inverter G7. J represents the output signal of the eighth inverter G8. Out1 represents the output signal of the first AND gate L1, that is, the first pulse signal. Out2 represents the output signal of the second AND gate L2, that is, the second pulse signal. By Fig.14 It can be seen that the first pulse signal Out1 output by the first AND gate L1 is at a high level during the duration of the falling edge of the signal C (i.e., the inverted signal of the first delayed signal), and is at a low level during the remaining period of the signal C. The second pulse signal Out2 output by the second AND gate L2 is at a high level during the duration of the falling edge of the signal I (i.e., the inverted signal of the second delayed signal), and is at a low level during the remaining period of the signal I.

[0079] In the present application embodiment Fig.12 In the pulse generating circuit shown, the received square wave signal can be first inverted by the first inverter G1 to obtain signal A. The square wave signal is delayed by the first capacitor C1 in cooperation with the internal resistance of the first inverter G1 to obtain signal B. Afterwards, the signal B is inverted by the third inverter G3 to obtain signal C. In addition, the square wave signal is inverted by the second inverter G2 to obtain signal D, and the signal C and the signal D are logically ANDed by the first AND gate L1 to obtain the first pulse signal Out1. In the pulse generating circuit, the signal D can also be inverted by the sixth inverter G6 to obtain signal F.

[0080] The signal F is delayed by the second capacitor C2 in cooperation with the internal resistance of the sixth inverter G6 to obtain a signal H. Then, the signal H is inverted by the seventh inverter G7 to obtain a signal I. In addition, the signal D is inverted by the eighth inverter G8 to obtain a signal J, and the signal I and the signal J are logically ANDed by the second AND gate L2 to obtain a second pulse signal Out2.

[0081] In the embodiment of the present application, the pulse generating circuit 1 can be composed of six inverters, two capacitors and two AND gates. The pulse generating circuit in the related art usually includes: a square wave receiving end, twelve inverters INV1-INV12, two P-type metal oxide semiconductor field effect transistors (Positive Channel Metal Oxide Semiconductor, PMOS) P1-P2, two N-type metal oxide semiconductor field effect transistors (N-Metal Oxide Semiconductor, NMOS) N1-N2, two resistors R1-R2, two capacitors CR1-CR2 and two NOR gates NOR1-NOR2. Among them, the square wave receiving end is used to receive a square wave signal.

[0082] The gate of PMOS P1 is connected to the square wave receiving end, the source of PMOS P1 is connected to the power supply end, and the drain of PMOS P1 is connected to one end of resistor R1, inverter INV1, and one end of capacitor CR1 respectively. The gate of NMOS N1 is connected to the square wave receiving end, the drain of NMOS N1 is connected to the other end of resistor R1, and the source of NMOS N1 is connected to the common end. The other end of capacitor CR1 is also connected to the common end. Inverter INV1 is also connected to the input end of NOR gate NOR1 through inverter INV2 and inverter INV3 in sequence. Inverter INV4 is connected to the square wave receiving end and the input end of NOR gate NOR1. The output end of NOR gate NOR1 is also connected to inverter INV5, inverter INV6, and the first pulse signal output end in sequence.

[0083] The gate of PMOS P2 is connected to inverter INV4, the source of PMOS P2 is connected to the power supply terminal, and the drain of PMOS P2 is connected to one end of resistor R2, inverter INV7, and one end of capacitor CR2 respectively. The gate of NMOS N2 is connected to inverter INV4, the drain of NMOS N2 is connected to the other end of resistor R2, and the source of NMOS N2 is connected to the common terminal. The other end of capacitor CR2 is also connected to the common terminal. Inverter INV7 is also connected to the input end of NOR gate NOR2 through inverter INV8 and inverter INV9 in turn. Inverter INV10 is connected to the input end of inverter INV4 and NOR gate NOR2. The output end of NOR gate NOR2 is also connected to inverter INV11, inverter INV12, and the second pulse signal output end in turn. The pulse generating circuit 1 converts the square wave signal provided by the square wave input end into two narrow pulse width pulse signals, which are output through the first pulse signal output end and the second pulse signal output end respectively. Obviously, the pulse generating circuit 1 in the embodiment of the present application has the characteristics of low circuit complexity, simple structure, few components and high reliability.

[0084] In summary, in the pulse generating circuit provided by the embodiment of the present application, the first delay module in the first pulse unit can delay the falling edge of the square wave signal, generate and transmit the first delay signal to the first logic processing module, so that the first logic processing module can output the first pulse signal according to the first delay signal, and the high level duration of the first pulse signal is the falling edge duration of the first delay signal. The second delay module in the second pulse unit can delay the rising edge of the square wave signal, generate and transmit the second delay signal to the second logic processing module, so that the second logic processing module can output the second pulse signal according to the second delay signal, and the high level duration of the second pulse signal is the rising edge duration of the first delay signal. In this technical solution, the pulse generating circuit can delay the rising and falling edges of the input square wave signal to output a first pulse signal whose high level duration is the falling edge duration, and a second pulse signal whose high level duration is the rising edge duration, and the pulse width of the first pulse signal and the second pulse signal is narrower than the pulse width of the square wave signal, realizing the conversion from the square wave signal to the pulse signal with a narrow pulse width.

[0085] The embodiment of the present application also provides a driver chip. The driver chip may include the pulse generating circuit provided in the embodiment of the present application. Optionally, the driver chip may include the pulse generating circuit provided in the embodiment of the present application. Figure 1 , Figure 2 , Figure 4 , Figure 6 , Figure 8 , Fig.10 or Fig.12 The pulse generating circuit shown.

[0086] In some embodiments of the present application, Fig.15 As shown, the driver chip also includes: an interface logic circuit 2, a first level conversion circuit 3, a pulse generating circuit 1, a second level conversion circuit 4, a pulse recovery circuit 5 and an output driving circuit 6. The interface logic circuit 2 is sequentially connected to the first level conversion circuit 3, the pulse generating circuit 1, the second level conversion circuit 4, the pulse recovery circuit 5 and the output driving circuit 6. The pulse generating circuit 1 is a pulse generating circuit provided in an embodiment of the present application.

[0087] Among them, the interface logic circuit 2 can be used to receive a square wave signal of a first voltage provided by an external signal generating unit, and filter the noise in the square wave signal to improve the compatibility of the square wave signal. The interface logic circuit 2 can be used to output the square wave signal after noise is filtered to the first level conversion circuit 3. The first level conversion circuit 3 is used to convert the square wave signal of the first voltage into a square wave signal of the second voltage, and output the square wave signal of the second voltage to the pulse generating circuit 1. The second voltage is greater than the first voltage. The pulse generating circuit 1 is used to convert the received square wave signal of the second voltage into a first pulse signal and a second pulse signal, and output the first pulse signal and the second pulse signal to the second level conversion circuit 4. The first pulse signal and the second pulse signal are pulse signals of the second voltage, and the pulse width of the first pulse signal and the second pulse signal is less than the square wave signal of the second voltage.

[0088] The second level conversion circuit 4 is used to convert the first pulse signal of the second voltage into the first pulse signal of the third voltage, and convert the second pulse signal of the second voltage into the second pulse signal of the third voltage, and output the first pulse signal of the third voltage and the second pulse signal of the third voltage to the pulse recovery circuit 5. The third voltage is much greater than the second voltage. The pulse recovery circuit 5 is used to restore the square wave signal of the third voltage according to the first pulse signal of the third voltage and the second pulse signal of the third voltage, and output the square wave signal of the third voltage to the output drive circuit 6. The output drive circuit 6 is used to generate the driving current of the IGBT according to the square wave drive signal of the third voltage, so as to make the IGBT emit light.

[0089] In an embodiment of the present application, when the driver chip needs to convert the square wave signal of the second voltage into a square wave signal of the third voltage which is much larger than the second voltage, the pulse generating circuit 1 is used to first convert the square wave signal of the second voltage into a narrow pulse signal of the second voltage (i.e., the first pulse signal and the second pulse signal), thereby converting the narrow pulse signal of the second voltage into a narrow pulse signal of the third voltage. Then, the narrow pulse signal of the third voltage is restored to the square wave signal of the third voltage to realize the conversion of the square wave signal. In this way, since the signal pulse width in the level conversion process is reduced, the device loss in the level conversion process is reduced, thereby effectively improving the reliability of the driver chip and effectively optimizing the driver chip circuit.

[0090] In some embodiments of the present application, the interface logic circuit 2 can be used to output a square wave signal after noise is filtered to the pulse generating circuit 1. The pulse generating circuit 1 is also used to convert the square wave signal of the first voltage into a third pulse signal and a fourth pulse signal, and output the third pulse signal and the fourth pulse signal to the first level conversion circuit 3. The third pulse signal and the fourth pulse signal are pulse signals of the first voltage, and the pulse width of the third pulse signal and the fourth pulse signal is smaller than the square wave signal of the first voltage.

[0091] The first level conversion circuit 3 converts the third pulse signal of the first voltage into the third pulse signal of the second voltage, and converts the fourth pulse signal of the first voltage into the fourth pulse signal of the second voltage, and outputs the third pulse signal of the second voltage and the fourth pulse signal of the second voltage to the pulse recovery circuit 5. The pulse recovery circuit 5 is also used to recover the square wave signal of the second voltage according to the third pulse signal of the second voltage and the fourth pulse signal of the second voltage.

[0092] In an embodiment of the present application, the driver chip can further use the pulse generating circuit 1 to convert the square wave signal of the first voltage into a narrow pulse signal of the first voltage (i.e., the third pulse signal and the fourth pulse signal) when it is necessary to convert the square wave signal of the first voltage into a square wave signal of the second voltage greater than the first voltage, thereby converting the narrow pulse signal of the first voltage into a narrow pulse signal of the second voltage. Then, the narrow pulse signal of the second voltage is restored to the square wave signal of the second voltage to achieve the conversion of the square wave signal. In this way, since the signal pulse width in the level conversion process is further reduced, the device loss in the level conversion process is further reduced, thereby effectively improving the reliability of the driver chip and further effectively optimizing the driver chip circuit.

[0093] For example, it is assumed that the first voltage is 3.3V, the second voltage is 15V, and the third voltage is 6.15V. The external signal generating unit may be an MCU, a controller, etc., which is used to provide a PWM square wave driving signal (a square wave signal). Fig.16 As shown, the 3.3V voltage PWM square wave driving signal provided by the MCU is referred to as the 3.3V square wave signal. The control method of the driver chip includes:

[0094] The control interface logic circuit 2 receives the 3.3V square wave signal provided by the MCU, filters out the noise in the 3.3V square wave signal, and improves the compatibility of the pulse signal. The control first level conversion circuit 3, i.e., the 3.3V-15V level conversion circuit, receives the 3.3V square wave signal output by the interface logic circuit 2, and converts the 3.3V square wave signal into a square wave signal of 15V voltage, referred to as the 15V square wave signal. The control pulse generating circuit 1 receives the 15V square wave signal, and converts the 15V square wave signal into an extremely narrow narrow pulse signal, which is a pulse signal of 15V voltage, referred to as the 15V narrow pulse signal. The control second level conversion circuit 4, i.e., the 15V-615V level conversion circuit, converts the 15V narrow pulse signal into a narrow pulse signal of 615V voltage, referred to as the 615V narrow pulse signal. The control pulse recovery circuit 5 receives the 615V narrow pulse signal, and converts the 615V narrow pulse signal into a square wave signal of 615V voltage, referred to as the 615V square wave signal. The control output drive circuit 6 receives the 615V square wave signal and generates a drive current for the IGBT to make the IGBT emit light.

[0095] In summary, in the driver chip provided by the embodiment of the present application, the first delay module in the first pulse unit in the pulse generating circuit can delay the falling edge of the square wave signal, generate and transmit the first delay signal to the first logic processing module, so that the first logic processing module can output the first pulse signal according to the first delay signal, and the high level duration of the first pulse signal is the duration of the falling edge of the first delay signal. The second delay module in the second pulse unit can delay the rising edge of the square wave signal, generate and transmit the second delay signal to the second logic processing module, so that the second logic processing module can output the second pulse signal according to the second delay signal, and the high level duration of the second pulse signal is the duration of the rising edge of the first delay signal. In this technical solution, the pulse generating circuit can delay the rising edge and falling edge of the input square wave signal to output a first pulse signal whose high level duration is equal to the duration of the falling edge, and a second pulse signal whose high level duration is equal to the duration of the rising edge. The pulse widths of the first pulse signal and the second pulse signal are narrower than the pulse width of the square wave signal, thereby realizing the conversion from a square wave signal to a pulse signal with a narrower pulse width.

[0096] The embodiment of the present application also provides an electronic device, which may include the pulse generating circuit provided by the embodiment of the present application. Alternatively, the electronic device may include the driver chip provided by the embodiment of the present application. In this way, in the electronic device provided by the embodiment of the present application, the first delay module in the first pulse unit in the pulse generating circuit may delay the falling edge of the square wave signal, generate and transmit a first delay signal to the first logic processing module, so that the first logic processing module may output a first pulse signal according to the first delay signal, and the high level duration of the first pulse signal is the duration of the falling edge of the first delay signal. The second delay module in the second pulse unit may delay the rising edge of the square wave signal, generate and transmit a second delay signal to the second logic processing module, so that the second logic processing module may output a second pulse signal according to the second delay signal, and the high level duration of the second pulse signal is the duration of the rising edge of the first delay signal. In this technical solution, the pulse generating circuit can delay the rising edge and falling edge of the input square wave signal to output a first pulse signal whose high level duration is equal to the duration of the falling edge, and a second pulse signal whose high level duration is equal to the duration of the rising edge. The pulse widths of the first pulse signal and the second pulse signal are narrower than the pulse width of the square wave signal, thereby realizing the conversion from a square wave signal to a pulse signal with a narrower pulse width.

[0097] Optionally, the electronic device may further include a processor and a memory. The memory is used to store a computer program. The processor is used to implement the control method of the driver chip in the method embodiment of the present application when executing the program stored in the memory.

[0098] The embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the control method of the above-mentioned driver chip is implemented. Wherein, the processor is the processor in the electronic device in the above-mentioned embodiment. The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0099] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A pulse generating circuit, characterized in that: The pulse generating circuit comprises: a square wave input end, a first pulse unit and a second pulse unit, wherein the square wave input end is used to receive a square wave signal; The first pulse unit comprises a first delay module and a first logic processing module, wherein the first delay module is connected to the square wave input terminal and the first logic processing module; The first delay module is used to delay the falling edge of the square wave signal, generate and transmit a first delay signal to the first logic processing module; The first logic processing module is used to output a first pulse signal according to the first delay signal, and the high level duration of the first pulse signal is the falling edge duration of the first delay signal; The second pulse unit comprises a second delay module and a second logic processing module, and the second delay module is connected to the square wave input terminal and the second logic processing module; The second delay module is used to delay the rising edge of the square wave signal, generate and transmit a second delay signal to the second logic processing module; The second logic processing module is used to output a second pulse signal according to the second delay signal, and the high level duration of the second pulse signal is the rising edge duration of the first delay signal.

2. The pulse generating circuit according to claim 1, characterized in that: The first delay module includes: a first inverter and a first capacitor; The first inverter is connected to the square wave input terminal, the first terminal of the first capacitor and the first logic processing module, and the second terminal of the first capacitor is grounded; The first inverter and the first capacitor are used to cooperate in delaying the rising edge and the falling edge of the square wave signal to generate and transmit the first delayed signal to the first logic processing module.

3. The pulse generating circuit according to claim 2, characterized in that: The first logic processing module is used to output a high-level signal during the rising edge duration period of the first delay signal, and output a low-level signal during the remaining period of the first delay signal to obtain the first pulse signal, and the remaining period is the period of the first delay signal except the rising edge duration period.

4. The pulse generating circuit according to claim 3, characterized in that: The first logic processing module includes: a second inverter, a third inverter and a first AND gate; The second inverter is connected to the square wave input terminal and the first AND gate, and the third inverter is connected to the first inverter and the first AND gate.

5. The pulse generating circuit according to claim 1, characterized in that: The second delay module is used to delay the falling edge of the inverted signal of the square wave signal, generate and transmit a second delayed signal to the second logic processing module.

6. The pulse generating circuit according to claim 5, characterized in that: The second delay module includes: a fourth inverter, a fifth inverter and a second capacitor; The fourth inverter is connected to the square wave input terminal and the fifth inverter, the fifth inverter is also connected to the first terminal of the second capacitor and the second logic processing module, and the second terminal of the second capacitor is grounded; The fifth inverter and the second capacitor are used to cooperate in delaying the rising edge and the falling edge of the inverted signal to generate and transmit a second delayed signal to the second logic processing module.

7. The pulse generating circuit according to claim 5, characterized in that: The first logic processing module includes a second inverter, a third inverter and a first AND gate; the second inverter is connected to the square wave input terminal and the first AND gate, and the third inverter is connected to the first inverter and the first AND gate; The second delay module includes: a sixth inverter and a third capacitor; the sixth inverter is connected to the second inverter, the first end of the third capacitor and the second logic processing module, and the second end of the third capacitor is grounded; The sixth inverter and the third capacitor are used to cooperate in delaying the rising edge and the falling edge of the inverted signal to generate and transmit a second delayed signal to the second logic processing module.

8. The pulse generating circuit according to claims 5 to 7, characterized in that: The second logic processing module is used to output a high-level signal during the rising edge duration period of the second delay signal, and output a low-level signal during the remaining period of the second delay signal to obtain the second pulse signal, and the remaining period of the second delay signal is the period of the second delay signal except the rising edge duration period.

9. The pulse generating circuit according to claim 8, characterized in that: The second logic processing module includes: an eighth inverter, a seventh inverter and a second AND gate; The eighth inverter is connected to the second AND gate and is used to receive the inverted signal of the square wave signal. The seventh inverter is connected to the fifth inverter and the second AND gate.

10. The pulse generating circuit according to claim 9, characterized in that: The second delay module includes a fourth inverter, a fifth inverter and a second capacitor, and the eighth inverter is connected to the fourth inverter; Alternatively, the second delay module includes: a sixth inverter and a third capacitor, and the eighth inverter is connected to the second inverter.

11. A driver chip IC, characterized in that: The driver IC includes the pulse generating circuit according to any one of claims 1 to 10.

12. An electronic device, characterized in that: The electronic device comprises the driver chip IC according to claim 11.

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