Serial port data wake-up circuit and method
By designing a serial port data wake-up circuit and using synchronization and displacement pulses to drive the shift register, the CPU wake-up complexity problem in low-power systems is solved, and a simple circuit design and normal serial port data reception are achieved.
Patent Information
- Application Number
- CN202411466529.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-02-11
AI Technical Summary
In low-power systems, CPUs and their peripheral devices enter a power-saving state when there is no data communication. When awakening these devices for data communication, complex state synchronization is required, resulting in complex software and hardware system design.
Design a serial port data wake-up circuit, including an interrupt wake-up module, a synchronization signal generation module, a displacement drive generation module and a data cache displacement module, generate synchronization pulses through the source signal RX, further generate displacement pulses, and drive shift registers for latch and displacement , until the CPU enters normal operating mode.
The system design is simplified, and the CPU is driven to communicate with the data through delay. After the delay is over, the CPU has entered the normal working mode, which is convenient for normal reception of serial port data, and the circuit design is simple and easy to promote.
Smart Images
Figure CN119420326A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of sleep awakening, and in particular to a serial port data awakening circuit and method. Background Art
[0002] In low-power system design, when there is no data communication, the CPU and its peripherals will enter a power-saving state. When the outside world needs to communicate with the system, it is often necessary to wake up the CPU system through a specific IO pin to put it into normal working mode, and then data communication can be carried out through the data exchange peripheral interface.
[0003] In this way, the status synchronization between systems is required, which will complicate the design of software and hardware systems and requires improvement. Summary of the invention
[0004] The purpose of the present invention is to provide a serial port data wake-up circuit and method to solve the problems raised in the above background technology.
[0005] To achieve the above object, the present invention provides the following technical solutions: A serial port data wake-up circuit, comprising: The interrupt wake-up module is used to use the source signal RX as the wake-up source and output it to the IO pin that wakes up the CPU; A synchronization signal generation module is used to generate a single pulse with a certain pulse width as a synchronization pulse based on the falling edge of the source signal RX, and output it to the displacement drive generation module; The displacement drive generation module is used to generate a displacement pulse when receiving a synchronization pulse, so that the data cache displacement module performs a latch and displacement; at the same time, it starts to reset the count until the next data signal arrives, and then generates a displacement pulse again and outputs it to the data cache displacement module; A data cache shift module, used for shifting under a shift driving signal, determining a final number of shifts based on the number of shift registers, and ending the shift after the final number of shifts; The output end of the interrupt wake-up module is connected to the IO pin of the CPU and the input end of the synchronization signal generation module, the output end of the synchronization signal generation module is connected to the input end of the displacement drive generation module, and the output end of the displacement drive generation module is connected to the input end of the data buffer displacement module.
[0006] As a further solution of the present invention: the synchronization signal generation module includes a first NOT gate, a first MOS tube, a second MOS tube, a first resistor, and a first capacitor. The input end of the first NOT gate is input with a source signal RX, the output end of the first NOT gate is connected to the G pole of the first MOS tube and the G pole of the second MOS tube, the S pole of the first MOS tube is connected to the power supply voltage VCC, the D pole of the first MOS tube is connected to the D pole of the second MOS tube and one end of the first capacitor, the S pole of the second MOS tube is connected to one end of the first resistor and the input end of the displacement drive generation module, the other end of the first resistor is grounded, and the other end of the first capacitor is grounded.
[0007] As a further solution of the present invention: the displacement drive generation module includes a second XOR gate, a third NOT gate, a counter, and a clock buffer. The clock signal CLOCK is introduced into the input end of the clock buffer, the output end of the clock buffer is connected to the first input end of the counter, the output end of the counter is connected to the first input end of the second XOR gate, the second input end of the second XOR gate is connected to the output end of the synchronization signal generation module, the output end of the second XOR gate is connected to the input end of the third NOT gate and the input end of the data buffer displacement module, and the output end of the third NOT gate is connected to the second input end of the counter.
[0008] As a further solution of the present invention: the data buffer shift module includes at least one shift register. When there are multiple shift registers, the shift registers are connected in series.
[0009] A serial port data wake-up method is applied to the serial port data wake-up circuit as described above, and the serial port data wake-up method comprises the following steps: Step 1, generating a synchronization pulse signal based on a source signal RX; Step 2, generating a displacement pulse signal based on the synchronization pulse signal; Step 3, based on the shift pulse signal, the shift register is latched and shifted. When the data is shifted to the end of the shift register, the CPU enters the normal working mode and receives the serial port data normally.
[0010] As a further solution of the present invention: Step 1 specifically comprises: Step 11, receiving a source signal RX output to an IO pin of the CPU; Step 12: Generate a synchronization pulse signal based on the falling edge of the source signal RX.
[0011] As a further solution of the present invention: Step 2 specifically includes: Step 21, the clock signal CLOCK is sequentially output to the second XOR gate through the clock buffer and the counter; Step 22, the synchronization pulse signal is output to the second XOR gate; Step 23: The second XOR gate generates a displacement pulse signal based on the input signal.
[0012] Compared with the prior art, the beneficial effect of the present invention is that after the source signal RX wakes up the CPU, the present invention delays driving the CPU to perform data communication through the synchronization signal generation module, the displacement drive generation module, and the data cache displacement module. After the delay ends, the CPU has entered the normal working mode and can receive serial port data normally. The circuit design is simple and easy to promote. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 The figure is a schematic diagram of a serial port data wake-up circuit.
[0014] Figure 2 Circuit diagram of the synchronization signal generation module.
[0015] Figure 3 Generate a circuit diagram for the displacement drive module. DETAILED DESCRIPTION
[0016] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0017] See also Figure 1 , a serial port data wake-up circuit, comprising: The interrupt wake-up module is used to use the source signal RX as the wake-up source and output it to the IO pin that wakes up the CPU; A synchronization signal generation module is used to generate a single pulse with a certain pulse width as a synchronization pulse based on the falling edge of the source signal RX, and output it to the displacement drive generation module; The displacement drive generation module is used to generate a displacement pulse when receiving a synchronization pulse, so that the data cache displacement module performs a latch and displacement; at the same time, it starts to reset the count until the next data signal arrives, and then generates a displacement pulse again and outputs it to the data cache displacement module; A data cache shift module, used for shifting under a shift driving signal, determining a final number of shifts based on the number of shift registers, and ending the shift after the final number of shifts; The output end of the interrupt wake-up module is connected to the IO pin of the CPU and the input end of the synchronization signal generation module, the output end of the synchronization signal generation module is connected to the input end of the displacement drive generation module, and the output end of the displacement drive generation module is connected to the input end of the data buffer displacement module.
[0018] In this example: See Figure 2The synchronization signal generating module includes a first NOT gate U1, a first MOS tube Q1, a second MOS tube Q2, a first resistor R1, and a first capacitor C1. The input end of the first NOT gate U1 inputs a source signal RX. The output end of the first NOT gate U1 is connected to the G pole of the first MOS tube Q1 and the G pole of the second MOS tube Q2. The S pole of the first MOS tube Q1 is connected to the power supply voltage VCCVCC. The D pole of the first MOS tube Q1 is connected to the D pole of the second MOS tube Q2 and one end of the first capacitor C1. The S pole of the second MOS tube Q2 is connected to one end of the first resistor R1 and the input end of the displacement drive generating module. The other end of the first resistor R1 is grounded, and the other end of the first capacitor C1 is grounded.
[0019] When the source signal RX is a falling edge, it passes through the first NOT gate U1 to be a high level, driving the second MOS tube Q2 to be turned on. At this time, the electric energy stored in the first capacitor C1 provides the second MOS tube Q2 to output a high level. When the source signal RX is a rising edge, it passes through the first NOT gate U1 to be a low level, driving the first MOS tube Q1 to be turned on, charging the first capacitor C1, and so on and so forth, so that the second MOS tube Q2 outputs a single pulse with a certain pulse width as a synchronous pulse signal based on the source signal RX.
[0020] In this example: See Figure 3 The displacement drive generation module includes a second XOR gate U2, a third NOT gate U3, a counter, and a clock buffer. The input end of the clock buffer introduces a clock signal CLOCK, the output end of the clock buffer is connected to the first input end of the counter, the output end of the counter is connected to the first input end of the second XOR gate U2, the second input end of the second XOR gate U2 is connected to the output end of the synchronization signal generation module, the output end of the second XOR gate U2 is connected to the input end of the third NOT gate U3 and the input end of the data buffer displacement module, and the output end of the third NOT gate U3 is connected to the second input end of the counter.
[0021] The clock signal CLOCK passes through the clock buffer and the counter, and the counter overflow signal is input to the first input terminal of the second XOR gate U2. The synchronization pulse signal is input to the second input terminal of the second XOR gate U2. A high level is output based on the difference in the input levels of the XOR gate, so that a displacement pulse signal is output through the second XOR gate U2. The counter period is determined by the baud rate of the data. In the presence of the synchronization pulse signal, the feedback signal through the third NOT gate U3 controls the accumulated error of the counter.
[0022] In this example: See Figure 1 The data buffer shift module includes at least one shift register. When there are multiple shift registers, the shift registers are connected in series.
[0023] Receive the shift pulse signal to shift once. When the counter starts to reset and counts to the next data signal, it generates a shift pulse again, causing the shift register to latch and shift once. When the data is shifted to the end of the register, the CPU has entered the normal working mode, and the serial port data can be received normally. The number of shift bits is determined by the buffer buffer time.
[0024] In this example: See Figure 1 , Figure 2 and Figure 3 , a serial port data wake-up method, applied to the serial port data wake-up circuit as described above, the serial port data wake-up method comprising the following steps: Step 1, generating a synchronization pulse signal based on a source signal RX; Step 2, generating a displacement pulse signal based on the synchronization pulse signal; Step 3, based on the shift pulse signal, the shift register is latched and shifted. When the data is shifted to the end of the shift register, the CPU enters the normal working mode and receives the serial port data normally.
[0025] In this example: See Figure 1 and Figure 2 , step 1 specifically includes: Step 11, receiving a source signal RX output to an IO pin of the CPU; Step 12: Generate a synchronization pulse signal based on the falling edge of the source signal RX.
[0026] In this example: See Figure 1 and Figure 3 , step 2 specifically includes: Step 21, the clock signal CLOCK is sequentially output to the second XOR gate U2 through the clock buffer and the counter; Step 22, the synchronization pulse signal is output to the second XOR gate U2; Step 23: The second XOR gate U2 generates a displacement pulse signal based on the input signal.
[0027] After the source signal RX wakes up the CPU, the present invention delays driving the CPU to perform data communication through a synchronization signal generation module, a displacement drive generation module, and a data cache displacement module. After the delay ends, the CPU has entered a normal working mode and can receive serial port data normally. The circuit design is simple and easy to promote.
[0028] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and range of equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.
[0029] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A serial port data wake-up circuit, characterized in that: The serial port data wake-up circuit includes: The interrupt wake-up module is used to use the source signal RX as the wake-up source and output it to the IO pin that wakes up the CPU; A synchronization signal generation module is used to generate a single pulse with a certain pulse width as a synchronization pulse based on the falling edge of the source signal RX, and output it to the displacement drive generation module; The displacement drive generation module is used to generate a displacement pulse when receiving a synchronization pulse, so that the data cache displacement module performs a latch and displacement; at the same time, it starts to reset the count until the next data signal arrives, and then generates a displacement pulse again and outputs it to the data cache displacement module; A data cache shift module, used for shifting under a shift driving signal, determining a final number of shifts based on the number of shift registers, and ending the shift after the final number of shifts; The output end of the interrupt wake-up module is connected to the IO pin of the CPU and the input end of the synchronization signal generation module, the output end of the synchronization signal generation module is connected to the input end of the displacement drive generation module, and the output end of the displacement drive generation module is connected to the input end of the data buffer displacement module.
2. The serial port data wake-up circuit according to claim 1, characterized in that: The synchronization signal generating module includes a first NOT gate, a first MOS tube, a second MOS tube, a first resistor, and a first capacitor. The input end of the first NOT gate inputs a source signal RX, the output end of the first NOT gate is connected to the G pole of the first MOS tube and the G pole of the second MOS tube, the S pole of the first MOS tube is connected to the power supply voltage VCC, the D pole of the first MOS tube is connected to the D pole of the second MOS tube and one end of the first capacitor, the S pole of the second MOS tube is connected to one end of the first resistor and the input end of the displacement drive generating module, the other end of the first resistor is grounded, and the other end of the first capacitor is grounded.
3. The serial port data wake-up circuit according to claim 1, characterized in that: The displacement drive generation module includes a second XOR gate, a third NOT gate, a counter, and a clock buffer. The input end of the clock buffer introduces a clock signal CLOCK, the output end of the clock buffer is connected to the first input end of the counter, the output end of the counter is connected to the first input end of the second XOR gate, the second input end of the second XOR gate is connected to the output end of the synchronization signal generation module, the output end of the second XOR gate is connected to the input end of the third NOT gate and the input end of the data buffer displacement module, and the output end of the third NOT gate is connected to the second input end of the counter.
4. The serial port data wake-up circuit according to claim 1, characterized in that: The data buffer shift module includes at least one shift register. When there are multiple shift registers, the shift registers are connected in series.
5. A serial port data wake-up method, applied to the serial port data wake-up circuit as claimed in any one of claims 1 to 4, characterized in that: The serial port data wake-up method comprises the following steps: Step 1, generating a synchronization pulse signal based on a source signal RX; Step 2, generating a displacement pulse signal based on the synchronization pulse signal; Step 3, based on the shift pulse signal, the shift register is latched and shifted. When the data is shifted to the end of the shift register, the CPU enters the normal working mode and receives the serial port data normally.
6. The serial port data wake-up method according to claim 5, characterized in that: Step 1 specifically includes: Step 11, receiving a source signal RX output to an IO pin of the CPU; Step 12: Generate a synchronization pulse signal based on the falling edge of the source signal RX.
7. The serial port data wake-up method according to claim 5, characterized in that: Step 2 specifically includes: Step 21, the clock signal CLOCK is sequentially output to the second XOR gate through the clock buffer and the counter; Step 22, the synchronization pulse signal is output to the second XOR gate; Step 23: The second XOR gate generates a displacement pulse signal based on the input signal.