Test method and device and storage medium

Abstract

The invention discloses a test method and device and a storage medium. The method comprises the following steps: acquiring a video test signal generated by an upper computer; inputting the video test signal into a target field programmable gate array module through a corresponding transceiver module; the target field programmable gate array module is one of a plurality of target field programmable gate array modules with different processing scales; the number of receiving and transmitting paths of the corresponding receiving and transmitting module corresponds to the processing scale of the target field-variable gate array module; obtaining an output signal of the target field programmable gate array module; and obtaining a test result according to the output signal. The embodiment of the invention can be suitable for various different test scenes.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and more specifically, to a testing method, device and storage medium. Background Art

[0002] The ARINC818 bus is a digital video interface standard widely used in the aerospace field, which can realize the reliable transmission of high-definition video and control data. Due to its high bandwidth, low latency and reliability, it is suitable for flight display systems, aerial cameras and other avionics equipment.

[0003] However, since ARINC818 bus simulation and testing are both based on FPGA, the performance of simulation and testing will be constrained by the performance of the FPGA chip. Once the FPGA chip is determined, if the product needs to be upgraded, a new hardware circuit needs to be redesigned. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a test method, a device and a storage medium, which can facilitate testing of multi-channel video test signals of different numbers.

[0005] In a first aspect, an embodiment of the present application provides a test method, comprising: obtaining a first multi-channel video test signal of a flight electronic device generated by a host computer; determining the number of transceiver paths of the first multi-channel video test signal; according to the number of transceiver paths of the first multi-channel video test signal, inputting the first multi-channel video test signal into a first target field programmable gate array module through a corresponding first multi-channel optical transceiver module; the first target field programmable gate array module is one of a plurality of field programmable gate array modules with different processing scales; the number of transceiver paths of the corresponding first multi-channel optical transceiver module corresponds to the processing scale of the first target field programmable gate array module; obtaining a first output signal generated by the first target field programmable gate array module processing the video test signal; obtaining a first test result according to the first output signal; after obtaining the first multi-channel video test signal of the flight electronic device generated by the host computer, the method further comprises: obtaining a first output signal of the host computer A second multi-channel video test signal of the flight electronic equipment is generated; the number of transceiver channels of the second multi-channel video test signal is different from that of the first multi-channel video test signal; the number of transceiver channels of the second multi-channel video test signal is determined; according to the number of transceiver channels of the second multi-channel video test signal, the second multi-channel video test signal is input into the second target field programmable gate array module through the corresponding second multi-channel optical transceiver module; the second target field programmable gate array module is one of the field programmable gate array modules with different processing scales; the processing scales of the first target field programmable gate array module and the second target field programmable gate array module are different; the number of transceiver channels of the second multi-channel optical transceiver module and the first multi-channel optical transceiver module are different; a second output signal generated by the second target field programmable gate array module processing the video test signal is obtained; and a second test result is obtained according to the second output signal.

[0006] In a possible implementation manner, before obtaining the output signal of the first target field programmable gate array module, it also includes: converting the physical channel address of the first multi-channel video test signal into a physical channel address equivalent value; determining the quantity value range of the whole package of each video test signal in the first multi-channel video test signal according to the number of channels of the first multi-channel video test signal and the equivalent value; using the first target field programmable gate array module, segmenting each video test signal in the first multi-channel video test signal to obtain a data segment of each video test signal; generating a sequence number, a whole package number and a unique serial number for each of the data segments; according to the quantity value range, combining the first multi-channel video test signal into multiple whole packages, each whole package including at least one data segment, to obtain bus data; converting the bus data into a first optical signal; and using the first optical signal as the first output signal.

[0007] In a possible implementation, obtaining a first test result according to the first output signal includes: outputting the first optical signal to a test module outside the field programmable gate array module; receiving a second optical signal returned by the test module according to the first optical signal; converting the second optical signal into a differential signal, wherein a frequency of the differential signal is greater than a preset frequency threshold; performing an unpacking operation on the second optical signal to obtain unpacked data of the second optical signal; and comparing the unpacked data of the second optical signal with the first multi-channel video test signal to obtain the first test result.

[0008] In a possible implementation manner, the use of the first target field programmable gate array module to segment each of the multiple video test signals to obtain a data segment of each video test signal also includes: parsing the video test signal; sending a first storage instruction and a first related parameter to a double rate synchronous dynamic random access memory through a signal bus; and sending a second storage instruction and a second related parameter to the double rate synchronous dynamic random access memory through an address bus; the first storage instruction and / or the second storage instruction include a row activation instruction; the double rate synchronous dynamic random access memory determines a row address for storing the first multiple video test signals according to the first storage instruction and the first related parameter, and activates the first storage instruction. storage instruction, first related parameters, second storage instruction and second related parameters, perform storage control decoding operation to obtain storage address and column address; the row address, the storage address and the column address are used to read the first multi-channel video test signal; the double rate synchronous dynamic random access memory reads the first multi-channel video test signal in the sensing amplifier in the row address to the storage unit of the double rate synchronous dynamic random access memory; the comparison of the unpacked data of the second optical signal and the first multi-channel video test signal to obtain the first test result includes: taking out the parsed first multi-channel video test signal from the double rate synchronous dynamic random access memory, and comparing it with the unpacked data of the second optical signal to obtain the first test result.

[0009] In a possible implementation, the first multi-channel optical transceiver module and the second multi-channel optical transceiver module are fixed to the carrier board through a transceiver module socket (which can be equivalent to a multi-channel optical transceiver module socket), and the multiple field programmable gate array modules with different processing scales are fixed to the core board; the carrier board and the core board are connected by a connector; the connector includes a carrier board connector and a core board connector; the core board connector includes a plurality of grooves, and the carrier board connector includes a plurality of protrusions; the core board also includes a double rate synchronous dynamic random access memory and a queued serial peripheral interface flash memory; the carrier board also includes an optical module socket for setting the multiple multi-channel optical transceiver modules; the multiple multi-channel optical transceiver modules include the first multi-channel optical transceiver module and the second multi-channel optical transceiver module; the multiple multi-channel optical transceiver modules are connected to the panel of the carrier board through an S-shaped wiring; the panel of the carrier board is perpendicular to the optical module socket.

[0010] In a possible implementation, the multi-channel optical transceiver module includes a plurality of modules, and the number of parallel signal transmission and reception of the plurality of multi-channel optical transceiver modules is different; determining the number of transceiver paths of the first video test signal includes: obtaining an address bit symbol of the first multi-channel video test signal; determining an address of a physical channel for transmitting the first multi-channel video test signal according to the address bit symbol; and determining the number of transceiver paths of the first multi-channel video test signal according to the address of the physical channel.

[0011] In a possible implementation, when the physical channel address of the first multi-channel video test signal indicates that the number of transceiver channels of the first multi-channel video test signal is less than a first threshold, the first target field programmable gate array is a first-level field programmable gate array; when the number of transceiver channels of the first multi-channel video test signal is greater than or equal to the first threshold and less than a second threshold, the first target field programmable gate array is a second-level field programmable gate array; when the physical channel address of the first multi-channel video test signal indicates that the number of transceiver channels of the video test signal is greater than or equal to the second threshold, the first target field programmable gate array is a third-level field programmable gate array; the processing scale corresponding to the first level is smaller than the processing scale corresponding to the second level, and the processing scale corresponding to the second level is smaller than the processing scale corresponding to the third level.

[0012] In a possible implementation, obtaining a first test result based on the first output signal includes: when the first output signal is an analog signal, inputting the first output signal into an analog signal recognition model; obtaining a clarity recognition result and a corresponding object recognition result of the output signal based on output data of the analog signal recognition model; when the object recognition result is of a set type, determining whether the clarity recognition result is within a clarity range corresponding to the set type; when the clarity recognition result is not within a clarity range corresponding to the set type, the first test result indicates failure.

[0013] In a second aspect, an embodiment of the present application provides a test device, including: a test signal module, used to obtain a first multi-channel video test signal of a flight electronic device generated by a host computer; a transceiver number module, used to determine the number of transceiver paths of the first multi-channel video test signal; an input module, used to input the first multi-channel video test signal into a first target field programmable gate array module through a corresponding first multi-channel optical transceiver module according to the number of transceiver paths of the first multi-channel video test signal; the first target field programmable gate array module is one of a plurality of field programmable gate array modules with different processing scales; the number of transceiver paths of the corresponding first multi-channel optical transceiver module corresponds to the processing scale of the first target field programmable gate array module; an output module, used to obtain a first output signal generated by the first target field programmable gate array module processing the video test signal; an output signal processing module, used to obtain a first test result according to the first output signal.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, the electronic device comprising: a processor and a memory; The memory is used to store a program for the electronic device to execute the information verification method based on the product lifecycle management system as provided in any embodiment of the present application, and to store data involved in implementing the information verification method based on the product lifecycle management system; The processor is configured to execute the program stored in the memory.

[0015] In a fourth aspect, an embodiment of the present application further provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute a method provided by any embodiment of the present application.

[0016] The test method, device and storage medium provided in the embodiments of the present application can input the corresponding target field programmable gate array module according to the number of video test signal paths, thereby realizing the testing of video test signals with different numbers of paths. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 A schematic diagram of a method flow chart provided in an embodiment of the present application; Figure 2 This is a schematic diagram of a carrier structure of an embodiment of the present application; Figure 3 This is a schematic diagram of the structure of the core board connector of an embodiment of the present application; Figure 4 This is a schematic structural diagram of a carrier connector according to an embodiment of the present application; Figure 5 This is a schematic diagram of the structure of a multi-channel optical transceiver module according to an embodiment of the present application; Figure 6 This is a schematic diagram of the core board structure of this application example; Figure 7 This is a schematic diagram of the carrier structure of the present application example; Figure 8 This is a partial schematic diagram of the connection between the core board and the carrier board of the present application example. DETAILED DESCRIPTION

[0019] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0020] A testing method provided in an embodiment of the present application includes the following steps S11 to S15.

[0021] Step S11: obtaining a multi-channel video test signal of the flight electronic equipment generated by the host computer.

[0022] In this embodiment, the multi-channel video test signal may include a first multi-channel video test signal and / or a second multi-channel video test signal.

[0023] Each video test signal may include at least one standard video package, and each video package may further include one or more video files. The host computer may obtain the video test signal from other devices, or may obtain the video file from the camera device configured by the host computer itself.

[0024] In a possible implementation, a standard video packet may be a data packet obtained by encoding data of one or more video files and encapsulating them in a certain encapsulation format. The encapsulation format may include formats such as transport stream (TS), moving picture expert group 4 (MP4), etc. Exemplarily, a standard video packet may include parts such as a header, a payload, and an adaptive adjustment field. The header may include the type, length, and synchronization information of the video packet. The payload may include video content, audio content, or other business data. The adaptive adjustment field may include a symbol for adjusting the length of the packet so that it meets the fixed length requirement. Among them, the synchronization information may include a decoding timestamp (DTS), a display timestamp (PTS), and a system reference clock (SCR).

[0025] Exemplarily, the multi-channel video test signal can be transmitted through a physical channel with the same number of transceiver channels. For example, when the multi-channel video test signal is a 4-channel video test signal, it is transmitted through physical channel 1. When the multi-channel video test signal is a 12-channel unidirectional signal, it is transmitted through physical channel 2. When the multi-channel video test signal is a 12-channel bidirectional signal, it is transmitted through physical channel 3. When the multi-channel video test signal is a 48-channel signal, it is transmitted through physical channel 4.

[0026] In a possible implementation, the host computer can generate a standard video package and use the standard video package as a multi-channel video test signal. In a specific implementation, the host computer can generate and control various standard video packages as multi-channel video test signals through a preset software module or program module. These signals include but are not limited to monochrome images, color bars, static pictures, dynamic scroll bars, etc. In addition, the host computer can also customize and generate specific test patterns according to test requirements, such as geometric correction test images, brightness contrast test images, etc., and then generate multi-channel video test signals according to the test patterns.

[0027] Step S12: Determine the number of receiving and transmitting channels of the multi-channel video test signals.

[0028] Exemplarily, the number of receiving and transmitting paths of the multi-channel video test signal can be determined by the address of the physical channel used to transmit the multi-channel test signal. The address of the physical channel used to transmit the multi-channel video test signal can be set in the file name of the video package, so that when a video package of the multi-channel video test signal is received, the physical channel address and the number of receiving and transmitting paths corresponding to the multi-channel video test signal can be determined through the file name of the video package.

[0029] In a possible implementation, physical channels of different numbers of multi-channel video test signals are connected to corresponding multi-channel optical modules, so that when the multi-channel video test signals are received, the number of channels of the multi-channel video test signals can be determined according to the optical module used to transmit the multi-channel video test signals. The multi-channel optical module can be one of the optical modules in other embodiments of the present application, and the multi-channel optical module can be a part of the physical channel.

[0030] Step S13: According to the number of receiving and transmitting paths of the multi-channel video test signal, the multi-channel video test signal is input into a target field programmable gate array module through a corresponding multi-channel optical transceiver module; the target field programmable gate array module is one of a plurality of field programmable gate array (FPGA) modules with different processing scales; the number of receiving and transmitting paths of the corresponding multi-channel optical transceiver module corresponds to the processing scale of the target field programmable gate array module.

[0031] In this embodiment, the multi-channel optical transceiver module may include the first multi-channel optical transceiver module and / or the second multi-channel optical transceiver module in the above embodiment. The target field programmable gate array module may include the first target field programmable gate array module and / or the second target field programmable gate array module in the above embodiment.

[0032] The video test signal may include multiple groups of different signals. The above-mentioned multi-channel optical transceiver module may include multiple ones. Each group of different video test signals can be input into the target field programmable gate array through the corresponding multi-channel optical transceiver module. Exemplarily, the multi-channel optical transceiver module may include a 4-channel optical transceiver module, a 12-channel optical transceiver module, a 12-channel receiving optical module, a 12-channel sending optical module and a 48-channel optical transceiver module.

[0033] The field programmable gate arrays of the above-mentioned different processing scales can be configured with different resources. The resources configured by the field programmable gate array can be on-chip resources, including: configurable logic block resources, input and output resources, and wiring resources. Different processing scales correspond to the resource scale of the field programmable gate array, and the resource scale of the field programmable gate array can include the first scale (also known as the third gear), the second scale (also known as the second gear), and the third scale (also known as the first gear). Among them, the resource level of the first scale is higher than the second scale, and the resource level of the second scale is higher than the third scale. The third scale field programmable gate array is used in the following scenarios of 48-way transmission and reception, the second scale field programmable gate array is used for 48 to 96 channels, and the first scale field programmable gate array can be used for 96 to 152 channels.

[0034] In a possible implementation, the FPGA may be divided into multiple gears (also referred to as gears). For example, the FPGA may be divided into a high gear (i.e., the third gear in the aforementioned embodiment), a middle gear (i.e., the second gear in the aforementioned embodiment), and a low gear (i.e., the first gear in the aforementioned embodiment) according to the number of transceiver paths.

[0035] FPGAs can be divided into grades based on the number of high-speed interfaces, logic resources, memory capacity, etc. For example, the Virtex UltraScale (super range) + series FPGAs have 40 pairs of low-end VU3P high-speed interfaces, 862050 logic resources, and 25.3Mb BRAM. The mid-range VU5P has 80 pairs of high-speed interfaces, 1313763 logic resources, and 36Mb BRAM. The high-end VU13P has 128 pairs of high-speed interfaces, 3780000 logic resources, and 94.5Mb BRAM. One pair of high-speed interfaces is required for one transceiver. Therefore, if the number of transceivers is greater than 40, VU3P cannot be used, and VU5P or VU13P needs to be used, and so on.

[0036] Step S14: obtaining an output signal generated by the target field programmable gate array module processing the video test signal.

[0037] In this embodiment, the output signal may include the first output signal and / or the second output signal mentioned above.

[0038] The target field programmable gate array module can reframe and package the multi-channel video test signals sent by the host computer into data frames according to the data frame structure defined by the ARINC818 protocol, and send the packaged data frames to the sending buffer area; then read the received data frame in the receiving buffer area, and parse the data according to the ARINC818 protocol, including parsing pixel data, control information and synchronization signals, and performing error detection and correction. Finally, the sent data and the received data are compared to obtain the test results.

[0039] The above-mentioned ARINC818 protocol, whose full name is Avionics Digital Video Bus protocol, is an international standard developed by the Aviation Electronics Industries Association (ARINC) specifically for the design of avionics video systems.

[0040] Step S15: Obtain a test result according to the output signal.

[0041] In this embodiment, the test result may include the first test result and / or the second test result mentioned above.

[0042] In one implementation, obtaining a test result based on the output signal includes: when the output signal is an analog signal, inputting the output signal into an analog signal recognition model; obtaining a clarity recognition result and a corresponding object recognition result of the output signal based on the output data of the analog signal recognition model; when the object recognition result is of a set type, determining whether the clarity recognition result is within a clarity range corresponding to the set type; when the clarity recognition result is not within the clarity range corresponding to the set type, the test result indicates failure.

[0043] In another implementation, obtaining a test result based on the output signal may include: when the output signal is a digital signal, comparing the transmitted video test signal and the received video test signal one by one, and recording inconsistent unit signals as bit errors; using the following formula to calculate the bit error rate based on the recorded bit errors: bit error rate = number of bit errors / total amount of data; when the bit error rate is less than the minimum requirement for normal passage, a qualified test result is obtained, otherwise an unqualified test result is obtained.

[0044] Through the testing method provided in the embodiment of the present application, the FPGA can be divided into multiple gears, and signals of different numbers can be received and sent through multiple different multi-channel transceiver modules, and transmitted to the target field programmable gate array module of the corresponding gear. Therefore, when testing signals of different specifications, there is no need to reassemble the FPGA and other modules, thereby improving the test efficiency.

[0045] In the embodiment of the present application, multiple video test signals of different numbers can be tested by using the same set of test equipment, thereby improving the availability of the test equipment.

[0046] In one embodiment, before obtaining the output signal of the target field programmable gate array module, it also includes: using the target field programmable gate array module to perform packet processing on the video test signal to obtain bus data; converting the bus data into a first optical signal; and using the first optical signal as the output signal.

[0047] In one embodiment, the target field programmable gate array module is used to perform packet processing on the video test signal to obtain bus data, including: converting the physical channel addresses of the multiple video test signals into physical channel address equivalent numerical values; determining the number value range of the whole packets of each video test signal in the multiple video test signals according to the number of channels of the multiple video test signals and the equivalent numerical values; using the target field programmable gate array module, segmenting each video test signal in the multiple video test signals to obtain data segments of each video test signal; generating a sequence number, a whole packet number and a unique serial number for each of the data segments; and combining the multiple video test signals into multiple whole packets according to the number value range, each whole packet including at least one data segment, to obtain bus data.

[0048] Exemplarily, when converting the physical channel address into an equivalent numerical value, the conversion can be performed in a certain conversion method. For example, the last character of the physical channel address can be converted into an equivalent numerical value according to the correspondence between the character and the numerical value. At the same time, each equivalent numerical value can pre-set the quantity value range of the whole package, so that when identifying and parsing multi-channel video test signals, the channel corresponding to the whole package can be determined according to the quantity value range of the whole package, thereby avoiding the disorder of the order of the multi-channel video test signals when they are combined or split. Segmenting each video test signal in the multi-channel video test signal can include: segmenting each video test signal according to a preset segmentation interval. The order of each segment in the whole package can be determined by sequential numbering. The whole package number can be used to determine the whole package to which each segment belongs. The unique sequence number can be used to determine that there is no duplication of the segment.

[0049] In a possible implementation, the multi-channel optical transceiver module includes multiple modules, and the number of parallel signal reception and transmission of the multiple multi-channel optical transceiver modules is different; determining the number of transceiver channels of the multi-channel video test signal includes: obtaining the address bit symbol of the multi-channel video test signal; determining the address of the physical channel used to transmit the multi-channel video test signal according to the address bit symbol; and determining the number of transceiver channels of the multi-channel video test signal according to the address of the physical channel.

[0050] In the embodiment of the present application, multi-channel video test signals of different scales are sent through different physical channels.

[0051] In a possible implementation, when the physical channel address of the multi-channel video test signal indicates that the number of transceiver channels of the multi-channel video test signal is less than a first threshold, the target field programmable gate array is a first-level field programmable gate array; when the number of transceiver channels of the multi-channel video test signal is greater than or equal to the first threshold and less than a second threshold, the target field programmable gate array is a second-level field programmable gate array; when the physical channel address of the multi-channel video test signal indicates that the number of transceiver channels of the multi-channel video test signal is greater than or equal to the second threshold, the target field programmable gate array is a third-level field programmable gate array.

[0052] In an embodiment of the present application, the target field programmable gate array module can be used to convert multiple video test signals into electrical signals and optical signals.

[0053] In one embodiment, obtaining the test result according to the output signal includes: outputting the first optical signal to a test module outside the field programmable gate array module; receiving a second optical signal returned by the multi-channel test module according to the first optical signal; converting the second optical signal into a differential signal, wherein the frequency of the differential signal is greater than a preset frequency threshold; performing an unpacking operation on the second optical signal to obtain unpacked data of the second optical signal; and comparing the unpacked data of the second optical signal with the multi-channel video test signal to obtain the test result.

[0054] In the embodiment of the present application, the second optical signal may be a high-speed differential signal.

[0055] In one embodiment, the method of using the target field programmable gate array module to perform packet processing on the multi-channel video test signals to obtain bus data also includes: parsing the multi-channel video test signals; storing the parsed multi-channel video test signals in a double-rate synchronous dynamic random access memory; and comparing the unpacked data of the second optical signal with the multi-channel video test signals to obtain the test results, including: taking out the parsed multi-channel video test signals from the double-rate synchronous dynamic random access memory, and comparing them with the unpacked data of the second optical signal to obtain the test results.

[0056] In one embodiment, storing the parsed multi-channel video test signals into a double rate synchronous dynamic random access memory comprises: sending a first storage instruction (command) and a first related parameter to the double rate synchronous dynamic random access memory through a signal bus; and sending a storage instruction and the second storage instruction and the second related parameter to the double rate synchronous dynamic random access memory through an address bus; the first storage instruction and / or the second storage instruction comprises a row activation instruction; the double rate synchronous dynamic random access memory determines a row address for storing the multi-channel video test signals according to the first storage instruction and the first related parameter, and performs a storage body control decoding operation on the first storage instruction, the first related parameter, the second storage instruction and the second related parameter to obtain a storage body address and a column address; the row address, the storage body address and the column address are used to read the multi-channel video test signals; the double rate synchronous dynamic random access memory reads the multi-channel video test signals in the sense amplifier in the row address into the storage unit of the double rate synchronous dynamic random access memory.

[0057] In one embodiment, the multi-channel optical transceiver module is fixed to the carrier board through a transceiver module socket, and multiple field programmable gate array modules are fixed to the core board; the carrier board and the core board are connected by a connector; the connector includes a carrier board connector and a core board connector; the core board connector includes multiple grooves, and the carrier board connector includes multiple protrusions; the core board also includes a double-rate synchronous dynamic random access memory and a queued serial peripheral interface flash memory; the carrier board also includes an optical module socket for setting the multiple multi-channel optical transceiver modules; the multiple multi-channel optical transceiver modules are connected to the panel of the carrier board through S-shaped wiring; the panel of the carrier board is perpendicular to the optical module socket.

[0058] In one implementation, multiple field programmable gate array modules include field programmable gate array modules of multiple different gears, and each field programmable gate array module of each gear corresponds to a multi-channel optical transceiver module. The field programmable gate array modules of different gears correspond to multi-channel optical transceiver modules with different transceiver paths. Therefore, based on the carrier board and core board provided in the present application, the testing of video test signals of different numbers can be realized.

[0059] Accordingly, in one embodiment of the present application, based on the above core board and carrier board, the testing method may include the following steps: Obtaining a first multi-channel video test signal of the flight electronic equipment generated by the host computer; Determining the number of receiving and transmitting channels of the first multi-channel video test signal; According to the number of transceiver paths of the first multi-channel video test signal, the first multi-channel video test signal is input into a first target field programmable gate array module through a corresponding first multi-channel optical transceiver module; the first target field programmable gate array module is one of a plurality of field programmable gate array modules with different processing scales; the number of transceiver paths of the corresponding first multi-channel optical transceiver module corresponds to the processing scale of the first target field programmable gate array module; Obtaining a first output signal generated by the first target field programmable gate array module processing the video test signal; Obtaining a first test result according to the first output signal; After obtaining the first multi-channel video test signal of the flight electronic equipment generated by the host computer, the method further includes: Obtaining a second multi-channel video test signal of the flight electronic equipment generated by the host computer; the number of transceiver channels of the second multi-channel video test signal is different from the number of transceiver channels of the first multi-channel video test signal; Determining the number of receiving and transmitting channels of the second multi-channel video test signal; According to the number of transceiver paths of the second multi-channel video test signal, the second multi-channel video test signal is input into a second target field programmable gate array module through a corresponding second multi-channel optical transceiver module; the second target field programmable gate array module is one of the field programmable gate array modules with different processing scales; the processing scales of the first target field programmable gate array module and the second target field programmable gate array module are different; the second multi-channel optical transceiver module is different from the first multi-channel optical transceiver module; Obtaining a second output signal generated by the second target field programmable gate array module processing the video test signal; A second test result is obtained according to the second output signal.

[0060] Among them, the first multi-channel video test signal and the second multi-channel video test signal can be processed in parallel or serially, so that the embodiment of the present application can use the same set of carrier board and core board equipment to test video test signals with different transceiver numbers.

[0061] In one implementation, the structure of the carrier board can refer to Figure 2As shown. The carrier board may include: a multi-channel optical transceiver module socket, an FPGA core board, DDR, FPGA, power supply, clock, PXIe (Peripheral Component Interconnect Express Extended, auxiliary parts connection interface extension) connector and QSPI (quad serial peripheral interface, quad serial peripheral interface) flash memory. Among them, the FPGA is connected to the FPGA core board in a detachable manner. The multi-channel optical transceiver module socket is used to fix each multi-channel optical transceiver module. The structure of the multi-channel optical transceiver module socket is as shown Figure 5 As shown in the figure. DDR, power supply, and clock are fixed to the FPGA core board. The PXIe connector is used for data transmission with the host computer. DDR and QSPI flash memory are used to store data required by the carrier board during the test process.

[0062] The structure of the core board connector can refer to Figure 3 As shown. In a possible implementation, the core board connector may include a plurality of grooves 31, and high-speed signal contact springs 32 are provided at both ends of the grooves 31. In the embodiment of the present application, the high-speed signal contact spring 32 may be a contact component used in a high-speed connector, which utilizes the elastic properties of the spring to ensure stable contact with the corresponding connector, thereby achieving high-speed, high-quality signal transmission.

[0063] The structure of the carrier board connector can refer to Figure 4 In a possible implementation, the carrier connector may include a plurality of protrusions 41, and high-speed signal contact springs 32 are provided at both ends of the protrusions 41. The protrusions 41 of the carrier connector may be connected to the grooves of the core board connector, so that the carrier and the core board are fixed.

[0064] In one example of the present application, the structure of the core board can refer to Figure 6 As shown. The core board includes Figure 2In addition to the structure shown, it also includes multiple capacitors 61, DDR particles 63, resistors 64, passive crystal oscillators (crystals) 65, light emitting diodes (LEDs) 66, quad serial peripheral interface flash (quad serial peripheral interface flash, QSPI flash) 67, crystal oscillators 68, low-dropout regulators (LDO) 612, and level conversion chips 69, as well as power supplies 610, field effect transistors 611, joint test action group (JTGA) test circuits 613, field programmable gate array mezzanine connectors (FPGA mezzanine connection, FMC) 614, and embedded memory (Embedded Multi Media Card, eMMC) 615.

[0065] The DDR particle 63 is the DDR in the above-mentioned embodiment. Figure 2 Based on the example shown, by Figure 6 The various components shown connect DDR, FPGA, QSPI flash memory and clock to achieve normal operation of DDR, FPGA, QSPI flash memory and clock.

[0066] Figure 7 for Figure 2 A possible structural diagram of a carrier board shown in FIG. 1 includes an optical module 71, a multi-fiber push on (MPO) 72, a mini display port (mini-DP) 73, an LED 74, an FMC 75, an MPO flange 76, a USB (universal serial bus) 77, and a panel 78. The multi-fiber push on is equivalent to the multi-channel receiving and emitting light module socket in the aforementioned embodiment. Figure 7 The interfaces and other structures shown in the figure connect the multi-channel receiving and emitting light module socket and the optical module, and connect the carrier board and the core board. Figure 7 The optical module 71 and the multi-fiber plug 72 are connected via an S-shaped cable. The FMC is equivalent to the connector between the carrier board and the core board in the above-mentioned embodiment.

[0067] Figure 8 for Figure 7 The FMC connector of the carrier board is connected to the FMC connector of the core board to achieve the connection between the carrier board and the core board. At the same time, the core board can be at the bend of the S-shaped connection line.

[0068] The embodiment of the present application also provides a test device, including: a test signal module, used to obtain a first multi-channel video test signal of a flight electronic device generated by a host computer; a transceiver number module, used to determine the number of transceivers of the first multi-channel video test signal; an input module, used to input the first multi-channel video test signal into a first target field programmable gate array module through a corresponding multi-channel optical transceiver module according to the number of transceivers of the first multi-channel video test signal; the first target field programmable gate array module is one of a plurality of field programmable gate array modules with different processing scales; the number of transceivers of the corresponding multi-channel optical transceiver module corresponds to the processing scale of the first target field programmable gate array module; an output module, used to obtain a first output signal generated by the first target field programmable gate array module processing the first multi-channel video test signal; an output signal processing module, used to obtain a first test result according to the first output signal.

[0069] In a possible implementation, the test device further includes: a first test signal module, used to obtain a second multi-channel video test signal of the flight electronic equipment generated by the host computer; the number of transceiver paths of the second multi-channel video test signal is different from the number of transceiver paths of the first multi-channel video test signal; a first transceiver path number module, used to determine the number of transceiver paths of the second multi-channel video test signal; a first input module, used to input the second multi-channel video test signal into a second target field programmable gate array module through a corresponding second multi-channel optical transceiver module according to the number of transceiver paths of the second multi-channel video test signal; the second target field programmable gate array module is one of the field programmable gate array modules with different processing scales; the processing scales of the first target field programmable gate array module and the second target field programmable gate array module are different; the second multi-channel optical transceiver module is different from the first multi-channel optical transceiver module; a first output module, used to obtain a second output signal generated by the second target field programmable gate array module processing the first multi-channel video test signal; a first output signal processing module, used to obtain a second test result according to the second output signal.

[0070] In a possible implementation, the test device also includes: a first conversion module, used to convert the physical channel address of the multi-channel video test signal into a physical channel address equivalent value; a quantity value range module, used to determine the quantity value range of the whole package of the multi-channel video test signal according to the number of channels of the multi-channel video test signal and the equivalent value; a segmentation module, used to segment each video test signal in the multi-channel video test signal using the target field programmable gate array module to obtain a data segment of each video test signal; a numbering module, used to generate a sequential number, a whole package number and a unique serial number for each of the data segments; a bus data module, used to combine the multi-channel video test signals into multiple whole packages according to the quantity value range, each whole package includes at least one data segment, and obtain bus data; a second conversion module, used to convert the bus data into a first optical signal; an output module, used to use the first optical signal as the output signal.

[0071] In a possible implementation, the transceiver module is fixed to the carrier board through a transceiver module socket, and multiple field programmable gate array modules are fixed to the core board; the carrier board and the core board are connected through a connector; the connector includes a carrier board connector and a core board connector; the core board connector includes multiple grooves, and the carrier board connector includes multiple protrusions; the core board also includes a double-rate synchronous dynamic random access memory and a queued serial peripheral interface flash memory; the carrier board also includes an optical module socket for setting the multiple multi-channel optical transceiver modules; the multiple transceiver modules are connected to the panel of the carrier board through S-shaped wiring; the panel of the carrier board is perpendicular to the optical module socket.

[0072] The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise mentioned, elements or features may be considered as optional. Each element or feature may be put into practice without being combined with other elements or features. In addition, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some configurations of any one embodiment may be included in another embodiment, and may be replaced by the corresponding configuration of another embodiment. It is obvious to those skilled in the art that claims that do not have a clear reference relationship to each other in the attached claims may be combined into embodiments of the present invention, or may be included as new claims in the amendment after submitting the present invention.

[0073] In a firmware or software configuration, the embodiments of the present invention may be implemented in the form of modules, procedures, functions, etc. The software code may be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and may send data to and receive data from the processor via various known means.

[0074] Various aspects of the systems and methods described herein may be implemented as functions programmed into any of a variety of circuits, including programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electronic programmable logic and storage devices, standard cell-based devices, and application-specific integrated circuits (ASICs). Some other possibilities for implementing these aspects of the system include: microcontrollers with memory, such as electronically erasable programmable read-only memory (EEPROM), embedded microprocessors, firmware, software, etc. In addition, these aspects of the system may be embodied in microprocessors with software-based circuit simulation, discrete logic (sequential and combinational), custom devices, fuzzy (neural) logic, quantum devices, and combinations of any of the above various device types. Of course, the underlying device technology may be provided in a variety of component types, such as metal oxide semiconductor field effect transistor (MOSFET) technology such as complementary metal oxide semiconductor (CMOS), bipolar technology such as emitter coupled logic (ECL), polymer technology (e.g., silicon conjugated polymer and metal conjugated polymer metal structure), hybrid analog and digital, etc.

[0075] The various functions or processes disclosed herein may be described as data and / or instructions embodied in various computer-readable media in terms of their behavior, register transfers, logic components, transistors, geometric layouts, and / or other characteristics. Computer-readable media that may contain such formatted data and / or instructions include, but are not limited to, various forms of non-volatile storage media (e.g., optical, magnetic, or semiconductor storage media) and carrier waves, which may be used to transmit such formatted data and / or instructions via wireless, optical, or wired signal media, or any combination thereof. When received in any of a variety of circuits (e.g., computers), such data and / or instructions may be processed by a processing entity (e.g., one or more processors).

[0076] The above description of the illustrated embodiments of the systems and methods is not intended to be exhaustive or to limit the systems and methods to the precise forms disclosed. Although specific embodiments and examples of the system components and methods are described herein for illustrative purposes, it will be appreciated by those skilled in the art that various equivalent modifications may be made within the scope of the systems, components, and methods. The teachings of the systems and methods provided herein may be applied to other processing systems and methods, not just to the above-described systems and methods.

[0077] Those skilled in the art will appreciate that many variations and / or modifications may be made to the invention shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. Therefore, the present embodiments are to be considered in all respects as illustrative and not restrictive. In addition, the present invention includes any combination of features described for the different embodiments (including those in the abstract), even if the feature or combination of features is not explicitly specified in the claims or the detailed description of the embodiments.

[0078] Generally, in the following claims, the terms used should not be construed to limit the systems and methods to the specific embodiments disclosed in the specification and the claims, but should be construed to include all processing systems that operate under the claims. Therefore, the systems and methods are not limited by the present disclosure, but rather the scope of the systems and methods is determined entirely by the claims.

[0079] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include", "including", "comprising", etc. should be interpreted in an inclusive sense and not in an exclusive or exhaustive sense; that is, in the sense of "including but not limited to". Words using the singular or plural number also include the singular or plural number, respectively. In addition, "herein", "herein below", "above", "hereafter" and words of similar meaning refer to this application as a whole and not to any particular part of this application. When the word "or" is used in a list involving two or more items, the word "or" includes all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

[0080] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0081] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A testing method, characterized in that: include: Obtaining a first multi-channel video test signal of the flight electronic equipment generated by the host computer; Determining the number of receiving and transmitting channels of the first multi-channel video test signal; According to the number of transceiver paths of the first multi-channel video test signal, input the first multi-channel video test signal into the first target field programmable gate array module through the corresponding first multi-channel optical transceiver module; The first target field programmable gate array module is one of a plurality of field programmable gate array modules with different processing scales; the number of transceiver paths of the corresponding first multi-path optical transceiver module corresponds to the processing scale of the first target field programmable gate array module; Obtaining a first output signal generated by the first target field programmable gate array module processing the first multi-channel video test signal; Obtaining a first test result according to the first output signal; After obtaining the first multi-channel video test signal of the flight electronic equipment generated by the host computer, the method further includes: obtaining a second multi-channel video test signal of the flight electronic equipment generated by the host computer; the number of transceiver channels of the second multi-channel video test signal is different from the number of transceiver channels of the first multi-channel video test signal; Determining the number of receiving and transmitting channels of the second multi-channel video test signal; According to the number of transceiver paths of the second multi-channel video test signal, the second multi-channel video test signal is input into a second target field programmable gate array module through a corresponding second multi-channel optical transceiver module; the second target field programmable gate array module is one of the field programmable gate array modules with different processing scales; the processing scales of the first target field programmable gate array module and the second target field programmable gate array module are different; the second multi-channel optical transceiver module is different from the first multi-channel optical transceiver module; Obtaining a second output signal generated by the second target field programmable gate array module processing the second multi-channel video test signal; A second test result is obtained according to the second output signal.

2. The method according to claim 1, characterized in that Before obtaining the output signal of the first target field programmable gate array module, the method further includes: Converting the physical channel addresses of the first multi-channel video test signals into physical channel address equivalent values; Determine the value range of the number of whole packets of each video test signal in the first multi-channel video test signal according to the number of the first multi-channel video test signals and the equivalent value; Using the first target field programmable gate array module, segmenting each of the first multiple video test signals to obtain a data segment of each video test signal; Generate a sequence number, a whole packet number and a unique serial number for each of the data segments; According to the quantity value range, the first multi-channel video test signals are combined into a plurality of whole packets, each whole packet including at least one data segment, to obtain bus data; Converting the bus data into a first optical signal; The first optical signal is used as the first output signal.

3. The method according to claim 2, characterized in that The step of obtaining a first test result according to the first output signal includes: Outputting the first optical signal to a test module outside the field programmable gate array module; receiving a second optical signal returned by the test module according to the first optical signal; Converting the second optical signal into a differential signal, wherein the frequency of the differential signal is greater than a preset frequency threshold; performing an unpacking operation on the second optical signal to obtain unpacked data of the second optical signal; The unpacked data of the second optical signal is compared with the first multi-channel video test signal to obtain the first test result.

4. The method according to claim 3, characterized in that Before the step of using the first target field programmable gate array module to segment each of the multiple video test signals to obtain a data segment of each video test signal, the method further comprises: parsing the video test signal; Sending a first storage instruction and a first related parameter to the double rate synchronous dynamic random access memory through a signal bus; and sending a second storage instruction and a second related parameter to the double rate synchronous dynamic random access memory through an address bus; the first storage instruction and / or the second storage instruction includes a row activation instruction; The double rate synchronous dynamic random access memory determines a row address for storing the first multi-channel video test signal according to the first storage instruction and the first related parameter, and performs a storage control decoding operation on the first storage instruction, the first related parameter, the second storage instruction and the second related parameter to obtain a storage address and a column address; the row address, the storage address and the column address are used to read the first multi-channel video test signal; The double rate synchronous dynamic random access memory reads the first multi-channel video test signal from the sense amplifier in the row address to the storage unit of the double rate synchronous dynamic random access memory; The comparing the unpacked data of the second optical signal with the first multi-channel video test signal to obtain the first test result includes: The parsed first multi-channel video test signal is retrieved from the double rate synchronous dynamic random access memory and compared with the unpacked data of the second optical signal to obtain the first test result.

5. The method according to claim 1, characterized in that The first multi-channel optical transceiver module and the second multi-channel optical transceiver module are fixed to the carrier board through the transceiver module socket, and the multiple field programmable gate array modules with different processing scales are fixed to the core board; the carrier board and the core board are connected by a connector; the connector includes a carrier board connector and a core board connector; the core board connector includes a plurality of grooves, and the carrier board connector includes a plurality of protrusions; the core board also includes a double rate synchronous dynamic random access memory and a queued serial peripheral interface flash memory; the carrier board also includes an optical module socket for arranging multiple multi-channel optical transceiver modules; the multiple multi-channel optical transceiver modules include the first multi-channel optical transceiver module and the second multi-channel optical transceiver module; the multiple multi-channel optical transceiver modules are connected to the panel of the carrier board through S-shaped wiring; the panel of the carrier board is perpendicular to the optical module socket.

6. The method according to claim 5, characterized in that The multi-channel optical transceiver modules include a plurality of modules, and the plurality of multi-channel optical transceiver modules have different numbers of signals that can be received and transmitted in parallel; and determining the number of receiving and transmitting channels of the first multi-channel video test signal includes: Obtaining address bit symbols of the first multi-channel video test signals; Determining, according to the address bit symbol, an address of a physical channel for transmitting the first multi-channel video test signal; The number of receiving and transmitting channels of the first multi-channel video test signal is determined according to the address of the physical channel.

7. The method according to claim 6, characterized in that When the physical channel address of the first multi-channel video test signal indicates that the number of transceiver channels of the first multi-channel video test signal is less than a first threshold, the first target field programmable gate array is a field programmable gate array of the first gear; when the number of transceiver channels of the first multi-channel video test signal is greater than or equal to the first threshold and less than the second threshold, the first target field programmable gate array is a field programmable gate array of the second gear; when the physical channel address of the first multi-channel video test signal indicates that the number of transceiver channels of the video test signal is greater than or equal to the second threshold, the first target field programmable gate array is a field programmable gate array of the third gear; the processing scale corresponding to the first gear is smaller than the processing scale corresponding to the second gear, and the processing scale corresponding to the second gear is smaller than the processing scale corresponding to the third gear.

8. The method according to claim 1, characterized in that: The step of obtaining a first test result according to the first output signal includes: In the case where the first output signal is an analog signal, inputting the first output signal into an analog signal recognition model; Obtaining a definition recognition result of the output signal and a corresponding object recognition result according to the output data of the analog signal recognition model; When the object recognition result is of a set type, determining whether the clarity recognition result is within a clarity range corresponding to the set type; When the definition recognition result is not within the definition range corresponding to the set type, the first test result indicates failure.

9. A testing device, characterized in that: include: A test signal module, used for obtaining a first multi-channel video test signal of the flight electronic equipment generated by the host computer; A transceiver number module, used to determine the transceiver number of the first multi-channel video test signal; An input module, used for inputting the first multi-channel video test signal into a first target field programmable gate array module through a corresponding first multi-channel optical transceiver module according to the number of transceiver channels of the first multi-channel video test signal; The first target field programmable gate array module is one of a plurality of field programmable gate array modules with different processing scales; the number of transceiver paths of the corresponding first multi-path optical transceiver module corresponds to the processing scale of the first target field programmable gate array module; An output module, used for obtaining a first output signal generated by the first target field programmable gate array module processing the first multi-channel video test signal; The output signal processing module is used to obtain a first test result according to the first output signal.

10. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-8.

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