Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a first gate structure, a first epitaxial structure and a first gap wall structure. The substrate comprises an active region and shallow trench isolation, and the shallow trench isolation comprises at least one groove. The first gate structure is arranged on the shallow trench isolation and comprises a first gate dielectric layer and a first gate layer which are stacked in sequence. The first epitaxial structure is arranged in the active region at two sides of the first gate structure. The first gap wall structure is arranged on the side wall of the first gate structure and located in the groove of the shallow trench isolation, and the lowest point of the first gap wall structure is lower than the lowest point of the first gate structure. Therefore, the structural stability of the gap wall is enhanced, the isolation effect of the gap wall is improved, and the semiconductor device can achieve more optimized operation performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, to a semiconductor device with a composite spacer and a manufacturing method thereof. Background Art

[0002] Semiconductor devices, such as field effect transistors (FETs), are constantly developing towards miniaturization. The trend of miniaturization can be seen in various types of field effect transistors, including metal oxide semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOSs). However, the miniaturization of semiconductor devices has led to various electrical and / or process limitations. In view of this, in order to improve the problem of the shrinking distance between adjacent gate structures, the industry has developed various improvement technologies to cope with the defects caused by the shrinking line width. Summary of the invention

[0003] The present invention aims to provide a semiconductor device and a method for manufacturing the same, wherein a composite spacer structure is arranged on the sidewall of a gate structure to enhance the structural stability of the spacer and improve its isolation effect, so that the semiconductor device can achieve a more optimized operating performance.

[0004] A semiconductor device provided by one embodiment of the present invention includes a substrate, a first gate structure, a first epitaxial structure and a first spacer structure. The substrate includes an active area and a shallow trench isolation, and the shallow trench isolation includes at least one groove. The first gate structure is arranged on the shallow trench isolation, and includes a first gate dielectric layer and a first gate layer stacked in sequence. The first epitaxial structure is arranged in the active area on both sides of the first gate structure. The first spacer structure is arranged on the sidewall of the first gate structure and is located in the groove of the shallow trench isolation, wherein the lowest point of the first spacer structure is lower than the lowest point of the first gate structure.

[0005] A method for manufacturing a semiconductor device provided by an embodiment of the present invention comprises the following steps. A substrate is provided, wherein the substrate comprises an active area and a shallow trench isolation. A first gate structure is formed on the shallow trench isolation, comprising a first gate dielectric layer and a first gate layer stacked in sequence. A first epitaxial structure is formed in the active area on both sides of the first gate structure. A first spacer structure is formed on the sidewall of the first gate structure, wherein the first spacer structure contacts the shallow trench isolation, and the bottommost surface of the first spacer structure is lower than the bottommost surface of the first gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings provide a deeper understanding of this embodiment and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0007] Figure 1 is a cross-sectional schematic diagram of a semiconductor device in a first embodiment of the present invention;

[0008] Figure 2 is a cross-sectional schematic diagram of a semiconductor device after a gate structure is formed;

[0009] Figure 3 is a schematic cross-sectional view of a semiconductor device after trenches are formed;

[0010] Figure 4 is a cross-sectional schematic diagram of a semiconductor device after forming an epitaxial structure;

[0011] Figure 5 is a schematic cross-sectional view of a semiconductor device after a first etching process is performed;

[0012] Figure 6 is a schematic cross-sectional view of the semiconductor device after the second etching process is performed;

[0013] Figure 7 is a schematic cross-sectional view of a semiconductor device after a deposition process is performed;

[0014] Figure 8 is a schematic cross-sectional view of a semiconductor device after a thinning process is performed;

[0015] Fig. 9 is a schematic cross-sectional view of a semiconductor device after a stop layer is formed;

[0016] Fig.10 is a schematic cross-sectional view of the semiconductor device after the second etching process is performed;

[0017] Fig.11 is a schematic cross-sectional view of a semiconductor device after a thinning process is performed;

[0018] Fig.12 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

[0019] Description of reference numerals:

[0020] 10, 30: semiconductor devices;

[0021] 100: substrate;

[0022] 100t: top surface;

[0023] 102: active region;

[0024] 104: Shallow Trench Isolation;

[0025] 104t: top surface;

[0026] 106: groove;

[0027] 110: first gate structure;

[0028] 110b: lowest point;

[0029] 112: a first gate dielectric layer;

[0030] 114: first gate layer;

[0031] 120: first epitaxial structure;

[0032] 122: a first metal silicide layer;

[0033] 130: a first spacer structure;

[0034] 130b: lowest point;

[0035] 132: first spacer wall;

[0036] 132b: bottommost surface;

[0037] 134: second spacer wall;

[0038] 134b: bottommost surface;

[0039] 136: third interspace wall;

[0040] 136b: bottommost surface;

[0041] 136s: gap;

[0042] 140: contact stop etching layer;

[0043] 142: first stop etching layer;

[0044] 144: second stop etching layer;

[0045] 150: second gate structure;

[0046] 160: second epitaxial structure;

[0047] 170: second spacer structure;

[0048] 172: first spacer wall;

[0049] 172b: bottommost surface;

[0050] 174: second spacer wall;

[0051] 174b: bottommost surface;

[0052] 176: third interspace wall;

[0053] 176b: bottommost surface;

[0054] 178: Fourth interstitial wall;

[0055] 178b: bottommost surface;

[0056] 180, 186: plug structure;

[0057] 182: barrier layer;

[0058] 184: conductive layer;

[0059] 190: interlayer dielectric layer;

[0060] 210, 250: gate structure;

[0061] 212, 252: gate dielectric layer;

[0062] 214, 254: gate layer;

[0063] 214t, 254t: top surface;

[0064] 216, 256: insulation layer;

[0065] 218, 258: cap layer;

[0066] 220, 260: groove;

[0067] 230, 270: spacer stacking structure;

[0068] 232, 234, 236, 238: spacer material layer;

[0069] 242: first stop etching the material layer;

[0070] 244: second stop etching the material layer;

[0071] 272, 274, 276, 278: spacer material layer;

[0072] 280: first material layer;

[0073] 282: second material layer;

[0074] 330: first spacer structure;

[0075] 332: first spacer;

[0076] 332b: bottommost surface;

[0077] 332t: top surface;

[0078] 334: second spacer;

[0079] 334b: bottommost surface;

[0080] 334t: top surface;

[0081] 336: third interspace wall;

[0082] 336s: gap;

[0083] 338: fourth interstitial wall;

[0084] 370: second spacer structure;

[0085] 372: first spacer;

[0086] 372t: top surface;

[0087] 374: second spacer;

[0088] 374t: top surface;

[0089] 376: third interstitial wall;

[0090] B1: lowest point;

[0091] D1: horizontal direction;

[0092] D2: opposite direction;

[0093] S1: distance;

[0094] T1: thickness;

[0095] V1: stoma;

[0096] Y: vertical direction. DETAILED DESCRIPTION

[0097] In order to enable a person skilled in the art to further understand the present invention, the following lists the preferred embodiments of the present invention and describes in detail the components and intended effects of the present invention in conjunction with the accompanying drawings. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention.

[0098] Please refer to Figure 1 As shown, Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device 10 according to a first embodiment of the present invention. Figure 1As shown, the semiconductor device 10 includes a substrate 100, a first gate structure 110, a first epitaxial structure 120, and a first spacer structure 130. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials. At least one shallow trench isolation (STI) 104 is disposed in the substrate 100, and an active area (AA) 102 is defined in the substrate 100, but the present invention is not limited thereto. The first gate structure 110 is disposed on the shallow trench isolation 104 in the substrate 100, and includes in detail a first gate dielectric layer 112 and a first gate layer 114 stacked in sequence. The first epitaxial structure 120 is disposed in the active region 102 on both sides of the first gate structure 110, and includes, for example, doped or undoped semiconductor materials, such as silicon, silicon germanium (SiGe), silicon phosphor (SiP), silicon carbon or other similar materials. It should be noted that the shallow trench isolation 104 also includes at least one groove 106, which is located on one side of the first gate structure 110, and the first spacer structure 130 is disposed on the sidewall of the first gate structure 110 and is partially located in the groove 106 of the shallow trench isolation 104, so that the lowest point 130b of the first spacer structure 130 is lower than the lowest point 110b of the first gate structure 110. Under this configuration, the first gate structure 110 can be used as a dummy gate line (passing gate) and is arranged across the corresponding shallow trench isolation 104. With the help of the first spacer structures 130 on both sides, they partially extend into the groove 106 of the shallow trench isolation 104 to obtain a better isolation effect and have enhanced structural stability to resist the stress from the epitaxial structure, so that the semiconductor device 10 can achieve more optimized operating performance.

[0099] In one embodiment, the first gate dielectric layer 112, for example, includes a high-k dielectric material, and the first gate layer 114, for example, includes a semiconductor material, such as doped polysilicon, doped silicon, doped amorphous silicon, etc., but not limited thereto. The first gate layer 114 has a thickness T1, for example, in the vertical direction Y perpendicular to the substrate 100, and the distance S1 between the lowest point 110b of the first gate structure 110 and the lowest point 130b of the first spacer structure 130 is not less than 0.5 times the thickness T1, so as to ensure that the first spacer structure 130 can effectively extend into the groove 106 to achieve effective structural stability and electrical isolation. In detail, the shallow trench isolation 104, for example, includes two grooves 106, which are respectively located on two opposite sides of the first gate structure 110, and the first spacer structure 130 is disposed on two opposite sidewalls of the first gate structure 110 and partially extends into the two grooves 106.

[0100] The first spacer structure 130 includes a first spacer 132, a second spacer 134, and a third spacer 136 which are sequentially disposed on the two opposite sidewalls of the first gate structure 110 in the horizontal direction D1 or the opposite direction D2 thereof. In one embodiment, the first spacer 132, the second spacer 134, and the third spacer 136, for example, respectively include different insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, etc., but the present invention is not limited thereto. Among them, the first spacer 132 is directly set on the top surface 104t of the shallow trench isolation 104, so that the bottom surface 132b of the first spacer 132 physically contacts the top surface 104t of the shallow trench isolation 104, and the second spacer 134 and the third spacer 136 are partially extended into the groove 106 of the shallow trench isolation 104, and are sandwiched between the first epitaxial structure 120 and the shallow trench isolation 104 in the horizontal direction D1, so that the bottom surface 136b of the third spacer 136 is lower than the bottom surface 132b of the first spacer 132, and the bottom surface 134b of the second spacer 134 is lower than the bottom surface 132b of the first spacer 132 and the bottom surface 136b of the third spacer 136 at the same time. Furthermore, in one embodiment, the third spacer 136 further includes a gap 136S extending into the groove 106 of the shallow trench isolation 104 and located above the shallow trench isolation 104, wherein the lowest point B1 of the gap 136S is lower than the top surface 100t of the substrate 100. Figure 1 shown.

[0101] For example Figure 1As shown, the semiconductor device 10 further includes a second gate structure 150 and a second spacer structure 170 disposed on the active region 102, and a second epitaxial structure 160 disposed in the active region 102. The second gate structure 150 includes a second gate dielectric layer 152 and a second gate layer 154 sequentially stacked on the active region 102, wherein the second gate dielectric layer 152, for example, includes a high dielectric constant dielectric material, preferably includes the same material as the first gate dielectric layer 112, and the second gate layer 154, for example, includes doped polysilicon, doped silicon, doped amorphous silicon, etc., preferably includes the same material as the first gate layer 114, but is not limited thereto. The second spacer structure 170 is disposed on the top surface 100t of the substrate 100 and on two opposite sidewalls of the second gate structure 150, and further includes a first spacer 172, a second spacer 174, a third spacer 176, and a fourth spacer 178 disposed in sequence on the two opposite sidewalls of the second gate structure 150 in the horizontal direction D1 or the opposite direction D2. The bottommost surface 172b of the first spacer 172, the bottommost surface 174b of the second spacer 174, the bottommost surface 176bt of the third spacer 176, and the bottommost surface 178b of the fourth spacer 178 are all physically in contact with the top surface 100t of the substrate 100 at the same time, and are flush with the bottommost surface 132b of the first spacer 132.

[0102] It should be noted that the fourth spacer 178 covers the first spacer 172, the second spacer 174 and the third spacer 176, and is partially disposed between the third spacer 176 and the second epitaxial structure 160, and additionally includes a pore V1 sandwiched between the third spacer 176 and the second epitaxial structure 160. In one embodiment, the first spacer 172, the second spacer 174, the third spacer 176 and the fourth spacer 178, for example, respectively include different insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, etc., the first spacer 172 and the third spacer 176 of the second spacer structure 170 and the first spacer 132 of the first spacer structure 130 preferably include the same insulating material, and the fourth spacer 178 of the second spacer structure 170 and the second spacer 134 of the first spacer structure 130 preferably include the same insulating material, but the present invention is not limited thereto. In addition, the second epitaxial structure 160 is disposed in the active region 102 on two opposite sides of the second gate structure 150, and includes, for example, doped or undoped semiconductor materials, such as silicon, silicon germanium, silicon phosphorus, silicon carbon or other similar materials. In a preferred embodiment, the second epitaxial structure 160 and the first epitaxial structure 120 include, for example, dopants of the same conductive type, such as P-type dopants, but not limited thereto.

[0103] The semiconductor device 10 further includes a first metal silicide layer 122 disposed on the first gate structure 110 and the first epitaxial structure 120, and a second metal silicide layer 162 disposed on the second gate structure 150 and the second epitaxial structure 160, respectively, a contact stop etch layer 140 and an interlayer dielectric layer 190 that integrally cover the substrate 100, the first gate structure 110, the second gate structure 150, the first spacer structure 130, the second spacer structure 170, the first epitaxial structure 120, and the second epitaxial structure 160, and a plurality of plug structures 180, 186 that electrically connect the second epitaxial structure 160 and the second gate structure 150, respectively. In one embodiment, the first metal silicide layer 122 and the second metal silicide layer 162 include, for example, silicides of the following metal materials, such as tungsten, aluminum, copper, titanium, tantalum, cobalt, nickel, platinum, or alloys thereof, but are not limited thereto. The contact stop etch layer 140 conformally covers the substrate 100, the first gate structure 110, the second gate structure 150, the first spacer structure 130, the second spacer structure 170, the first epitaxial structure 120 and the second epitaxial structure 160, and specifically includes a first stop etch layer 142 and a second stop etch layer 144 stacked in sequence. In one embodiment, the first stop etch layer 142 and the second stop etch layer 144 include different insulating materials such as silicon oxide, silicon nitride, silicon carbonitride, etc., but the present invention is not limited thereto.

[0104] The interlayer dielectric layer 190 further covers the contact stop etch layer 140 and has an overall flat top surface. In one embodiment, the interlayer dielectric layer 190 includes, for example, an insulating material such as silicon oxide, silicon nitride, silicon carbonitride, etc., preferably including an insulating material different from the first stop etch layer 142 or the second stop etch layer 144, but not limited thereto. The plug structures 180 and 186 are respectively disposed in the interlayer dielectric layer 190, penetrate the contact stop etch layer 140 and physically contact the second metal silicide layer 162 below. In another embodiment, the plug structures 180 and 186 respectively include a barrier layer 182 and a conductive layer 184 disposed in sequence, wherein the barrier layer 182 includes, for example, a conductive barrier material such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, and the conductive layer 184 includes, for example, copper, aluminum, tungsten or other suitable low-resistivity conductive materials, but not limited thereto.

[0105] According to the semiconductor device 10 of the present embodiment, since the second epitaxial structure 160 includes P-type dopants, the second gate structure 150, the second epitaxial structure 160 and the second spacer structure 170 can together form a P-type transistor component (PMOS), and the first gate structure 110 can be used as a dummy gate line of another P-type transistor component. Therefore, by disposing the first spacer structure 130 partially extending into the groove 106 of the shallow trench isolation 104 on the sidewall of the dummy gate line (the first gate structure 110), the dummy gate line can have a better isolation effect with the help of the first spacer structure 130, and has enhanced structural stability to resist the stress from the epitaxial structure, so that the semiconductor device 10 can achieve a more optimized operating performance. A person skilled in the art should be able to easily understand that, although the semiconductor device 10 of the present embodiment is described using a P-type transistor component as a specific implementation, the semiconductor device 10 of the present invention is not limited thereto. In another embodiment, an N-type transistor component with an opposite conductive form may be selectively disposed on other active regions 102 of the semiconductor device 10, and a dummy gate line disposed across the corresponding shallow trench isolation 104, so as to achieve the desired operating performance.

[0106] In order to enable a person skilled in the art to which the present invention pertains to easily understand the semiconductor device 10 of the present invention, a method for manufacturing the semiconductor device 10 of the present invention will be further described below.

[0107] See also Figures 2 to 9 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device 10 in a preferred embodiment of the present invention. First, Figure 2 As shown, a substrate 100 is provided, and at least one shallow trench isolation 104 is formed on the substrate 100, and an active area 102 is defined in the substrate 100. Next, two gate structures 210 and 250 separated from each other and respectively located on the shallow trench isolation 104 and the active area 102 are formed on the substrate 100 by a similar process, and then spacer stack structures 230 and 270 are formed respectively on the sidewalls of the two gate structures 210 and 250. In one embodiment, the manufacturing process of the gate structures 210 and 250 includes, for example, but is not limited to the following steps. First, a dielectric material layer (not shown, for example, including dielectric materials such as silicon oxide and silicon oxynitride), a semiconductor material layer (not shown, for example, including semiconductor materials such as doped polysilicon, doped silicon, and doped amorphous silicon), an insulating material layer (not shown, for example, including insulating materials such as silicon oxide and silicon oxynitride), and a capping material layer (not shown, for example, including insulating materials such as silicon nitride or silicon carbonitride) are sequentially stacked on the substrate 100, and finally, a patterning process is performed to simultaneously form the following. Figure 2The gate structures 210 and 250 are shown. The gate structure 210 includes a gate dielectric layer 212, a gate layer 214, an insulating layer 216 and a cap layer 218 stacked in sequence from bottom to top in the vertical direction Y, while the gate structure 250 includes a gate dielectric layer 252, a gate layer 254, an insulating layer 256 and a cap layer 258 stacked in sequence from bottom to top in the vertical direction Y.

[0108] In another embodiment, the manufacturing process of the spacer stack structures 230 and 270 includes, but is not limited to, the following steps: First, multiple deposition and back-etching processes are performed on the substrate 100 to sequentially deposit and back-etch a first spacer material layer (e.g., silicon oxide, silicon oxynitride), a second spacer material layer (e.g., silicon nitride, silicon carbonitride), a third spacer material layer (e.g., silicon oxide, silicon oxynitride) and a fourth spacer material layer (e.g., silicon nitride, silicon carbonitride) on the gate structures 210 and 250, and finally, the spacer stack structures 230 and 270 are formed on two opposite sidewalls of the gate structures 210 and 250, respectively. Among them, the details of the spacer stack structure 230 include a spacer material layer 232, a spacer material layer 234, a spacer material layer 236 and a spacer material layer 238 formed in sequence on the two opposite side walls of the gate structure 210 in the horizontal direction D1 or the opposite direction D2, and the details of the spacer stack structure 270 include a spacer material layer 272, a spacer material layer 274, a spacer material layer 276 and a spacer material layer 278 formed in sequence on the two opposite side walls of the gate structure 250 in the horizontal direction D1 or the opposite direction D2. It should be noted that since the spacer stacking structures 230 and 270 can be formed simultaneously, the film thickness and material of the spacer material layer 232, the spacer material layer 234, the spacer material layer 236 and the spacer material layer 238 of the spacer stacking structure 230 are, for example, respectively equivalent to the film thickness and material of the spacer material layer 272, the spacer material layer 274, the spacer material layer 276 and the spacer material layer 278 of the spacer stacking structure 270, and the spacer material layer 232, the spacer material layer 236, the spacer material layer 272, and the spacer material layer 276 preferably include the same material, and the spacer material layer 234, the spacer material layer 238, the spacer material layer 274, and the spacer material layer 278 preferably include materials different from the aforementioned materials, but are not limited to this.

[0109] like Figure 3As shown, an etching process is performed through a mask layer (not shown) to simultaneously form trenches 220 and 260 in the substrate 100, which are located on two opposite sides of the gate structures 210 and 250, respectively, and then the mask layer is completely removed. It should be noted that when forming the trench 220, the etching selectivity of the etching process is adjusted so that the shallow trench isolation 104 adjacent to the trench 220 and the spacer stack structure 230 above it (for example, at least including the bottom of the spacer material layer 234, the spacer material layer 236 and the spacer material layer 238, etc.) are etched simultaneously, and a groove 106 is formed in the shallow trench isolation 104. Among them, the groove 106 is, for example, located between the two trenches 220 and the gate structure 250 in the horizontal direction D1 or its opposite direction D2, as shown in FIG. Figure 3 shown.

[0110] like Figure 4 As shown, an epitaxial growth process is performed to form a first epitaxial structure 120 in the trench 220, and a second epitaxial structure 160 in the trench 260. The first epitaxial structure 120 and the second epitaxial structure 160 include, for example, doped or undoped semiconductor materials, such as silicon, silicon germanium, silicon phosphorus, silicon carbon or other similar materials, and preferably include dopants of the same conductive form, such as P-type dopants, but not limited thereto.

[0111] like Figure 5 As shown, a first removal process is performed, such as a dry etching process, a wet etching process, or a dry etching process and a wet etching process performed in sequence, to selectively remove the spacer material layer 232, the spacer material layer 236, the spacer material layer 272, and the spacer material layer 276 including silicon oxide material from the spacer stack structures 230 and 270. It should be noted that when the first removal process is performed, the spacer material layer 232, the spacer material layer 236, the spacer material layer 272, and the spacer material layer 276 are etched inward from the exposed portions, so that the spacer material layer 232 can be etched from the exposed top and the bottom exposed from the recess 106 at the same time, and a relatively large portion is removed, while the spacer material layer 236, the spacer material layer 272, and the spacer material layer 276 are only etched from the exposed top, and a relatively small portion is removed, such as Figure 5 shown.

[0112] like Figure 6As shown, a second removal process is performed, such as a dry etching process, a wet etching process, or a dry etching process and a wet etching process performed in sequence, to selectively remove the spacer material layer 234, the spacer material layer 238, the spacer material layer 274, and the spacer material layer 278 comprising silicon nitride material. It should be noted that when the second removal process is performed, the spacer material layer 234, the spacer material layer 238, the spacer material layer 274, and the spacer material layer 278 are also etched inward from the exposed portion, so that the spacer material layer 234, the spacer material layer 238, and the spacer material layer 278 with a larger exposure range can be completely removed. On the other hand, the spacer material layer 274 can only be etched from its exposed top, and a relatively small portion is removed to form a second spacer 174.

[0113] In addition, the etching selectivity of the second removal process can be adjusted synchronously, so that the cap layer 218 and the insulating layer 216 of the gate structure 210 are completely removed synchronously, and only the gate dielectric layer 212 and the gate layer 214 are retained, and the remaining portion of the spacer material layer 236 is also completely removed, while the spacer material layer 232 is partially removed to form a first spacer 132. The first spacer 132 is located on the sidewalls of the gate dielectric layer 212 and the gate layer 214, and its top surface is lower than the top surface 214t of the gate layer 214, as shown in FIG. Figure 6 As shown, but not limited to this. On the other hand, the cap layer 258 and the insulating layer 256 of the gate structure 250 are also completely removed simultaneously, leaving only the gate dielectric layer 252 and the gate layer 254, and the spacer material layer 272 and the spacer material layer 276 can also be further partially etched from the exposed top to form the first spacer 172 and the third spacer 176. The first spacer 172, the second spacer 174 and the third spacer 176 are sequentially located on the sidewalls of the gate dielectric layer 252 and the gate layer 254 in the horizontal direction D1 or the opposite direction D2, and the first spacer 172 and the second spacer 174 have flush top surfaces and are lower than the top surface 254t of the gate layer 254, as shown in FIG. Figure 6 As shown, but not limited to.

[0114] like Figure 7As shown, a deposition process is performed to sequentially form a first material layer 280 and a second material layer 282 on the substrate 100, conformally covering the substrate 100, the first epitaxial structure 120, the gate layer 214, the first spacer 132, the gate layer 254, the first spacer 172, the second spacer 174, the third spacer 176, and the second epitaxial structure 160. It should be noted that the first material layer 280 is also formed on the surface of the groove 106, and the second material layer 282 preferably has a relatively large film thickness to further fill the groove 106. In one embodiment, the first material layer 280 and the second material layer 282, for example, respectively include different dielectric materials such as silicon oxide, silicon nitride, silicon carbonitride, etc. For example, the first material layer 280 includes silicon oxide, and the second material layer 282 includes silicon nitride, but is not limited thereto. It should also be noted that when forming the first material layer 280 , part of the first material layer 280 is partially filled into the space between the third spacer 176 and the second epitaxial structure 160 , and a pore V1 sandwiched between the third spacer 176 and the second epitaxial structure 160 is formed in the first material layer 280 .

[0115] As shown in FIG. 8 , an etch-back process is performed to completely remove the second material layer 282 covering the substrate 100, the first epitaxial structure 120, the gate layer 214 and the first spacer 132, and thin the second material layer 282 filled in the groove 106 to form a third spacer 136. Furthermore, the first material layer 280 covering the substrate 100, the first epitaxial structure 120, the gate layer 214 and the top surface of the first spacer 132 is further removed, and only the first material layer 280 covered by the third spacer 136 is retained to form a second spacer 134. In this way, the first spacer 132, the second spacer 134 and the third spacer 136 stacked in sequence in the horizontal direction D1 or the opposite direction D2 form the first spacer structure 130 together. The third spacer 136 also includes a gap 136S extending into the groove 106 of the shallow trench isolation 104 and located above the shallow trench isolation 104. On the other hand, during the etching back process, the second material layer 282 covering the gate layer 254, the first spacer 172, the second spacer 174, the third spacer 176 and the second epitaxial structure 160 is also completely removed, and the first material layer 280 covering the top surface of the gate layer 254 and the second epitaxial structure 160 is completely removed, forming a fourth spacer 178 that conformally covers the first spacer 172, the second spacer 174 and the third spacer 176, which still retains the air hole V1 sandwiched between the third spacer 176 and the second epitaxial structure 160. In this way, the first spacer 172, the second spacer 174, the third spacer 176 and the fourth spacer 178 stacked in sequence on the sidewall of the second gate structure 150 in the horizontal direction D1 or the opposite direction D2 form the second spacer structure 170 together.

[0116] Then, after the etching back process, a metal silicide process is performed to form a first metal silicide layer 122 and a second metal silicide layer 162 on the exposed top surfaces of the first epitaxial structure 120, the gate layer 214, the gate layer 254, and the second epitaxial structure 160, respectively. In one embodiment, the metal silicide process includes but is not limited to the following steps. First, a selective deposition process is performed to form a metal layer (not shown), such as a metal material suitable for reacting with silicon materials, such as tungsten, aluminum, copper, titanium, tantalum, cobalt, nickel, platinum or its alloy, and then a heat treatment process is performed to make the metal layer react with the exposed top surfaces of the first epitaxial structure 120, the gate layer 214, the gate layer 254, and the second epitaxial structure 160, respectively, to form a first metal silicide layer 122 and a second metal silicide layer 162. Then, the unreacted metal layer is removed. Among them, the first metal silicide layer 122 and the second metal silicide layer 162, for example, include silicides of the aforementioned metal materials, etc., but are not limited thereto. In addition, after the first metal silicide layer 122 and the second metal silicide layer 162 are formed, the gate dielectric layer 212 and the gate layer 214 stacked in sequence below the first metal silicide layer 122 respectively form a first gate dielectric layer 112 and a first gate layer 114 stacked in sequence, and together form a first gate structure 110, and the gate dielectric layer 252 and the gate layer 254 stacked in sequence below the second metal silicide layer 162 respectively form a second gate dielectric layer 152 and a second gate layer 154 stacked in sequence, and together form a second gate structure 150, as shown in FIG. Figure 8 Thus, the second gate structure 150, the second spacer structure 170 and the second epitaxial structure 160 including P-type dopants together form a P-type transistor component, and the first gate structure 110 can form a dummy gate line of another P-type transistor component.

[0117] As shown in FIG. 9 , a deposition process is performed to sequentially form a first etching stop material layer 242 and a second etching stop material layer 244 on the substrate 100, conformally covering the substrate 100, the first gate structure 110, the first spacer structure 130, the second gate structure 150, and the second spacer structure 170, and physically contacting the first metal silicide layer 122 and the second metal silicide layer 162 formed on the first gate structure 110 and the second gate structure 150. In one embodiment, the first etching stop material layer 242 and the second etching stop material layer 244, for example, respectively include different etching stop materials such as silicon oxide, silicon nitride, silicon carbonitride, etc. For example, the first etching stop material layer 242, for example, includes silicon oxide or silicon oxynitride, and the second etching stop material layer 244, for example, includes silicon nitride or silicon carbonitride, but is not limited thereto.

[0118] Then, an interlayer dielectric layer 190 and plug structures 180 and 186 (such as the ones shown in FIG. 1 ) that cover the entire substrate 100 are formed on the second etching stop material layer 244. Figure 1 As shown), it can be formed as Figure 1 The semiconductor device 10 shown, wherein the plug structures 180, 186 are formed in the interlayer dielectric layer 190, and sequentially penetrate the second stop etching material layer 244 and the first stop etching material layer 242 to physically contact the second metal silicide layer 162 below. In one embodiment, the production of the plug structures 180, 186 includes but is not limited to the following steps. First, the interlayer dielectric layer 190, the second stop etching material layer 244 and the first stop etching material layer 242 are partially removed through a mask layer (not shown), and a plurality of plug holes (not shown), a second stop etching layer 144 and a first stop etching layer 142 are simultaneously formed. The first stop etching layer 142 and the second stop etching layer 144 stacked in sequence together form a Figure 1 The contact stop etching layer 140 is shown, and each of the plug holes penetrates the interlayer dielectric layer 190 and the contact stop etching layer 140 thereunder. Next, a barrier material layer (not shown, for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide) and a conductive material layer (not shown, for example, including copper, aluminum, tungsten or other suitable low-resistivity conductive materials) are sequentially stacked in each of the plug holes, and finally a planarization process is performed to form a conductive layer such as Figure 1 The barrier layer 182 and the conductive layer 184 are shown to form plug structures 180 , 186 .

[0119] Thus, the manufacturing of the semiconductor device 10 of the present embodiment is completed. According to the manufacturing method of the semiconductor device 10 of the present embodiment, when the trench 220 of the first epitaxial structure 120 is manufactured, the recess 106 is simultaneously etched in the shallow trench isolation 104, so that at least part of the bottom of the spacer stack structure 230 (for example, at least including the spacer material layer 234, the spacer material layer 236 and the spacer material layer 238, etc.) can be exposed from the recess 106, and the etching rate and degree of at least part of the spacer stack structure 230 in the subsequent first removal process and / or the second removal process are partially accelerated. In this way, the first spacer structure 130 that partially extends into the recess 106 is formed on the sidewall of the dummy gate line (the first gate structure 110), so that the dummy gate line can have a better isolation effect with the help of the first spacer structure 130, and has enhanced structural stability to resist the stress from the epitaxial structure, so that the semiconductor device 10 can achieve a more optimized operating performance. In addition, a person skilled in the art should be able to easily understand that, although the manufacturing method of this embodiment is described using the manufacturing steps of a P-type transistor component as an implementation example, the actual manufacturing process is not limited thereto, and in another embodiment, an N-type transistor component with an opposite conductive form may be formed or formed simultaneously, and a dummy gate line across the corresponding shallow trench isolation 104 may be provided to achieve the desired operational performance.

[0120] A person skilled in the art of the present invention should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device and the method for manufacturing the same may also have other aspects and are not limited to the above. The following will further describe other embodiments or variations of the semiconductor device and the method for manufacturing the same of the present invention. In order to simplify the description, the following description mainly describes the differences between the embodiments, and will not repeat the same aspects. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0121] Please refer to Figures 10 to 12 , which is a schematic diagram of the steps of the manufacturing method of the semiconductor device 30 in the second embodiment of the present invention. The structure and manufacturing steps of the semiconductor device 30 in this embodiment are substantially the same as those of the semiconductor device 10 in the aforementioned embodiment, with the main difference being that the first spacer structure 330 disposed on the sidewall of the first gate structure 110 includes a first spacer 332, a second spacer 334, a fourth spacer 338 and a third spacer 336 disposed in sequence in the horizontal direction D1 or in the opposite direction D2, and the second spacer structure 370 disposed on the sidewall of the second gate structure 150 includes a first spacer 372, a second spacer 374 and a third spacer 376 disposed in sequence in the horizontal direction D1 or in the opposite direction D2.

[0122] In detail, this embodiment is formed as described above. Figure 4 When the trenches 220 and 260 are formed, the shallow trench isolation 104 adjacent to the trench 220 and the spacer stack structure 230 (including the spacer stack structure 230) above the trench 220 are simultaneously etched by adjusting the etching selectivity of the etching process. Figure 4 The bottom of the spacer material layer 232, the spacer material layer 234, the spacer material layer 236 and the spacer material layer 238 are formed to form a groove (not shown) that can simultaneously expose the spacer material layer 232, the spacer material layer 234, the spacer material layer 236 and the spacer material layer 238. Fig.10 As shown, the following can be done as mentioned above Figure 5 The first removal process shown, and the Figure 6 After the second removal process shown, the spacer material layer 236 and the spacer material layer 238 are completely removed to form a first spacer 332 and a second spacer 334 on the sidewalls of the first gate structure 110, and the spacer material layer 276 and the spacer material layer 278 are completely removed, and the spacer material layer 272 and the spacer material layer 274 are partially removed to form a first spacer 372 and a second spacer 374 on the sidewalls of the second gate structure 150.

[0123] In this operation, the first spacer 372 and the second spacer 374 are disposed above the top surface 104t of the shallow trench isolation 104, and the first spacer 332 and the second spacer 334 have top surfaces 332t / 334t and bottom surfaces 332b / 334b flush with each other, the top surfaces 332t / 334t contact each other and are lower than the top surface of the first gate layer, and the bottom surfaces 332b / 334b contact each other and are higher than the top surface 100t of the substrate 100, as shown in FIG. Fig.10 As shown, but not limited to this. On the other hand, the first spacer 372 and the second spacer 374 are arranged on the top surface 100t of the substrate 100, and also have top surfaces 372t / 374t that are flush with each other, wherein the top surface 372t / 374t is lower than the top surface of the second gate layer 154. Then, a deposition process is performed to sequentially form a first material layer 280 and a second material layer 282 on the substrate 100, conformally covering the substrate 100, the first epitaxial structure 120, the first gate layer, the first spacer 332, the second spacer 334, the second gate layer 154, the first spacer 372, the second spacer 374 and the second epitaxial structure 160, wherein the first material layer 280 is conformally formed on the surface of the groove 106, and the second material layer 282 further fills the groove 106, as shown in FIG. Fig.10 shown.

[0124] like Fig.11As shown, an etch-back process is performed to completely remove the second material layer 282 covering the substrate 100, the first epitaxial structure 120 and the first gate layer, and at the same time thin the second material layer 282 filled in the groove 106 to form a third spacer 336, and further remove the first material layer 280 covering the substrate 100, the first epitaxial structure 120 and the top surface of the first gate layer, and retain the first material layer 280 covered by the third spacer 336 to form a fourth spacer 338. The fourth spacer 338 directly covers and contacts the top surface 332t / 334t and the bottom surface 332b / 334b of the first spacer 332 and the second spacer 334. Thus, the first spacer 132, the second spacer 134, the fourth spacer 338 and the third spacer 136 are sequentially stacked in the horizontal direction D1 or the opposite direction D2, and together form the first spacer structure 330 of the present embodiment, wherein the third spacer 336 further includes a slit 336S extending into the groove 106 of the shallow trench isolation 104 and located above the shallow trench isolation 104. The lowest point B1 of the slit 336S is also lower than the top surface 100t of the substrate 100.

[0125] On the other hand, when the etching back process is performed, the second material layer 282 covering the second epitaxial structure 160, the second gate layer 154, the first spacer 372 and the second spacer 374 is also completely removed, and the first material layer 280 covering the top surface of the second epitaxial structure 160 and the second gate layer 154 is completely removed to form a third spacer 376 that conformally covers the first spacer 372 and the second spacer 374. In this way, the first spacer 372, the second spacer 374 and the third spacer 376 are stacked in sequence in the horizontal direction D1 or the opposite direction D2, and can together form the second spacer structure 370 of the present embodiment. It should be noted that the first spacer 372, the second spacer 374 and the third spacer 376 of the second spacer structure 370 respectively include the same insulating material as the first spacer 132, the second spacer 134 and the fourth spacer 338 of the first spacer structure 330, but the present invention is not limited to this. Then, as shown in FIG. Fig.11 As shown, a metal silicide process is performed after the etch-back process to form a first metal silicide layer 122 and a second metal silicide layer 162 on the exposed top surfaces of the first epitaxial structure 120 , the first gate layer, the second epitaxial structure 160 and the second gate layer 154 , respectively.

[0126] like Fig.12 As shown, continue to form as mentioned above Fig. 9The first stop etching material layer 242 and the second stop etching material layer 244 are conformally covered on the substrate 100, the first gate structure 110, the first spacer structure 330, the second gate structure 150 and the second spacer structure 370, and then the interlayer dielectric layer 190 and the plug structures 180 and 186 are formed by the manufacturing method described in the above embodiment, so as to form the semiconductor device 30 of this embodiment. In detail, the semiconductor device 30 is also provided on the sidewall of the dummy gate line (the first gate structure 110) by partially extending the first spacer structure 330 into the groove 106, so that the dummy gate line can have a better isolation effect with the help of the first spacer structure 330, and has enhanced structural stability to resist the stress from the epitaxial structure, so that the semiconductor device 30 can achieve a more optimized operating performance. Among them, the third spacer 336 of the first spacer structure 330 also has a gap 336S above the shallow trench isolation 104, the lowest point B1 of which is lower than the top surface 100t of the substrate 100. Thus, the third spacers 336 are provided to strengthen the structural stability of the first spacer structure 330 and improve its isolation effect, so that the semiconductor device 30 of the present embodiment can achieve a more optimized operating performance.

[0127] According to the manufacturing method of the semiconductor device 30 of the present embodiment, when manufacturing the trench 220 of the first epitaxial structure 120, a recess 106 is simultaneously etched in the shallow trench isolation 104, so that the bottom of the spacer stack structure 230 (including the spacer material layer 232, the spacer material layer 234, the spacer material layer 236 and the spacer material layer 238, etc.) can be exposed from the recess 106, thereby accelerating the etching rate and degree of the spacer stack structure 230 in the subsequent first removal process and / or the second removal process. In this way, the first spacer structure 330 partially extending into the recess 106 of the shallow trench isolation 104 can be formed on the sidewall of the dummy gate line (the first gate structure 110), so that the dummy gate line can have a better isolation effect with the help of the first spacer structure 330, and has enhanced structural stability to resist the stress from the epitaxial structure, so that the semiconductor device 30 can achieve a more optimized operating performance.

[0128] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device, comprising: A substrate including an active area and a shallow trench isolation, wherein the shallow trench isolation includes at least one groove; A first gate structure, disposed on the shallow trench isolation, comprises a first gate dielectric layer and a first gate layer stacked in sequence; a first epitaxial structure, disposed in the active region on one side of the first gate structure; as well as A first spacer structure is disposed on a sidewall of the first gate structure and is located in the groove of the shallow trench isolation, wherein the lowest point of the first spacer structure is lower than the lowest point of the first gate structure.

2. The semiconductor device according to claim 1, wherein: The first spacer structure comprises: A first spacer, a second spacer and a third spacer are sequentially arranged on the side wall of the first gate structure in the horizontal direction, wherein the second spacer and the third spacer of the first spacer structure partially extend into the shallow trench isolation and are sandwiched between the shallow trench isolation and the first epitaxial structure.

3. The semiconductor device according to claim 2, characterized in that The bottommost surface of the first spacer of the first spacer structure physically contacts the top surface of the shallow trench isolation.

4. The semiconductor device according to claim 2, characterized in that The bottommost surface of the first spacer of the first spacer structure contacts the bottommost surface of the second spacer of the first spacer structure and is higher than the top surface of the substrate.

5. The semiconductor device according to claim 4, characterized in that The first spacer structure further includes: A fourth spacer is disposed between the second spacer and the third spacer in the horizontal direction, and the fourth spacer of the first spacer structure contacts the bottommost surfaces of the second spacer and the third spacer.

6. The semiconductor device according to claim 2, wherein: The bottommost surface of the second spacer of the first spacer structure is lower than the bottommost surface of the first spacer.

7. The semiconductor device according to claim 2, characterized in that The bottommost surface of the third spacer of the first spacer structure is lower than the bottommost surface of the first spacer.

8. The semiconductor device according to claim 2, wherein: The third spacer of the first spacer structure further includes a gap disposed on the portion extending into the shallow trench isolation.

9. The semiconductor device according to claim 8, characterized in that The lowest point of the gap is lower than the top surface of the substrate.

10. The semiconductor device according to claim 1, wherein: The first gate layer has a thickness in a direction perpendicular to the substrate, and a distance between the lowest point of the first gate structure and the lowest point of the first spacer structure is not less than 0.5 times of the thickness.

11. The semiconductor device according to claim 1, wherein: Also includes: A second gate structure, disposed on the active region, comprising a second gate dielectric layer and a second gate layer stacked in sequence; a second epitaxial structure, disposed in the active region on one side of the second gate structure; as well as The second spacer structure is arranged on the sidewall of the second gate structure and located on the top surface of the substrate.

12. The semiconductor device according to claim 11, characterized in that The second spacer structure comprises: A first spacer, a second spacer and a third spacer are sequentially arranged on the sidewall of the second gate structure in the horizontal direction, and the bottommost surfaces of the first spacer, the second spacer and the third spacer of the second spacer structure all physically contact the top surface of the substrate.

13. The semiconductor device according to claim 12, characterized in that Also includes: A first metal silicide layer, disposed on the first epitaxial structure and the first gate layer; as well as The second metal silicide layer is disposed on the second gate layer and the second epitaxial structure.

14. The semiconductor device according to claim 13, characterized in that Also includes: A contact stop etch layer conformally covers the substrate, the first gate structure, the first spacer structure, the second gate structure and the second spacer structure; as well as A plurality of plug structures are respectively arranged on the second gate layer and the second epitaxial structure.

15. The semiconductor device according to claim 14, characterized in that It also includes a fourth spacer, which is partially disposed between the third spacer and the second epitaxial structure and includes air holes sandwiched between the second epitaxial structure and the third spacer.

16. The semiconductor device according to claim 1, wherein: The shallow trench isolation includes two grooves respectively located on both sides of the first gate structure. The first spacer structure is arranged on the sidewalls of both sides of the first gate structure and is located in the two grooves of the shallow trench isolation.

17. A method for manufacturing a semiconductor device, comprising: Providing a substrate, the substrate comprising an active area and shallow trench isolation; forming a first gate structure on the shallow trench isolation, comprising a first gate dielectric layer and a first gate layer stacked in sequence; forming a first epitaxial structure in the active region on one side of the first gate structure; as well as A first spacer structure is formed on the sidewall of the first gate structure, the first spacer structure contacts the shallow trench isolation, and the lowest point of the first spacer structure is lower than the lowest point of the first gate structure.

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that: Also includes: forming a second gate structure on the active area, comprising a second gate dielectric layer and a second gate layer stacked in sequence; forming a second epitaxial structure in the active region on one side of the second gate structure; as well as A second spacer structure is formed on the sidewall of the second gate structure, and the second spacer structure is entirely formed on the top surface of the substrate.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that: Also includes: Forming a spacer stack structure on the sidewalls of the first gate structure and the second gate structure respectively, including at least one first spacer material layer and at least one second spacer material layer alternately stacked in a horizontal direction; Forming trenches in the active regions on both sides of each gate stack structure; as well as The first epitaxial structure and the second epitaxial structure are respectively formed in the trench.

20. The method for manufacturing a semiconductor device according to claim 19, characterized in that: Also includes: After forming the first epitaxial structure and the second epitaxial structure, performing a first removal process to at least partially remove the at least one first spacer material layer; After the first removal process, performing a second removal process to at least partially remove the at least one second spacer material layer; as well as After the second removal process is performed, a first material layer and a second material layer are formed on the remaining portion of the at least one first spacer material layer or the at least one second spacer material layer.

21. The method for manufacturing a semiconductor device according to claim 20, characterized in that: Also includes: The second material layer and the first material layer are partially removed so that the remaining second material layer, the remaining first material layer and the remaining at least one first spacer material layer together form the first spacer structure, wherein the first spacer structure includes a first spacer, a second spacer and a third spacer sequentially arranged on the side wall of the first gate structure in a horizontal direction, wherein the second spacer and the third spacer of the first spacer structure partially extend into the shallow trench isolation and are sandwiched between the shallow trench isolation and the first epitaxial structure, and the bottommost surface of the first spacer of the first spacer structure physically contacts the top surface of the shallow trench isolation.

22. The method for manufacturing a semiconductor device according to claim 20, characterized in that: Also includes: The second material layer and the first material layer are partially removed so that the remaining second material layer, the remaining first material layer, the remaining at least one first spacer material layer and the remaining at least one second spacer material layer together form the first spacer structure, the first spacer structure comprising a first spacer, a second spacer, a fourth spacer and a third spacer arranged in sequence on the side wall of the first gate structure in the horizontal direction, wherein the fourth spacer of the first spacer structure contacts the bottommost surfaces of the second spacer and the third spacer.

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