GaN vertical complementary field effect transistor and phase inverter

Abstract

The invention discloses a GaN vertical complementary field effect transistor (VCFET) and an inverter, the VCFET comprises a substrate, a first transistor, a second transistor and a common gate electrode, and the first transistor and the second transistor are sequentially and vertically stacked on the substrate; the first transistor is an n-type transistor, the second transistor is a p-type transistor, and an integral structural form of a GaN buffer layer, an n-tube GaN channel layer, an AlGaN barrier layer, a p-tube GaN channel layer and a p-tube GaN doping layer is formed; the control of the n-type channel and the p-type channel at the same time is realized through a common gate electrode. On the basis of the structure, the source electrode of the p-type transistor is connected with a high level, the source electrode of the n-type transistor is connected with a low level, the drain electrodes of the two transistors are connected together and serve as an output end at the same time, and the gate electrodes serve as an input end, so that the phase inverter can be realized. According to the VCFET, the electronic transmission characteristics of high efficiency and low power consumption are realized, the occupied area is smaller while the high performance is maintained, and the integration level is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a GaN vertical complementary field effect transistor (VCFET) and an inverter. Background Art

[0002] The materials of the GaN system, namely the Group III nitride materials, have a series of excellent physical properties, including large bandgap, high critical breakdown electric field, high mobility, and high electron saturation velocity. In addition, the polarization coefficient of the Group III nitride materials is relatively high, resulting in a high concentration of two-dimensional electron gas at the Group III nitride heterojunction interface. These excellent material properties enable GaN high electron mobility transistors (HEMTs) to have excellent performance such as high breakdown voltage, low on-resistance, low gate charge, high switching speed, and high energy conversion efficiency, making them core devices for applications in electric vehicles, power grids, high-speed railways, consumer electronics power modules and other fields.

[0003] The trend of miniaturization of RF and power electronic systems has put forward an urgent demand for GaN chips with monolithic integrated digital and analog integrated circuits. However, the traditional method requires discrete Si CMOS drive circuit modules, which increases the system volume and the complexity of system design. Therefore, GaN digital and analog circuits monolithically integrated with GaN HEMT RF and power electronic devices are of great significance. GaN field effect transistors and inverters are the core components of GaN digital and analog circuits, but there is still a lack of mature technology for GaN complementary field effect transistors and inverters. It has been reported in the literature that PMOS is realized by using p-GaN gate materials of normally-off GaN HEMTs and NMOS is realized by HEMT structures. However, the p-type impurity concentration of p-GaN has a high ionization energy, a low hole concentration, and a low hole mobility, resulting in a low output current of p-GaN PMOS; in addition, NMOS and PMOS are arranged horizontally, and the chip occupies a relatively large area. Summary of the invention

[0004] In order to overcome the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a GaN vertical complementary field effect transistor and an inverter, so that the complementary field effect transistor and the inverter have higher performance and smaller footprint.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] A first aspect of the present invention provides a GaN vertical complementary field effect transistor, comprising a substrate, a first transistor, a second transistor and a common gate electrode, wherein the first transistor and the second transistor are vertically stacked on the substrate in sequence;

[0007] The first transistor is an n-type transistor, comprising a GaN buffer layer, an n-tube GaN channel layer and a common AlGaN barrier layer arranged in sequence in a direction away from the substrate, wherein the GaN buffer layer is directly arranged on the substrate, and a two-dimensional electron gas is formed at a heterojunction interface between the GaN channel layer and the AlGaN barrier layer, and the two-dimensional electron gas region serves as an n-type channel, i.e., a conductive channel of the first transistor;

[0008] The second transistor is a p-type transistor, comprising the AlGaN barrier layer, the p-tube GaN channel layer and the p-tube GaN doping layer arranged in sequence in a direction away from the substrate, holes are accumulated at the heterojunction interface between the p-tube GaN channel layer and the AlGaN barrier layer to form a two-dimensional hole gas, and the two-dimensional hole gas region will serve as a p-type channel, i.e., a conductive channel of the second transistor;

[0009] The n-type channel and the p-type channel are stacked vertically; the first source electrode and the first drain electrode of the first transistor are arranged in the n-tube GaN channel layer, the second source electrode and the second drain electrode of the second transistor are arranged in the p-tube GaN channel layer, and the first transistor and the second transistor use the gate electrode together to achieve simultaneous control of the n-type channel and the p-type channel.

[0010] In one embodiment, the first source electrode and the first drain electrode of the first transistor are arranged at both ends of the n-tube GaN channel layer along the horizontal direction; the second source electrode and the second drain electrode of the second transistor are arranged at both ends of the p-tube GaN channel layer along the horizontal direction; and the gate electrode is arranged at both sides of the structure of the GaN vertical complementary field effect transistor along the horizontal direction.

[0011] In one embodiment, a horizontal direction in which the first source electrode and the first drain electrode are arranged, and a horizontal direction in which the second source electrode and the second drain electrode of the second transistor are arranged, are both perpendicular to a horizontal direction in which the gate electrode is arranged.

[0012] In one embodiment, the substrate is Si, SiC, sapphire or diamond, and is further selected to be Si.

[0013] In one embodiment, the underlying metal of the gate electrode is one of Ni, Ti, Mo, and Ta. Other metals except the underlying metal are different materials from the underlying metal and are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti, and are further selected from bottom to top as Ni / Au.

[0014] In one embodiment, the underlying metal of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode is one of Ti, Mo, and Ta, and the other metals except the underlying metal are different from the underlying metal and are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti, and are further selected from bottom to top to be Ti / Al / Ni / Au.

[0015] In one embodiment, the AlGaN barrier layer is unintentionally doped, with a molar composition of aluminum of 5-100% and a thickness of 3-30 nm, and further with an aluminum composition of 25% and a thickness of 20 nm to provide sufficient barrier height to prevent leakage current.

[0016] In one embodiment, the n-tube GaN channel layer has a thickness of 50-500 nm, is unintentionally doped, or is n-type doped, and is further selected to have a thickness of 200 nm, and is unintentionally doped.

[0017] In one embodiment, the p-tube GaN channel layer has a thickness of 10-30 nm, is unintentionally doped, or p-type doped, and is further selected to have a thickness of 20 nm, and is unintentionally doped.

[0018] In one embodiment, the p-type GaN doping layer has a thickness of 10-150 nm, is unintentionally doped, or heavily p-type doped, and the doping impurities of the p-type GaN doping layer are Mg or Zn. The impurity concentration of the p-type GaN doping layer is 1×10 18 -1×10 21 cm -3 The thickness is further selected as 80nm, the doping impurity is Mg, and the impurity concentration is 1×10 20 cm -3 .

[0019] In one embodiment, a gate dielectric layer is provided between the gate electrode and the n-tube GaN channel layer and the p-tube GaN channel layer, and the gate dielectric layer is used to insulate the n-tube GaN channel layer and the gate electrode and the p-tube GaN channel layer and the gate electrode.

[0020] In one embodiment, the gate dielectric layer is made of SiO2, SiN, Al2O3, HfO2, ZrO2 or AlN.

[0021] The second aspect of the present invention further provides a GaN vertical complementary field effect transistor inverter, which is based on the GaN vertical complementary field effect transistor described in the first aspect, wherein the gate electrode is the input terminal, the first drain electrode and the second drain electrode are connected and serve as the output terminal, the first source electrode is connected to a low level, and the second source electrode is connected to a high level, thereby realizing the logical inversion of the output terminal and the input terminal.

[0022] The third aspect of the present invention further provides a method for preparing a GaN vertical complementary field effect transistor as described in the first aspect, comprising the following steps:

[0023] Step 1, epitaxially growing a GaN buffer layer on a substrate;

[0024] Step 2, growing an n-tube GaN channel layer on the GaN buffer layer;

[0025] Step 3, forming a first source electrode and a first drain electrode at the end of the n-tube GaN channel layer;

[0026] Step 4, epitaxially growing an AlGaN barrier layer on the n-tube GaN channel layer;

[0027] Step 5, growing a p-tube GaN channel layer on the AlGaN barrier layer;

[0028] Step 6, making a second source electrode and a second drain electrode at the end of the p-tube GaN channel layer;

[0029] Step 7, growing a p-tube GaN doping layer on the p-tube GaN channel layer;

[0030] Step eight, make gate electrodes on both sides of the transistor.

[0031] In one embodiment, the GaN buffer layer, the n-tube GaN channel layer, the p-tube GaN channel layer and the p-tube GaN doping layer are all formed by MOCVD process at a process temperature of 1000° C.

[0032] The first source electrode, the first drain electrode, the second source electrode and the second drain electrode are all made by photolithography process to make a photoresist mask to expose the electrodes to be made, and then multi-layer metal is grown on the exposed area by electron beam evaporation. After peeling, the corresponding electrodes are formed.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] (1) Since the CFET structure stacks the first transistor (N-type transistor) and the second transistor (P-type transistor) vertically on the substrate layer in sequence, the area occupied by the two transistors on the horizontal plane is greatly reduced, so that a higher transistor density can be achieved on a smaller chip area. In other words, the CFET structure simultaneously achieves the miniaturization of the device volume in the horizontal direction and the vertical direction.

[0035] (2) The gate electrode design on both sides of the CFET structure can provide better gate electrode control, reduce leakage current, and increase switching speed.

[0036] (3) The vertical stacking structure of the CFET helps to reduce parasitic capacitance and resistance, improving the overall performance of the device.

[0037] (4) In the CFET structure, by using a double heterojunction structure of p-GaN layer-AlGaN barrier layer-n-GaN layer, the conductive channels of N-type transistors and P-type transistors can be simultaneously produced, and the thickness of the conductive channel can be reduced to a certain extent, thereby further miniaturizing the size and thickness of the device.

[0038] (5) Since the n-type and p-type transistors are closely arranged, faster switching speeds can be provided, which is an important advantage for CMOS inverters, especially in high-speed digital logic applications. Due to the lower leakage current of the CFET structure, the power consumption of the CMOS inverter in static and dynamic operations will also be reduced accordingly.

[0039] (6) Since the vertical stacking structure of the transistors facilitates vertical conduction of heat, rather than horizontal conduction in a planar structure, this helps improve the thermal management of the CMOS inverter, reduce thermal resistance, and improve the long-term stability of the device. The vertical stacking structure also helps reduce parasitic capacitance and resistance, improving the overall electrical performance of the CMOS inverter.

[0040] (7) In addition, the technology proposed by the present invention is compatible with the original process, and the process manufacturing steps are relatively simple.

[0041] The overview of the technical solution of the present invention only provides a preliminary outline. In order to deeply understand the technical details and implementation methods of the present invention, the actual operation can be carried out with reference to the detailed contents of this specification. In addition, in order to more clearly show the various items, features and advantages of the present invention, a specific embodiment of the present invention will be described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] By carefully reading the detailed description of the following specific embodiments, professionals in the field will be able to clearly recognize the many additional advantages and benefits of the present invention. The drawings provided are only for the purpose of showing specific embodiments and should not be regarded as any limitation of the present invention. In addition, in all drawings, the same parts are represented by consistent reference numerals to maintain consistency and clarity of the description. In the drawings:

[0043] Figure 1 It is a three-dimensional structural diagram of the GaN vertical complementary field effect transistor (VCFET) of the present invention.

[0044] Figure 2 It is a schematic diagram of the three-dimensional structure and cross-sectional position of the GaN vertical complementary field effect transistor (VCFET) of the present invention.

[0045] Figure 3 The GaN vertical complementary field effect transistor (VCFET) of the present invention is Figure 2 Cross-sectional view along direction A.

[0046] Figure 4 The GaN vertical complementary field effect transistor (VCFET) of the present invention is Figure 2 Cross-sectional view along direction B.

[0047] Figure 5 The gate electrode (50) in the GaN vertical complementary field effect transistor (VCFET) of the present invention is Figure 2 Cross-sectional view along the C direction.

[0048] Figure 6-Figure 14 It is a partial schematic diagram of a formation process of a GaN vertical complementary field effect transistor (VCFET) provided by an embodiment of the present invention.

[0049] In the figure:

[0050] 10-substrate; 21-n-tube GaN doping layer; 22-n-tube GaN channel layer; 23-first source electrode; 24-first drain electrode; 30-AlGaN barrier layer; 41-p-tube GaN doping layer; 42-p-tube GaN channel layer; 43-second source electrode; 44-second drain electrode; 50-gate electrode; 51-gate dielectric layer. DETAILED DESCRIPTION

[0051] The embodiments of the present invention are described in detail below with reference to the accompanying drawings and examples.

[0052] It should be noted that the drawings show various structural schematic diagrams drawn according to the embodiments of the present invention, which are not made according to the actual scale. Some details are enlarged for clearer expression, and some details may be omitted to simplify the display. The shapes of the regions and layers shown in the drawings and their relative sizes and positional relationships are all exemplary in nature, and may differ in actual production due to manufacturing tolerances or technical constraints. In addition, professionals in this field can design regions or layers with different shapes, sizes and relative layouts according to actual needs.

[0053] In the discussion herein, when a layer / element is mentioned as being "above" another layer / element, this means that the layer / element may directly cover the other layer / element, or other layers / element may be interposed therebetween. Similarly, if a layer / element is "above" another layer / element in a particular direction, it is "below" the layer / element in the opposite direction. In the description herein, similar or identical parts may be identified using consistent or similar numbers.

[0054] In order to have a deeper understanding of the aforementioned technical solution, the following will be elaborated in detail in conjunction with a specific implementation scheme. It should be understood that the embodiments of the present disclosure and their specific features are specific descriptions of the technical solution of the present application and do not constitute a limitation on the technical solution of the present application. Without violating the principles, the embodiments of the present application and the technical elements contained therein can be combined with each other.

[0055] Example 1

[0056] like Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the present invention is a GaN vertical complementary field effect transistor (VCFET), comprising a substrate 10, a first transistor, a second transistor and a common gate electrode 50. The first transistor and the second transistor are vertically stacked on the substrate 10 in sequence.

[0057] For ease of description, the present invention may define an XYZ coordinate system, where the Z direction is defined as the thickness direction of the transistor, i.e., the stacking direction. Figure 1 In the above diagram, the Y direction is defined as the length direction of the layer. Figure 1 In the figure, it is represented as the left and right direction, and the X direction is defined as the width direction of the layer. Figure 1 The middle represents the front-to-back direction.

[0058] The first transistor of the present invention is an n-type transistor, comprising a GaN buffer layer 21, an n-tube GaN channel layer 22, a first source electrode 23, a first drain electrode 24 and a common AlGaN barrier layer 30, wherein the GaN buffer layer 21 is directly arranged on the substrate 10, and the GaN buffer layer 21, the n-tube GaN channel layer 22 and the AlGaN barrier layer 30 are arranged in sequence in a direction away from the substrate 10. The first source electrode 23 and the first drain electrode 24 of the first transistor are arranged on the n-tube GaN channel layer 22, and a two-dimensional electron gas (2DEG) is formed at the heterojunction interface between the GaN channel layer 22 and the AlGaN barrier layer 30, and the 2DEG region serves as an n-type channel, i.e., a conductive channel of the first transistor.

[0059] The second transistor of the present invention is a p-type transistor, including an AlGaN barrier layer 30, a p-tube GaN channel layer 42, a p-tube GaN doping layer 41, a second source electrode 43, and a second drain electrode 44. The p-tube GaN channel layer 42 is directly arranged on the AlGaN barrier layer 30, and is opposite to the GaN channel layer 22 up and down. The AlGaN barrier layer 30, the p-tube GaN channel layer 42, and the p-tube GaN doping layer 41 are arranged in sequence in a direction away from the substrate 10. The second source electrode 43 and the second drain electrode 44 of the second transistor are arranged in the p-tube GaN channel layer 42. At the heterojunction interface between the p-tube GaN channel layer 42 and the AlGaN barrier layer 30, holes accumulate to form a two-dimensional hole gas (2DHG), and the 2DHG region will serve as a p-type channel, that is, a conductive channel of the second transistor.

[0060] In the present invention, the n-type channel and the p-type channel are stacked vertically, wherein the common AlGaN barrier layer 30 means that the AlGaN barrier layer 30 is a common layer of the first transistor and the second transistor. The common gate electrode 50 means that the gate electrode 50 is a common gate of the first transistor and the second transistor. The first transistor and the second transistor use the gate electrode 50 together, which can realize the control of the n-type channel and the p-type channel at the same time.

[0061] The complementary field effect transistor provided in the embodiment of the present invention reduces the area occupied by the two transistors on the horizontal plane by vertically stacking the first transistor and the second transistor on the substrate, thereby achieving a higher transistor density on a smaller chip area. At the same time, this vertical stacking structure can also reduce parasitic capacitance and resistance.

[0062] Through the shared AlGaN barrier layer, the present invention forms a double heterojunction structure of p-GaN layer-AlGaN barrier layer-n-GaN layer, which can not only simultaneously manufacture the conductive channels of n-type transistors and p-type transistors, but also reduce the thickness of the conductive channels to a certain extent, further reducing the thickness of the transistors.

[0063] In general, the VCFET of the present invention realizes high-efficiency, low-power consumption electronic transmission characteristics, has a smaller footprint while maintaining high performance, and improves integration.

[0064] For example, the first source electrode 23 and the first drain electrode 24 of the first transistor of the present invention are arranged at the left and right ends of the n-tube GaN channel layer 22 in the horizontal direction, that is, the two ends in the Y direction, and the first source electrode 23 and the first drain electrode 24 have the same thickness as the n-tube GaN channel layer 22. The second source electrode 43 and the second drain electrode 44 of the second transistor are arranged at the left and right ends of the p-tube GaN channel layer 42 in the horizontal direction, that is, the two ends in the Y direction, and the second source electrode 43 and the second drain electrode 44 have the same thickness as the p-tube GaN channel layer 42. The gate electrode 50 is arranged on the front and back sides of the structure of the GaN vertical complementary field effect transistor in the horizontal direction, that is, the two sides in the X direction. The gate electrode 50 can be directly arranged on the substrate 10 and is consistent with the total thickness of the GaN buffer layer 21, the n-tube GaN channel layer 22, the AlGaN barrier layer 30, the p-tube GaN channel layer 42, and the p-tube GaN doping layer 41. The structure designed on both sides of the gate electrode 50 can provide better gate electrode control, reduce leakage current, and improve switching speed.

[0065] Example 2

[0066] On the basis of Example 1, the present invention provides a GaN vertical complementary field effect transistor inverter, with the gate electrode 50 as the input terminal, the first drain electrode 24 and the second drain electrode 44 are connected and used as the output terminal, the first source electrode 23 is connected to a low level, and the second source electrode 43 is connected to a high level, so that the output terminal and the input terminal can be logically reversed.

[0067] Since the present invention adopts a structure in which n-type and p-type transistors are closely arranged, it can provide a faster switching speed. At the same time, since the leakage current of the CFET structure of the present invention is low, the power consumption of the inverter in static and dynamic operations can also be reduced accordingly.

[0068] At the same time, since the transistor of the present invention adopts a vertical stacking structure, vertical heat conduction is more conducive to heat dissipation, which makes the stability of the inverter better. In addition, the transistor has smaller parasitic capacitance and resistance, which also makes the overall electrical performance of the inverter better.

[0069] Example 3

[0070] On the basis of Embodiment 1, a gate dielectric layer 51 is provided between the gate electrode 50 and the n-tube GaN channel layer 22 and between the p-tube GaN channel layer 42. The material of the gate dielectric layer 51 can be SiO2, SiN, Al2O3, HfO2, ZrO2 or AlN. In this embodiment, HfO2 is selected. The gate dielectric layer 51 can insulate the n-tube GaN channel layer 22 and the gate electrode 50 and the p-tube GaN channel layer 42 and the gate electrode 50.

[0071] Example 4

[0072] The present invention provides a process flow for manufacturing a complementary field effect transistor with a vertical stacking structure as follows:

[0073] Step 1: a silicon oxide film is formed on the side of the substrate 10 for stacking the first transistor and the second transistor. Figure 5 As shown, hydrogen is introduced into the reaction chamber at a high temperature of 1000° C. to remove pollutants on the surface of the substrate 10 and form a microscopic step structure on the substrate surface to facilitate the subsequent epitaxial growth of various epitaxial layers. The substrate 10 is made of silicon with a thickness of 800 μm.

[0074] Step 2: epitaxially grow a GaN buffer layer 21 on the substrate 10, such as Figure 6 shown.

[0075] The temperature is raised to 1000° C. and a GaN buffer layer 21 with a thickness of 1000 nm is grown on the substrate 10 by MOCVD. The GaN buffer layer 21 is n-type doped, specifically silicon (Si) doped, with a doping concentration of 1×10 18 cm -3 .

[0076] Step 3: Prepare n-tube GaN channel layer 22, such as Figure 7 shown.

[0077] The n-type GaN channel layer 22 is grown on the GaN buffer layer 21 at a temperature of 1000°C by MOCVD. The n-type GaN channel layer 22 is doped with n-type, specifically silicon (Si) doping, with a doping concentration of 1×10 18 cm -3 .

[0078] Step 4: fabricate a first source electrode 23 and a first drain electrode 24 on both sides of the n-tube GaN channel layer 22 in the horizontal direction. Figure 8 , Fig. 9 shown.

[0079] A photolithography process is used to make a photoresist mask to expose the first source electrode 23 and the first drain electrode 24 of the first transistor to be manufactured, and then multiple layers of metal Ti / Al / Ni / Au are grown in the area by electron beam evaporation, namely, 50nm thick Ti, 150nm thick Al, 50nm thick Ni, and 50nm thick Au from bottom to top. After peeling, the first transistor source electrode 23 and the first drain electrode 24 are formed.

[0080] Step 5: Continue to make the AlGaN barrier layer 30, such as Fig.10 shown.

[0081] An AlGaN barrier layer 30 with a thickness of 30 nm is epitaxially grown on the n-tube GaN channel layer 22 . The AlGaN barrier layer 30 is undoped and has an aluminum composition of 0.3.

[0082] Step 6: Prepare the p-tube GaN channel layer 42, such as Fig.11 shown.

[0083] By using the MOCVD method, at a temperature of 1000° C., a p-type GaN channel layer 42 with a thickness of 300 nm is grown on the AlGaN barrier layer 30, wherein the p-type GaN channel layer 42 is doped with p-type, specifically with magnesium (Mg), and the doping concentration is 1×10 18 cm -3 .

[0084] Step 7: Make a second source electrode 43 and a second drain electrode 44 on both sides of the p-tube GaN channel layer 42 in the horizontal direction. Fig.12 , Fig.13 shown.

[0085] A photolithography process is used to make a photoresist mask to expose the second source electrode 43 and the first drain electrode 44 of the second transistor to be manufactured, and then multiple layers of metal Ti / Al / Ni / Au are grown in the area by electron beam evaporation, namely, 50nm thick Ti, 150nm thick Al, 50nm thick Ni, and 50nm thick Au from bottom to top. After peeling, the second transistor source electrode 43 and the second drain electrode 44 are formed.

[0086] Step eight, making a p-tube GaN doping layer 41, such as Fig.13 shown.

[0087] The temperature is raised to 1000°C, and a p-type GaN doping layer 41 with a thickness of 1000 nm is grown on the p-type GaN channel layer 42 by MOCVD. The p-type GaN doping layer 41 is doped with p-type, specifically magnesium (Mg), and the doping concentration is 1×10 18 cm -3 .

[0088] Step nine, forming gate electrodes 50 on both sides of the transistor, such as Figure 4 As shown, the gate electrode 50 is made of Ti / Au, and hafnium oxide can be set as the gate dielectric layer 51.

[0089] According to the above steps, the VCFET of the present invention can be manufactured, and its process is compatible with the original process.

[0090] The above description is only a specific example of the present invention and does not constitute any limitation to the present invention. It is obvious that for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention, as long as the scope of the technical solution in the specification is met. However, these modifications and changes based on the ideas of the present invention are still within the protection scope of the present invention.

Claims

1. A GaN vertical complementary field effect transistor, characterized in that: It comprises a substrate (10), a first transistor, a second transistor and a common gate electrode (50), wherein the first transistor and the second transistor are vertically stacked in sequence on the substrate (10); The first transistor is an n-type transistor, comprising a GaN buffer layer (21), an n-tube GaN channel layer (22) and a common AlGaN barrier layer (30) arranged in sequence in a direction away from the substrate (10), wherein the GaN buffer layer (21) is directly arranged on the substrate (10), and a two-dimensional electron gas is formed at a heterojunction interface between the GaN channel layer (22) and the AlGaN barrier layer (30), and the two-dimensional electron gas region serves as an n-type channel, i.e., a conductive channel of the first transistor; The second transistor is a p-type transistor, comprising the AlGaN barrier layer (30), a p-tube GaN channel layer (42) and a p-tube GaN doping layer (41) arranged in sequence in a direction away from the substrate (10); holes are accumulated at the heterojunction interface between the p-tube GaN channel layer (42) and the AlGaN barrier layer (30) to form a two-dimensional hole gas, and the two-dimensional hole gas region will serve as a p-type channel, i.e., a conductive channel of the second transistor; The n-type channel and the p-type channel are stacked vertically; the first source electrode (23) and the first drain electrode (24) of the first transistor are arranged on the n-tube GaN channel layer (22), the second source electrode (43) and the second drain electrode (44) of the second transistor are arranged on the p-tube GaN channel layer (42), and the first transistor and the second transistor use the gate electrode (50) together to achieve simultaneous control of the n-type channel and the p-type channel.

2. A GaN vertical complementary field effect transistor according to claim 1, characterized in that: The first source electrode (23) and the first drain electrode (24) of the first transistor are arranged at two ends of the n-tube GaN channel layer (22) in the horizontal direction; the second source electrode (43) and the second drain electrode (44) of the second transistor are arranged at two ends of the p-tube GaN channel layer (42) in the horizontal direction; and the gate electrode (50) is arranged at two sides of the structure of the GaN vertical complementary field effect transistor in the horizontal direction.

3. The GaN vertical complementary field effect transistor according to claim 2, characterized in that: The horizontal direction in which the first source electrode (23) and the first drain electrode (24) are arranged, and the horizontal direction in which the second source electrode (43) and the second drain electrode (44) of the second transistor are arranged, are both perpendicular to the horizontal direction in which the gate electrode (50) is arranged.

4. A GaN vertical complementary field effect transistor according to claim 2 or 3, characterized in that: The substrate (10) is Si, SiC, sapphire or diamond; the bottom layer metal of the gate electrode (50) is one of Ni, Ti, Mo and Ta; the other metals except the bottom layer metal are different from the bottom layer metal and are composed of one or more of Au, Ni, Al, Mo, Ta and Ti; the bottom layer metal of the first source electrode (23), the first drain electrode (24), the second source electrode (43) and the second drain electrode (44) is one of Ti, Mo and Ta; the other metals except the bottom layer metal are different from the bottom layer metal and are composed of one or more of Au, Ni, Al, Mo, Ta and Ti.

5. The GaN vertical complementary field effect transistor according to claim 1, characterized in that: The AlGaN barrier layer (30) is unintentionally doped, and the molar composition of aluminum is 5-100%, and the thickness is between 3-30nm, so as to provide a sufficient barrier height to prevent leakage current; the n-tube GaN channel layer (22) has a thickness of 50-500nm, and is unintentionally doped, or n-type doped; the p-tube GaN channel layer (42) has a thickness of 10-30nm, and is unintentionally doped, or p-type doped; the p-tube GaN doping layer (41) has a thickness of 10-150nm, and is unintentionally doped, or p-type heavily doped; the doping impurities of the p-tube GaN doping layer (41) are Mg or Zn, and the impurity concentration of the p-tube GaN doping layer (41) is 1×10 18 -1×10 21 -3 cm.

6. The GaN vertical complementary field effect transistor according to claim 1, characterized in that: A gate dielectric layer (51) is provided between the gate electrode (50) and the n-tube GaN channel layer (22) and the p-tube GaN channel layer (42); the gate dielectric layer (51) is used to insulate the n-tube GaN channel layer (22) and the gate electrode (50), and the p-tube GaN channel layer (42) and the gate electrode (50).

7. The GaN vertical complementary field effect transistor according to claim 6, characterized in that: The material of the gate dielectric layer (51) is SiO2, SiN, Al2O3, HfO2, ZrO2 or AlN.

8. A GaN vertical complementary field effect transistor inverter, characterized in that: A GaN vertical complementary field effect transistor according to any one of claims 1 to 7, wherein the gate electrode (50) is an input terminal, the first drain electrode (24) and the second drain electrode (44) are connected and serve as an output terminal, the first source electrode (23) is connected to a low level, and the second source electrode (43) is connected to a high level, so as to achieve logical inversion between the output terminal and the input terminal.

9. A method for preparing a GaN vertical complementary field effect transistor according to any one of claims 1 to 7, comprising the following steps: Step 1: epitaxially growing a GaN buffer layer (21) on a substrate (10); Step 2: growing an n-tube GaN channel layer (22) on the GaN buffer layer (21); Step three, manufacturing a first source electrode (23) and a first drain electrode (24) at the end of the n-tube GaN channel layer (22); Step 4, epitaxially growing an AlGaN barrier layer (30) on the n-tube GaN channel layer (22); Step 5, growing a p-tube GaN channel layer (42) on the AlGaN barrier layer (30); Step six, manufacturing a second source electrode (43) and a second drain electrode (44) at the end of the p-tube GaN channel layer (42); Step seven, growing a p-tube GaN doping layer (41) on the p-tube GaN channel layer (42); Step eight, forming gate electrodes (50) on both sides of the transistor.

10. The method for preparing a GaN vertical complementary field effect transistor according to claim 9, characterized in that: The GaN buffer layer (21), the n-tube GaN channel layer (22), the p-tube GaN channel layer (42) and the p-tube GaN doping layer (41) are all formed using an MOCVD process at a process temperature of 1000° C.; The first source electrode (23), the first drain electrode (24), the second source electrode (43) and the second drain electrode (44) are all formed by photolithography to produce a photoresist mask to expose the electrodes to be produced, and then multiple layers of metal are grown on the exposed areas by electron beam evaporation. After peeling, corresponding electrodes are formed.

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