Heterogeneous channel gate-all-around device and preparation method thereof

Abstract

The heterogeneous channel ring gate device comprises an NMOS device and a PMOS device which are adjacently arranged, the NMOS device and the PMOS device are respectively provided with a gate structure surrounding the side face of the respective channel, the channel material of the NMOS device is different from the channel material of the PMOS device, and the gate structures are arranged on the side faces of the channels of the NMOS device and the PMOS device. And the composition and the material of the work function layer in the gate structure of the NMOS device are the same as the composition and the material of the work function layer in the gate structure of the PMOS device. According to the invention, the NMOS and the PMOS are provided with the heterogeneous channels, the improvement of the carrier mobility of the PMOS is facilitated, the on-state current of the device is further improved, and the same set of work function gate material is adopted for the NMOS and the PMOS through the combination of the heterogeneous channels, so that the gate stacking process of the ring gate device is simplified.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a heterogeneous channel gate-all-around device and a preparation method thereof. Background Art

[0002] At present, the development of integrated circuit technology has encountered some bottlenecks. As the size of transistors gradually approaches the physical limit, quantum effects and parasitic effects cause the power consumption density to increase, resulting in the increasing difficulty and cost of research and development of proportional miniaturization of transistor size. Therefore, in recent years, the speed of integration has gradually fallen behind the prediction of "Moore's Law", and the industry has entered the "post-Moore era".

[0003] In the "post-Moore era", research on integrated circuits has changed from the original planar process miniaturization to seeking opportunities in the vertical direction, including the research of advanced process nodes such as Nanosheet and Forksheet after FinFET, hoping to continue "Moore's Law" by integrating devices or chips in the vertical direction.

[0004] At the 2 / 3nm node, we are entering the all-around gate device technology. Unlike the FinFET channel which is surrounded by gates on three sides, the all-around gate device is surrounded by gates on four sides, so it is called an all-around gate device. However, in the gate stacking process of the traditional all-around gate device, since NMOS and PMOS use the same Si material channel, it is necessary to process the work function layer of the NMOS gate and the work function layer of the PMOS gate separately, which not only complicates the process, but also because the composition difference between the work function layer of the NMOS gate and the work function layer of the PMOS gate is large, the spacing between NMOS and PMOS is restricted by the thickness of the work function layer of PMOS, which affects the miniaturization of the device.

[0005] Therefore, it is necessary to provide a novel all-around gate device and gate stacking technology thereof to solve the above-mentioned problems existing in the prior art. Summary of the invention

[0006] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and to provide a heterogeneous channel gate-all-around device and a preparation method thereof.

[0007] To achieve the above object, the technical solution of the present invention is as follows: The present invention provides a heterogeneous channel gate-all-around device, comprising: an NMOS device and a PMOS device arranged adjacent to each other, wherein the NMOS device and the PMOS device are respectively provided with a gate structure enclosed on the side of their respective channels, the channel material of the NMOS device is different from the channel material of the PMOS device, and the work function layer composition and material in the gate structure of the NMOS device are the same as the work function layer composition and material in the gate structure of the PMOS device.

[0008] Further, the NMOS device and the PMOS device are adjacently arranged on one side of the substrate, the NMOS device is provided with a first channel and a first gate structure enclosed on the side of the first channel, the first gate structure is provided with a first work function layer, the first work function layer includes a plurality of first sub-work function layers, the PMOS device is provided with a second channel and a second gate structure enclosed on the side of the second channel, the second gate structure is provided with a second work function layer, the second work function layer includes a plurality of second sub-work function layers, the material of the first channel is a first semiconductor, the material of the second channel is a second semiconductor different from the first semiconductor, each of the first sub-work function layers is arranged corresponding to each of the second sub-work function layers, and the material of each of the first sub-work function layers is the same as the material of a corresponding second sub-work function layer.

[0009] Furthermore, the first gate structure is also provided with a first gate metal layer enclosed outside the first work function layer, and the second gate structure is also provided with a second gate metal layer enclosed outside the second work function layer, and the first gate metal layer and the second gate metal layer are connected between the NMOS device and the PMOS device.

[0010] Further, the NMOS device includes a plurality of first channels arranged in parallel in a direction away from the substrate, and the first work function layer and the first gate metal layer are sequentially enclosed on the side of each first channel. The PMOS device includes a plurality of second channels arranged in parallel in a direction away from the substrate, and the second work function layer and the second gate metal layer are sequentially enclosed on the side of each second channel. The first gate metal layer is also filled between any two adjacent first channels, the second gate metal layer is also filled between any two adjacent second channels, and the first gate metal layer and the second gate metal layer are also filled between the first channel and the second channel to be tightly connected.

[0011] Furthermore, a material of the first gate metal layer is the same as a material of the second gate metal layer, forming a gate metal layer shared by the first gate structure and the second gate structure.

[0012] Further, the cross-sectional dimensions of the first channel are the same as the cross-sectional dimensions of the second channel, the thickness of the first work function layer is the same as the thickness of the second work function layer, or the thickness of each of the first sub-work function layers is the same as the thickness of a corresponding second sub-work function layer; and / or, the first channel and the second channel are staggered in a direction away from the substrate.

[0013] Further, the first semiconductor includes Si, and the second semiconductor includes SiGe; and / or, the number of the first sub-work function layer and the second sub-work function layer is three, which include a TiN layer, a TiAl layer and a TiN layer from the inside to the outside; and / or, a SiO2 layer and a HfO2 layer are provided in sequence from the inside to the outside between the first channel and the first work function layer, and between the second channel and the second work function layer.

[0014] Further, the thickness of the TiN layer is 1~2nm, the thickness of the TiAl layer is 3~4nm, the thickness of the TiN layer is 1~2nm, or the thickness of the first work function layer and the second work function layer is 8~11nm; the thickness of the SiO2 layer is less than 1nm, and the thickness of the HfO2 layer is 1~2nm.

[0015] Furthermore, the heterogeneous channel gate-all-around device includes an inverter.

[0016] The present invention also provides a method for preparing a heterogeneous channel gate-all-around device, comprising: Adjacently arranged NMOS devices and PMOS devices are formed, so that the NMOS device and the PMOS device are respectively formed with gate structures enclosed on the sides of their respective channels, the channel material of the NMOS device is different from the channel material of the PMOS device, and the work function layer composition and material in the gate structure of the NMOS device are the same as the work function layer composition and material in the gate structure of the PMOS device.

[0017] Furthermore, the method for forming the NMOS device and the PMOS device specifically includes: providing a substrate; A first channel of the NMOS device and a second channel of the PMOS device are formed on one side of the substrate; the material of the first channel is a first semiconductor, and the material of the second channel is a second semiconductor different from the first semiconductor; A first gate structure enclosed on the side of the first channel and a second gate structure enclosed on the side of the second channel are formed; the first gate structure includes a first work function layer, the first work function layer includes a plurality of first sub-work function layers, the second gate structure is provided with a second work function layer, the second work function layer includes a plurality of second sub-work function layers, each of the first sub-work function layers is arranged corresponding to each of the second sub-work function layers, and the material of each of the first sub-work function layers is the same as the material of a corresponding second sub-work function layer.

[0018] Furthermore, the method for forming the first channel and the second channel specifically includes: Alternatingly forming a plurality of second semiconductor layers and a plurality of first semiconductor layers on the surface of the substrate whose material is the first semiconductor; Patterning the second semiconductor layer and the first semiconductor layer to form a plurality of fins on the surface of the substrate, including adjacent first fins and second fins, and forming isolation trenches downward on the surface of the substrate at both sides of the fins; forming a first dielectric layer on the surface of the substrate to fill the isolation trench; forming a dummy gate across the first fin and the second fin, and an outer wall layer covering the dummy gate, the first fin and the second fin, and then removing the first fin and the second fin exposed outside the two sides of the dummy gate; At least partially remove the second semiconductor layer material exposed on both ends of the first fin and the first semiconductor layer material exposed on both ends of the second fin to form a recess, and then form an inner sidewall in the recess; forming a first source and a drain at two ends of the first semiconductor layer exposed by the first fin, and forming a second source and a drain at two ends of the second semiconductor layer exposed by the second fin; An opening is formed at the top of the outer wall layer to expose the top of the dummy gate below, and then the dummy gate is removed to form a cavity, and the remaining second semiconductor layer material on the first fin and the remaining first semiconductor layer material on the second fin are removed, thereby forming a plurality of first channels corresponding to the plurality of first semiconductor layers on the first fin, and forming a plurality of second channels corresponding to the plurality of second semiconductor layers on the second fin.

[0019] Furthermore, the method for forming the first gate structure and the second gate structure specifically includes: forming a work function layer including a plurality of sub-work function layers on the side surfaces of the first channel and the second channel in the cavity, wherein the sub-work function layer on the side surface of the first channel serves as the first sub-work function layer, and the sub-work function layer on the side surface of the second channel serves as the second sub-work function layer; And a gate metal layer is filled in the cavity.

[0020] Furthermore, the first semiconductor includes Si, and the second semiconductor includes SiGe; and / or, the number of the sub-work function layers is three, including a TiN layer, a TiAl layer and a TiN layer from the inside to the outside.

[0021] Furthermore, before forming the work function layer, it also includes: firstly forming a SiO2 layer and a HfO2 layer in sequence on the side surfaces of the first channel and the second channel in the cavity, and then forming the work function layer on the HfO2 layer.

[0022] Furthermore, after forming the gate metal layer, the method further includes: forming a cap layer on the opening to seal the gate metal layer.

[0023] It can be seen from the above technical scheme that the present invention uses an integration technology of using different channel materials for NMOS devices and PMOS devices (for example, the first channel material of the NMOS device uses Si, and the second channel material of the PMOS device uses SiGe) to enable NMOS and PMOS to have heterogeneous channels, which is beneficial to improving the carrier mobility of PMOS, thereby increasing the on-state current of the device, and is beneficial to using the same set of work function gate materials for NMOS and PMOS through the combination of heterogeneous channels, thereby simplifying the gate stacking process of the ring-gate device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The figure is a schematic structural diagram of a heterogeneous channel gate-all-around device according to a preferred embodiment of the present invention.

[0025] Figure 2 The present invention is a flowchart of a method for preparing a heterogeneous channel gate-all-around device according to a preferred embodiment of the present invention.

[0026] Figure 3-Figure 24 A preferred embodiment of the present invention is based on Figure 2 Methods A schematic diagram of the process steps for preparing a heterogeneous channel gate-all-around device.

[0027] Fig.25 The figure is a schematic diagram of a gate-all-around structure of a heterogeneous channel gate-all-around device according to a preferred embodiment of the present invention.

[0028] Fig.26 The figure is a schematic diagram of a gate-all-around structure of an existing homogeneous channel gate-all-around device. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0030] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0031] refer to Figure 1 and Fig.25 , Figure 1 FIG. 1 is a schematic structural diagram of a heterogeneous channel gate-all-around device according to a preferred embodiment of the present invention. Fig.25 FIG. 1 is a schematic diagram of a gate-all-around structure of a heterogeneous channel gate-all-around device according to a preferred embodiment of the present invention. Figure 1 and Fig.25 As shown, a heterogeneous channel gate-all-around device of the present invention comprises: an NMOS device and a PMOS device arranged adjacent to each other. The NMOS device and the PMOS device are respectively provided with a channel and a gate structure enclosed on the side of each channel. The material of the channel of the NMOS device is different from the material of the channel of the PMOS device; and the composition and material of the work function layer in the gate structure of the NMOS device are the same as the composition and material of the work function layer in the gate structure of the PMOS device.

[0032] refer to Figure 1 and Fig.25 In some embodiments, the NMOS device and the PMOS device are disposed adjacent to each other on one side of the substrate 10 . Figure 1 A structure in which an NMOS device and a PMOS device are adjacently disposed on the upper surface of a substrate 10 is shown.

[0033] The channel of the NMOS device is defined as the first channel 13, the gate structure of the NMOS device is the first gate structure 14, and the first gate structure 14 is surrounded on the side of the first channel 13. That is, the first channel 13 is surrounded by the first gate structure 14 on all four sides. The channel of the PMOS device is defined as the second channel 18, the gate structure of the PMOS device is the second gate structure 17, and the second gate structure 17 is surrounded on the side of the second channel 18. That is, the second channel 18 is surrounded by the second gate structure 17 on all four sides.

[0034] In some embodiments, the first gate structure 14 of the NMOS device is provided with a first work function layer 141 enclosed on the side of the first channel 13, and the first work function layer 141 includes a plurality of first sub-work function layers 1411 sequentially enclosed on the side of the first channel 13. That is, the first channel 13 is surrounded on all four sides by the first work function layer 141 and its first sub-work function layer 1411. The second gate structure 17 of the PMOS device is provided with a second work function layer 172 enclosed on the side of the second channel 18, and the second work function layer 172 includes a plurality of second sub-work function layers 1721 sequentially enclosed on the side of the second channel 18. That is, the second channel 18 is surrounded on all four sides by the second work function layer 172 and its second sub-work function layer 1721.

[0035] In some embodiments, the material of the first channel 13 is a first semiconductor, and the material of the second channel 18 is a second semiconductor different from the first semiconductor material. Therefore, the channel material of the NMOS device is different from the channel material of the PMOS device, forming a heterogeneous channel all-around device structure.

[0036] In some embodiments, each first sub-work function layer 1411 of the first gate structure 14 is disposed correspondingly to each second sub-work function layer 1721 of the second gate structure 17, and the material of each first sub-work function layer 1411 is the same as the material of a corresponding second sub-work function layer 1721. In other words, the number of layers of the first sub-work function layer 1411 is the same as the number of layers of the second sub-work function layer 1721, and the material of the first sub-work function layer 1411 and the material of the second sub-work function layer 1721 located in the same layer are the same.

[0037] In some embodiments, any two adjacent first sub-work function layers 1411 are made of different materials. Any two adjacent second sub-work function layers 1721 are made of different materials.

[0038] In some embodiments, the first gate structure 14 is further provided with a first gate metal layer 142 enclosed outside the first work function layer 141. That is, the first channel 13 is surrounded by the first gate metal layer 142 on all four sides. The second gate structure 17 is further provided with a second gate metal layer 171 enclosed outside the second work function layer 172. That is, the second channel 18 is surrounded by the second gate metal layer 171 on all four sides. Moreover, the first gate metal layer 142 and the second gate metal layer 171 are connected between the NMOS device and the PMOS device. In this embodiment, the first gate metal layer 142 and the second gate metal layer 171 are closely connected as a whole between the NMOS device and the PMOS device.

[0039] refer to Figure 1 and Fig.25 In some embodiments, the NMOS device includes a plurality of first channels 13 sequentially arranged in parallel in a direction away from the upper surface of the substrate 10, and the side of each first channel 13 is sequentially enclosed by a first work function layer 141 and a first gate metal layer 142. The PMOS device includes a plurality of second channels 18 sequentially arranged in parallel in a direction away from the upper surface of the substrate 10, and the side of each second channel 18 is sequentially enclosed by a second work function layer 172 and a second gate metal layer 171. The first gate metal layer 142 is also filled between any two adjacent first channels 13, the second gate metal layer 171 is also filled between any two adjacent second channels 18, and the first gate metal layer 142 and the second gate metal layer 171 are also filled between the first channel 13 and the second channel 18, so that the first gate metal layer 142 and the second gate metal layer 171 are closely connected as a whole.

[0040] In some embodiments, the material of the first gate metal layer 142 is the same as the material of the second gate metal layer 171. By forming the first gate metal layer 142 and the second gate metal layer 171 as one, a gate metal layer 38 shared by the first gate structure 14 and the second gate structure 17 is formed, thereby forming a gate stacking structure of a heterogeneous channel ring gate device on the surface of the substrate 10. Multi-threshold voltage can be achieved by the ring gate device of the present invention. It should be noted that the present invention does not limit the number of stacking layers in the gate stacking structure, that is, the number of the first channel 13 / first gate structure 14 and the second channel 18 / second gate structure 17.

[0041] In some embodiments, the cross-sectional dimensions of the first channel 13 are the same as the cross-sectional dimensions of the second channel 18. For example, the first channel 13 has a cross-sectional width and height that are consistent with those of the second channel 18.

[0042] In some embodiments, the thickness of the first work function layer 141 and the thickness of the second work function layer 172 are the same.

[0043] Further, the thickness of each first sub-work function layer 1411 of the first work function layer 141 is the same as the thickness of a corresponding second sub-work function layer 1721 of the second work function layer 172 .

[0044] In some other embodiments, the cross-sectional dimensions of the first channel 13 and the cross-sectional dimensions of the second channel 18 may be different. For example, the first channel 13 has a cross-sectional width and height different from those of the second channel 18 .

[0045] In some embodiments, the first channel 13 and the second channel 18 are staggered in a direction away from the upper surface of the substrate 10. Figure 1 For example, the spacing between two first channels 13 adjacent to each other may correspond to the height of the second channel 18, or the spacing between two second channels 18 adjacent to each other may correspond to the height of the first channel 13. Then, on the vertical projection plane, the first channels 13 and the second channels 18 will be arranged alternately in the vertical direction.

[0046] In some embodiments, the first semiconductor includes Si and the second semiconductor includes SiGe. The substrate 10 includes a Si substrate 10 of a first semiconductor material.

[0047] refer to Figure 1 and Fig.25 In some embodiments, the number of the first sub-work function layer 1411 and the second sub-work function layer 1721 is three layers, which include a TiN layer, a TiAl layer and a TiN layer from the inside to the outside. That is, in the gate stacking structure, the three first sub-work function layers 1411 in the first work function layer 141 of the NMOS device and the three second sub-work function layers 1721 in the second work function layer 172 of the PMOS device are all TiN layers, TiAl layers and TiN layers arranged from the inside to the outside, so that the composition and materials of the work function layers of the NMOS device and the PMOS device are exactly the same, forming a unified work function layer 37 and sub-work function layer 371 structure of the NMOS device and the PMOS device.

[0048] In some embodiments, a SiO2 layer and a HfO2 layer are disposed from inside to outside respectively between the first channel 13 and the first work function layer 141, and between the second channel 18 and the second work function layer 172. That is, the NMOS device and the PMOS device have the same SiO2 layer and HfO2 layer.

[0049] In some embodiments, the thickness of the SiO2 layer is less than 1 nm, and the thickness of the HfO2 layer is 1-2 nm.

[0050] The thickness of the TiN layer is 1~2nm. The thickness of the TiAl layer is 3~4nm. The thickness of the TiN layer is 1~2nm.

[0051] In some embodiments, the thickness of the first work function layer 141 and the second work function layer 172 is about 8-11 nm. In some embodiments, a trench isolation structure 12 is provided on the surface of the Si substrate 10. The trench isolation structure 12 is formed by filling a first dielectric layer 11 in an isolation trench.

[0052] In some embodiments, an outer wall 19 is provided on the side of the gate structure of the NMOS device and the PMOS device to enclose the gate structure. In addition, a second dielectric layer 15 (ILD layer) is provided on the surface of the Si substrate 10, and the second dielectric layer 15 encloses the outer wall 19 from the side, and the second dielectric layer 15 is connected to the surface of the first dielectric layer 11 below as a whole.

[0053] In some embodiments, a capping layer 16 is disposed on the top of the gate structures of the NMOS device and the PMOS device. The capping layer 16 is connected to the top of the outer sidewall 19 to isolate the gate structures of the NMOS device and the PMOS device from the outside.

[0054] In some embodiments, the heterogeneous channel gate-all-around device of the present invention includes an inverter, but the present invention is not limited thereto.

[0055] The following further describes in detail a method for preparing a heterogeneous channel gate-all-around device of the present invention through specific implementation modes and in combination with the accompanying drawings.

[0056] A method for preparing a heterogeneous channel gate-all-around device of the present invention comprises: Adjacently arranged NMOS devices and PMOS devices are formed so that the NMOS devices and the PMOS devices respectively have gate structures enclosed on the sides of their respective channels, the channel material of the NMOS device is different from the channel material of the PMOS device, and the work function layer composition and material in the gate structure of the NMOS device are the same as the work function layer composition and material in the gate structure of the PMOS device.

[0057] refer to Figure 2 , Figure 2 Flow chart of a method for preparing a heterogeneous channel all-around gate device according to a preferred embodiment of the present invention. In some embodiments, a method for preparing a heterogeneous channel all-around gate device according to the present invention can be used to prepare, for example Figure 1 A heterogeneous channel gate-all-around device of the present invention is shown, and includes the following steps: Step S1: providing a substrate.

[0058] like Figure 3 As shown, a Si substrate 10 is used to prepare a heterogeneous channel gate-all-around device of the present invention on the substrate 10 through the heterogeneous channel gate stacking process of the present invention.

[0059] Step S2: preparing the source and drain of the NMOS device and the PMOS device.

[0060] like Figure 3 As shown, an epitaxial process is used to alternately form multiple SiGe layers and multiple Si layers on the surface of the Si substrate 10. Among them, the SiGe layer is used as the second semiconductor layer 181, and the Si layer is used as the first semiconductor layer 131. In this embodiment, an epitaxial process is used to alternately form three SiGe layers and two Si layers on the surface of the Si substrate 10, that is, three second semiconductor layers 181 and two first semiconductor layers 131 are alternately formed on the surface of the Si substrate 10, and the top layer is a SiGe layer (second semiconductor layer 181), and its thickness is greater than the thickness of each SiGe layer and the thickness of each Si layer in the lower layer.

[0061] Then, the second semiconductor layer 181 and the first semiconductor layer 131 are patterned by a patterning process to form a plurality of fins on the surface of the Si substrate 10. The fins include adjacent first fins and second fins. And by continuing the patterning process, isolation trenches are formed downward on the surface of the Si substrate 10 on both sides of the formed fins. In this embodiment, Figure 4 As shown in FIG. 1 , a first silicon oxide layer 201 and a first silicon nitride layer 202 are sequentially deposited on the surface of the uppermost SiGe layer as a first hard mask layer 20. Afterwards, a photoresist is spin-coated on the surface of the first hard mask layer 20, and a first photoresist pattern 21 is formed on the surface of the first silicon nitride layer 202 by a photolithography process. Figure 5 As shown, then, an etching process is adopted to form a first fin 22 and a second fin 23 on the surface of the Si substrate 10 by pattern transfer, and isolation trenches are formed by etching downward on the surface of the Si substrate 10 on both sides of the formed fins. In this embodiment, the first fin 22 and the second fin 23 are composed of a five-layer pattern structure of SiGe layer, Si layer, SiGe layer, Si layer, and SiGe layer alternately arranged from bottom to top. Afterwards, the remaining photoresist is removed, and there is a remaining patterned first hard mask layer 20 (including a patterned first silicon oxide layer 201 and a patterned first silicon nitride layer 202) on the top of the fin.

[0062] like Figure 5 As shown, next, a dielectric deposition process is used to deposit a first dielectric layer 11 on the surface of the Si substrate 10 to fill the isolation trench, and the first dielectric layer 11 covers the first hard mask layer 20 pattern on the top of the fin. Then, a planarization process is used, such as a chemical mechanical polishing process, to planarize the surface of the first dielectric layer 11 to expose the remaining surface of the first silicon nitride layer 202.

[0063] like Figure 6As shown, the chemical mechanical polishing process is then continued to be used to thin the top of the first dielectric layer 11 until the surface of the uppermost SiGe layer on the first fin 22 and the second fin 23 is exposed from the surface of the thinned first dielectric layer 11, and the remaining thickness of the uppermost SiGe layer on the first fin 22 and the second fin 23 is consistent with (or substantially consistent with) the thickness of each SiGe layer below.

[0064] Next, the first dielectric layer 11 is selectively etched, for example, by using a dielectric etch-back process, the first dielectric layer 11 is thinned and etched, so that the surface of the etched first dielectric layer 11 is reduced to a height position flush with or substantially flush with the surface of the Si substrate 10, thereby forming a trench isolation structure 12 filled with the first dielectric layer 11. At this time, the first fin 22 and the second fin 23 will be completely exposed on the surface of the Si substrate 10. Then, a dielectric protection layer 24 is deposited on the surface of the Si substrate 10 through a dielectric deposition process, so that the dielectric protection layer 24 covers the surface of the first dielectric layer 11 and the top and side surfaces of the first fin 22 and the second fin 23, so as to protect the surfaces of the first fin 22 and the second fin 23.

[0065] like Figure 7 As shown, then, a deposition process is used to deposit, for example, a polysilicon layer 25 for forming a dummy gate on the surface of the dielectric protection layer 24 (omitted in the figure, the same below), to cover the top of the first fin 22 and the second fin 23, and a chemical mechanical polishing process is used to flatten the surface of the polysilicon layer 25. Then, a second silicon nitride layer 261 and a second silicon oxide layer 262 are sequentially deposited on the flat surface of the polysilicon layer 25 as a second hard mask layer 26. Thereafter, a photoresist is spin-coated on the surface of the second hard mask layer 26, and a second photoresist pattern 27 is formed on the surface of the second silicon oxide layer 262 by a photolithography process.

[0066] like Figure 8 As shown, then, the polysilicon layer 25 is patterned by pattern transfer using an etching process, and after the polysilicon layer 25 is etched, a polysilicon dummy gate 251 spanning the first fin 22 and the second fin 23 is formed. Both ends of the first fin 22 and the second fin 23 need to be exposed on both sides of the dummy gate 251. Afterwards, the remaining photoresist is removed.

[0067] like Fig. 9As shown, a selective etching process is used to remove the remaining second silicon oxide layer 262 located on the top of the patterned second hard mask layer 26, and the second silicon nitride layer 261 located at the lower layer in the pattern of the second hard mask layer 26 is retained. Then, by depositing a third silicon nitride layer on the surface of the Si substrate 10 again, an outer wall layer 28 covering the dummy gate 251, the second silicon nitride layer 261, the first fin 22 and the second fin 23 is formed. The outer wall layer 28 also covers the dielectric protection layer 24 at the same time. The dielectric protection layer 24 needs to use a dielectric material with a large etching selectivity ratio with silicon nitride.

[0068] like Fig.10 As shown, then, an etching process, such as an etch-back process, is used to etch the outer wall layer 28 to remove the outer wall layer 28 covering the dielectric protection layer 24. By using the second silicon nitride layer 261 in the retained second hard mask layer 26, it is possible to avoid exposing the top of the dummy gate 251 and damaging the dummy gate 251 due to insufficient thickness of the top of the outer wall layer 28 when etching the outer wall layer 28.

[0069] Next, the dielectric protection layer 24 exposed outside the two sides of the dummy gate 251 (actually, exposed outside the two sides of the outer wall layer 28 covering the dummy gate 251) is removed using the outer wall layer 28 as a mask, exposing the surface of the first fin 22 and the second fin 23. The first fin 22 and the second fin 23 exposed outside the two sides of the dummy gate 251 are further cut off by an etching process, and the end faces of the cut first fin 22 and the second fin 23 are exposed on the two side surfaces of the outer wall layer 28. Then, the top of the outer wall layer 28 is flattened by a chemical mechanical polishing process to form an outer wall 19, and the flat top of the dummy gate 251 is exposed.

[0070] like Fig.11 As shown, then, spin-coat photoresist on the structure formed after the above steps, and form a third photoresist pattern 29 through a photolithography process, and use the third photoresist pattern 29 to block the PMOS device area and expose the NMOS device area. And use a lateral etching process to at least partially remove the SiGe second semiconductor layer 181 material exposed at both ends of the first fin 22, and form a lateral first recess 1811 in situ. Then, remove the remaining photoresist in the PMOS device area. Then, use the same process, that is, spin-coat photoresist again, and form a fourth photoresist pattern 30 through a photolithography process, and use the fourth photoresist pattern 30 to block the NMOS device area and expose the PMOS device area. And use a lateral etching process to at least partially remove the Si first semiconductor layer 131 material exposed at both ends of the second fin 23, and form a lateral second recess 1311 in situ, as shown Fig.12 Afterwards, the remaining photoresist in the NMOS device area is removed.

[0071] like Fig.13 As shown, a dielectric deposition process is then used to deposit, for example, silicon oxide material on the surface of the Si substrate 10 to cover the top of the dummy gate 251. Then, a selective etching process, such as a dielectric etch-back process, is used to etch the silicon oxide material deposited in the previous step until the original surface of the first dielectric layer 11 is exposed. Thus, the silicon oxide material that has not been etched away is filled in the first recess 1811 and the second recess 1311, and the inner sidewall 31 is formed in situ.

[0072] like Fig.14 As shown, then, spin-coat photoresist on the structure formed after the above steps, and form a fifth photoresist pattern 32 through a photolithography process, and use the fifth photoresist pattern 32 to block the PMOS device area to expose the NMOS device area. And use an N-type doped epitaxial source-drain process to form a first source-drain 132 (one end is the source end, and the other end is the drain end) at both ends of the Si first semiconductor layer 131 exposed by the first fin 22. Then, remove the remaining photoresist in the PMOS device area. Then, spin-coat the photoresist again, and form a sixth photoresist pattern 33 through a photolithography process, and use the sixth photoresist pattern 33 to block the NMOS device area to expose the PMOS device area, and use a P-type doped epitaxial source-drain process to form a second source-drain 182 (one end is the source end, and the other end is the drain end) at both ends of the SiGe second semiconductor layer 181 exposed by the second fin 23, as shown. Fig.15 As shown. Afterwards, the remaining photoresist in the NMOS device area is removed. Thus, the source and drain preparation of the NMOS device and the PMOS device is completed.

[0073] Step S3: preparing channels of NMOS devices and PMOS devices.

[0074] like Fig.16 As shown, next, a dielectric deposition process is used to grow a second dielectric layer 15 (ILD layer) on the surface of the first dielectric layer 11 to cover the device structure formed in the previous step. Then, a chemical mechanical polishing process is used to flatten the surface of the second dielectric layer 15 to expose the flat top of the dummy gate 251 and the outer sidewall 19, thereby forming an opening at the top of the outer sidewall 19. Fig.17 Shows Fig.16 The device structure is revealed after the first dielectric layer 11 and the second dielectric layer 15 are processed through perspective.

[0075] like Fig.18As shown, a wet etching process is then used to remove the dummy gate 251 through the opening formed at the top of the outer sidewall 19, and a cavity 34 is formed in situ within the outer sidewall 19, exposing the first fin 22 and the second fin 23 located in the cavity 34. Then, a wet etching process is used to remove the dielectric protection layer 24 covering the surface of the first fin 22 and the second fin 23 in the cavity 34. Fig.19 Shows the Fig.18 The half-section structure of the device formed in the fin section direction clearly shows the first fin 22 and the second fin 23 located in the cavity 34 after the dielectric protection layer 24 is removed.

[0076] like Fig. 20 As shown, then, a photoresist is spin-coated on the structure formed after the above steps, and a seventh photoresist pattern 35 is formed by a photolithography process. The seventh photoresist pattern 35 is used to block the PMOS device area and expose the NMOS device area. Note that the second fin 23 located in the cavity 34 needs to be completely blocked. Then, a wet etching process is used to remove the SiGe second semiconductor layer 181 material on the exposed first fin 22, and the Si first semiconductor layer 131 material on the first fin 22 is retained, so that the Si first channels 13 of multiple NMOS devices are formed corresponding to the multiple mutually spaced Si first semiconductor layers 131 on the formed first fin 22. After the SiGe second semiconductor layer 181 material is removed, the inner sidewall 31 will be exposed.

[0077] like Fig.21 As shown, the remaining photoresist in the PMOS device area is removed. Then, the photoresist is spin-coated again, and an eighth photoresist pattern 36 is formed by a photolithography process. The NMOS device area is shielded by the eighth photoresist pattern 36 to expose the PMOS device area. Note that the first channel 13 that has been prepared in the cavity 34 needs to be completely shielded. Then, a wet etching process is used to remove the Si first semiconductor layer 131 material on the exposed second fin 23, and the SiGe second semiconductor layer 181 material on the second fin 23 is retained, so that the SiGe second channels 18 of multiple PMOS devices are formed corresponding to the multiple mutually spaced SiGe second semiconductor layers 181 on the formed second fin 23. After the Si first semiconductor layer 131 material is removed, the inner sidewall 31 will be exposed. After that, the remaining photoresist in the NMOS device area is removed. Thereby, the channels of the NMOS device and the PMOS device are prepared.

[0078] Step S4: preparing gate structures of NMOS devices and PMOS devices.

[0079] like Fig. 22 and Fig.25As shown, a SiO2 layer is first grown as an interface layer on the side of the first channel 13 and the second channel 18 in the cavity 34 by a thermal oxidation process. Then, a HfO2 layer is deposited on the surface of the second dielectric layer 15 by, for example, an ALD process, and the deposited HfO2 layer covers the surface of the SiO2 layer on the side of the first channel 13 and the second channel 18. Then, a TiN layer, a TiAl layer, and a TiN layer are sequentially deposited on the surface of the HfO2 layer by, for example, an ALD process, and the deposited TiN layer, TiAl layer, and TiN layer sequentially cover the side of the first channel 13 and the second channel 18 in the cavity 34, that is, cover the surface of the HfO2 layer as an interface layer. Figure 1 The first gate structure 14 and the second gate structure 17 shown have a common three-layer structure of a sub-work function layer 371 (i.e., each first sub-work function layer 1411 of the first work function layer 141 and the second sub-work function layer 1721 of the corresponding second work function layer 172 are made of the same material). In this way, a work function layer 37 having three identical sub-work function layers 371 is prepared and formed on the side of the first channel 13 and the second channel 18. Among them, the sub-work function layer 371 located on the side of the first channel 13 is used as the first sub-work function layer 1411, and the sub-work function layer 371 located on the side of the second channel 18 is used as the second sub-work function layer 1721. This allows the NMOS device and the PMOS device to have a unified work function layer 37 structure, as shown in FIG. Fig.25 shown.

[0080] like Fig.23 As shown, next, a gate metal layer 38 is filled in the cavity 34, for example, metal tungsten is filled in the cavity 34 as the gate metal layer 38, and planarization is performed to expose the top surface of the tungsten gate metal layer 38 in the cavity 34. Thus, a first gate structure 14 of the NMOS device enclosed on the side of the first channel 13 and a second gate structure 17 of the PMOS device enclosed on the side of the second channel 18 are prepared in the cavity 34 (that is, the NMOS device and the PMOS device have a gate metal layer 38 with a unified integral structure, and the first gate metal layer 142 and the second gate metal layer 171 are formed by preparing the gate metal layer 38 in one step). Thus, the gate stacking structure of the present invention is prepared, and the NMOS device and the PMOS device are formed.

[0081] Step S5: preparing the cover layer 16 .

[0082] like Fig.24 As shown, the top of the tungsten gate metal layer 38 exposed in the cavity 34 is etched to form a groove at the opening of the top of the cavity 34. Finally, a fourth silicon nitride layer, for example, is deposited in the groove and planarized, and a cap layer 16 is formed on the opening of the cavity 34 to seal the tungsten gate metal layer 38. Thus, the preparation of the heterogeneous channel all-around gate device of the present invention is completed.

[0083] refer to Fig.26 , Fig.26 The schematic diagram of the ring gate structure of an existing homogeneous channel ring gate device is shown in FIG. In the existing NMOS and PMOS ring gate devices, NMOS and PMOS use a homogeneous Si material channel, and on this basis, a ring gate structure is formed by a gate stacking process. Among them, the ring gate structure of NMOS includes a SiO2 layer, a HfO2 layer, a TiN layer, a TiAl layer, a TiN layer and a W layer that are arranged in sequence from the inside to the outside around the Si channel of NMOS, and the ring gate structure of PMOS includes a SiO2 layer, a HfO2 layer, a TiN layer, a TaN layer, a TiN layer, a TiAl layer, a TiN layer and a W layer that are arranged in sequence from the inside to the outside around the Si channel of PMOS.

[0084] The gate stacking process of existing NMOS and PMOS all-around gate devices (AS-IS traditional all-around gate devices) is generally: Using the ALD process, SiO2 layer (<1nm), HfO2 layer (1~2nm), TiN layer (1~2nm) and TaN layer (1~2nm) are deposited on the channel side of NMOS and PMOS in sequence; then, PMOS is covered (using BARC) and the TaN layer of NMOS is etched away; the photoresist is removed, and then TiN (1~2nm), TiAl layer (3~4nm) and TiN (1~2nm) are deposited together with NMOS and PMOS. The final work function thickness of NMOS is about 8~11nm, and the work function thickness of PMOS is about 12~15nm. The process is complicated because the work function layers of NMOS and PMOS need to be processed separately. In addition, due to the large difference in composition between the work function layers of NMOS and PMOS, the spacing between NMOS and PMOS is restricted by the thickness of the work function layer of PMOS, which affects the miniaturization of the device.

[0085] refer to Fig.25 , Fig.25 The schematic diagram of the ring gate structure of a heterogeneous channel ring gate device of a preferred embodiment of the present invention. The NMOS and PMOS ring gate devices of the present invention, NMOS and PMOS use heterogeneous Si channels (first channels 13) and SiGe channels (second channels 18), and on this basis, a ring gate structure is formed by a gate stacking process. Among them, the ring gate structures of NMOS and PMOS both include Si channels surrounding NMOS and SiGe channels of PMOS respectively, and SiO2 layers, HfO2 layers, TiN layers, TiAl layers, TiN layers and W layers are sequentially arranged from the inside to the outside, wherein the TiN layers, TiAl layers and TiN layers form a work function layer 37, so that the work function layers of NMOS and PMOS are unified.

[0086] The gate stacking process of the NMOS and PMOS heterogeneous channel gate-all-around devices of the present invention comprises: By adopting the ALD process, SiO2 layer (<1nm), HfO2 layer (1~2nm), TiN layer (1~2nm), TiAl layer (3~4nm) and TiN (1~2nm) are deposited on the side of the Si channel of NMOS and the side of the SiGe channel of PMOS in sequence. The thickness of the first work function layer 141 of NMOS and the second work function layer 172 of PMOS are the same, which is about 8~11nm. Therefore, compared with the above-mentioned existing gate stacking process, the present invention greatly simplifies the process.

[0087] In summary, the present invention uses an integration technology that uses different channel materials for NMOS devices and PMOS devices (for example, the first channel 13 material of the NMOS device uses Si, and the second channel 18 material of the PMOS device uses SiGe) to enable NMOS and PMOS to have heterogeneous channels, which is beneficial to improving the carrier mobility of PMOS, thereby increasing the on-state current of the device, and is beneficial to using the same set of work function gate materials for NMOS and PMOS through the combination of heterogeneous channels, thereby simplifying the gate stacking process of the ring-gate device.

[0088] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A heterogeneous channel gate-all-around device, characterized in that: include: An NMOS device and a PMOS device are arranged adjacent to each other, wherein the NMOS device and the PMOS device are respectively provided with a gate structure enclosed on the side of their respective channels, the channel material of the NMOS device is different from the channel material of the PMOS device, and the work function layer composition and material in the gate structure of the NMOS device are the same as the work function layer composition and material in the gate structure of the PMOS device.

2. The heterogeneous channel gate-all-around device according to claim 1, characterized in that: The NMOS device and the PMOS device are adjacently arranged on one side of a substrate, the NMOS device is provided with a first channel and a first gate structure enclosed on a side of the first channel, the first gate structure is provided with a first work function layer, the first work function layer includes a plurality of first sub-work function layers, the PMOS device is provided with a second channel and a second gate structure enclosed on a side of the second channel, the second gate structure is provided with a second work function layer, the second work function layer includes a plurality of second sub-work function layers, the material of the first channel is a first semiconductor, the material of the second channel is a second semiconductor different from the first semiconductor, each of the first sub-work function layers is arranged correspondingly to each of the second sub-work function layers, and the material of each of the first sub-work function layers is the same as the material of a corresponding second sub-work function layer.

3. The heterogeneous channel gate-all-around device according to claim 2, characterized in that: The first gate structure is also provided with a first gate metal layer enclosed outside the first work function layer, and the second gate structure is also provided with a second gate metal layer enclosed outside the second work function layer, and the first gate metal layer and the second gate metal layer are connected between the NMOS device and the PMOS device.

4. The heterogeneous channel gate-all-around device according to claim 3, characterized in that: The NMOS device includes a plurality of first channels arranged in parallel in a direction away from the substrate, and the first work function layer and the first gate metal layer are sequentially enclosed on the side of each first channel. The PMOS device includes a plurality of second channels arranged in parallel in a direction away from the substrate, and the second work function layer and the second gate metal layer are sequentially enclosed on the side of each second channel. The first gate metal layer is also filled between any two adjacent first channels, the second gate metal layer is also filled between any two adjacent second channels, and the first gate metal layer and the second gate metal layer are also filled between the first channel and the second channel to be closely connected.

5. The heterogeneous channel gate-all-around device according to claim 4, characterized in that: The material of the first gate metal layer is the same as that of the second gate metal layer, forming a gate metal layer shared by the first gate structure and the second gate structure.

6. The heterogeneous channel gate-all-around device according to claim 4, characterized in that: The cross-sectional dimensions of the first channel are the same as the cross-sectional dimensions of the second channel, the thickness of the first work function layer is the same as the thickness of the second work function layer, or the thickness of each of the first sub-work function layers is the same as the thickness of a corresponding second sub-work function layer; and / or the first channel and the second channel are staggered in a direction away from the substrate.

7. The heterogeneous channel gate-all-around device according to claim 2, characterized in that: The first semiconductor includes Si, and the second semiconductor includes SiGe; and / or, the number of the first sub-work function layer and the second sub-work function layer is three, which include a TiN layer, a TiAl layer and a TiN layer from the inside to the outside; and / or, a SiO2 layer and a HfO2 layer are provided in sequence from the inside to the outside between the first channel and the first work function layer, and between the second channel and the second work function layer.

8. The heterogeneous channel gate-all-around device according to claim 7, characterized in that: The thickness of the TiN layer is 1~2nm, the thickness of the TiAl layer is 3~4nm, or the thickness of the first work function layer and the second work function layer is 8~11nm; the thickness of the SiO2 layer is less than 1nm, and the thickness of the HfO2 layer is 1~2nm.

9. The heterogeneous channel gate-all-around device according to claim 1, characterized in that: The heterogeneous channel gate-all-around device includes an inverter.

10. A method for preparing a heterogeneous channel gate-all-around device, characterized in that: include: Adjacently arranged NMOS devices and PMOS devices are formed, so that the NMOS device and the PMOS device are respectively formed with gate structures enclosed on the sides of their respective channels, the channel material of the NMOS device is different from the channel material of the PMOS device, and the work function layer composition and material in the gate structure of the NMOS device are the same as the work function layer composition and material in the gate structure of the PMOS device.

11. The method for preparing a heterogeneous channel gate-all-around device according to claim 10, characterized in that: The method for forming the NMOS device and the PMOS device specifically includes: providing a substrate; A first channel of the NMOS device and a second channel of the PMOS device are formed on one side of the substrate; the material of the first channel is a first semiconductor, and the material of the second channel is a second semiconductor different from the first semiconductor; A first gate structure enclosed on the side of the first channel and a second gate structure enclosed on the side of the second channel are formed; the first gate structure includes a first work function layer, the first work function layer includes a plurality of first sub-work function layers, the second gate structure is provided with a second work function layer, the second work function layer includes a plurality of second sub-work function layers, each of the first sub-work function layers is arranged corresponding to each of the second sub-work function layers, and the material of each of the first sub-work function layers is the same as the material of a corresponding second sub-work function layer.

12. The method for preparing a heterogeneous channel gate-all-around device according to claim 11, characterized in that: The method for forming the first channel and the second channel specifically includes: Alternatingly forming a plurality of second semiconductor layers and a plurality of first semiconductor layers on the surface of the substrate whose material is the first semiconductor; Patterning the second semiconductor layer and the first semiconductor layer to form a plurality of fins on the surface of the substrate, including adjacent first fins and second fins, and forming isolation trenches downward on the surface of the substrate at both sides of the fins; forming a first dielectric layer on the surface of the substrate to fill the isolation trench; forming a dummy gate across the first fin and the second fin, and an outer wall layer covering the dummy gate, the first fin and the second fin, and then removing the first fin and the second fin exposed outside the two sides of the dummy gate; At least partially remove the second semiconductor layer material exposed on both ends of the first fin and the first semiconductor layer material exposed on both ends of the second fin to form a recess, and then form an inner sidewall in the recess; forming a first source and a drain at two ends of the first semiconductor layer exposed by the first fin, and forming a second source and a drain at two ends of the second semiconductor layer exposed by the second fin; An opening is formed at the top of the outer wall layer to expose the top of the dummy gate below, and then the dummy gate is removed to form a cavity, and the remaining second semiconductor layer material on the first fin and the remaining first semiconductor layer material on the second fin are removed, thereby forming a plurality of first channels corresponding to the plurality of first semiconductor layers on the first fin, and forming a plurality of second channels corresponding to the plurality of second semiconductor layers on the second fin.

13. The method for preparing a heterogeneous channel gate-all-around device according to claim 12, characterized in that: The method for forming the first gate structure and the second gate structure specifically includes: forming a work function layer including a plurality of sub-work function layers on the sides of the first channel and the second channel in the cavity, wherein the sub-work function layer on the side of the first channel serves as the first sub-work function layer, and the sub-work function layer on the side of the second channel serves as the second sub-work function layer; and A gate metal layer is filled in the cavity.

14. The method for preparing a heterogeneous channel gate-all-around device according to claim 13, characterized in that: The first semiconductor includes Si, and the second semiconductor includes SiGe; and / or, the number of the sub-work function layers is three, which include a TiN layer, a TiAl layer and a TiN layer from the inside to the outside.

15. The method for preparing a heterogeneous channel gate-all-around device according to claim 13, characterized in that: Before forming the work function layer, the method further includes: firstly forming a SiO2 layer and a HfO2 layer in sequence on the side surfaces of the first channel and the second channel in the cavity, and then forming the work function layer on the HfO2 layer.

16. The method for preparing a heterogeneous channel gate-all-around device according to claim 13, characterized in that: After forming the gate metal layer, the method further includes: forming a cap layer on the opening to seal the gate metal layer.

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