Device testing tool and testing method

Abstract

According to the device testing tool and the testing method, the tested device is pressed downwards through the pressing plate on the testing clamp, so that the pins of the tested device are inserted into the socket, and the tested device is pressed downwards through the pressing plate, so that the pressure of the pins of the tested device can be ensured to be consistent; normal insertion of the pins of the tested device can be guaranteed, and the situation that the tested device is damaged due to pin bending caused by uneven stress when the tested device is inserted is avoided. After being inserted into the socket, a tested device is connected with the test circuit in the test mounting seat, the test equipment is connected with the tested device through the test circuit and the socket, the test equipment can send a control signal to the test circuit, on-off of the tested device is controlled through the test circuit, and a signal of the tested device can be fed back to the test equipment. Therefore, the testing process is more convenient, the working efficiency is improved, the testing tool is low in cost, manpower is saved, and a more accurate testing result can be obtained.

Description

Technical Field

[0001] The present application relates to the technical field of electronic device testing, and in particular to a device testing tool and a testing method. Background Art

[0002] As one of the core devices in the field of power electronics, insulated bipolar transistors (IGBTs) are widely used in new energy vehicles and rail transit, and play an important role. In order to ensure the performance and reliability of IGBTs, a series of performance tests need to be performed on them before the products are put into use. For the testing of multi-channel IGBT power modules, there is no dedicated test fixture. However, for the commonly used IGBT testing, the test clip is usually used to clamp the device pins and perform single-channel testing. When the traditional test method is tested, because the test clip is usually tight, it will cause irreversible damage to the device pins. At the same time, when the test clip is used for testing, the contact area between the clip and the device pin is small, and the test results are not ideal. Secondly, the traditional test method consumes a lot of manpower costs and has low work efficiency. The traditional test method not only increases the test cost, but also makes the test process complicated and inefficient. Summary of the invention

[0003] In view of this, the purpose of the present application is to propose a device testing tool and a testing method to solve the problems in the prior art of inaccurate testing of multi-channel IGBT device testing methods, and the waste of manpower and cost.

[0004] Based on the above objectives, the first aspect of the present application provides a device testing tool, including:

[0005] A test fixture, comprising a bracket and a pressing plate arranged on the bracket;

[0006] A test mounting seat, arranged on the bracket and located in the downward pressing direction of the pressing plate, the test mounting seat comprises a test board, a test circuit arranged on the test board and a socket, and the socket is connected to the test circuit;

[0007] A device under test, wherein the pins of the device under test are plugged into the socket;

[0008] The test device is connected to the socket of the test mount via a connecting line so that the test device is connected to the device under test, sends a control signal to the device under test, and obtains a feedback signal.

[0009] Optionally, the test circuit includes a first test unit, a second test unit, a third test unit, a fourth test unit, a fifth test unit, a sixth test unit, a seventh test unit and an eighth test unit;

[0010] The device under test includes a rectifier upper half, a rectifier lower half, an inverter upper half bridge, an inverter lower half bridge, a chopper and a chopper diode, the rectifier upper half and the inverter upper half bridge are both connected to the first test unit, the third test unit and the fifth test unit, the rectifier lower half and the inverter lower half bridge are both connected to the second test unit, the fourth test unit and the sixth test unit, the chopper is connected to the seventh test unit, and the chopper diode is connected to the eighth test unit;

[0011] The first test unit, the second test unit, the third test unit, the fourth test unit, the fifth test unit, the sixth test unit, the seventh test unit and the eighth test unit each include multiple groups of relays, and each group of relays is used to control the on and off states of the rectifier, inverter, chopper and chopper diode.

[0012] Optionally, the first test unit includes a first rectifier test unit, the third test unit includes a second rectifier test unit, the fifth test unit includes a third rectifier test unit, the upper half of the rectifier includes a first diode, a second diode and a third diode connected to each other, the first diode is connected to the first rectifier test unit, the second diode is connected to the second rectifier test unit, and the third diode is connected to the third rectifier test unit.

[0013] Optionally, the second test unit includes a fourth rectifier test unit, the fourth test unit includes a fifth rectifier test unit, the sixth test unit includes a sixth rectifier test unit, the lower half of the rectifier includes a fourth diode, a fifth diode and a sixth diode connected to each other, the fourth diode is connected to the fourth rectifier test unit, the fifth diode is connected to the fifth rectifier test unit, and the sixth diode is connected to the sixth rectifier test unit.

[0014] Optionally, the first test unit also includes a first inverter test unit connected to the first rectifier test unit, the third test unit also includes a second inverter test unit connected to the second rectifier test unit, the fifth test unit also includes a third inverter test unit connected to the third rectifier test unit, the inverter upper half-bridge includes a first upper half-bridge inverter, a second upper half-bridge inverter and a third upper half-bridge inverter connected to each other, the first upper half-bridge inverter is connected to the first inverter test unit, the second upper half-bridge inverter is connected to the second inverter test unit, and the third upper half-bridge inverter is connected to the third inverter test unit.

[0015] Optionally, the second test unit also includes a fourth inverter test unit connected to the fourth rectifier test unit, the fourth test unit also includes a fifth inverter test unit connected to the fifth rectifier test unit, the sixth test unit also includes a sixth inverter test unit connected to the sixth rectifier test unit, the inverter lower half-bridge includes a first lower half-bridge inverter, a second lower half-bridge inverter and a third lower half-bridge inverter connected to each other, the first lower half-bridge inverter is connected to the fourth inverter test unit, the second lower half-bridge inverter is connected to the fifth inverter test unit, and the third lower half-bridge inverter is connected to the sixth inverter test unit.

[0016] Optionally, the seventh test unit includes a chopper test unit, and the chopper is connected to the chopper test unit.

[0017] Optionally, the eighth test unit comprises a chopper diode test unit, and the chopper diode is connected to the chopper diode test unit.

[0018] Optionally, the bracket includes a bottom plate and a side frame, the side frame is arranged near the edge of the bottom plate, a pressing assembly is arranged near the top of the side frame, the pressing assembly includes a mounting frame, a pressure rod handle and a pressure rod column, the mounting frame is fixed to the side frame, the pressure rod handle is rotatably arranged on the mounting frame, one end of the pressure rod column passes through the mounting frame and is hinged to the pressure rod handle, and the pressure plate is arranged at one end of the pressure rod column away from the pressure rod handle;

[0019] The side frame is also provided with a guide block, the pressure plate is fixed with a guide rod, and the guide rod passes through the guide block.

[0020] Based on the same inventive concept, the present application also provides a device testing method, applicable to any of the device testing tools described above, comprising:

[0021] Placing the device under test on a test mount, and pressing the device under test down using a test fixture, so that the device under test is connected to a test circuit in the test mount;

[0022] The testing device sends a control signal to the testing circuit and receives a feedback signal from the device under test.

[0023] As can be seen from the above, the device testing tool and testing method provided by the present application include: a test fixture, including a bracket and a pressure plate arranged on the bracket; a test mounting seat, arranged on the bracket and located in the downward pressing direction of the pressure plate, the test mounting seat includes a test board, a test circuit and a socket arranged on the test board, and the socket is connected to the test circuit; a device under test, the pins of the device under test are plugged into the socket; a test device is connected to the socket of the test mounting seat through a connecting line so that the test device is connected to the device under test, sends a control signal to the device under test and obtains a feedback signal. The test fixture is used to clamp and plug the device under test plugged into the test mounting seat. The device under test is pressed down by the pressure plate on the test fixture, so that the pins of the device under test are plugged into the socket. The device under test is pressed down by the pressure plate, which can ensure that the pressure of each pin of the device under test is consistent, and can ensure the normal insertion of the pins of the device under test, avoiding uneven force when the device under test is inserted, resulting in bending of the pins, and causing damage to the device under test. After the device under test is inserted into the socket, it is connected to the test circuit in the test mounting seat. The test equipment is connected to the device under test through the test circuit and the socket. The test equipment can send a control signal to the test circuit to control the on and off of the device under test through the test circuit, and can feed back the signal of the device under test to the test equipment, making the test process more convenient and improving work efficiency. The test tooling in this application has a low cost, saves manpower, and can obtain more accurate test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 A schematic diagram of a device testing tool framework according to an embodiment of the present application;

[0026] Figure 2 This is a schematic diagram of the test fixture structure of an embodiment of the present application;

[0027] Figure 3 This is a schematic diagram of the circuit structure of a multi-channel IGBT power module according to an embodiment of the present application;

[0028] Figure 4 A schematic diagram of a rectifier test circuit according to an embodiment of the present application;

[0029] Figure 5 A schematic diagram of a part of an inverter test circuit of an embodiment of the present application;

[0030] Figure 6 A schematic diagram of another part of an inverter test circuit according to an embodiment of the present application;

[0031] Figure 7 A schematic diagram of a device testing method flow chart of an embodiment of the present application;

[0032] Figure 8 A schematic diagram of the hardware structure of an electronic device according to an embodiment of the present application.

[0033] Reference numerals:

[0034] 1. Bracket; 2. Pressing assembly; 3. Pressing plate; 4. Test mounting seat; 5. Guide assembly; 11. Bottom plate; 12. Side frame; 21. Mounting frame; 22. Pressing rod handle; 23. Pressing rod column; 51. Guide block; 52. Guide rod; Z, rectifier; Z1, upper half of rectifier; Z2, lower half of rectifier; N1, upper half bridge of inverter; N2, lower half bridge of inverter; D11, first diode; D12, second diode; D13, third diode; D21, fourth diode; D22, fifth diode; D23, sixth diode; T1, chopper; D3, chopper diode; U11, first upper half bridge inverter; U21, first lower half bridge inverter; V11, second upper half bridge Inverter; V21, second lower half-bridge inverter; W11, third upper half-bridge inverter; W21, third lower half-bridge inverter; K12, first inverter test unit; K22, fourth inverter test unit; K32, second inverter test unit; K42, fifth inverter test unit; K52, third inverter test unit; K62, sixth inverter test unit; K71, chopper test unit; K81, chopper diode test unit; K11, first rectifier test unit; K31, second rectifier test unit; K51, third rectifier test unit; K21, fourth rectifier test unit; K41, fifth rectifier test unit; K61, sixth rectifier test unit. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0036] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0037] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0038] Reference Figure 1 and Figure 2 , the present application provides a device testing tool, comprising:

[0039] A test fixture, comprising a bracket 1 and a pressing plate 3 arranged on the bracket 1;

[0040] A test mounting seat 4 is arranged on the bracket 1 and is located in the downward pressing direction of the pressing plate 3. The test mounting seat 4 includes a test board, a test circuit and a socket arranged on the test board, and the socket is connected to the test circuit;

[0041] A device under test, wherein the pins of the device under test are plugged into the socket;

[0042] The test equipment is connected to the socket of the test mounting seat 4 via a connecting line so that the test equipment is connected to the device under test, sends a control signal to the device under test, and obtains a feedback signal.

[0043] Specifically, in the present application, the device under test can be a multi-channel IGBT power module. The test fixture is used to clamp and plug the device under test plugged into the test mounting seat 4. The device under test is pressed down by the pressure plate 3 on the test fixture, so that the pins of the device under test are plugged into the socket. The device under test is pressed down by the pressure plate 3, which can ensure that the pressure of each pin of the device under test is consistent, and can ensure the normal insertion of the pins of the device under test, so as to avoid uneven force when the device under test is inserted, resulting in bending of the pins, causing damage to the device under test. After the device under test is inserted into the socket, it is connected to the test circuit in the test mounting seat 4, and the test equipment is connected to the device under test through the test circuit and the socket. The test equipment can send a control signal to the test circuit, control the on and off of the device under test through the test circuit, and can feed back the signal of the device under test to the test equipment, so that the test process is more convenient, and the work efficiency is improved. The test tooling cost in the present application is low, manpower is saved, and more accurate test results can be obtained.

[0044] Among them, the test mount 4 is connected to the test equipment through two lines, one line is used to send signals, and the other line is used to receive feedback signals. An adapter is connected to the line for sending signals, so that the test equipment can send suitable signals for different models of devices under test. To improve the accuracy of the test. Both lines can use flat wires, and the specific plugs can be configured according to actual conditions, which will not be specifically introduced in this application.

[0045] In some embodiments, Figure 3 As shown, the device under test includes a rectifier upper half Z1, a rectifier lower half Z2, an inverter upper half bridge N1, an inverter lower half bridge N2, a chopper T1 and a chopper diode D3.

[0046] In this embodiment, the multi-way IGBT power module includes multiple inverters, multiple rectifiers Z, a chopper T1 and a chopper diode D3. In the present application, the multiple rectifiers Z include the upper half Z1 of the rectifier and the lower half Z2 of the rectifier. The upper half Z1 of the rectifier includes a first diode D11, a second diode D12 and a third diode D13, and the lower half Z2 of the rectifier includes a fourth diode D21, a fifth diode D22 and a sixth diode D23. The multiple inverters include an upper half bridge N1 of the inverter and a lower half bridge N2 of the inverter. The upper half bridge N1 of the inverter includes a first upper half bridge inverter U11, a second upper half bridge inverter V11 and a third upper half bridge inverter W11 connected to each other; the lower half bridge N2 of the inverter includes a first lower half bridge inverter U21, a second lower half bridge inverter V21 and a third lower half bridge inverter W21 connected to each other. Each inverter includes a transistor and a diode, and the diode is connected in parallel with the collector and emitter of the transistor. Figure 3 Specific structure.

[0047] In this embodiment, if Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, the test circuit includes a first test unit, a second test unit, a third test unit, a fourth test unit, a fifth test unit, a sixth test unit, a seventh test unit and an eighth test unit;

[0048] The rectifier upper half Z1 and the inverter upper half bridge N1 are both connected to the first test unit, the third test unit, and the fifth test unit, the rectifier lower half Z2 and the inverter lower half bridge N2 are both connected to the second test unit, the fourth test unit, and the sixth test unit, the chopper T1 is connected to the seventh test unit, and the chopper diode D3 is connected to the eighth test unit.

[0049] Furthermore, if Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, the first test unit includes a first rectifier test unit K11, the third test unit includes a second rectifier test unit K31, the fifth test unit includes a third rectifier test unit K51, the rectifier upper half Z1 includes a first diode D11, a second diode D12 and a third diode D13 connected to each other, the first diode D11 is connected to the first rectifier test unit K11, the second diode D12 is connected to the second rectifier test unit K31, and the third diode D13 is connected to the third rectifier test unit K51;

[0050] The second test unit includes a fourth rectifier test unit K21, the fourth test unit includes a fifth rectifier test unit K41, the sixth test unit includes a sixth rectifier test unit K61, the rectifier lower half Z2 includes a fourth diode D21, a fifth diode D22 and a sixth diode D23 connected to each other, the fourth diode D21 is connected to the fourth rectifier test unit K21, the fifth diode D22 is connected to the fifth rectifier test unit K41, and the sixth diode D23 is connected to the sixth rectifier test unit K61;

[0051] The first test unit also includes a first inverter test unit K12 connected to the first rectifier test unit K11, the third test unit also includes a second inverter test unit K32 connected to the second rectifier test unit K31, the fifth test unit also includes a third inverter test unit K52 connected to the third rectifier test unit K51, the inverter upper half-bridge N1 includes a first upper half-bridge inverter U11, a second upper half-bridge inverter V11 and a third upper half-bridge inverter W11 connected to each other, the first upper half-bridge inverter U11 is connected to the first inverter test unit K12, the second upper half-bridge inverter V11 is connected to the second inverter test unit, and the third upper half-bridge inverter W11 is connected to the third inverter test unit K52.

[0052] The second test unit also includes a fourth inverter test unit K22 connected to the fourth rectifier test unit K21, the fourth test unit also includes a fifth inverter test unit K42 connected to the fifth rectifier test unit K41, the sixth test unit also includes a sixth inverter test unit K62 connected to the sixth rectifier test unit K61, the inverter lower half bridge N2 includes a first lower half bridge inverter U21, a second lower half bridge inverter V21 and a third lower half bridge inverter W21 connected to each other, the first lower half bridge inverter U21 is connected to the fourth inverter test unit K22, the second lower half bridge inverter V21 is connected to the fifth inverter test unit, and the third lower half bridge inverter W21 is connected to the sixth inverter test unit K62.

[0053] Specifically, in the present application, multiple test units are used to perform group tests on the components in the above-mentioned multi-channel IGBT power module, and different components use different test units. In this way, the test results of the multi-channel IGBT power module are more accurate and the test efficiency is improved. Exemplarily, the first test unit includes a first inverter test unit K12 and a first rectifier test unit K11 for testing the first diode D11 and the first upper half-bridge inverter U11 in the device under test; the third test unit includes a second inverter test unit K32 and a second rectifier test unit K31 for testing the second diode D12 and the second upper half-bridge inverter V11 in the device under test; the fifth test unit includes a third inverter test unit K52 and a third rectifier test unit K51 for testing the third diode D13 and the third upper half-bridge inverter W11 in the device under test. Test; the second test unit includes the fourth inverter test unit K22 and the fourth rectifier test unit K21 for testing the fourth diode D21 and the first lower half-bridge inverter U21 in the device under test; the fourth test unit includes the fifth inverter test unit K42 and the fifth rectifier test unit K41 for testing the fifth diode D22 and the second lower half-bridge inverter V21 in the device under test; the sixth test unit includes the sixth inverter test unit K62 and the sixth rectifier test unit K61 for testing the sixth diode D23 and the third lower half-bridge inverter W21 in the device under test. In this way, grouping all devices in the IGBT power module can make the test results of the IGBT power module more accurate and improve work efficiency.

[0054] Furthermore, if Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, the first test unit, the second test unit, the third test unit, the fourth test unit, the fifth test unit, the sixth test unit, the seventh test unit and the eighth test unit each include a plurality of groups of relays, and each group of the relays is used to control the on and off states of the rectifier, the inverter, the chopper T1 and the chopper diode D3.

[0055] Specifically, the structures of the first test unit, the second test unit, the third test unit, the fourth test unit, the fifth test unit and the sixth test unit are consistent. The first test unit includes a first inverter test unit K12 and a first rectifier test unit K11, the first rectifier test unit K11 includes two relays connected in parallel, the two relays include KDU11 and KDU12, one end of the first diode D11 of the upper half Z1 of the rectifier (exemplarily can be Figure 3 1 pin in the figure) are connected to the output EF and ES terminals of relays KDU11 and KDU12 at the same time (for example, Figure 4 The other end of the first diode D11 (exemplarily, it can be ES, EF ends of the right half of the relay KDU11, KDU12) is connected to the test equipment. Figure 3 20 pins in the rectifier) ​​are connected to the test equipment. Exemplarily, the first diode D11 and the relay connection end are used to input the control signal, and the first diode D11 and the test equipment connection end are used to output the feedback signal. The second diode D12 and the third diode D13 of the upper half Z1 of the rectifier are connected to the corresponding relays of the second rectifier test unit K31 and the third rectifier test unit K51, and the connection method is consistent with the connection method of the first diode D11 and each relay. The specific pins are different.

[0056] The first inverter test unit K12 includes relays KIC11, KIC12, KIB1, KIE11 and KIE12, wherein the relays KIC11 and KIC12 are connected in parallel and connected to the collector (C pole, exemplarily as Figure 3 18 interface in the circuit) is connected to control the on / off of the collector of the first upper half-bridge inverter U11; KIB1 is connected to the gate (B pole, exemplarily as Figure 3 4 interfaces) are connected to control the on / off of the gate of the first upper half-bridge inverter U11; relays KIE11 and KIE12 are connected in parallel and connected to the emitter (B pole, exemplarily as Figure 3 5 interfaces in the first upper half-bridge inverter U11) are connected to control the on / off of the emitter of the first upper half-bridge inverter U11. Specifically, the specific connection mode of the first upper half-bridge inverter U11 and the first inverter test unit K12 is as follows: the 18 interfaces of the first upper half-bridge inverter U11 are all connected to the CF and CS ports of the output ends of the relays KIC11 and KIC12 (the output ends of the relays KIC11 and KIC12 are also the CF and CS on the left), wherein the input ends CF and CS ports of the relays KIC11 and KIC12 (the output ends of the relays KIC11 and KIC12 are also the CF and CS on the right) are connected to the test equipment; the 4 interfaces of the first upper half-bridge inverter U11 are all the BS and EF ends of the output ends of the relay KIB1, and the 5 interfaces of the first upper half-bridge inverter U11 are all the ES and EF ends of the output ends of the relays KIE11 and KIE12.

[0057] The second test unit includes a second inverter test unit K32 and a second rectifier test unit K31. The second rectifier test unit K31 includes two relays connected in parallel. The two relays include KDV11 and KDV12. One end of the second diode D12 of the upper half Z1 of the rectifier (exemplarily, Figure 3 2 pins) are connected to the output EF and ES terminals of relays KDV11 and KDV12 at the same time (for example, Figure 4 The other end of the second diode D12 (exemplarily, it can be ES, EF ends of the right half of the relay KDV11, KDV12) is connected to the test equipment. Figure 3 20 pins in the PCB) to connect to the test equipment.

[0058] The second inverter test unit K32 includes relays KIC31, KIC32, KIB3, KIE31 and KIE32, wherein the relays KIC31 and KIC32 are connected in parallel and connected to the collector (C pole, exemplarily as Figure 3 18 interface in the middle) is connected to control the on / off of the collector of the second upper half-bridge inverter V11; KIB3 is connected to the gate (B pole, exemplarily as Figure 3 6 interface) is connected to control the on / off of the gate of the second upper half-bridge inverter V11; relays KIE31 and KIE32 are connected in parallel and connected to the emitter (B pole, exemplarily as Figure 3 The 7 interfaces in the second upper half-bridge inverter V11 are connected to control the on and off of the emitter of the second upper half-bridge inverter V11. The specific connection mode of the second upper half-bridge inverter V11 and the second inverter test unit K32 is as follows: the 18 interfaces of the second upper half-bridge inverter V11 are all connected to the CF and CS ports of the output ends of the relays KIC31 and KIC32 (the output ends of the relays KIC31 and KIC32 are also the CF and CS on the left), wherein the input ends CF and CS ports of the relays KIC31 and KIC32 (the output ends of the relays KIC31 and KIC32 are also the CF and CS on the right) are connected to the test equipment. The 6 interfaces of the second upper half-bridge inverter V11 are all the BS and EF ends of the output ends of the relay KIB3, and the 7 interfaces of the second upper half-bridge inverter V11 are all the ES and EF ends of the output ends of the relays KIE31 and KIE32.

[0059] The third test unit includes a third inverter test unit K52 and a third rectifier test unit K51. The third rectifier test unit K51 includes two relays connected in parallel. The two relays include KDW11 and KDW12. One end of the third diode D13 (exemplarily, Figure 3 The 3 pins in the figure are connected to the output EF and ES terminals of relays KDW11 and KDW12 at the same time (for example, Figure 4 The other end of the third diode D13 (exemplarily, it can be Figure 3 20 pins in the PCB) to connect to the test equipment.

[0060] The third inverter test unit K52 includes relays KIC51, KIC52, KIB5, KIE51 and KIE52, wherein the relays KIC51 and KIC52 are connected in parallel and connected to the collector (C pole, exemplarily as Figure 3 18 interface in the middle) is connected to control the on / off of the collector of the third upper half-bridge inverter W11; KIB5 is connected to the gate (B pole, exemplarily as Figure 3 8 interface) is connected to control the on / off of the gate of the third upper half-bridge inverter W11; relays KIE51 and KIE52 are connected in parallel and connected to the emitter (B pole, exemplarily as Figure 3 The 9 interfaces in the third upper half-bridge inverter W11 are connected to control the on and off of the emitter of the third upper half-bridge inverter W11. The specific connection mode of the third upper half-bridge inverter W11 and the third inverter test unit K52 is as follows: the 18 interfaces of the third upper half-bridge inverter W11 are all connected to the CF and CS ports of the output ends of the relays KIC51 and KIC52 (the output ends of the relays KIC51 and KIC52 are also the CF and CS on the left), wherein the input ends CF and CS ports of the relays KIC51 and KIC52 (the output ends of the relays KIC51 and KIC52 are also the CF and CS on the right) are connected to the test equipment. The 8 interfaces of the third upper half-bridge inverter W11 are all the BS and EF ends of the output ends of the relays KIB5, and the 9 interfaces of the third upper half-bridge inverter W11 are all the ES and EF ends of the output ends of the relays KIE51 and KIE52.

[0061] The fourth test unit includes a fourth inverter test unit K22 and a fourth rectifier test unit K21. The fourth rectifier test unit K21 includes two relays connected in parallel. The two relays include KDU21 and KDU22. One end of the fourth diode D21 of the lower half Z2 of the rectifier (exemplarily, it can be Figure 3 1 pin in the figure) are connected to the output CF and CS terminals of relays KDU21 and KDU22 at the same time (for example, Figure 4 The other end of the fourth diode D21 (exemplarily, the CS and CF ends of the right half of the relay KDU21 and KDU22) is connected to the test equipment. Figure 3 21 pins in the PCB) to connect to the test equipment.

[0062] The fourth inverter test unit K22 includes relays KIC21, KIC22, KIB2, KIE21 and KIE22, wherein the relays KIC21 and KIC22 are connected in parallel and connected to the collector (C pole, exemplarily as Figure 3 5 interface) is connected to control the on / off of the collector of the first lower half-bridge inverter U21; KIB2 is connected to the gate (B pole, exemplarily as Figure 3 15 interface) is connected to control the on / off of the gate of the first lower half-bridge inverter U21; relays KIE21 and KIE22 are connected in parallel and connected to the emitter (B pole, exemplarily as Figure 3 The 17 interface in the first lower half-bridge inverter U21 is connected to control the on-off of the emitter of the first lower half-bridge inverter U21. The specific connection mode of the first lower half-bridge inverter U21 and the fourth inverter test unit K22 is as follows: the 5 interfaces of the first lower half-bridge inverter U21 are all connected to the CF and CS ports of the output ends of the relays KIC21 and KIC22 (the output ends of the relays KIC21 and KIC22 are also the CF and CS on the left), wherein the input ends CF and CS ports of the relays KIC21 and KIC22 (the output ends of the relays KIC21 and KIC22 are also the CF and CS on the right) are connected to the test equipment. The 15 interfaces of the first lower half-bridge inverter U21 are all the BS and EF ends of the output ends of the relay KIB2, and the 17 interfaces of the first lower half-bridge inverter U21 are all the ES and EF ends of the output ends of the relays KIE21 and KIE22.

[0063] The fifth test unit includes a fifth inverter test unit K42 and a fifth rectifier test unit K41. The fifth rectifier test unit K41 includes two relays connected in parallel. The two relays include KDV21 and KDV22. One end of the fifth diode D22 of the lower half Z2 of the rectifier (exemplarily, it can be Figure 3 2 pins) are connected to the output CF and CS terminals of relays KDV21 and KDV22 at the same time (for example, Figure 4 The CS and CF ends of the right half of the relays KDV21 and KDV22 are connected to the test equipment. The other end of the fifth diode D22 (exemplarily, it can be Figure 3 21 pins in the PCB) to connect to the test equipment.

[0064] The fifth inverter test unit K42 includes relays KIC41, KIC42, KIB4, KIE41 and KIE42, wherein the relays KIC41 and KIC42 are connected in parallel and connected to the collector (C pole, exemplarily as Figure 3 7 interface in the figure) is connected to control the on / off of the collector of the second lower half-bridge inverter V21; KIB4 is connected to the gate (B pole, exemplarily as Figure 3 13 interface) is connected to control the on / off of the gate of the second lower half-bridge inverter V21; relays KIE41 and KIE42 are connected in parallel and connected to the emitter (B pole, exemplarily as Figure 3 The 17 interfaces in the second lower half-bridge inverter V21 are connected to control the on-off of the emitter of the second lower half-bridge inverter V21. The specific connection mode of the second lower half-bridge inverter V21 and the fifth inverter test unit K42 is as follows: the 7 interfaces of the second lower half-bridge inverter V21 are all connected to the CF and CS ports of the output ends of the relays KIC41 and KIC42 (the output ends of the relays KIC41 and KIC42 are also the CF and CS on the left), wherein the input ends CF and CS ports of the relays KIC41 and KIC42 (the output ends of the relays KIC41 and KIC42 are also the CF and CS on the right) are connected to the test equipment. The 13 interfaces of the second lower half-bridge inverter V21 are all the BS and EF ends of the output ends of the relays KIB4, and the 17 interfaces of the second lower half-bridge inverter V21 are all the ES and EF ends of the output ends of the relays KIE41 and KIE42.

[0065] The sixth test unit includes a sixth inverter test unit K62 and a sixth rectifier test unit K61. The sixth rectifier test unit K61 includes two relays connected in parallel. The two relays include KDW21 and KDW22. One end of the sixth diode D23 of the lower half Z2 of the rectifier (exemplarily, it can be Figure 3 The 3 pins in the figure are connected to the output CF and CS terminals of relays KDW21 and KDW22 at the same time (for example, Figure 4 The other end of the sixth diode D23 (exemplarily, the CS and CF ends of the right half of the relays KDW21 and KDW22) is connected to the test equipment. Figure 3 21 pins in the PCB) to connect to the test equipment.

[0066] The sixth inverter test unit K62 includes relays KIC61, KIC62, KIB6, KIE61 and KIE62, wherein the relays KIC61 and KIC62 are connected in parallel and connected to the collector (C pole, exemplarily as Figure 3 9 interface) is connected to control the on / off of the collector of the third lower half-bridge inverter W21; KIB6 is connected to the gate (B pole, exemplarily as Figure 3 12 interface in the middle) is connected to control the on / off of the gate of the third lower half-bridge inverter W21; relays KIE61 and KIE62 are connected in parallel and connected to the emitter (B pole, exemplarily as Figure 3 The 17 interfaces in the third lower half-bridge inverter W21 are connected to control the on-off of the emitter of the third lower half-bridge inverter W21. The specific connection mode of the third lower half-bridge inverter W21 and the sixth inverter test unit K62 is as follows: the 9 interfaces of the third lower half-bridge inverter W21 are all connected to the CF and CS ports of the output ends of the relays KIC61 and KIC62 (the output ends of the relays KIC61 and KIC62 are also the CF and CS on the left), wherein the input ends CF and CS ports of the relays KIC61 and KIC62 (the output ends of the relays KIC61 and KIC62 are also the CF and CS on the right) are connected to the test equipment. The 12 interfaces of the third lower half-bridge inverter W21 are all the BS and EF ends of the output ends of the relays KIB6, and the 17 interfaces of the third lower half-bridge inverter W21 are all the ES and EF ends of the output ends of the relays KIE61 and KIE62.

[0067] In some embodiments, Figure 3 and Figure 6 As shown, the seventh test unit includes a chopper T1 test unit, and the chopper T1 is connected to the chopper T1 test unit.

[0068] Specifically, the chopper T1 includes a triode, and the triode includes a collector (19 interface), a gate (i.e., 16 interface) and an emitter (i.e., 17 interface). The chopper T1 test unit includes relays KIC71, KIC72, KIB7, KIE71 and KIE72, wherein the relays KIC71 and KIC72 are connected in parallel and connected to the collector (C pole, exemplarily as Figure 3 19 interface) is connected to control the on and off of the collector of the chopper T1; KIB7 is connected to the gate (B pole, exemplarily as Figure 3 16 interface in the middle) is connected to control the on and off of the gate of the chopper T1; relays KIE71 and KIE72 are connected in parallel and connected to the emitter (B pole, exemplarily as Figure 3 The 17 interface of the chopper T1 is connected to control the on and off of the emitter of the chopper T1. The specific connection mode of the chopper T1 and the chopper T1 test unit is as follows: the 19 interface of the chopper T1 is connected to the CF and CS ports of the output ends of the relays KIC71 and KIC72 (the output ends of the relays KIC71 and KIC72 are also the CF and CS on the left), wherein the input ends CF and CS ports of the relays KIC71 and KIC72 (the output ends of the relays KIC71 and KIC72 are also the CF and CS on the right) are connected to the test equipment. The 16 interfaces of the chopper T1 are the BS and EF ends of the output ends of the relays KIB7, and the 17 interfaces of the chopper T1 are the ES and EF ends of the output ends of the relays KIE71 and KIE72.

[0069] In some embodiments, Figure 3 and Figure 5 As shown, the eighth test unit includes a chopper diode test unit K81, and the chopper diode D3 is connected to the chopper diode test unit K81.

[0070] Specifically, the chopper diode test unit K81 includes relays KIC81, KIC82, KIB8, KIE81 and KIE82, wherein the relays KIC81 and KIC82 are connected in parallel and connected to the first pole (C pole, exemplarily as Figure 3 19 interface in the figure) is connected to control the on-off of the first pole of the chopper diode D3; the relay KIB8, the relay KIE81 and the relay KIE82 are all connected to the second pole (E pole, exemplarily as Figure 3The 18 interfaces of the chopper diode D3 are connected to control the on and off of the emitter of the chopper diode D3. Relays KIE81 and KIE82 are connected in parallel. The specific connection method of the chopper diode D3 and the chopper diode D3 diode test unit is as follows: the 19 interfaces of the chopper diode D3 are connected to the CF and CS ports of the output ends of the relays KIC81 and KIC82 (the output ends of the relays KIC81 and KIC82 are also the CF and CS on the left), wherein the input ends CF and CS ports of the relays KIC81 and KIC82 (the output ends of the relays KIC81 and KIC82 are also the CF and CS on the right) are connected to the test equipment. The 18 interfaces of the chopper diode D3 are the BS and EF ends of the output end of the relay KIB8, and the 18 interfaces of the chopper diode D3 are the ES and EF ends of the output ends of the relays KIE81 and KIE82.

[0071] In some embodiments, Figure 2 As shown, the bracket 1 includes a bottom plate 11 and a side frame 12, the side frame 12 is arranged near the edge of the bottom plate 11, and a pressing assembly 2 is arranged near the top of the side frame 12, and the pressing assembly 2 includes a mounting frame 21, a pressing rod handle 22 and a pressing rod column 23, the mounting frame 21 is fixed on the side frame 12, the pressing rod handle 22 is rotatably arranged on the mounting frame 21, one end of the pressing rod column 23 passes through the mounting frame 21 and is hinged to the pressing rod handle 22, and the pressing plate 3 is arranged on the end of the pressing rod column 23 away from the pressing rod handle 22;

[0072] The side frame 12 is further provided with a guide block 51 , and the pressure plate 3 is fixed with a guide rod 52 , which passes through the guide block 51 .

[0073] Specifically, the test fixture is used to press down the device under test inserted on the test mounting seat 4, so that the pins of the device under test are plugged into the socket. By pressing down the device under test through the pressure plate 3, the pressure of each pin of the device under test can be guaranteed to be consistent, and the normal insertion of the pins of the device under test can be guaranteed, so as to avoid uneven force when the device under test is inserted, resulting in bending of the pins and damage to the device under test. The bracket 1 is L-shaped, and the side frame 12 is arranged at the edge of the bottom plate 11, so that the installation position of the test base can be reserved, and then the mounting frame 21 of the pressing assembly 2 is vertically fixed on the mounting frame 21, so that the mounting frame 21 is parallel to the bottom plate 11, which is convenient for the operation of the pressure rod handle 22, and the pressure rod plate is rotatably arranged on the mounting frame 21, and is connected to the pressure rod column 23 through the junction, and the pressure rod passes through the cylindrical tube on the mounting frame 21, so that the pressure rod can be guided and the pressure plate 3 can be stably controlled to move up and down. A guide rod 52 is also provided on the pressure plate 3. The guide rod 52 cooperates with the guide block 51 on the side frame 12 to ensure that the pressure plate 3 moves up and down stably, so that the pressure of each pin of the device under test is consistent, and the pins of the device under test can be inserted normally, avoiding bending of the pins due to uneven force when the device under test is inserted, thereby causing damage to the device under test.

[0074] Based on the same inventive concept, corresponding to any of the above embodiments and methods, Figure 7 As shown, the present application also provides a device testing method, which is applicable to any of the device testing tools described above, and comprises the following steps:

[0075] Step 102, placing the device under test on a test mount, and pressing the device under test downward using a test fixture to connect the device under test to a test circuit in the test mount;

[0076] Step 104: The test device sends a control signal to the test circuit and receives a feedback signal from the device under test.

[0077] Specifically, the test fixture is used to press down the device under test inserted on the test mount so that the pins of the device under test are plugged into the socket. By pressing down the device under test through the pressure plate, the pressure of each pin of the device under test can be guaranteed to be consistent, and the normal insertion of the pins of the device under test can be guaranteed, so as to avoid uneven force when the device under test is inserted, resulting in bending of the pins and damage to the device under test. In the present application, the components in the above-mentioned multi-channel IGBT power module are grouped and tested by multiple test units, and different components use different test units. In this way, the test results of the multi-channel IGBT power module are more accurate and the test efficiency is improved. Exemplarily, the first test unit includes a first inverter test unit and a first rectifier test unit for testing the first diode and the first upper half-bridge inverter in the device under test; the third test unit includes a second inverter test unit and a second rectifier test unit for testing the second diode and the second upper half-bridge inverter in the device under test; the fifth test unit includes a third inverter test unit and a third rectifier test unit for testing the third diode and the third upper half-bridge inverter in the device under test; the second test unit includes a fourth inverter test unit and a fourth rectifier test unit for testing the fourth diode and the first lower half-bridge inverter in the device under test; the fourth test unit includes a fifth inverter test unit and a fifth rectifier test unit for testing the fifth diode and the second lower half-bridge inverter in the device under test; the sixth test unit includes a sixth inverter test unit and a sixth rectifier test unit for testing the sixth diode and the third lower half-bridge inverter in the device under test. In this way, grouping and testing all devices in the IGBT power module can make the test result of the IGBT power module more accurate and improve work efficiency.

[0078] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0079] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0080] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a device failure testing method described in any of the above embodiments is implemented.

[0081] Figure 8 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.

[0082] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0083] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.

[0084] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0085] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).

[0086] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040).

[0087] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0088] The electronic device of the above embodiment is used to implement a corresponding device failure test method in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0089] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute a device failure testing method as described in any of the above embodiments.

[0090] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0091] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute a device failure testing method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0092] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0093] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0094] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0095] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A device testing tool, characterized in that: include: A test fixture (01) comprises a support (1) and a pressing plate (3) arranged on the support (1); A test mounting seat (4) is arranged on the bracket (1) and is located in the downward pressing direction of the pressing plate (3); the test mounting seat (4) comprises a test board (41), a test circuit arranged on the test board (41), and a socket, wherein the socket is connected to the test circuit; A device under test (6), wherein the pins of the device under test (6) are plugged into the socket; The test device (7) is connected to the socket of the test mount (4) via a connecting line, so that the test device (7) is connected to the device under test (6), sends a control signal to the device under test (6), and obtains a feedback signal.

2. A device testing tool according to claim 1, characterized in that: The test circuit includes a first test unit, a second test unit, a third test unit, a fourth test unit, a fifth test unit, a sixth test unit, a seventh test unit and an eighth test unit; The device under test comprises a rectifier upper half (Z1), a rectifier lower half (Z2), an inverter upper half bridge (N1), an inverter lower half bridge (N2), a chopper (T1) and a chopper diode (D3); the rectifier upper half (Z1) and the inverter upper half bridge (N1) are both connected to the first test unit, the third test unit and the fifth test unit; the rectifier lower half (Z2) and the inverter lower half bridge (N2) are both connected to the second test unit, the fourth test unit and the sixth test unit; the chopper (T1) is connected to the seventh test unit; and the chopper diode (D3) is connected to the eighth test unit; The first test unit, the second test unit, the third test unit, the fourth test unit, the fifth test unit, the sixth test unit, the seventh test unit and the eighth test unit each include a plurality of groups of relays, each group of the relays being used to control the on / off state of the rectifier (Z), the inverter (N), the chopper (T1) or the chopper diode (D3).

3. A device testing tool according to claim 2, characterized in that: The first test unit includes a first rectifier test unit (K11), the third test unit includes a second rectifier test unit (K31), the fifth test unit includes a third rectifier test unit (K51), the rectifier upper half (Z1) includes a first diode (D11), a second diode (D12) and a third diode (D13) connected to each other, the first diode (D11) is connected to the first rectifier test unit (K11), the second diode (D12) is connected to the second rectifier test unit (K31), and the third diode (D13) is connected to the third rectifier test unit (K51).

4. A device testing tool according to claim 2, characterized in that: The second test unit includes a fourth rectifier test unit (K21), the fourth test unit includes a fifth rectifier test unit (K41), the sixth test unit includes a sixth rectifier test unit (K61), the rectifier lower half (Z2) includes a fourth diode (D21), a fifth diode (D22) and a sixth diode (D23) connected to each other, the fourth diode (D21) is connected to the fourth rectifier test unit (K21), the fifth diode (D22) is connected to the fifth rectifier test unit (K41), and the sixth diode (D23) is connected to the sixth rectifier test unit (K61).

5. A device testing tool according to claim 2, characterized in that: The first test unit also includes a first inverter test unit (K12) connected to the first rectifier test unit (K11), the third test unit also includes a second inverter test unit (K32) connected to the second rectifier test unit (K31), the fifth test unit also includes a third inverter test unit (K52) connected to the third rectifier test unit (K51), the inverter upper half bridge (N1) includes a first upper half bridge inverter (U11), a second upper half bridge inverter (V11) and a third upper half bridge inverter (W11) connected to each other, the first upper half bridge inverter (U11) is connected to the first inverter test unit (K12), the second upper half bridge inverter (V11) is connected to the unit for testing the second inverter (N), and the third upper half bridge inverter (W11) is connected to the third inverter test unit (K52).

6. A device testing tool according to claim 2, characterized in that: The second test unit also includes a fourth inverter test unit (K22) connected to the fourth rectifier test unit (K21), the fourth test unit also includes a fifth inverter test unit (K42) connected to the fifth rectifier test unit (K41), the sixth test unit also includes a sixth inverter test unit (K62) connected to the sixth rectifier test unit (K61), the inverter lower half bridge (N2) includes a first lower half bridge inverter (U21), a second lower half bridge inverter (V21) and a third lower half bridge inverter (W21) connected to each other, the first lower half bridge inverter (U21) is connected to the fourth inverter test unit (K22), the second lower half bridge inverter (V21) is connected to the fifth inverter test unit (K42), and the third lower half bridge inverter (W21) is connected to the sixth inverter test unit (K62).

7. The device testing tool according to claim 5, characterized in that: The seventh test unit comprises a chopper test unit (K71), and the chopper (T1) is connected to the chopper test unit (K71).

8. The device testing tool according to claim 6, characterized in that: The eighth test unit includes a chopper diode test unit (K81), and the chopper diode (D3) is connected to the chopper diode test unit (K81).

9. The device testing tool according to claim 1, characterized in that: The support (1) comprises a bottom plate (11) and a side frame (12), wherein the side frame (12) is arranged near the edge of the bottom plate (11), and a pressing assembly (2) is arranged near the top of the side frame (12), wherein the pressing assembly (2) comprises a mounting frame (21), a pressing rod handle (22) and a pressing rod column (23), wherein the mounting frame (21) is fixed on the side frame (12), the pressing rod handle (22) is rotatably arranged on the mounting frame (21), one end of the pressing rod column (23) passes through the mounting frame (21) and is hingedly connected to the pressing rod handle (22), and the pressing plate (3) is arranged at one end of the pressing rod column (23) away from the pressing rod handle (22); A guide block (51) is also provided on the side frame (12), a guide rod (52) is fixed on the pressure plate (3), and the guide rod (52) is arranged to penetrate the guide block (51).

10. A device testing method, applicable to the device testing tool according to any one of claims 1 to 9, characterized in that: include: Placing the device under test on the test mount, and pressing the device under test down with a test fixture so that the device under test is plugged into a socket in the test mount to form a test circuit connection; The testing device sends a control signal to the testing circuit and receives a feedback signal from the device under test.

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