Test circuit and test method for TSV (Through Silicon Via) before binding based on enhanced loop oscillator

Abstract

The invention discloses a TSV (Through Silicon Via) pre-binding test circuit and test method based on an enhanced loop oscillator, and relates to the field of TSV test. The invention aims to solve the problem that an existing TSV pre-binding test method is difficult to meet accuracy and integration at the same time. No matter in a TSV open-circuit fault test mode or an electric leakage fault test mode, the test result of each loop can be output to the automatic test equipment from the counting port in a frequency counting mode, and the corresponding open-circuit position and electric leakage conductance information are given after analysis and calculation by the automatic test equipment. According to the invention, TSV open circuit, electric leakage and open circuit and electric leakage mixed faults can be effectively detected, and the severity of the faults can be quantitatively diagnosed. The open-circuit fault coverage rate can reach 95%, and the minimum capacitance resolution is 2.98 fF; for a leakage fault, the minimum leakage-detectable conductance is 4n Siemens, and the leakage conductance diagnosis error does not exceed 11%.

Description

Technical Field

[0001] The invention belongs to the field of circuits, and in particular relates to a TSV pre-binding test. Background Art

[0002] As a vertical interconnection path in three-dimensional integrated circuits, TSV (Through Silicon Via) may cause open circuit, leakage and open circuit leakage mixed faults during its manufacturing process. Pre-binding test of TSV can effectively find faulty TSV, so as to choose to abandon the faulty circuit or adopt corresponding repair strategies to improve the yield rate of three-dimensional integrated circuits. At present, many TSV pre-binding test methods have been proposed:

[0003] A TSV pre-binding test method based on a sensor amplifier determines whether the TSV is faulty by measuring the time required for the TSV to be charged to a preset level. Its main disadvantage is that it is easily affected by process, voltage, and temperature variations (PVT variations).

[0004] A TSV pre-binding test method based on a ring oscillator determines whether the TSV is faulty by measuring the oscillation frequency after the TSV is connected to the ring oscillator. The main disadvantage of this method is that it is easily affected by PVT deviation and cannot effectively detect faults occurring at the end of the TSV.

[0005] A TSV pre-binding test method resistant to PVT deviation has a higher fault resolution for TSV open circuit and leakage faults, but its main defect is that it cannot distinguish between open circuit and leakage mixed faults.

[0006] A TSV pre-binding test method based on pulse reduction is proposed. The method uses a pulse reduction circuit to detect the transmission delay of TSV, so as to determine whether TSV is faulty. The main advantage of this method is that it can effectively detect TSV open circuit, leakage and open circuit leakage mixed faults. The disadvantage is that it is easily affected by PVT deviation.

[0007] A TSV pre-binding test method based on a self-biased current source is proposed. The method uses a self-biased current source to charge and discharge the TSV, and determines whether the TSV is faulty by the change in the total charge and discharge time. The main advantage of this method is that it can effectively detect TSV open circuit, leakage, and open circuit leakage mixed faults and has good robustness. Its main disadvantage is that the test circuit uses a mixed digital-analog circuit, which is not easy to integrate compared to a pure digital circuit.

[0008] In summary, existing TSV pre-binding test methods all have certain shortcomings, which are not conducive to the accuracy and integration of TSV pre-binding tests. Summary of the invention

[0009] The present invention aims to solve the problem that the existing TSV pre-binding test method is difficult to meet both accuracy and integration, and now provides a TSV pre-binding test circuit and a test method based on an enhanced ring oscillator.

[0010] A TSV pre-binding test circuit based on an enhanced ring oscillator, comprising: a mode port, an instruction port, a clock port, a counting port, a D flip-flop 1 to a D flip-flop 2k, and a loop 1 to a loop k;

[0011] Loop 3 to loop k are each connected to a TSV under test;

[0012] D flip-flops 1 to D flip-flops k correspond one-to-one to loops 1 to k, respectively, and D flip-flops k+1 to D flip-flops 2k correspond one-to-one to loops 1 to k, respectively;

[0013] The D flip-flops 1 to 2k are connected in sequence head to tail, the output ports of the D flip-flops 1 to 2k are connected to the input enable ports of the corresponding loops, respectively, and the output ports of the D flip-flops k+1 to 2k are connected to the selection ports of the corresponding loops, respectively;

[0014] The clock ports are respectively connected to the clock ports of D flip-flops 1 to 2k;

[0015] The instruction port is connected to the instruction input port of the D flip-flop 1;

[0016] The mode ports are respectively connected to the mode enable ports of each loop;

[0017] The counting ports are respectively connected to the output ports of the loops.

[0018] Furthermore, the structures of the above loop 1 and loop 3 to loop k are the same and all include two upper tri-state drivers, two lower tri-state drivers and a multiplexer;

[0019] Loop 2 includes two upper tri-state drivers, six lower tri-state drivers, and a multiplexer;

[0020] In each loop, the output ends of the upper three-state driver and the lower three-state driver at the front end are respectively connected to the input ends of the upper three-state driver and the lower three-state driver at the back end, the output end of the multiplexer is connected to the enable end of the upper three-state driver at the front end, the enable ends of all the lower three-state drivers are used as the mode enable port of the loop, the enable end of the upper three-state driver at the back end and an input end of the multiplexer are used as the input enable port of the loop, the selection end of the multiplexer is used as the selection port of the loop, and the output end of the upper three-state driver at the back end is used as the output port of the loop;

[0021] In loops 3 to k, the output ends of the upper tri-state driver and the lower tri-state driver at the front end of each loop are connected to a TSV to be tested.

[0022] Furthermore, the TSV pre-binding test circuit further includes a delay circuit, a positive phase converter and a phase inverter;

[0023] The output ports of all loops are connected to the input end of the delay circuit, the output end of the delay circuit is respectively connected to the counting port, the input end of the positive phase detector and the input end of the inverter, the output end of the positive phase detector is respectively connected to the other input end of each multiplexer, and the output end of the inverter is respectively connected to the input end of the upper three-state driver located at the front end in each loop.

[0024] Furthermore, in loops 3 to k, the input end of the lower tri-state driver at the front end and the output end of the lower tri-state driver at the back end are both connected to the logic circuit of the TSV under test.

[0025] Furthermore, the above-mentioned TSV pre-binding test circuit includes an open circuit fault test mode and a leakage fault test mode.

[0026] Furthermore, within k+1 clock cycles, the instruction port inputs a "0" signal in the first clock cycle and a "1" signal in the remaining k clock cycles, so that D flip-flop 1 to D flip-flop k provide enable signals En1 to Enk to the upper three-state drivers in loop 1 to loop k in turn. Under the action of the enable signals En1 to Enk, loop 1 to loop k enter the open circuit fault test mode in turn.

[0027] Furthermore, within k+1 clock cycles, the instruction port inputs a "0" signal in the first clock cycle and a "1" signal in the remaining k clock cycles, so that D flip-flop 1 to D flip-flop k provide enable signals En1 to Enk to the upper three-state drivers at the rear end in loop 1 to loop k in turn, and at the same time, D flip-flop k+1 to D flip-flop 2k provide "0" selection signals to the multiplexers in loop 1 to loop k in turn, and under the joint action of enable signals En1 to Enk and the "0" selection signal, loop 1 to loop k enter the leakage fault test mode in turn.

[0028] Furthermore, the TSV pre-binding test method is implemented based on the TSV pre-binding test circuit based on the enhanced ring oscillator, and the TSV pre-binding test method includes:

[0029] In the open circuit fault test mode, the open circuit position x is calculated according to the following formula:

[0030] x=ΔT2 / ΔT1,

[0031] Where ΔT2 = T 待测 -T c1 , ΔT1=T 无故障 -T c1 , T c1 and T c2 are the oscillation periods of loop 1 and loop 2 in the open circuit fault test mode, T 无故障 and T 待测 The oscillation periods of the loop where the fault-free TSV is located and the loop where the TSV to be detected is located;

[0032] In the leakage fault test mode, the leakage conductance G of the TSV to be tested is calculated according to the following formula: TSV :

[0033]

[0034] Among them, R on , R off and C p are the on-resistance, high-resistance resistance and total parasitic capacitance of the three-state driver, V DD Supply voltage for the test circuit, V th is the three-state driver driving threshold voltage, C TSV is the load capacitance of the fault-free TSV, ΔT6 = T 待测 -T 无故障 .

[0035] Furthermore, when x=0.5, it indicates that the open circuit is located in the middle of the TSV; when x=0.1, it indicates that the open circuit is located at 10% of the upper end of the TSV; and when x=1, it indicates that the TSV has no open circuit fault.

[0036] Furthermore, the on-resistance, high-resistance resistance and total parasitic capacitance R of the above three-state driver are on , R off and C p Obtained by the following formula:

[0037]

[0038] ΔT5=R off C p ln(V DD / V th )-R on 2C p ln(V DD / V th ),

[0039]

[0040] Where ΔT3 = T R1 -Tc1 , ΔT4=T c2 -T c1 , ΔT5=T R2 -T c2 , T R1 and T R2 are the oscillation periods of loop 1 and loop 2 in leakage fault test mode respectively.

[0041] The TSV pre-binding test circuit based on an enhanced ring oscillator described in the present invention has the following main advantages:

[0042] 1. It can effectively detect TSV open circuit, leakage and open circuit leakage mixed faults, and can quantitatively diagnose the severity of the fault. For open circuit faults, the coverage rate can reach 95%, and the minimum capacitance resolution is 2.98fF; for leakage faults, the minimum measurable leakage conductance is 4n Siemens, and the leakage conductance diagnosis error does not exceed 11%.

[0043] 2. Able to resist the influence of PVT deviation and has good robustness.

[0044] 3. The test circuit adopts standard gate circuit design and pure digital structure, which is easier to integrate.

[0045] 4. The test time overhead and chip area overhead are small. The average test time required for each TSV is 4.27 microseconds, and the chip area occupied by each TSV test circuit is about 7.27 square microns. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 The overall structure diagram of the TSV pre-binding test circuit based on the enhanced ring oscillator;

[0047] Figure 2 This is a test effect diagram of the TSV pre-binding test circuit based on the enhanced ring oscillator. DETAILED DESCRIPTION

[0048] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0049] Specific implementation method 1: refer to Figure 1Specifically describing this embodiment, the TSV pre-binding test circuit based on the enhanced ring oscillator described in this embodiment has three test control signal input ports, namely: mode port, instruction port and clock port, one test result output port: counting port; k loops, namely: loop 1 to loop k; 2k D flip-flops, namely D flip-flop 1 to D flip-flop 2k.

[0050] Loop 1 and loop 3 to loop k have the same structure, and all include two upper three-state drivers, two lower three-state drivers, and a multiplexer. The output ends of the upper three-state driver and the lower three-state driver at the front end are connected to the input ends of the upper three-state driver and the lower three-state driver at the back end; the output ends of the upper three-state driver at the back end are connected to the input ends of the delay circuit. The output end of the multiplexer is connected to the enable end of the upper three-state driver at the front end.

[0051] The difference between loop 2 and other loops is that it includes 6 lower-layer three-state drivers, including three front-end lower-layer three-state drivers and three rear-end lower-layer three-state drivers, and all front-end three-state driver outputs are connected to the inputs of the rear-end three-state drivers.

[0052] Loop 1 and loop 2 do not contain the TSV under test, and their test results will be used for de-embedding, thereby improving the robustness of the test circuit in the face of PVT deviations. The output terminals of the two three-state drivers at the front end of loop 3 to loop k are each connected to a TSV under test. The input terminal of the lower three-state driver at the front end and the output terminal of the lower three-state driver at the back end of loop 3 to loop k are both used to connect the logic circuit corresponding to the TSV.

[0053] The output end of the delay circuit is connected to the input end of the inverter, the input end of the phase-matching device and the counting port respectively. The output end of the phase-matching device is connected to one input end of each multiplexer respectively. The output end of the inverter is connected to the input end of each upper tri-state driver located at the front end respectively.

[0054] The mode port is connected to the enable terminal Mode of the lower three-state driver in each loop.

[0055] When the mode port input enable signal is valid (the signal is "0"), these lower-layer three-state drivers are in a working state, so that each TSV is connected to its corresponding logic circuit, and all TSVs are in a normal working state; when the mode port input enable signal is invalid (the signal is "1"), these lower-layer three-state drivers are in a high-impedance state, so that each TSV is isolated from its corresponding logic circuit, and all TSVs are in a test state.

[0056] 2k D flip-flops are connected end to end to form a shift register.

[0057] The instruction port is connected to the instruction input port of the D flip-flop 1.

[0058] The clock port is connected to the clock ports of all D flip-flops respectively.

[0059] The output terminals of the D flip-flops 1 to D flip-flops k are respectively connected to the enable terminals of the upper tri-state drivers at the rear end in each loop and the other input terminal of the multiplexer.

[0060] The output ends of the D flip-flop k+1 to the D flip-flop 2k are respectively connected to the selection ends (Control1 to Control k) of the multiplexers in each loop.

[0061] The working principle of the TSV pre-binding test circuit based on the enhanced ring oscillator described in this embodiment is as follows:

[0062] When TSV is in normal working state, let the instruction port input "1". After inputting "2k" clock cycles at the clock port, all D flip-flops will output "1" signal, which makes the upper two tri-state drivers in each loop in high impedance state, and each TSV will be isolated from the test circuit.

[0063] When TSV is in the testing state, it can be divided into two situations:

[0064] First, let the instruction port input "0" for one clock cycle, and then continue to maintain "1". Then, within k clock cycles, D flip-flops 1 to D flip-flops k will provide enable signals En1 to Enk to the upper two tri-state drivers in loops 1 to k in turn. Under the action of the enable signal, loops 1 to k will enter the open circuit fault test mode in turn. Under the action of the clock signal, loops 3 to k will complete the open circuit fault test of the tested TSV in turn.

[0065] Secondly, after completing the open circuit fault test, let the instruction port input "0" for one clock cycle, and then continue to maintain "1". In the next k clock cycles, D flip-flop 1 to D flip-flop k will provide enable signals En1 to Enk to the upper right tri-state drivers in loops 1 to loops k in turn, and D flip-flop k+1 to D flip-flop 2k will provide "0" selection signals to the multiplexers in loops 1 to loops k in turn. Under the joint action of enable signals En1 to Enk and "0" selection signals, loops 1 to loops k will enter the leakage fault test mode in turn. Under the action of the clock signal, loops 3 to loops k complete the leakage fault test of the tested TSV in turn.

[0066] Regardless of the TSV open circuit fault test or leakage fault test mode, the test results of each loop will be output from the counting port to the automatic test equipment in the form of frequency counts, and the automatic test equipment will give the corresponding open circuit position and leakage conductance information after analysis and calculation.

[0067] Specific implementation method 2: The TSV pre-binding test method based on the enhanced ring oscillator described in this implementation method includes:

[0068] Assume that in the open circuit fault test, the oscillation period measured by loop 1 is T c1 , the oscillation period measured by loop 2 is T c2 , the oscillation period of the loop where the fault-free TSV is located is T 无故障 The oscillation period measured in the loop where the TSV to be detected is T 待测 According to the design principle of the TSV pre-binding test circuit described in the first embodiment, if the effective load capacitance of the TSV to be tested is C TSV1 , the load capacitance of the fault-free TSV is C TSV , then it satisfies the open circuit capacitance calculation formula:

[0069]

[0070] Where ΔT2 = T 待测 -T c1 , ΔT1=T 无故障 -T c1 .

[0071] The effective load capacitance C of the TSV to be tested TSV1 It is proportional to the open circuit position x, which satisfies x=C TSV1 / C TSV ;

[0072] When x = 0.5, it indicates that the open circuit is in the middle of the TSV;

[0073] When x = 0.1, it indicates that the open circuit is at the upper 10% of the TSV;

[0074] When x=1, it indicates that there is no open circuit fault in the TSV.

[0075] Since the failure rate of TSV is between 0.1% and 0.01%, this means that most of the TSVs to be tested in a test group are fault-free TSVs. Therefore, in the calculation process, the oscillation period T of the loop where the fault-free TSV is located is 无故障 It can be calculated from the average value of each loop oscillation period.

[0076] Assume that in the leakage fault test, the oscillation period measured by loop 1 is T R1 , the oscillation period measured by loop 2 is T R2 The oscillation period measured in the loop where the TSV to be detected is T 待测 , then use T R1 、T R2 、T c1 、T c2The on-resistance R of the three-state driver can be calculated on , high resistance resistor R off and the total parasitic capacitance C p :

[0077]

[0078] ΔT5=R off C p ln(V DD / V th )-R on 2C p ln(V DD / V th ),

[0079]

[0080] Where ΔT3 = T R1 -T c1 , ΔT4=T c2 -T c1 , ΔT5=T R2 -T c2 .

[0081] Finally, the leakage conductance G of the TSV to be tested can be calculated according to the leakage conductance calculation formula. TSV :

[0082]

[0083] Where ΔT6 = T 待测 -T 无故障 ; V DD The power supply voltage for the test circuit is 1.1V; V th The three-state driver driving threshold voltage is 0.5V.

[0084] Specific implementation method three: refer to Figure 2 The present embodiment is described in detail, which is a TSV pre-binding test circuit based on an enhanced ring oscillator.

[0085] Figure 2The test effect diagram of TSV open circuit leakage fault test using TSV pre-binding test circuit k=32 based on enhanced ring oscillator, that is, 32 loops (including 30 TSVs) are shown. In the figure, loop 1 and loop 2 do not contain TSVs, and their test results are only used for de-embedding. Loops 3 to 32 each contain a tested TSV, among which the TSV of loop 12 has an open circuit fault in the middle, the TSV of loop 17 has an open circuit fault at 1 / 6 of its entry depth, the TSV of loop 22 has a leakage fault of 100 microSiemens, and the TSV of loop 32 has an open circuit leakage mixed fault. The open circuit position is 3 / 4 of its entry depth, and the leakage size is 20 microSiemens. The TSVs of all other loops are fault-free TSVs. The TSV at the top of the figure is c1 represents the oscillation period measured in loop 1 during the open circuit fault test, T c2 It represents the oscillation period measured by loop 2 in the open circuit fault test, and so on; T R22 represents the oscillation period measured by loop 22 in the leakage fault test, T R32 represents the oscillation period measured by loop 32 in the leakage fault test, and so on. According to the above test period and the ring oscillator principle of the open circuit resistance and leakage conductance calculation formula, the fault detection and diagnosis results shown in Table 1 can be given.

[0086] Table 1 Fault detection and diagnosis results

[0087]

[0088] From the results in Table 1, it can be seen that the test circuit can effectively detect and diagnose TSV open circuit, leakage and open circuit leakage mixed faults, and has a high fault resolution and a small diagnosis error.

[0089] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that the features described in conjunction with a single embodiment may be used in other described embodiments.

Claims

1. A TSV pre-bonding test circuit based on an enhanced ring oscillator, characterized in that: include: Mode port, instruction port, clock port, counting port, D flip-flop 1 to D flip-flop 2k and loop 1 to loop k; Loop 3 to loop k are each connected to a TSV under test; D flip-flops 1 to D flip-flops k correspond one-to-one to loops 1 to k, respectively, and D flip-flops k+1 to D flip-flops 2k correspond one-to-one to loops 1 to k, respectively; The D flip-flops 1 to 2k are connected in sequence head to tail, the output ports of the D flip-flops 1 to 2k are connected to the input enable ports of the corresponding loops, respectively, and the output ports of the D flip-flops k+1 to 2k are connected to the selection ports of the corresponding loops, respectively; The clock ports are respectively connected to the clock ports of D flip-flops 1 to 2k; The instruction port is connected to the instruction input port of the D flip-flop 1; The mode ports are respectively connected to the mode enable ports of each loop; The counting ports are respectively connected to the output ports of the loops.

2. The TSV pre-binding test circuit based on an enhanced ring oscillator according to claim 1, characterized in that: The structures of loop 1 and loop 3 to loop k are the same and all include two upper tri-state drivers, two lower tri-state drivers and a multiplexer; Loop 2 includes two upper tri-state drivers, six lower tri-state drivers, and a multiplexer; In each loop, the output ends of the upper three-state driver and the lower three-state driver at the front end are respectively connected to the input ends of the upper three-state driver and the lower three-state driver at the back end, the output end of the multiplexer is connected to the enable end of the upper three-state driver at the front end, the enable ends of all the lower three-state drivers are used as the mode enable port of the loop, the enable end of the upper three-state driver at the back end and an input end of the multiplexer are used as the input enable port of the loop, the selection end of the multiplexer is used as the selection port of the loop, and the output end of the upper three-state driver at the back end is used as the output port of the loop; In loops 3 to k, the output ends of the upper tri-state driver and the lower tri-state driver at the front end of each loop are connected to a TSV to be tested.

3. The TSV pre-binding test circuit based on an enhanced ring oscillator according to claim 2, characterized in that: Also included are delay circuits, phase positives and phase inverters; The output ports of all loops are connected to the input end of the delay circuit, the output end of the delay circuit is respectively connected to the counting port, the input end of the positive phase detector and the input end of the inverter, the output end of the positive phase detector is respectively connected to the other input end of each multiplexer, and the output end of the inverter is respectively connected to the input end of the upper three-state driver located at the front end in each loop.

4. The TSV pre-binding test circuit based on an enhanced ring oscillator according to claim 2, characterized in that: In loops 3 to k, the input end of the lower tri-state driver at the front end and the output end of the lower tri-state driver at the back end are both connected to the logic circuit of the TSV to be tested.

5. The TSV pre-binding test circuit based on an enhanced ring oscillator according to claim 1, 2, 3 or 4, characterized in that: The TSV pre-binding test circuit includes an open circuit fault test mode and a leakage fault test mode.

6. The TSV pre-binding test circuit based on an enhanced ring oscillator according to claim 5, characterized in that: Within k+1 clock cycles, the instruction port inputs a "0" signal in the first clock cycle and a "1" signal in the remaining k clock cycles, so that D flip-flop 1 to D flip-flop k provide enable signals En1 to Enk to the upper three-state drivers in loop 1 to loop k in turn. Under the action of the enable signals En1 to Enk, loop 1 to loop k enter the open circuit fault test mode in turn.

7. The TSV pre-binding test circuit based on an enhanced ring oscillator according to claim 5, characterized in that: Within k+1 clock cycles, the instruction port inputs a "0" signal in the first clock cycle and a "1" signal in the remaining k clock cycles, so that D flip-flops 1 to D flip-flops k provide enable signals En1 to Enk to the upper three-state drivers at the rear end in loops 1 to loops k in turn. At the same time, D flip-flops k+1 to D flip-flops 2k provide "0" selection signals to the multiplexers in loops 1 to loops k in turn. Under the joint action of the enable signals En1 to Enk and the "0" selection signal, loops 1 to loops k enter the leakage fault test mode in turn.

8. A TSV pre-binding test method based on an enhanced ring oscillator, characterized in that: The TSV pre-binding test method is implemented based on the TSV pre-binding test circuit based on the enhanced ring oscillator according to any one of claims 1 to 7, and the TSV pre-binding test method includes: In the open circuit fault test mode, the open circuit position x is calculated according to the following formula: x=ΔT2 / ΔT1, Where ΔT2 = T 待测 -T c1 , ΔT1=T 无故障 -T c1 , T c1 and T c2 are the oscillation periods of loop 1 and loop 2 in the open circuit fault test mode, T 无故障 and T 待测 The oscillation periods of the loop where the fault-free TSV is located and the loop where the TSV to be detected is located; In the leakage fault test mode, the leakage conductance G of the TSV to be tested is calculated according to the following formula: TSV : Among them, R on , R off and C p are the on-resistance, high-resistance resistance and total parasitic capacitance of the three-state driver, V DD Supply voltage for the test circuit, V th is the three-state driver driving threshold voltage, C TSV is the load capacitance of the fault-free TSV, ΔT6 = T 待测 -T 无故障 .

9. The TSV pre-binding test method based on an enhanced ring oscillator according to claim 8, characterized in that: When x = 0.5, it indicates that the open circuit is in the middle of the TSV; When x = 0.1, it indicates that the open circuit is at 10% of the upper end of the TSV; When x=1, it indicates that there is no open circuit fault in the TSV.

10. The TSV pre-binding test method based on an enhanced ring oscillator according to claim 8, characterized in that: The on-resistance, high-resistance resistance and total parasitic capacitance R of the tri-state driver on , R off and C p Obtained by the following formula: ΔT5=R off C p ln(V DD / V th )-R on 2C p ln(V DD / V th ), Where ΔT3 = T R1 -T c1 , ΔT4=T c2 -T c1 , ΔT5=T R2 -T c2 , T R1 and T R2 are the oscillation periods of loop 1 and loop 2 in leakage fault test mode respectively.

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