Method for resetting hardware unit in integrated circuit and integrated circuit

Abstract

The invention discloses a method and device for resetting a hardware unit in an integrated circuit, and the method comprises the steps: detecting that a first hardware unit in a first operating system needs to be reset, and before the first hardware unit is reset, resetting the first hardware unit based on the working state of an interface between the first hardware unit and a bus; determining an adjustment strategy of a data channel between a second hardware unit in a second operating system sharing a bus with the first operating system and the first hardware unit, so as to complete an uncompleted access request between the first hardware unit and the second hardware unit by adjusting a flow control state of the data channel, and intercepting an access request newly generated by the first hardware unit and transmitting the access request to the bus. Therefore, when the first hardware unit is reset, the bus can still work normally, and the second hardware unit sharing the bus can still work normally, so that the second operating system running through the second hardware unit can still run normally, and the running stability of each operating system is greatly improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a method for resetting a hardware unit in an integrated circuit and an integrated circuit. Background Art

[0002] A system on chip (SoC), also known as an integrated circuit, may include multiple hardware units, which may support the running of multiple operating systems (OS), so that multiple operating systems may be run on the integrated circuit. When the multiple hardware units run their respective corresponding operating systems, they may share some hardware resources in the integrated circuit, such as a bus, that is, the multiple hardware units may access each other through the bus.

[0003] When an abnormality occurs in the operating system, the normal operation of the operating system in which the abnormality occurs (hereinafter referred to as the "abnormal operating system") can be restored by resetting the hardware unit that causes the abnormality (hereinafter referred to as the "abnormal hardware unit"). Summary of the invention

[0004] When the abnormal hardware unit in the abnormal operating system is reset, it cannot normally process the access requests that have not been completed, and the abnormal hardware unit will continue to transmit new access requests to the bus, which will cause the bus to become abnormal, resulting in abnormalities in other hardware units sharing the bus, and then causing abnormalities in the operating system running through the other hardware units.

[0005] In order to solve the above technical problems, the present disclosure provides a method for resetting a hardware unit in an integrated circuit and an integrated circuit, which can solve the problem that when an abnormal hardware unit in an abnormal operating system is reset, other hardware units on a shared bus will become abnormal, and the operating system running through the other hardware units will also become abnormal.

[0006] A first aspect of the present disclosure provides a method for resetting a hardware unit in an integrated circuit, comprising: reading a state of a reset signal from a register, wherein the reset signal is used to request resetting a first hardware unit, and the first hardware unit corresponds to a first operating system; determining a working state of an interface between the first hardware unit and a bus based on the state of the reset signal; determining an adjustment strategy for two or more data channels between the first hardware unit and a second hardware unit based on the working state of the interface, wherein the second hardware unit corresponds to a second operating system; adjusting a flow control state of the data channel based on the adjustment strategy; and resetting the first hardware unit based on the working state of the interface.

[0007] The second aspect of the present disclosure provides an integrated circuit, including: a first hardware unit, corresponding to a first operating system; a second hardware unit, corresponding to a second operating system; a reset security module, corresponding to the first hardware unit; a register, storing a state of a reset signal, the reset signal being used to request resetting the first hardware unit; the reset security module is used to read the state of the reset signal from the register; the reset security module is also used to determine, based on the state of the reset signal, a working state of an interface between the first hardware unit and a bus; the reset security module is also used to determine, based on the working state of the interface, an adjustment strategy for two or more data channels between the first hardware unit and the second hardware unit; the reset security module is also used to adjust the flow control state of the data channel based on the adjustment strategy; the reset security module is also used to reset the first hardware unit based on the working state of the interface.

[0008] According to a third aspect of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program for executing the method for resetting a hardware unit in an integrated circuit provided in the first aspect.

[0009] The fourth aspect of the present disclosure provides an electronic device, which includes: a processor; a memory for storing processor executable instructions; the processor is used to read the executable instructions from the memory and execute the instructions to implement the method for resetting a hardware unit in an integrated circuit provided in the first aspect above, or the electronic device includes the integrated circuit provided in the second aspect above.

[0010] A fifth aspect of the present disclosure provides a computer program product. When instructions in the computer program product are executed by a processor, the method for resetting a hardware unit in an integrated circuit provided in the first aspect is performed.

[0011] Based on the method for resetting a hardware unit in an integrated circuit provided by the present disclosure, when it is detected that a first hardware unit in a first operating system needs to be reset, before resetting the first hardware unit, based on the working state of the interface between the first hardware unit and the bus, an adjustment strategy for a data channel between a second hardware unit and the first hardware unit in a second operating system that shares a bus with the first operating system is determined, so as to complete an uncompleted access request between the first hardware unit and the second hardware unit by adjusting the flow control state of the data channel, and intercept the transmission of a newly generated access request of the first hardware unit to the bus. As a result, the bus can still work normally when the first hardware unit is reset, and the second hardware unit that shares the bus can still work normally, so the second operating system running through the second hardware unit can still work normally, which greatly improves the operating stability of each operating system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram of the architecture of an integrated circuit provided by an exemplary embodiment of the present disclosure;

[0013] Figure 2 is a schematic diagram of the architecture of an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0014] Figure 3 is a schematic diagram of the architecture of an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0015] Figure 4 is a flowchart of a method for resetting a hardware unit in an integrated circuit provided by an exemplary embodiment of the present disclosure;

[0016] Figure 5 is a flowchart of a method for resetting a hardware unit in an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0017] Figure 6 is a flowchart of a method for resetting a hardware unit in an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0018] Figure 7 is a flowchart of a method for resetting a hardware unit in an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0019] Figure 8 is a flowchart of a method for resetting a hardware unit in an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0020] Fig. 9 is a flowchart of a method for resetting a hardware unit in an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0021] Fig.10 It is a structural schematic diagram of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0023] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0024] Application Overview

[0025] A system on chip (SoC), also known as an integrated circuit, may include multiple hardware units, through which multiple operating systems (OS) can be supported, so that multiple operating systems can be run on the integrated circuit. When the multiple hardware units run their corresponding operating systems, they can share some hardware resources in the integrated circuit, such as a bus, that is, the multiple hardware units can access each other through the bus.

[0026] When an operating system is abnormal, the normal operation of the abnormal operating system can be restored by resetting the abnormal hardware unit.

[0027] However, when the abnormal hardware unit is reset, it cannot normally process the access requests that have not been completed, and the abnormal hardware unit will continue to transmit new access requests to the bus, which will cause the bus to become abnormal, causing other hardware units sharing the bus to become abnormal, and then causing the operating system running through the other hardware units to become abnormal.

[0028] In order to solve the above technical problems, the embodiments of the present disclosure provide a device and method for resetting a hardware unit in an integrated circuit.

[0029] The device may include: a first hardware unit, corresponding to a first operating system; a second hardware unit, corresponding to a second operating system; a reset security module, corresponding to the first hardware unit; a register, storing a state of a reset signal, the reset signal being used to request resetting the first hardware unit; the reset security module being used to read the state of the reset signal from the register; the reset security module being also used to determine, based on the state of the reset signal, a working state of an interface between the first hardware unit and a bus; the reset security module being also used to determine, based on the working state of the interface, an adjustment strategy for two or more data channels between the first hardware unit and the second hardware unit; the reset security module being also used to adjust, based on the adjustment strategy, a flow control state of the data channel; the reset security module being also used to reset the first hardware unit based on the working state of the interface.

[0030] The method includes: when it is detected that the first hardware unit in the first operating system needs to be reset, before resetting the first hardware unit, based on the working state of the interface between the first hardware unit and the bus, determining the adjustment strategy of the data channel between the second hardware unit and the first hardware unit in the second operating system that shares the bus with the first operating system, so as to complete the unfinished access request between the first hardware unit and the second hardware unit by adjusting the flow control state of the data channel, and intercept the access request newly generated by the first hardware unit and transmit it to the bus. As a result, when the first hardware unit is reset, the bus can still work normally, and the second hardware unit sharing the bus can still work normally. Therefore, the second operating system running through the second hardware unit can still work normally, which greatly improves the operation stability of each operating system.

[0031] The method for resetting a hardware unit in an integrated circuit in the present disclosure is further described below with reference to the accompanying drawings.

[0032] Exemplary Systems

[0033] Figure 1 Schematic diagram of the architecture of an integrated circuit provided by an exemplary embodiment of the present disclosure.

[0034] like Figure 1 As shown, the integrated circuit can run multiple operating systems, such as a first operating system 11 and a second operating system 12. Each operating system can be run through at least one hardware unit, for example, the first operating system 11 can be run through a first hardware unit 13, and the second operating system 12 can be run through a second hardware unit 14. When the first hardware unit 13 and the second hardware unit 14 run their respective corresponding operating systems, they can share a bus 15 in the integrated circuit, that is, the first hardware unit 13 and the second hardware unit 14 can access each other through the bus 15.

[0035] The integrated circuit also includes reset security modules corresponding to the hardware units, and the hardware units access the bus 15 through the corresponding reset security modules. For example, the first hardware unit 13 accesses the bus 15 through the first reset security module 161, and the second hardware unit 14 accesses the bus 15 through the second reset security module 162.

[0036] In some embodiments, before a hardware unit is reset, the state of the interface between the hardware unit and the bus can be monitored by a reset security module corresponding to the hardware unit, and the flow control state of the data channel between the hardware unit and other hardware units can be adjusted based on the state of the interface by the reset security module.

[0037] Figure 2 is a schematic diagram of the architecture of an integrated circuit provided by another exemplary embodiment of the present disclosure.

[0038] In some examples, in the above Figure 1 Based on the architecture shown, Figure 2 As shown, taking the first reset security module 161 as an example, the structure of the reset security module is exemplarily shown. The first reset security module 161 may include three counters, such as a first counter 211, which may also be called a read command counter; a second counter 212, which may also be called a write command counter; and a third counter 213, which may also be called a write data counter. Among them, the first counter 211 is used to count the number of read command requests that have not been transmitted between the first hardware unit 13 and the second hardware unit 14, the second counter 212 is used to count the number of write command requests that have not been transmitted between the first hardware unit 13 and the second hardware unit 14, and the third counter 213 is used to count the number of write data requests that have not been transmitted between the first hardware unit 13 and the second hardware unit 14.

[0039] The first reset security module 161 may include multiple logic control unit groups, each of which may include at least one logic control unit, wherein different logic control unit groups correspond to data channels of different request types, and each logic control unit group is used to control the flow control state of the data channel of the corresponding channel type.

[0040] Exemplarily, the first logic control unit group 222 corresponds to a data channel 221 for transmitting a read command request (hereinafter referred to as a “read command channel”) and is used to control a flow control state of the read command channel.

[0041] Exemplarily, the second logic control unit group 232 corresponds to a data channel 231 for transmitting a read data request (hereinafter referred to as a “read data channel”) and is used to control a flow control state of the read data channel.

[0042] Exemplarily, the third logic control unit group 242 corresponds to a data channel 241 for transmitting a write command request (hereinafter referred to as a “write command channel”), and is used to control the flow control state of the write command channel.

[0043] Exemplarily, the fourth logic control unit group 252 corresponds to a data channel 251 for transmitting a write response request (hereinafter referred to as a “write response channel”), and is used to control the flow control state of the write response channel.

[0044] Exemplarily, the fifth logic control unit group 262 corresponds to a data channel 261 for transmitting write data (hereinafter referred to as “write data channel”) and is used to control the flow control state of the write data channel.

[0045] The flow control state of the data channel includes release and block. If the flow control state of the data channel is release, it means that the access request is allowed to be transmitted through the data channel; if the flow control state of the data channel is block, it means that the access request is not allowed to be transmitted through the data channel.

[0046] The reset safety module may also include a timeout counting module, such as Figure 2 As shown, the first reset security module 161 may include a timeout counting module 27, which is used to detect whether the reset request is successful. Whether the reset request is successful is used to indicate whether the first reset security module 161 resets the first hardware unit 13 based on the reset request, wherein if the reset request is successful, the first reset security module 161 resets the first hardware unit 13 based on the reset request; if the reset request fails, the first reset security module 161 does not reset the first hardware unit 13 based on the reset request.

[0047] In some embodiments, before the hardware unit is reset, the hardware unit and the bus may be isolated by resetting the security module.

[0048] Figure 3 FIG. 4 is a schematic diagram of an integrated circuit architecture provided by another exemplary embodiment of the present disclosure.

[0049] In some examples, in the above Figure 2 Based on the structure of the first reset safety module 161, as shown in Figure 3 As shown, the first reset security module 161 further includes an isolation control unit 31 , and the isolation control unit 31 is used to isolate the first hardware unit 13 from the bus 15 .

[0050] like Figure 1 As shown, the integrated circuit further includes a register 17, which can be used to store the state of the reset signal.

[0051] Exemplary Methods

[0052] Figure 4 FIG. 1 is a flow chart of a method for resetting a hardware unit in an integrated circuit provided by an exemplary embodiment of the present disclosure. This embodiment can be applied to an electronic device, which may include Figure 1-Figure 3 In any of the integrated circuits shown in , the embodiments of the present disclosure take the hardware unit that needs to be reset as the first hardware unit 13 as an example to illustrate the method for resetting the hardware unit in the integrated circuit.

[0053] like Figure 4 As shown, the method includes the following steps 41 to 45.

[0054] Step 41: Read the state of the reset signal from the register.

[0055] The register 17 stores state information of a reset signal, where the reset signal is used to request resetting the first hardware unit 13 . The state information of the reset signal may be a state bit related to the reset signal.

[0056] The reset signal may carry status information, where the status information is used to indicate the status of the reset signal, and the status of the reset signal is used to indicate whether to initiate a reset request to the hardware unit.

[0057] Exemplarily, the state of the reset signal may include a first preset state and a fourth preset state, wherein the first preset state is used to indicate initiating a reset request, which may also be referred to as a valid state, and the fourth preset state is used to indicate not initiating a reset request, which may also be referred to as an invalid state.

[0058] In some examples, the first preset state of the reset signal may be a high level state, and the fourth preset state of the reset signal may be a low level state.

[0059] The register 17 may also store identification information of the hardware unit that is requested to be reset by the reset signal. For example, if the reset signal is used to request to reset the first hardware unit 13 , the register 17 stores identification information of the first hardware unit 13 .

[0060] In some examples, different hardware units may correspond to different registers 17, so as to more accurately manage the relevant information of the reset signal used to request to reset each hardware unit.

[0061] The first reset security module 161 corresponding to the first hardware unit 13 can read the status information of the reset signal for requesting to reset the first hardware unit 13 from the register 17 , and determine the status of the reset signal based on the status information, that is, determine whether to initiate a reset request for the first hardware unit 13 .

[0062] Step 42: Determine the working state of the interface between the first hardware unit and the bus based on the state of the reset signal.

[0063] The working state of the interface between the first hardware unit 13 and the bus 15 is used to indicate whether there is an access request for uncompleted transmission between the first hardware unit 13 and the second hardware unit 14 .

[0064] Exemplarily, the working state of the interface may include a second preset state and a third preset state. The second preset state indicates that there is an uncompleted transmission access request between the first hardware unit 13 and the second hardware unit 14, which may also be referred to as a non-idle state; the third preset state indicates that there is no uncompleted transmission access request between the first hardware unit 13 and the second hardware unit 14, which may also be referred to as an idle state.

[0065] It can be understood that when the first hardware unit 13 is reset, if the working state of the interface is the second preset state, that is, the working state of the interface is a non-idle state, it means that there are unfinished access requests between the first hardware unit 13 and the second hardware unit 14; the first hardware unit 13 may also continue to generate access requests to access the second hardware unit 14, and transmit the newly generated access requests to the bus 15. Based on this, the reset of the first hardware unit 13 will affect the bus 15, and then affect the second hardware unit 14; if the working state of the interface is the third preset state, that is, the working state of the interface is an idle state, it means that there are no unfinished access requests between the first hardware unit 13 and the second hardware unit 14, but the first hardware unit 13 may continue to generate access requests to access the second hardware unit 14, and transmit the newly generated access requests to the bus 15. Based on this, the reset of the first hardware unit 13 will also affect the bus 15 and the second hardware unit 14.

[0066] The first reset security module 161 may determine whether to initiate a reset request to the first hardware unit 13 based on the state of the reset signal.

[0067] Among them, if the state of the reset signal indicates that a reset request is initiated to the first hardware unit 13, in order to avoid the reset of the first hardware unit 13 affecting the bus 15 and the second hardware unit 14, the first reset security module 161 needs to determine the working state of the interface between the first hardware unit 13 and the bus 15, so as to facilitate the subsequent determination of the access requests that will affect the bus 15 and the second hardware unit 14 when the first hardware unit 13 is reset based on the working state of the interface, and thus perform corresponding processing on these access requests.

[0068] If the state of the reset signal indicates that a reset request is not initiated to the first hardware unit 13 , the first reset security module 161 may determine that there is no need to determine the working state of the interface, that is, it may determine that there is no need to process the access request between the first hardware unit 13 and the second hardware unit 14 .

[0069] Step 43: Based on the working status of the interface, determine an adjustment strategy for more than two data channels between the first hardware unit and the second hardware unit.

[0070] Based on the working state of the interface, the first reset security module 161 can determine the access requests that will affect the bus 15 and the second hardware unit 14 when the first hardware unit 13 is reset, and determine the flow control state that each data channel between the first hardware unit 13 and the second hardware unit 14 needs to be adjusted to based on these access requests. Further, the first reset security module 161 can determine the adjustment strategy corresponding to each data channel based on the flow control state that each data channel needs to be adjusted to. The adjustment strategy includes a method of adjusting the flow control state of the corresponding data channel to the flow control state that needs to be adjusted, and for example, the method can include adjusting the level state of the signal corresponding to the request type of the data channel transmission access request.

[0071] Step 44: Based on the adjustment strategy, adjust the flow control state of the data channel.

[0072] The first reset security module 161 adjusts the flow control state of the data channel based on the adjustment strategy. The first reset security module 161 can determine a target logical control unit group for adjusting the flow control state of the data channel based on the adjustment strategy, and adjust the flow control state of the corresponding data channel through the target logical control unit group.

[0073] After the first reset security module 161 adjusts the flow control state of the data channel, the access requests that have not been completed between the first hardware unit 13 and the second hardware unit 14 can be transmitted through the data channel after the flow control state is adjusted, while the access requests newly generated by the first hardware unit 13 will not be able to be transmitted to the bus 15 through the data channel after the flow control state is adjusted. This can achieve the effect of clearing the access requests that have not been completed between the first hardware unit 13 and the second hardware unit 14 before the first hardware unit 13 is reset, and intercepting the access requests newly generated by the first hardware unit 13.

[0074] Step 45: Reset the first hardware unit based on the working status of the interface.

[0075] After adjusting the flow control state of the data channel, the first reset security module 161 may determine the working state of the interface again.

[0076] If the working state of the interface is the third preset state, it means that the reset of the first hardware unit 13 will not affect the bus 15 and the second hardware unit 14, and the first reset security module 161 can reset the first hardware unit 13. For example, the first reset security module 161 can generate first indication information, and the first indication information is used to indicate that the reset request is successful, that is, the first hardware unit 13 can be reset. The first reset security module 161 can write the first indication information into the register 17, and can reset the first hardware unit 13 based on the first indication information.

[0077] If the working state of the interface is the second preset state, it means that the reset of the first hardware unit 13 will affect the bus 15 and the second hardware unit 14. The first hardware unit 13 cannot be reset at present. It is necessary to wait for the working state of the interface to change to the third preset state before resetting the first hardware unit 13.

[0078] In the method for resetting the hardware unit in the integrated circuit provided by the embodiment of the present disclosure, if the first reset security module 161 determines that the first hardware unit 13 in the first operating system 11 needs to be reset, before resetting the first hardware unit 13, based on the working state of the interface between the first hardware unit 13 and the bus 15, by adjusting the flow control state of the data channel between the first hardware unit 13 and the second hardware unit 14, the access request of the uncompleted transmission between the first hardware unit 13 and the second hardware unit 14 can be completed, and the access request newly generated by the first hardware unit 13 can be intercepted and transmitted to the bus 15. Therefore, when the first hardware unit 13 is reset, the bus 15 can still work normally, and the second hardware unit 14 sharing the bus 15 can still work normally. Therefore, the second operating system 12 running through the second hardware unit 14 can still run normally, which greatly improves the operating stability of the second operating system 12.

[0079] Figure 5 It is a flowchart of a method for resetting a hardware unit in an integrated circuit provided by another exemplary embodiment of the present disclosure.

[0080] In some embodiments, Figure 5 As shown in the above Figure 4 Based on the illustrated embodiment, the above step 42 may include steps 421 and 422.

[0081] Step 421 : In response to the state of the reset signal being a first preset state, determine the number of first access requests.

[0082] In response to the reset signal being in the first preset state, the first reset security module 161 may determine to initiate a reset request to the first hardware unit 13, i.e., to reset the first hardware unit 13. Based on this, the first reset security module 161 determines the working state of the interface between the first hardware unit 13 and the bus 15 before resetting the first hardware unit 13.

[0083] Based on the working state of the interface used to indicate whether there are uncompleted access requests between the first hardware unit 13 and the second hardware unit 14, the first reset security module 161 determines the number of first access requests, wherein the first access request is the uncompleted access request among the access requests of the first hardware unit 13 requesting to access the second hardware unit 14.

[0084] Step 422: Determine the working status of the interface based on the number of first access requests.

[0085] If the number of first access requests is 0, it means that there is no access request that has not been transmitted, so the first reset security module 161 can determine that the working state of the interface is the third preset state, that is, the idle state.

[0086] If the number of first access requests is greater than 0, it indicates that there are access requests that have not been transmitted, so the first reset security module 161 may determine that the working state of the interface is the second preset state, ie, the non-idle state.

[0087] According to the method for resetting a hardware unit in an integrated circuit provided by the embodiment of the present disclosure, after determining that the first hardware unit 13 needs to be reset, the first reset security module 161 can accurately determine the working state of the interface between the first hardware unit 13 and the bus 15 based on the number of first access requests that have not been completed transmitted between the first hardware unit 13 and the second hardware unit 14, thereby ensuring the accuracy of the adjustment strategy of the data channel determined based on the working state of the interface.

[0088] Figure 6 It is a flowchart of a method for resetting a hardware unit in an integrated circuit provided by another exemplary embodiment of the present disclosure.

[0089] In some embodiments, Figure 6 As shown in the above Figure 5 Based on the illustrated embodiment, the above step 422 may include steps 4221 to 4223.

[0090] Step 4221: Determine the request type in the first access request.

[0091] The request type of the first access request may include a read command request, a write command request, and a write data request.

[0092] Step 4222: Determine the number of requests corresponding to the request type in the first access request.

[0093] Combination Figure 2 and Figure 3 The number of read command requests can be counted by the first counter 211, the number of write command requests can be counted by the second counter 212, and the number of write data requests can be counted by the third counter 213.

[0094] Exemplarily, the first counter 211 increases the count by 1 each time it detects a read command request transmitted by the first hardware unit 13 through the read command channel 221, and decreases the count by 1 each time it detects a valid RLAST signal transmitted by the second hardware unit 14 through the read data channel 231. The first reset security module 161 may read the count of the first counter 211 and determine the count as the request number of the read command request in the first access request.

[0095] Exemplarily, the second counter 212 increases the count by 1 each time it detects a write command request transmitted by the first hardware unit 13 through the write command channel 241, and decreases the count by 1 each time it detects a write response transmitted by the second hardware unit 14 through the write response channel 251. The first reset security module 161 may read the count of the second counter 212 and determine the count as the request number of the write command request in the first access request.

[0096] Exemplarily, the third counter 213 increases the count by 1 each time it detects a WLAST signal in a write data request transmitted by the first hardware unit 13 through the write data channel 261, and decreases the count by 1 each time it detects a write response transmitted by the second hardware unit 14 through the write response channel 251. The first reset security module 161 may read the count of the third counter 213 and determine the count as the request number of the write data request in the first access request.

[0097] Step 4223: Based on the number of requests, determine the working status of the interface.

[0098] Among them, if the request number of the read command request is greater than 0, the first reset security module 161 can determine that the data channel corresponding to the read operation is in a non-idle state; if the request number of the read command request is equal to 0, the first reset security module 161 can determine that the data channel corresponding to the read operation is in an idle state.

[0099] If the request number of at least one request type among the request number of write command requests and the request number of write data requests is greater than 0, the first reset security module 161 can determine that the data channel corresponding to the write operation is in a non-idle state; if the request number of write command requests and the request number of write data requests are both equal to 0, and the third counter 213 determines that the detected WVAL ID signal transmitted by the first hardware unit 13 through the write data channel 261 corresponds to the last write data request, or, the request number of write command requests and the request number of write data requests are both equal to 0, and the third counter 213 has not detected the WVALID signal transmitted by the first hardware unit 13 through the write data channel 261, the first reset security module 161 can determine that the data channel corresponding to the write operation is in an idle state.

[0100] The first reset security module 161 determines the working state of the interface based on the state of the data channel corresponding to the read operation and the state of the data channel corresponding to the write operation. If at least one of the state of the data channel corresponding to the read operation and the state of the data channel corresponding to the write operation is a non-idle state, the first reset security module 161 can determine that the working state of the interface is a second preset state, i.e., a non-idle state; if both the state of the data channel corresponding to the read operation and the state of the data channel corresponding to the write operation are idle states, the first reset security module 161 can determine that the working state of the interface is a third preset state, i.e., an idle state.

[0101] In the method for resetting a hardware unit in an integrated circuit provided by the embodiment of the present disclosure, after determining that the first hardware unit 13 needs to be reset, the first reset security module 161 can classify and monitor first access requests of different request types, so that after determining that there is a first access request, the request type corresponding to the first access request can be quickly determined. Since the request type is associated with the data channel, the efficiency of determining the adjustment strategy of the data channel can be improved.

[0102] Figure 7 It is a flowchart of a method for resetting a hardware unit in an integrated circuit provided by yet another exemplary embodiment of the present disclosure.

[0103] In some embodiments, Figure 7 As shown in the above Figure 4 Based on the illustrated embodiment, the above step 43 may include steps 431 and 432.

[0104] Step 431: Determine a first data channel and a second data channel from more than two data channels based on the working state of the interface.

[0105] The flow control state of the first data channel that needs to be adjusted is blocking, and the flow control state of the second data channel that needs to be adjusted is releasing.

[0106] In some examples, if the working state of the interface is the second preset state, i.e., the non-idle state, the first reset security module 161 determines the operation type corresponding to the first access request. The operation type corresponding to the first access request may include a read operation and a write operation, wherein the read command request in the first access request corresponds to the read operation, and the write command request and the write data request in the first access request correspond to the write operation.

[0107] The first reset security module 161 determines a first data channel and a second data channel from at least two data channels between the first hardware unit 13 and the second hardware unit 14 based on the operation type corresponding to the first access request.

[0108] If the operation type corresponding to the first access request is a read operation, the first reset security module 161 may determine that the first data channel includes a read command channel 221 , and the second data channel includes a read data channel 231 .

[0109] If the operation type corresponding to the first access request is a write operation, the first reset security module 161 can determine the size relationship between the number of write command requests and the number of write data requests in the first access request. Exemplarily, the first reset security module 161 can read the current count from the second counter 212, which is the number of write command requests, and the first reset security module 161 can read the current count from the third counter 213, which is the number of write data requests. The first reset security module 161 compares the above two counts to determine the size relationship between the two counts, which is the size relationship between the number of write command requests and the number of write data requests. Based on the size relationship, the first reset security module 161 can determine the first data channel and the second data channel.

[0110] Exemplarily, if the size relationship is that the number of write data requests is greater than or equal to the number of write command requests, and the third counter 213 determines that a valid WVALID signal and a valid WLAST signal transmitted by the first hardware unit 13 through the write data channel 261 are detected, the first reset security module 161 can determine that the first data channel includes the write data channel 261, and the second data channel includes the write command channel 241.

[0111] Alternatively, if the size relationship is that the number of write data requests is equal to the number of write command requests, and the third counter 213 has not detected the WVALID signal transmitted by the first hardware unit 13 through the write data channel 261, the first reset security module 161 can determine that the first data channel includes the write data channel 261, and the second data channel includes the write command channel 241.

[0112] Exemplarily, if the size relationship is that the number of write command requests is greater than or equal to the number of write data requests, the first reset security module 161 may determine that the first data channel includes a write command channel 241 , and the second data channel includes a write data channel 261 and a write response channel 251 .

[0113] In some examples, if the working state of the interface is a third preset state, i.e., an idle state, the first reset security module 161 may determine all of the two or more data channels between the first hardware unit 13 and the second hardware unit 14 as first data channels, i.e., adjust the flow control state of all data channels to blocking to intercept the newly generated access request of the first hardware unit 13 from being transmitted to the bus 15.

[0114] Step 432: Determine adjustment strategies corresponding to the first data channel and the second data channel respectively.

[0115] The first reset security module 161 determines an adjustment strategy corresponding to the first data channel, where the adjustment strategy is used to adjust the flow control state of the first data channel to blocking.

[0116] Exemplarily, if the first data channel includes a read command channel, the first reset security module 161 can determine that the adjustment strategy corresponding to the read command channel 221 is to adjust the ARVALID signal transmitted in the read command channel 221 to a low level state and adjust the ARREADY signal transmitted in the read command channel 221 to a high level state.

[0117] Exemplarily, if the first data channel includes a write command channel 241, the first reset security module 161 may determine that the adjustment strategy corresponding to the write command channel 241 is to adjust the AWVALID signal transmitted in the write command channel 241 to a low level state and to adjust the AWREADY signal transmitted in the write command channel 241 to a high level state.

[0118] Exemplarily, if the first data channel includes the write data channel 261, the first reset security module 161 can determine that the adjustment strategy corresponding to the write data channel 261 is to adjust the WVALID signal transmitted in the write data channel 261 to a low level state and adjust the WREADY signal transmitted in the write data channel 261 to a high level state.

[0119] The first reset security module 161 determines an adjustment strategy corresponding to the second data channel, where the adjustment strategy is used to adjust the flow control state of the second data channel to release.

[0120] Exemplarily, if the second data channel includes the read data channel 231 , the first reset security module 161 may determine that the adjustment strategy corresponding to the read data channel 231 is to adjust the RREADY signal transmitted in the read data channel 231 to a high level state.

[0121] Exemplarily, if the second data channel includes the write response channel 251 , the first reset security module 161 may determine that the adjustment strategy corresponding to the write response channel 251 is to adjust the BREADY signal transmitted in the write response channel 251 to a high level state.

[0122] In some examples, when the state of the reset request is the fourth preset state, that is, when the reset request is not initiated to the first hardware unit 13, that is, when the first hardware unit 13 and the second hardware unit 14 can be accessed normally, the flow control states of the write command channel 241 and the write data channel 261 are both released. Based on this, if the first reset security module 161 determines that the second data channel includes the write command channel 241 and / or the write data channel 261, it can be determined that the adjustment strategy corresponding to the two is to maintain the original level state of the signal transmitted on each data channel.

[0123] In some examples, the first reset security module 161 may adjust the level state of the signal transmitted in the corresponding data channel through a logic control unit group corresponding to the adjustment strategy.

[0124] The method for resetting the hardware unit in the integrated circuit provided by the embodiment of the present disclosure can accurately determine the flow control state that each data channel needs to be adjusted to based on the first access request, and accurately determine the adjustment strategy corresponding to each data channel based on the flow control state that each data channel needs to be adjusted to. After adjusting the flow control state of each data channel based on the adjustment strategy, the access request of the uncompleted transmission can be effectively cleared, and the access request newly generated by the first hardware unit 13 can be intercepted.

[0125] Figure 8 It is a flowchart of a method for resetting a hardware unit in an integrated circuit provided by yet another exemplary embodiment of the present disclosure.

[0126] In some embodiments, Figure 8 As shown in the above Figure 4 Based on the illustrated embodiment, the above step 45 may include steps 451 to 453.

[0127] Step 451: Read the first duration from the register.

[0128] If the first reset security module 161 determines that the first hardware unit 13 needs to be reset, the request status of the reset request for the first hardware unit 13 can be determined by the timeout counting module 27. If the request status is a successful request, it can be determined that the first hardware unit 13 is actually reset, and if the request status is a failed request, it can be determined that the first hardware unit 13 is not reset.

[0129] The timeout counting module 27 can read a first duration from the register 17 when the state of the reset signal is the fourth preset state, and the first duration is a duration threshold for monitoring timeout. In some examples, the timeout counting module 27 can control the QDENY signal to be adjusted to a low level state to indicate that a reset request is not currently initiated for the first hardware unit 13.

[0130] Step 452: Determine a matching relationship between the working state of the interface and a third preset state within the first time period.

[0131] The timeout counting module 27 can start timing from the presence of the first access request, or start timing from the time when the data channel corresponding to the write operation and the data channel corresponding to the read operation are both in a non-idle state, and monitor whether the working state of the interface is a third preset state within the first time period, that is, monitor whether the adjustment strategy is effective, that is, monitor whether the transmission of each first access request has been completed after adjusting the flow control state of the data channel, and whether all new access requests generated by the first hardware unit 13 have been intercepted.

[0132] Step 453: reset the first hardware unit based on the matching relationship.

[0133] If the working state of the interface matches the matching relationship of the third preset state within the first time period, it means that the adjustment strategy is effective, and the reset of the first hardware unit 13 will not affect the bus 15 and the second hardware unit 14, and the first hardware unit 13 can be reset. Accordingly, the timeout counting module 27 can determine that the request status of the reset request is successful, and can generate indication information that the request status is successful, and the first reset security module 161 can reset the first hardware unit 13 based on the indication information.

[0134] If the matching relationship between the working state of the interface and the third preset state does not match within the first time period, it means that the adjustment strategy is invalid, and the reset of the first hardware unit 13 will still affect the bus 15 and the second hardware unit 14, and the first hardware unit 13 cannot be reset. Accordingly, the timeout counting module 27 can determine that the request state is failed, and can generate indication information that the request state is failed, and the first reset safety module 161 can not reset the first hardware unit 13 based on the indication information.

[0135] The method for resetting the hardware unit in the integrated circuit provided in the embodiment of the present disclosure can use timeout monitoring to promptly terminate the resetting of the first hardware unit 13 when it is monitored that the working state of the interface has not been adjusted to the idle state within the specified time period, thereby ensuring that the bus 15 can still work normally, and the second hardware unit 14 sharing the bus 15 can also still work normally.

[0136] Fig. 9 It is a flowchart of a method for resetting a hardware unit in an integrated circuit provided by yet another exemplary embodiment of the present disclosure.

[0137] In some embodiments, Fig. 9 As shown in the above Figure 8Based on the illustrated embodiment, the above step 453 may include step 4531 - step 4532.

[0138] Step 4531: Based on the matching relationship indicating that the working state of the interface matches the third preset state, the logical state of the interface is processed into a preset logical state.

[0139] The matching relationship indicates that the working state of the interface matches the third preset state, and it can be determined that the adjustment strategy is effective. When the third hardware unit 13 is reset, there will be no abnormality in the bus 15 and the second hardware unit 14 due to the access request that has not been completed. However, when the first hardware unit 13 is reset, it will generate some unstable signals. If these unstable signals are transmitted to the bus 15, they will affect the bus 15 and the second hardware unit 14.

[0140] In order to solve this problem, the first reset security module 161 can isolate the first hardware unit 13 and the bus 15 through the isolation control unit 31. Among them, the isolation control unit 31 processes the logic state of the interface between the first hardware unit 13 and the bus 15 into a preset logic state. The preset logic state is a fixed 0 or 1, so that the first hardware unit 13 will transmit a signal to the bus 15 according to the preset logic state, that is, the first hardware unit 13 will output a fixed 0 or 1, that is, a stable signal, to the bus 15. Since the stable signal output by the first hardware unit 13 will not affect the bus 15, it is equivalent to isolating the first hardware unit 13 from the bus 15.

[0141] Step 4532: reset the first hardware unit.

[0142] After the first reset security module 161 isolates the first hardware unit 13 , even if the first hardware unit 13 is reset, the first hardware unit 13 will transmit a stable signal to the bus 15 according to a preset logic state without affecting the bus 15 and the second hardware unit 14 .

[0143] The method for resetting the hardware unit in the integrated circuit provided by the embodiment of the present disclosure can be performed by setting the logic state of the interface between the first hardware unit 13 and the bus 15 to a preset logic state, so that the first hardware unit 13 can output a stable signal to the bus 15 according to the preset logic state when resetting, and the stable signal will not affect the bus 15. Therefore, when the first hardware unit 13 is reset, the bus 15 can still work normally, and the second hardware unit 14 sharing the bus 15 can still work normally. Therefore, the second operating system 12 running through the second hardware unit 14 can still run normally, which greatly improves the operating stability of the second operating system 12.

[0144] Exemplary Electronic Devices

[0145] Fig.10 1 is a schematic diagram of a structure of an electronic device provided by an exemplary embodiment of the present disclosure. The electronic device includes an integrated circuit 101, which may be Figure 1 , Figure 2 and Figure 3 The integrated circuit 101 includes at least one processor 1011 and a memory 1012.

[0146] The processor 1011 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

[0147] The memory 1012 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1011 may execute one or more computer program instructions to implement the method for resetting the hardware unit in the integrated circuit and / or other desired functions of the various embodiments of the present disclosure described above.

[0148] In one example, the electronic device may further include: an input device 102 and an output device 103 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0149] Of course, to simplify, Fig.10 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0150] Exemplary computer program products and computer-readable storage media

[0151] In addition to the above-mentioned methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the method for resetting a hardware unit in an integrated circuit in various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.

[0152] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0153] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, causes the processor to execute the steps of the method for resetting a hardware unit in an integrated circuit in various embodiments of the present disclosure described in the above “Exemplary Method” section.

[0154] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or device including electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0155] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and cannot be considered as necessary for each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, rather than limitation, and the above details do not limit the present disclosure to being implemented by adopting the above specific details.

[0156] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A method for resetting a hardware unit in an integrated circuit, the method comprising: Reading a state of a reset signal from a register, wherein the reset signal is used to request resetting a first hardware unit, the first hardware unit corresponding to a first operating system; determining a working state of an interface between the first hardware unit and a bus based on a state of the reset signal; Determining, based on the working state of the interface, an adjustment strategy for two or more data channels between the first hardware unit and a second hardware unit, wherein the second hardware unit corresponds to a second operating system; Based on the adjustment strategy, adjusting the flow control state of the data channel; The first hardware unit is reset based on the working status of the interface.

2. The method for resetting a hardware unit in an integrated circuit according to claim 1, wherein: The determining, based on the state of the reset signal, the working state of the interface between the first hardware unit and the bus comprises: In response to the state of the reset signal being a first preset state, determining the number of first access requests, wherein the first access request is an access request of the first hardware unit requesting access to the second hardware unit that has not been completely transmitted; Based on the number of the first access requests, an operating state of the interface is determined.

3. The method for resetting a hardware unit in an integrated circuit according to claim 2, wherein: The determining the working state of the interface based on the number of the first access requests includes: determining a request type in the first access request; Determine the number of requests corresponding to the request type in the first access request; Based on the number of requests, an operating status of the interface is determined.

4. The method for resetting a hardware unit in an integrated circuit according to any one of claims 1 to 3, wherein: The step of determining, based on the working state of the interface, an adjustment strategy for two or more data channels between the first hardware unit and the second hardware unit includes: Based on the working state of the interface, determining a first data channel and a second data channel from the two or more data channels; The adjustment strategies corresponding to the first data channel and the second data channel are determined respectively.

5. The method for resetting a hardware unit in an integrated circuit according to claim 4, wherein: The determining the first data channel and the second data channel from the two or more data channels based on the working state of the interface includes: In response to the working state of the interface being a second preset state, determining an operation type corresponding to the first access request; Based on the operation type, the first data channel and the second data channel are determined from more than two data channels.

6. The method for resetting a hardware unit in an integrated circuit according to claim 5, wherein: The determining the first data channel and the second data channel from two or more data channels based on the operation type includes: In response to the operation type being a write operation type, determining a magnitude relationship between the number of write command requests and the number of write data requests in the first access request; Based on the size relationship, the first data channel and the second data channel are determined from more than two data channels.

7. The method for resetting a hardware unit in an integrated circuit according to claim 4, wherein: The determining the first data channel and the second data channel from the two or more data channels based on the working state of the interface includes: In response to the working state of the interface being a third preset state, all of the more than two data channels are determined as the first data channels.

8. The method for resetting a hardware unit in an integrated circuit according to any one of claims 1 to 3, resetting the first hardware unit based on the working state of the interface, comprising: Reading a first duration from the register; Determining a matching relationship between the working state of the interface and a third preset state within the first time period; Based on the matching relationship, the first hardware unit is reset.

9. The method for resetting a hardware unit in an integrated circuit according to claim 8, wherein: The resetting the first hardware unit based on the matching relationship includes: Based on the matching relationship indicating that the working state of the interface matches the third preset state, processing the logical state of the interface into a preset logical state; Reset the first hardware unit.

10. An integrated circuit comprising: A first hardware unit, corresponding to the first operating system; A second hardware unit corresponding to a second operating system; Reset the security module, corresponding to the first hardware unit; a register storing a state of a reset signal, wherein the reset signal is used to request resetting the first hardware unit; The reset security module is used to read the state of the reset signal from the register; The reset security module is further used to determine the working state of the interface between the first hardware unit and the bus based on the state of the reset signal; The reset security module is further used to determine, based on the working state of the interface, an adjustment strategy for two or more data channels between the first hardware unit and the second hardware unit; The reset security module is further used to adjust the flow control state of the data channel based on the adjustment strategy; The reset security module is further configured to reset the first hardware unit based on the working state of the interface.

11. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the method for resetting a hardware unit in an integrated circuit according to any one of claims 1 to 9.

12. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is configured to read the executable instruction from the memory and execute the instruction to implement the method for resetting a hardware unit in an integrated circuit according to any one of claims 1 to 9; Alternatively, the electronic device comprises the integrated circuit as claimed in claim 10.

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