State recognition method and device, electronic equipment and storage medium
By using memory blocks and detectors in the first chip, combined with DMA technology, identifying the input signal status sent by the second chip, the problem of excessive CPU load in the prior art is solved, and the input signal status recognition under a slight load is realized .
Patent Information
- Application Number
- CN202411376701.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-02-14
AI Technical Summary
In the prior art, chip A monitors the system status information of chip B through interruption, resulting in excessive CPU load, especially when the input signal frequency is high, resulting in significant pressure and delay.
By using the first memory block in the first chip to determine the state of the input signal, detect the edge changes of the input signal using the detector and the accessor, and transfer the detected point-in-time data to the memory block through DMA, avoiding the CPU An interrupt is generated for changes in the edge of the IO port, which only brings a slight load on the CPU.
It realizes accurate identification of the status of the input signal without increasing the CPU load, reducing the pressure and delay of the system.
Smart Images
Figure CN119441087A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of computer technology, and in particular to a state recognition method, device, electronic device, and computer-readable storage medium. Background Art
[0002] Currently, there are application scenarios where two chips frequently interact with each other. For example, chip A needs to interact with chip B and monitor the system status information of chip B.
[0003] In the related art, chip A generally has a monitoring program that uses an interrupt method to capture the input signal from chip B (reflecting the system status information of chip B) and obtain the edge trigger of the input signal, but this will cause a load burden on the processor (CPU, Central Processing Unit) of chip A.
[0004] Generally, the higher the frequency of the input signal, the greater the chip load. For example, when the input signal exceeds 400KHz, it consumes more than 50% of the CPU load rate for most chips. When the input signal exceeds 800KHz, the CPU load rate reaches 100% for most chips. This will inevitably affect other programs in chip A to handle other tasks, causing obvious pressure and delay. Summary of the invention
[0005] The present disclosure provides a state recognition method, device, electronic device and storage medium to at least solve the above technical problems existing in the prior art.
[0006] In a first aspect, an embodiment of the present disclosure provides a state identification method, the method is applied to a first chip, the first chip includes: a first memory block, the method includes:
[0007] Determine first information of the first memory block, where the first information is at least used to indicate whether storage data in the first memory block changes;
[0008] Second information of the second chip is determined according to the first information, where the second information is used to indicate a state of an input signal sent by the second chip to the first chip.
[0009] In a second aspect, an embodiment of the present disclosure provides a state recognition device, the device comprising a first chip and a second chip, the first chip comprising: a first memory block;
[0010] The first chip is used to determine first information of the first memory block, where the first information is at least used to indicate whether the storage data in the first memory block has changed;
[0011] Second information of the second chip is determined according to the first information, where the second information is used to indicate a state of an input signal sent by the second chip to the first chip.
[0012] In a third aspect, an embodiment of the present disclosure provides an electronic device, including:
[0013] at least one processor; and
[0014] a memory communicatively connected to the at least one processor; wherein,
[0015] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the state identification method.
[0016] In a fourth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the state identification method.
[0017] The disclosed embodiments provide a state identification method, device, electronic device, and storage medium, which are applied to a first chip, wherein the first chip includes: a first memory block, and the method includes: determining first information of the first memory block, wherein the first information is at least used to indicate whether the stored data in the first memory block has changed; and determining second information of a second chip based on the first information, wherein the second information is used to indicate the state of an input signal sent by the second chip to the first chip. In this way, the state identification of the input signal is realized based on the change of the stored data, and only a slight load is brought.
[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 A flow chart of a state identification method provided by an embodiment of the present disclosure;
[0020] Figure 2 A connection diagram of an electronic device provided by an embodiment of the present disclosure;
[0021] Figure 3 A schematic diagram of the structure of a first chip provided in an embodiment of the present disclosure;
[0022] Figure 4 A flow chart of a state identification method provided for an application embodiment of the present disclosure;
[0023] Figure 5A schematic diagram of connecting a first chip and a second chip provided in an embodiment of the present disclosure;
[0024] Figure 6 A schematic diagram of another connection between a first chip and a second chip provided in an embodiment of the present disclosure;
[0025] Figure 7 A schematic diagram of a structure of a combination of two sets of detectors and a memory block provided in an embodiment of the present disclosure;
[0026] Figure 8 A schematic diagram of the structure of a state recognition device provided by an embodiment of the present disclosure;
[0027] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0028] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.
[0029] Before further describing the embodiments of the present disclosure in detail, the related technologies involved in the embodiments of the present disclosure are described.
[0030] Due to functional requirements, there is a situation where the state of an input signal of a certain input / output (IO) port of a chip needs to be detected.
[0031] In the related technology, the chip can use an interrupt method to identify the input status. Specifically, whenever an edge change occurs in the IO, the CPU generates an interrupt, and records the interrupt timestamp and trigger mode (the trigger mode is a rising edge trigger or a falling edge trigger) in the interrupt function to calculate the frequency of the input signal, etc.
[0032] However, the above interruption method will inevitably cause a significant CPU load burden. For example, the CPU main frequency of the MCU chip is generally within 600MHz, and each time the CPU responds to an interrupt, it will take about 1us; at the same time, the program in the chip is a multi-tasking program that will handle many tasks at the same time. When the frequency of the IO port input is very high, such as when the external input signal exceeds 100KHz square wave, it will bring a significant increase in the CPU load rate of the program in the MCU chip; when the external input signal exceeds 400KHz, it will bring significant pressure and delay to the program in the MCU chip when processing other tasks; when the external input signal exceeds 800KHz, the MCU chip with a main frequency of 600MHZ can basically not handle other tasks. This will inevitably lead to operational problems of the device to which the chip belongs.
[0033] Based on this, the embodiment of the present disclosure provides a state identification method, which is applied to a first chip, the first chip includes: a first memory block, the method includes: determining first information of the first memory block, the first information is at least used to indicate whether the storage data in the first memory block has changed; according to the first information, determining second information of the second chip, the second information is used to indicate the state of the input signal sent by the second chip to the first chip. In this way, only a slight load is brought to the CPU, and the state identification of the input signal can be realized according to the change of the storage data.
[0034] Figure 1 A flow chart of a state identification method provided by an embodiment of the present disclosure; Figure 1 As shown, the state identification method is applied to a first chip, the first chip includes: a first memory block, and the method includes:
[0035] Step 101: determine first information of the first memory block, where the first information is at least used to indicate whether storage data in the first memory block has changed;
[0036] Step 102: Determine second information of a second chip according to the first information, where the second information is used to indicate a state of an input signal sent by the second chip to the first chip.
[0037] In some embodiments, the first chip further comprises: a detector and an accessor; the first chip receives an input signal sent by the second chip through a first interface;
[0038] The method further comprises:
[0039] The detector detects whether an edge change occurs in the input signal received through the first interface within a first period;
[0040] When it is determined that the input signal has an edge change, a first time is recorded and a first instruction is sent to the access device; the first time is the time when the input signal has an edge change;
[0041] The accessor moves the first time to the first memory block based on the first instruction.
[0042] Here, the first chip has a first interface, and the first chip communicates with the second chip through the first interface. The first interface may be an IO port. For example, the first chip receives an input signal sent by the second chip through the first interface.
[0043] Here, the edge change includes: rising edge triggering and falling edge triggering;
[0044] If the detector determines that an edge change occurs in the input signal, the first time (ie, the time when the edge change occurs in the input signal) is recorded, and a first instruction is sent to the access device. The access device moves the first time to the first memory block based on the first instruction.
[0045] In some embodiments, the detector is a device for capturing signals, for example, the detector is an event timer (etimer), which can detect events (here, signal edge change events) and event occurrence time (such as the first time).
[0046] The detector may include a Capture count register for recording a time point of edge change.
[0047] The detector may also communicate with the access device, such as sending a first instruction to trigger the access device to move the time point data (such as the first time) recorded by the Capture count register to the first memory block.
[0048] The access device is a direct memory access (DMA), which can manage the process of direct memory access and can move data from one place to another without the intervention of the processor.
[0049] Here, DMA is used to transfer the edge change of the input signal detected by the detector to the first memory block at the first time. In this way, the above function is realized by DMA in the first chip, and there is no need for the processor of the first chip (such as CPU core) to generate an interrupt for the edge change of the IO port. That is, through the method provided by the embodiment of the present disclosure, only a slight load is brought to the CPU (the load here refers to the load caused by the periodic processing of the timer), and the input signal detection can be realized.
[0050] In some embodiments, determining the first information of the first memory block includes:
[0051] Determine a change in the stored data in the first memory block within a first cycle;
[0052] If the change amount is 0, it is determined that the input signal has not changed;
[0053] If the change amount is greater than 0, it is determined that the input signal has changed.
[0054] Here, the first chip may also include: a processor, a timer, or a functional module for executing tasks.
[0055] The following explanation takes a processor as an example. The processor can access the first memory block and determine the change in the stored data in the first memory block within the first cycle (the change can be determined based on the amount of data moved by the accessor in the first memory block), and determine whether an edge change occurs in the input signal based on the change.
[0056] Specifically, the state of the input signal may include: whether the input signal has an edge change, such as whether it changes from a high level to a low level, or from a low level to a high level.
[0057] If the change amount is 0, it is determined that the input signal is in the first state, that is, no change occurs;
[0058] If the change amount is greater than 0, it is determined that the input signal is in the second type of state, that is, a change occurs.
[0059] In some embodiments, the first chip further includes: a second interface, a second interface module;
[0060] If it is determined that the input signal has not changed, the method further includes:
[0061] Switching the first input mode to the second input mode, wherein the first input mode is that the first chip receives the input signal sent by the second chip through the first interface, and the second input mode is that the first chip receives the input signal sent by the second chip through the second interface;
[0062] Using the second interface module, a frequency of an input signal received through the second interface is determined.
[0063] Specifically, the first interface is an IO interface;
[0064] The second interface may be a general-purpose input / output (GPIO) interface;
[0065] The second interface module may be a submodule in a processor, a timer or a functional module for executing a task. The second interface module may also be called a GPIO module, which is used to detect an input signal received by a GPIO interface.
[0066] The first input mode is that the first chip receives an input signal sent by the second chip through a first interface (IO interface);
[0067] The second input mode is that the first chip receives the input signal sent by the second chip through the second interface (GPIO interface).
[0068] If it is determined that the input signal has not changed (i.e., there is no external edge change from the previous cycle to the current cycle), the processor can switch the IO input mode of the first chip to the GPIO input mode. In this way, the GPIO module can be used to determine whether the input signal sent externally is a high level or a low level, that is, the input signal received by the current IO interface can be obtained as a high level or a low level.
[0069] Here, considering that if there is no edge trigger for a long time, it is impossible to determine whether the level state of the input signal is a high level or a low level by using the detector and the accessor, therefore, the second interface module (i.e., the GPIO module) is used to detect the level state of the input signal received through the second interface. Here, the second interface module can directly read the level state of the input signal of the second interface, that is, determine whether it is a high level or a low level.
[0070] It should be noted that the first interface and the second interface can be the same interface in hardware. When a detector is used to detect the input signal, the interface is the first interface (IO port); when a GPIO module is used to detect the input signal, the interface is the second interface (GPIO port).
[0071] The switching between the first input mode and the second input mode can be achieved by configuring the pins of the interface. If the pins of the interface multiplex the function of the detector, the interface serves as the first interface; if the pins of the interface multiplex the function of the GPIO module, the interface serves as the second interface.
[0072] Of course, the first interface and the second interface may also be different hardware interfaces, and switching the IO input mode of the first chip to the GPIO input mode may be switching from receiving input signals through the IO port to receiving input signals through the GPIO port. This is not limited here.
[0073] Through the above method, the frequency of the input signal can be detected first to determine whether the frequency is too high. If it is determined that the edge has not changed within a long period of time (such as two cycles, three cycles or other long periods of time), it can be considered that the frequency is not high. In this way, the GPIO module is used to detect the high level or low level of the input signal, which can realize the detection of high and low levels without generating excessive CPU load.
[0074] In some embodiments, after determining the level state of the input signal by using the second interface module, the method may further include:
[0075] Switch the second input mode to the first input mode.
[0076] Here, considering that the level state of the input signal is known to be high level or low level, even if the first input mode is continued to be used subsequently, the detector can detect whether an edge change occurs to determine whether it is a high level or a low level after each change.
[0077] In some embodiments, if it is determined that the input signal has changed, the method further includes:
[0078] determining at least two first times within a second cycle stored in the first memory block;
[0079] If the variation is greater than or equal to a first threshold, determining the frequency of the input signal according to the at least two first times;
[0080] If the variation is smaller than the first threshold, the frequency of the input signal is determined according to at least two first times in a next second period.
[0081] Here, the at least two first times may include: first time 1, first time 2, and first time 3.
[0082] Here, the working clock determines the accuracy of time measurement, and the high-frequency clock can provide a more accurate time point. When applied, according to the first time 1, the first time 2 and the first time 3, and the working clock of the detector, the actual time 1 (the time determined based on the first time 1), time 2 (the time determined based on the first time 2), and time 3 (the time determined based on the first time 3) can be known.
[0083] The first time 1 and the first time 3 should be the same edge change (rising edge change or falling edge change), and the edge change of the first time 2 is different. Therefore, the period of the input signal is: time 1-time 3. The frequency of the input signal is: 1 / (time 1-time 3).
[0084] Here, the second period and the first period may be the same or different, and the specific value is set based on actual needs, and there is no limitation on the setting of the period length.
[0085] Here, the first threshold value can be set based on the number of bytes of the time data. For example, if the size of the first time data to be transported is N bytes, and it is necessary to capture three edge changes to calculate a complete period of a square wave, the first threshold value can be set to 3*N bytes. Assuming that N is 4, the first threshold value can be set to 3*4 bytes.
[0086] The first threshold can also be determined in combination with the edge capture requirements. For example, the size of the data at the first time of transportation is N bytes, and the first threshold is M*N; if it is double-edge capture, the first threshold can be 3*N bytes; if it is single-edge capture (rising edge or falling edge), the first threshold is 2*N bytes.
[0087] In an example, in the case of double-edge capture (assuming N is 4), the amount of data acquired in one cycle can be as follows:
[0088] The first case: the amount of data (i.e., the amount of change) is greater than or equal to 3*4, then the frequency of the input signal can be directly calculated based on the data obtained in this cycle;
[0089] The second case: data volume = 0*4, it is considered that there is no edge change in the input signal from the previous cycle to the current cycle, and it remains at a high level or a low level. Then, the input signal of this cycle can be directly determined to be a high level or a low level based on the high level or the low level determined in the previous cycle;
[0090] The third case: the data volume is between 0 and 12. Since the complete square wave cycle of the input signal is not captured, it is necessary to continue to obtain data in the next cycle to calculate the frequency of the input signal (satisfying the data volume>=3*4).
[0091] The above description is for the case of setting double-edge capture, that is, the case where both the rising edge and the falling edge of the input signal trigger the detector.
[0092] In another example, in the case of single edge capture (rising edge capture or falling edge capture), the amount of data acquired in one cycle has the following three cases:
[0093] Case 1: If the data volume is greater than or equal to 2*4, the frequency of the input signal can be directly calculated based on the data obtained in this cycle;
[0094] The second case: data volume = 0*4, it is considered that there is no edge change in the input signal from the previous cycle to the current cycle, and it remains at a high level or a low level. Then, the input signal of this cycle can be directly determined to be a high level or a low level based on the high level or the low level determined in the previous cycle;
[0095] The third case: the data volume is between 0 and 8. Since the complete square wave cycle of the input signal is not captured, it is necessary to continue to obtain data in the next cycle to calculate the frequency of the input signal (satisfying the data volume>=2*4).
[0096] In some embodiments, the method further comprises:
[0097] The first time stored in the first memory block is stored in the second memory block in chronological order; the first memory block is a memory block of a circular covering type;
[0098] Correspondingly, determining the first information of the first memory block includes: determining a change amount of data stored in the second memory block within a first cycle.
[0099] Here, the first chip may also include: a second memory block, which is used to sort the data of the first memory block according to the time sequence, so that the latest data is always at the end, so as to facilitate the sequential acquisition of time data and perform corresponding judgment and calculation. In addition, DMA can also be prevented from tampering with the data in the first memory block.
[0100] The above-mentioned operation of storing (or moving or copying) the data stored in the first memory block (i.e., multiple first times) in the second memory block in sequence according to the chronological order can be implemented by the processor (or the above-mentioned timer, or the above-mentioned functional module for executing the task). The processor can determine when to move the first time in the first memory block to the second memory block based on polling operations, timing, etc.
[0101] In some embodiments, the detector includes: a first register and a second register;
[0102] The first time of recording includes:
[0103] The first register determines the first time, and the first time is saved in the second register.
[0104] Here, the first register is a Capture count register, and the second register is a FIFO (First Input First Output) register.
[0105] The Capture count register is used to obtain time data and store the time data in the FIFO register, that is, the FIFO register is used to store time data;
[0106] Correspondingly, the accessor is used to move the time data in the FIFO register to the first memory block.
[0107] In some embodiments, the first chip may be: MCU (Microcontroller Unit), IC (Integrated Circuit), SOC, FPGA (Field Programmable Gate Array), microprocessor (MPU), communication integrated circuit, sensor chip, etc.;
[0108] The second chip may be: MCU, IC, SOC, FPGA, MPU, communication integrated circuit, sensor chip, etc.
[0109] The SOC may be a multi-core heterogeneous chip. Multi-core heterogeneity refers to a chip architecture design in which multiple processing cores (cores) are integrated and at least two of these cores are different in structure, function or performance. Some tasks may be more suitable for high-performance general-purpose processor cores, while other tasks may require more specialized processor cores to improve efficiency. Multi-core heterogeneity can better balance factors such as performance, power consumption and cost, and provide more flexible and efficient solutions.
[0110] A multi-core heterogeneous chip refers to a chip that integrates two or more processor cores in a single chip. Each processor core can act as an independent processor and independently run the instructions stored in the memory corresponding to the processor core.
[0111] The processor, the detector, the access device, etc. may be IP / IP cores in a SOC, respectively.
[0112] IP, also known as IP core (Intellectual Property Core), refers to the mature design of a circuit module with independent functions in a chip. This circuit module design can be applied to other chip design projects that contain this circuit module, thereby reducing the design workload, shortening the design cycle, and improving the success rate of chip design. IP core can also be understood as an intermediate component of chip design.
[0113] The processor, the detector, the access device, etc. may belong to a multi-purpose domain (MP) in the SOC, or may belong to different multi-purpose domains. The processor, the detector, the access device, etc. may belong to an application domain, or may belong to different application domains. The processor, the detector, the access device, etc. may belong to a safety domain in the SOC, or may belong to different safety domains.
[0114] A hardware domain is a set of hardware that may include hardware resources such as processor cores, interrupt controllers, clock controllers, and memory. The number of processor cores in a hardware set may be one or more. One hardware domain runs one operating system, and different hardware domains may run different operating systems.
[0115] Application domain: refers to one or more hardware domains, which means that the hardware domain has strong computing performance and can support application programs with high computing performance requirements.
[0116] Security domain: is one or more hardware domains, including at least one of the following characteristics: having a high functional safety architecture, running an operating system that meets high functional safety requirements, and processing tasks that require high functional safety.
[0117] The multifunctional domain is one or more hardware domains, which are configured with processor components with certain processing capabilities and specific hardware components that respond to various different requirements, such as processors, for processing various types of tasks.
[0118] In some embodiments, the method in the embodiments of the present disclosure can be applied to chips in transportation equipment, including but not limited to balance vehicles, cars, buses, subways, trains, and airplanes.
[0119] The method provided by the embodiment of the present disclosure can be applied to any application scenario where two chips need to interact with each other. For example, a certain transportation device has a first chip and a second chip, and the first chip and the second chip are responsible for controlling different systems or different functions respectively, and the two need to interact.
[0120] like Figure 2 In one example provided, the first chip may be an MCU, the second chip may be an SOC, and the MCU may detect a state of an input signal sent by the SOC.
[0121] Specifically, in the automotive semiconductor field, there are scenarios where MCU and SOC are interconnected. SOC may be responsible for functions such as smart cockpit or smart driving, while MCU may be responsible for regional control functions, such as the left front domain of the car, chassis domain, etc. In this scenario, there is a frequent need for interaction between MCU and SOC. MCU needs to monitor SOC system status information. MCU and SOC can be connected through a first interface. The first interface of MCU can have multiple input states, such as high level, low level, 390kHz (square wave), 6.25MHz (square wave) and other input states. MCU uses the method provided in the embodiment of the present disclosure to monitor the input signal state of the first interface, thereby executing corresponding actions.
[0122] The input signal may be a system error management fault signal, an oil pump control signal, a wheel speed signal, etc.
[0123] The above is only an example of the first chip, the second chip, and the input signal, and is not limiting.
[0124] Figure 3 A schematic diagram of the structure of a first chip provided in an embodiment of the present disclosure; Figure 3 As shown, the first chip includes: DMA (an example of an access device), etimer (an example of a detector), a first memory block, a second memory block, and a CPU (an example of a processor, which may also be a timer or other functional module).
[0125] Among them, DMA is used to move data, CPU is used to move data and perform calculations; etimer is used to capture input signals, and etimer has Capture count register and FIFO register.
[0126] The configuration of DMA can be as follows:
[0127] Transfer type: DEV2MEM, that is, DMA moves data from the Capture count register to the first memory block.
[0128] Transfer mode: continuous, that is, the DMA working mode is continuous. As long as there is a trigger signal, the DMA transfer will be triggered once and will never stop;
[0129] Memory mode: CIRCULAR, that is, the memory address block of the DMA operation is a circular overwrite type;
[0130] Source address increment: No, that is, the timestamp data is fixedly stored at the address of the Capture count register;
[0131] Target address increment: Yes, that is, the timestamp is stored in the target address in a circular overwriting manner;
[0132] Source address width: 4, that is, the data size of the timestamp is 4 bytes;
[0133] Target address width: 4, that is, the data size of the timestamp is 4 bytes;
[0134] Source address burst length: 1, that is, each DMA trigger only moves one timestamp;
[0135] Target address burst length: 1, that is, each DMA trigger only moves one timestamp. Here, the source address burst length is the same as the target address burst length, which can be 1, 2, 3, 4, etc.
[0136] Interrupt type: 0, in order to minimize the CPU load rate, DMA does not generate interrupts;
[0137] Trigger mode: hardware, edge change of external IO port connected to SOC;
[0138] Source address: address of etimer channel FIFO;
[0139] Target address: first memory block, variable name: dma_test_des;
[0140] Transmission length: total_array_number*4, where total_array_number indicates the number of timestamps. For example, if total_array_number is 8, 4 indicates that each timestamp data is 4 bytes.
[0141] In actual application, the electronic device starts the DMA and etimer input capture functions (at this time, the etimer will not generate an interrupt, and the DMA will not generate an interrupt), detects the input signal and the state of the input signal. Figure 3 The structure shown in the figure, the method of the embodiment of the present disclosure is as follows Figure 4 As shown, specifically including:
[0142] Step 401: Create a timer or task cycle to obtain the cumulative number of bytes transferred by DMA.
[0143] For example, the timer or task cycle is 1 second. The specific time needs to be set in combination with the difference in IO input frequency, which is not limited here.
[0144] Step 402: determine the state change according to the number of bytes transferred cumulatively by DMA, and determine the state of the input signal in combination with the determination result.
[0145] Here, the number of bytes cumulatively transferred by DMA may be determined by detecting the amount of data change (denoted as diff) in the first memory block.
[0146] If the number of bytes transferred by the DMA last acquired is count1, and the number of bytes transferred by the DMA currently acquired is count2;
[0147] In the first case, if diff=count2-count1=0, it means that there is no edge change from the previous cycle to the current cycle, and the high level or low level is maintained. At this time, the IO of the chip MCU can be switched to GPIO (general input / output) input, and the GPIO module can be used to determine whether it is a high level or a low level, that is, the current IO input can be obtained to be a high level or a low level.
[0148] In the second case, if diff=count2-count1<the first threshold, since a complete square wave cycle of the input signal is not captured, the frequency of the input signal can be calculated in the next cycle of the timer or task.
[0149] Here, if it is a double-edge capture, the first threshold may be 3*4; if it is a single-edge (rising edge or falling edge) capture, the first threshold is 2*4.
[0150] In the third case, if diff=count2-count1>=the first threshold (DMA will copy 4 bytes for each edge change, and at least 3 edge changes need to be captured to calculate the complete period of the square wave), the following operations can be performed to determine the frequency of the input signal:
[0151] 1) Refresh the target address of DMA transfer and the cache of the first memory block to ensure that the timestamp of the first memory block is the latest. The variable name of the first memory block is: dma_test_des, and the starting address of the first memory block is: dst_addr.
[0152] 2) The timer or task module in the MCU obtains the target address shadow_dst_addr of the first memory block that the DMA is about to operate.
[0153] Here, the index number of the latest data is index = (shadow_dst_addr-dst_addr) / 4. Here, it is divided by 4 because the size of each timestamp data is 4 bytes. If the size of the timestamp data changes, the formula here also changes accordingly.
[0154] 3) According to the above index number index, the timestamp information of the target address variable dma_test_des of the DMA operation is arranged in chronological order to the second memory block (the variable name of the second memory block is recorded as time_data_array).
[0155] Here, the second memory block is used to sort the data of the first memory block according to the chronological order, and the latest data is always at the end, that is, the data of the second memory block is updated according to the data of the first memory block.
[0156] 4) Determine the frequency of the input signal based on the timestamp information of time_data_array[total_array_number-1] and time_data_array[total_array_number-3] and the working clock of etimer.
[0157] Here, time_data_array[total_array_number-1] represents the latest timestamp information;
[0158] time_data_array[total_array_number-2] indicates the latest timestamp information;
[0159] time_data_array[total_array_number-3] represents the latest timestamp information;
[0160] And so on.
[0161] Assuming that the working clock of etimer is 200MHZ and each beat is 5ns, combined with the timestamp information, the actual time can be known. The actual time of time_data_array[total_array_number-1] minus the actual time of time_data_array[total_array_number-3] is obtained to get the period of the input signal, and then the frequency of the input signal is obtained.
[0162] Figure 5 A schematic diagram of a connection between a first chip and a second chip provided in an embodiment of the present disclosure; Figure 5 As shown, the first chip may have a first interface and a second interface, and each interface may be connected to a second chip, wherein the first interface is an IO port and the second interface is a GPIO port.
[0163] Figure 6 A schematic diagram of another connection between a first chip and a second chip provided in an embodiment of the present disclosure; Figure 6 As shown, the first chip may also have multiple first interfaces and second interfaces, connecting different interfaces of different second chips.
[0164] The first chip can use the above state identification method to identify the signal state for input signals from different second chips received through different first interfaces and second interfaces. If multiple input signals need to be identified at the same time, there can be a combination of multiple sets of detectors and memory blocks; each combination of detectors and memory blocks includes: a detector, a first memory block, and a second memory block.
[0165] like Figure 7 As shown, an example of a combination of two groups of detectors and memory blocks is provided. If more groups are needed, they can be adaptively increased, which will not be described in detail here.
[0166] Figure 8 A schematic diagram of the structure of a state recognition device provided in an embodiment of the present disclosure; Figure 8As shown, the device includes: a first chip and a second chip, the first chip includes: a first memory block;
[0167] The first chip is used to determine first information of the first memory block, where the first information is at least used to indicate whether the storage data in the first memory block has changed;
[0168] Second information of the second chip is determined according to the first information, where the second information is used to indicate a state of an input signal sent by the second chip to the first chip.
[0169] In some embodiments, the first chip further comprises: a detector and an accessor; the first chip receives an input signal sent by the second chip through a first interface;
[0170] The detector is used to detect whether the input signal received through the first interface has an edge change in a first period;
[0171] When it is determined that the input signal has an edge change, a first time is recorded and a first instruction is sent to the access device; the first time is the time when the input signal has an edge change;
[0172] The accessor is used to move the first time to the first memory block based on the first instruction.
[0173] In some embodiments, the apparatus further comprises: a processor configured to determine a change in the stored data in the first memory block during a first cycle;
[0174] If the change amount is 0, it is determined that the input signal has not changed;
[0175] If the change amount is greater than 0, it is determined that the input signal has changed.
[0176] In some embodiments, the first chip further includes: a second interface, a second interface module;
[0177] If it is determined that the input signal has not changed, the processor is further configured to switch the first input mode to a second input mode, wherein the first input mode is that the first chip receives the input signal sent by the second chip through the first interface, and the second input mode is that the first chip receives the input signal sent by the second chip through the second interface;
[0178] Using the second interface module, a frequency of an input signal received through the second interface is determined.
[0179] In some embodiments, if it is determined that the input signal has changed, the processor is further configured to determine at least two first times within a second cycle stored in the first memory block;
[0180] If the variation is greater than or equal to a first threshold, determining the frequency of the input signal according to the at least two first times;
[0181] If the variation is smaller than the first threshold, the frequency of the input signal is determined according to at least two first times in a next second period.
[0182] In some embodiments, the processor is further used to store the first time stored in the first memory block in the second memory block in chronological order; the first memory block and the second memory block are memory blocks of a circular covering type;
[0183] Correspondingly, determining the first information of the first memory block includes: determining a change amount of data stored in the second memory block within a first cycle.
[0184] In some embodiments, the detector includes: a first register and a second register;
[0185] The first register is used to determine the first time and save the first time to the second register.
[0186] It should be noted that, when the device provided in the above embodiment implements the corresponding method, the above processing can be assigned to different modules as needed to complete all or part of the above-described processing. In addition, the device provided in the above embodiment and the embodiment of the corresponding method belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.
[0187] The embodiment of the present disclosure also provides a component on a traffic device, wherein the component includes a chip, and the chip can execute the above-mentioned state identification method.
[0188] In some embodiments, the components may be circuit board-level components, automotive electrical system-level components, or automotive assembly components. As an example, the components may be the engine, chassis, body, and electrical and electronic equipment of the vehicle. The electrical and electronic equipment of the vehicle may include headlights for lighting, management equipment for controlling the engine, and central control equipment for receiving broadcasts, navigation, listening to music, and entertainment.
[0189] The embodiment of the present disclosure also provides a transportation device, the transportation device includes a chip. The chip can execute the above-mentioned state recognition method. The first chip can be a multi-core heterogeneous chip, and the transportation device includes but is not limited to a balance car, a car, a bus, a train, etc.
[0190] An embodiment of the present disclosure provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored. When the executable instructions are executed by a processor, the processor will be triggered to execute the state identification method provided by the embodiment of the present disclosure.
[0191] In some embodiments, the computer-readable storage medium may be a ferroelectric random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disk, or a CD-ROM; it may also be various devices including one or any combination of the above memories.
[0192] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, model, subroutine or other unit suitable for use in a computing environment.
[0193] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.
[0194] An embodiment of the present disclosure provides a computer program product, which includes a computer program / instructions. When the computer program / instructions are executed by a processor, the state identification method described in the present disclosure is implemented.
[0195] Fig. 9 The structure diagram of an electronic device provided by the embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the electronic device 90 includes: a processor 901 and a memory 902 for storing a computer program that can be run on the processor; when the processor 901 is used to run the computer program, it executes the state recognition method provided by the embodiment of the present disclosure.
[0196] The electronic device may further include: a detector, an access device, etc.
[0197] In actual application, the electronic device 90 may further include: at least one network interface 903. The various components in the electronic device 90 are coupled together via a bus system 904. It is understood that the bus system 904 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 904 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Fig. 9 In the figure, various buses are marked as bus system 904. There may be at least one processor 901. The network interface 903 is used for wired or wireless communication between the electronic device 90 and other devices.
[0198] The memory 902 in the embodiment of the present disclosure is used to store various types of data to support the operation of the electronic device 90 .
[0199] The method disclosed in the above embodiment of the present disclosure can be applied to the processor 901, or implemented by the processor 901. The processor 901 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 901 or the instruction in the form of software. The above processor 901 may be a general processor, a digital signal processor (DSP, DiGital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 901 can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present disclosure. The general processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the present disclosure can be directly embodied as a hardware decoding processor to execute, or the hardware and software modules in the decoding processor are combined to execute. The software module can be located in a storage medium, which is located in the memory 902. The processor 901 reads the information in the memory 902 and completes the steps of the above method in combination with its hardware.
[0200] In some embodiments, the electronic device 90 can be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to execute the aforementioned method.
[0201] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.
[0202] In the above description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0203] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as those commonly understood by those skilled in the art to which this disclosure belongs. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.
[0204] It should be understood that in the various embodiments of the present disclosure, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.
[0205] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0206] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A state recognition method, characterized in that: The method is applied to a first chip, the first chip includes: a first memory block, and the method includes: Determine first information of the first memory block, where the first information is at least used to indicate whether storage data in the first memory block changes; Second information of the second chip is determined according to the first information, where the second information is used to indicate a state of an input signal sent by the second chip to the first chip.
2. The method according to claim 1, characterized in that The first chip further includes: a detector and an access device; the first chip receives an input signal sent by the second chip through a first interface; The method further comprises: The detector detects whether an edge change occurs in the input signal received through the first interface within a first period; When it is determined that the input signal has an edge change, a first time is recorded and a first instruction is sent to the access device; the first time is the time when the input signal has an edge change; The accessor moves the first time to the first memory block based on the first instruction.
3. The method according to claim 1 or 2, characterized in that: The determining the first information of the first memory block includes: Determine a change in the stored data in the first memory block within a first cycle; If the change amount is 0, it is determined that the input signal has not changed; If the change amount is greater than 0, it is determined that the input signal has changed.
4. The method according to claim 3, characterized in that The first chip further includes: a second interface and a second interface module; If it is determined that the input signal has not changed, the method further includes: Switching the first input mode to the second input mode, wherein the first input mode is that the first chip receives the input signal sent by the second chip through the first interface, and the second input mode is that the first chip receives the input signal sent by the second chip through the second interface; Using the second interface module, a frequency of an input signal received through the second interface is determined.
5. The method according to claim 3, characterized in that: If it is determined that the input signal has changed, the method further includes: determining at least two first times within a second cycle stored in the first memory block; If the variation is greater than or equal to a first threshold, determining the frequency of the input signal according to the at least two first times; If the variation is smaller than the first threshold, the frequency of the input signal is determined according to at least two first times in a next second period.
6. The method according to claim 3, characterized in that The method further comprises: The first time stored in the first memory block is stored in the second memory block in chronological order; the first memory block is a memory block of a circular covering type; Correspondingly, determining the first information of the first memory block includes: determining a change amount of data stored in the second memory block within a first cycle.
7. The method according to claim 2, characterized in that: The detector comprises: a first register and a second register; The first time of recording includes: The first register determines the first time, and the first time is saved in the second register.
8. A state recognition device, characterized in that: The device comprises a first chip and a second chip, wherein the first chip comprises: a first memory block; The first chip is used to determine first information of the first memory block, where the first information is at least used to indicate whether the storage data in the first memory block has changed; Second information of the second chip is determined according to the first information, where the second information is used to indicate a state of an input signal sent by the second chip to the first chip.
9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.
10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to make a computer execute the method according to any one of claims 1 to 7.