Limit calculation accelerator
By designing an extreme computing accelerator with 16 accelerator units and using non-blocking cross switches to realize algorithm transmission, the problem of lack of efficient extreme computing accelerator in the prior art is solved, and efficient acceleration of computing power is achieved.
Patent Information
- Application Number
- CN202310955058.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-01
- Publication Date
- 2025-02-14
AI Technical Summary
There is a lack of a device that can effectively accelerate limit calculations in the prior art.
An extreme computing accelerator is designed, including 16 accelerator units, each of which consists of a RISC-V-based control unit, an FPGA accelerator unit and a memory, and uses a non-blocking cross switch to realize algorithmic transmission between layers.
It achieves efficient acceleration of computing power, and can use 28nm or below processes to build a pipeline configuration. The calculation rate is independent of the data size and calculation complexity.
Smart Images
Figure CN119441120A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computing power acceleration technology, and in particular to an extreme computing accelerator. Background Art
[0002] The significance of computing power acceleration to the times is profound and important. With the continuous advancement of science and technology and the advent of the digital age, the improvement of computing power has become a key factor in promoting social development and economic progress. As a core technology, computing power acceleration is of great significance to the times in the following aspects:
[0003] 1. Promote scientific and technological progress: Computing acceleration technology provides strong support for scientific and technological research in various fields. From basic scientific research to artificial intelligence, biomedicine, engineering simulation and other applications, high-performance computing capabilities are required to process complex data and perform precise simulations. The application of computing acceleration technology has driven scientists to make greater progress in exploring unknown areas, solving complex problems and achieving breakthrough results.
[0004] 2. Promote innovation and industrial upgrading: High-performance computing capabilities accelerate product development, design and optimization processes, shorten development cycles, and promote product innovation. For enterprises, computing power acceleration means more efficient data processing and more accurate simulation analysis, allowing them to stand out in market competition. Accelerating innovation and industrial upgrading improves the core competitiveness of enterprises.
[0005] 3. Improve the quality of life: Computing acceleration also has a positive impact on people's daily lives. In the medical field, high-performance computing accelerates genomic analysis, drug development, etc., providing more accurate solutions for disease diagnosis and treatment. In the field of intelligent transportation, computing acceleration technology brings safer and more efficient transportation experience to autonomous driving, traffic flow optimization, etc.
[0006] 4. Solve complex social problems: High-performance computing capabilities make it possible to analyze and process large-scale data; governments and social organizations can use computing acceleration technology to better respond to complex social problems such as climate change, natural disasters, and public health, and improve the scientificity and accuracy of decision-making.
[0007] 5. Promote the development of the digital economy: In the digital age, the amount of data continues to grow, and the demand for computing power is also increasing. The acceleration of computing power provides a solid foundation for the development of the digital economy; the rise of digital industries such as data analysis, cloud computing, and artificial intelligence cannot be separated from the support of high-performance computing.
[0008] In summary, the significance of computing acceleration to the times lies in promoting scientific and technological progress, promoting innovation and industrial upgrading, improving the quality of life, solving complex social problems, and promoting the prosperity and development of the digital economy. With the continuous evolution of technology, computing acceleration will continue to play an important role and make greater contributions to the continuous progress and development of human society. However, computing acceleration is rarely used in various industries at present. Summary of the invention
[0009] The technical problem to be solved by the present invention is to overcome the deficiencies in the prior art and provide an extreme computing accelerator.
[0010] The technical solution adopted by the present invention to solve its technical problem is: an extreme computing accelerator, having 16 accelerator units, each accelerator unit is composed of a RISC-V-based control unit, an FPGA accelerator unit and a memory, wherein the control unit has a top-level master RISC-V and several master RISC-Vs, the FPGA accelerator unit has several FPGA accelerators, and the memory includes an erasable and controllable read-only memory.
[0011] Furthermore, the top-level master RISC-V controls I / O transmission and distributes work tasks to 16 accelerator units.
[0012] Furthermore, the top-level master RISC-V is configured by an erasable and controllable read-only memory, and the master RISC-V unit configures an accelerator unit and a non-blocking switch.
[0013] Furthermore, there are four non-blocking switches, and the master RISC-V and 16 accelerator units are interconnected through non-blocking switches, wherein three non-blocking switches realize 32 connections from the master RISC-V to the accelerator unit, and one non-blocking switch realizes the connection between each FPGA accelerator.
[0014] Furthermore, the master RISC-V includes a master RISC-V calculator, which is implemented by two FPGA accelerators. The master RISC-V calculator manages I / O transmission and distributes tasks to 16 accelerator units.
[0015] Further, the non-blocking switch uses dynamically controlled switch blocks, and the connection allows the interconnected switch blocks and the wiring structure to be changed by the running RISC-V code and / or signals generated within the FPGA.
[0016] Furthermore, the dynamically controlled switch block is controlled by an initially configured or adjacent CLB in a fixed or dynamic mode, and each CLB sets a mode during configuration to act as an adjacent switch block controller.
[0017] Furthermore, the CLB sets the control switch blocks that need to be connected during configuration.
[0018] Furthermore, the dynamically controlled switch block configuration needs to be reset by loading a new bitstream into the local switch block portion of the j-tag chain and then loading the j-tag into the control point or by parallel loading from adjacent configuration registers.
[0019] Furthermore, the dynamically controlled switch block is controlled by a set of registers and is fixed during configuration, wherein one register is used to store the current connection configuration and one register is used to store the next configuration.
[0020] Furthermore, each of the 16 accelerator units is implemented by providing a means for rewriting local configuration information.
[0021] Furthermore, the FPGA accelerator uses FPGA dedicated hardware to implement multiple 16x 16 actual crossbar switches, which are connected together to make a larger crossbar switch.
[0022] Furthermore, the module connected to the 16 accelerator units uses a single-ended 6-wire standard speed control signal group.
[0023] The beneficial effects of the present invention are:
[0024] The extreme computing accelerator of the present invention can use 28nm, 14nm and below processes to build a pipeline long configuration, and realize the algorithm transmission between layers by non-blocking crossbar switches to accelerate the computing power;
[0025] Instead of implementing a full 16x16 high-speed crossbar on all switches, the 6-wire standard speed control signal groups connected to the 16 accelerator unit modules are single-ended and do not use the FPGA’s serial transceiver (SerDes) hardware.
[0026] The calculation rate of FPGA has nothing to do with the amount of data. When the pipeline is full, no matter how large the amount of data is, the sBal calculation of one data element is still completed at the end of each clock tick;
[0027] The calculation rate of FPGA is also unrelated to the complexity of the calculation. More complex calculations just mean more pipeline steps. The pipeline is filled, and the sBal calculation of one data element is completed at the end of each clock tick. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The present invention is further described below in conjunction with the accompanying drawings and embodiments.
[0029] Figure 1The diagram is a layout diagram of an extreme computing accelerator of the present invention.
[0030] Figure 2 A top-level block diagram of an extreme computing accelerator of the present invention.
[0031] Figure 3 Another top-level block schematic diagram of an extreme computing accelerator of the present invention.
[0032] Figure 4 A schematic diagram of an accelerator unit node block of an extreme computing accelerator of the present invention.
[0033] Figure 5 A schematic diagram of a non-blocking switch of an extreme computing accelerator of the present invention.
[0034] Figure 6 A schematic diagram of an embedded system of an extreme computing accelerator of the present invention.
[0035] Figure 7 A schematic diagram of another embedded system of an extreme computing accelerator of the present invention.
[0036] Figure 8 This is a schematic diagram of pipeline states within each clock tick of an embedded system of an extreme computing accelerator of the present invention, taking the calculation of cash flow as an example.
[0037] Fig. 9 This is a schematic diagram of the first step of the pipeline calculation process in each clock tick, taking four groups of data elements as an example of an extreme calculation accelerator of the present invention.
[0038] Fig.10 This is a second extreme computing accelerator of the present invention, which takes four groups of data elements as an example to illustrate the second step calculation process of the pipeline in each clock tick.
[0039] Fig.11 This is a third type of extreme computing accelerator of the present invention, which takes four groups of data elements as an example to illustrate the third step calculation process of the pipeline in each clock tick.
[0040] Fig.12 This is a fourth type of extreme computing accelerator of the present invention, which takes four groups of data elements as an example to illustrate the fourth step calculation process of the pipeline in each clock tick.
[0041] Fig.13 This is a schematic diagram of the last step of the calculation process of the pipeline in each clock tick, taking four groups of data elements as an example of an extreme calculation accelerator of the present invention. DETAILED DESCRIPTION
[0042] The present invention will now be further described in conjunction with the accompanying drawings and preferred embodiments. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.
[0043] like Figure 1 As shown, an extreme computing accelerator has 16 accelerator units (ACU), each of which is composed of a RISC-V-based control unit (RISC-V CPU is implemented in FPGA), an FPGA accelerator unit and a memory, wherein the control unit has a top-level master RISC-V (implemented in 2 FPGA chips) and several master RISC-Vs, the FPGA accelerator unit has several FPGA accelerators, and the memory includes an erasable and controllable read-only memory. Among them, the 16 accelerator units are all implemented by providing a means for rewriting local configuration information. The FPGA accelerator uses FPGA-specific hardware to implement multiple 16×16 actual cross switches, which are connected together to make larger cross switches. The modules connected to the 16 accelerator units use a single-ended 6-wire standard speed control signal group.
[0044] Among them, the top-level master RISC-V controls I / O transmission and assigns work tasks to 16 accelerator units. The top-level master RISC-V is configured by an erasable and controllable read-only memory (EPROM), and the master RISC-V unit configures the accelerator unit and the non-blocking switch (each switch is implemented in the FPGA). There are 4 non-blocking switches, and the master RISC-V and 16 accelerator units are connected to each other through non-blocking switches, among which 3 non-blocking switches realize 32 connections from the master RISC-V to the accelerator unit, and 1 non-blocking switch realizes the connection between each FPGA accelerator.
[0045] Non-blocking switches use dynamically controlled switch blocks, where connections allow the interconnected switch blocks and routing structure to be changed by the running RISC-V code and / or signals generated inside the FPGA. Dynamically controlled switch blocks are controlled by initial configuration or adjacent CLBs in fixed or dynamic mode, where each CLB sets a mode at configuration time to act as an adjacent switch block controller. The CLB sets the control switch block that needs to be connected at configuration time. Dynamically controlled switch blocks require the switch block configuration to be reset, specifically: by loading a new bitstream into the local switch block portion of the j-tag chain and then loading the j-tag to the control point or by parallel loading from an adjacent configuration register. Dynamically controlled switch blocks are controlled by a set of registers and are fixed at configuration time, where one register is used to save the current connection configuration and one register is used to save the next configuration.
[0046] The non-blocking switch using the above-mentioned embodiment can be applied to a method of loading and storing multiple switch block configurations local to each dynamic switch block and selecting to use a global selection signal; it can also be applied to a method of dynamically controlling CLB inputs and outputs to required wires, which method can be part of an adjacent dynamic switch block control structure or a separate structure; it can also be applied to a method of dynamically controlling LUT and other CLB configuration settings, which method can be part of an adjacent dynamic switch block control structure or a separate structure.
[0047] like Figure 2 and Figure 3 As shown, the master RISC-V includes a master RISC-V calculator, which is implemented by two FPGA accelerators. The master RISC-V calculator manages I / O transmission and distributes tasks to 16 accelerator units.
[0048] like Figure 4 As shown, the FPGA of this embodiment is PH1A400SFG900, equipped with 32GB RAM and Samsung K4ABG165WB-MCWE 2G x 1 (or equivalent Changxin memory chip). Figure 5 As shown in Figure 1, implementing the accelerator non-blocking switch in the PH1A400SFG900 FPGA does not require all switches to be implemented as a full 16x16 high-speed crossbar. The 6-wire standard speed control signal group connected to the 16 modules is single-ended and does not use the FPGA's serial transceiver (SerDes) hardware.
[0049] like Figure 6 As shown, the embedded system works with a traditional "open system" host (X86), and the host's task is to run the operating system or application that uses the embedded system, handle I / O, store configuration files for the embedded system, control loading of the appropriate configuration for the task at hand, and use the embedded system to process tasks.
[0050] like Figure 7 As shown, the configuration parameters of the embedded system are: 64-bit 66MHz PCI, 72-bit data path (8 bytes + ECC), 4Xilinx Virtex 1000 field programmable gate arrays (FPGAs), up to 12GB of SDRAM, which can be configured as 4 physical memories that can run independently and in parallel, or as a large memory, a 72-bit × 9 crossbar switch that connects any physical memory to any FPGA, and a very long word instruction memory - 216-bit × 256K word SRAM.
[0051] It should be noted that in embedded systems, one FPGA clock is approximately equal to 10 clocks of a 1GHZ general-purpose processor. Although the clock frequency of the FPGA is lower, in fact, the distributed parallelism of the FPGA is much higher than that of a general-purpose processor.
[0052] The C++ code for calculating cash flow will be used as an example to illustrate how FPGA in embedded systems can be accelerated. In this embodiment, the embedded system is about 160 times faster than the C++ open environment.
[0053]
[0054] like Figure 8 As shown, take the calculation of sBal as an example. [Loan_Coupon, WAM, c0] is a set of input data elements. The calculation of sBal can be divided into the following steps, each of which can be implemented in FPGA reconfigurable resources. It should be pointed out that sBal requires 6 steps in FPGA pipeline calculation. The first step is a, the second step is to calculate b, c, f, g at the same time, the third step is to calculate d and h at the same time, the fourth step is to calculate e and k at the same time, the fifth step is m, and the sixth step is sBal.
[0055] like Figures 9 to 12 As shown in the figure, four groups of data elements (represented by circles of four colors) are used as examples to illustrate the pipeline status in each clock tick. At the end of each clock tick, the data moves to the next step for calculation. It can be seen that it takes a total of 9 clock ticks to complete the sBal pipeline calculation of data 1 to 4 (when clock tick 9 ends, all calculations have been completed).
[0056] Fig. 9 Specifically, data 1 to 4 are waiting to enter the pipeline, and no calculation is performed in the pipeline; then, data 1 enters the pipeline and a is calculated; then, data 2 enters the pipeline and a is calculated; at the same time, data 1 moves and b, c, f, and g are calculated.
[0057] Fig.10 Specifically, data 3 enters the pipeline and a is calculated; at the same time, data 2 moves and b, c, f, g are calculated; data 1 moves and d and h are calculated; then, data 4 enters the pipeline and a is calculated; at the same time, data 3 moves and b, c, f, g are calculated; data 2 moves and d and h are calculated; data 1 moves and e and k are calculated; then, data 4 moves and b, c, f, g are calculated; at the same time, data 3 moves and d and h are calculated; data 2 moves and e and k are calculated; data 1 moves and m is calculated.
[0058] Fig.11Specifically, data 4 moves to calculate d and h; at the same time, data 3 moves to calculate e and k; data 2 moves to calculate m, and data 1 moves to calculate sBal; then, data 4 moves to calculate e and k; at the same time, data 3 moves to calculate m; data 2 moves to calculate sBal; data 1 completes the calculation and leaves the pipeline; then, data 4 moves to calculate m; at the same time, data 3 moves to calculate sBal; data 2 completes the calculation and leaves the pipeline.
[0059] Fig.12 Specifically, data 4 moves and sBal is calculated; data 3 completes the calculation and leaves the pipeline; finally, data 4 completes the calculation and leaves the pipeline, and there is no calculation in the pipeline.
[0060] In practical applications, the amount of data usually far exceeds the number of steps in the pipeline, so the pipeline is almost full (each step has a data element being calculated). At this time, for each clock tick of the FPGA, one data element can be processed, that is, at the end of each clock tick, the sBal of a data element is calculated, such as Fig.13 shown.
[0061] Therefore, the calculation rate of FPGA has nothing to do with the amount of data. When the pipeline is full, no matter how large the data volume is, the sBal calculation of one data element will be completed at the end of each clock tick.
[0062] In the same way, the calculation rate of FPGA has nothing to do with the complexity of calculation. In fact, more complex calculations only mean more pipeline steps. Assuming that another xBal calculation requires 20 pipeline steps, it only takes 20 clock ticks for the pipeline to be filled. After that, the xBal calculation of a data element will be completed at the end of each clock tick.
[0063] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with this technology to understand the content of the present invention and implement it. They cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.
Claims
1. An extreme computing accelerator, characterized in that: It has 16 accelerator units, each of which is composed of a RISC-V-based control unit, an FPGA accelerator unit and a memory, wherein the control unit has a top-level master RISC-V and several master RISC-Vs, the FPGA accelerator unit has several FPGA accelerators, and the memory includes an erasable and controllable read-only memory.
2. The extreme computing accelerator according to claim 1, characterized in that: The top-level master RISC-V controls I / O transfers and distributes work tasks to the 16 accelerator units.
3. The extreme computing accelerator according to claim 1, characterized in that: The top-level master RISC-V is configured by an erasable and controllable read-only memory, and the master RISC-V unit configures an accelerator unit and a non-blocking switch.
4. The extreme computing accelerator according to claim 3, characterized in that: There are four non-blocking switches, and the master RISC-V and 16 accelerator units are connected to each other through the non-blocking switches, wherein three non-blocking switches realize 32 connections from the master RISC-V to the accelerator unit, and one non-blocking switch realizes the connection between each FPGA accelerator.
5. The extreme computing accelerator according to claim 1, characterized in that: The master RISC-V includes a master RISC-V calculator, which is implemented by two FPGA accelerators. The master RISC-V calculator manages I / O transmission and distributes tasks to 16 accelerator units.
6. The extreme computing accelerator according to claim 1, characterized in that: The non-blocking switch uses dynamically controlled switch blocks, and the connections allow the interconnected switch blocks and the wiring structure to be changed by the running RISC-V code and / or signals generated inside the FPGA.
7. The extreme computing accelerator according to claim 6, characterized in that: The dynamically controlled switch blocks are controlled in fixed or dynamic mode by the initial configuration or adjacent CLBs, each CLB setting a mode during configuration to act as a controller for the adjacent switch blocks.
8. An extreme computing accelerator as claimed in claim 7, characterized in that: The CLB sets the control switch blocks that need to be connected during configuration.
9. The extreme computing accelerator according to claim 6, characterized in that: The dynamically controlled switch block switch block configuration needs to be reset, specifically by loading a new bit stream into the local switch block portion of the j-tag chain and then loading the j-tag into the control point or by parallel loading from adjacent configuration registers.
10. The extreme computing accelerator according to claim 9, characterized in that: The dynamically controlled switch block is controlled by a set of registers and is fixed during configuration, wherein one register is used to store the current connection configuration and one register is used to store the next configuration.
11. The extreme computing accelerator according to claim 1, characterized in that: Each of the 16 accelerator units is implemented by providing a means for rewriting local configuration information.
12. The extreme computing accelerator according to claim 1, characterized in that: The FPGA accelerator uses FPGA-specific hardware to implement multiple 16 x 16 actual crossbars that are connected together to make a larger crossbar.
13. The extreme computing accelerator according to claim 1, characterized in that: The module connects to 16 accelerator units using a single-ended 6-wire standard speed control signal set.