Security management method and system applied to preparation of storage chip

Abstract

The invention relates to the technical field of chip management, and discloses a safety management method and system applied to storage chip preparation, and the method comprises the steps: determining a chip manufacturing protocol corresponding to chip process equipment, and formulating a safety early warning index corresponding to the chip process equipment; collecting chip preparation data of the storage chip in a preparation project, analyzing a preparation characteristic dimension corresponding to the chip process equipment based on the chip preparation data, calculating an index safety factor corresponding to the safety early warning index, and evaluating equipment safety performance corresponding to the chip process equipment; analyzing chip physical attributes corresponding to the storage chip, analyzing microscopic circuit characteristics corresponding to the storage chip, and calculating a quality reliability index corresponding to the storage chip; analyzing the storage integrating degree of the storage chip in the storage area; and formulating a security management strategy corresponding to the storage chip, and executing security management of the storage chip under preparation to obtain a management result. The main purpose of the invention is to solve the problem of low security management under the preparation of the memory chip.

Description

Technical Field

[0001] The present invention relates to a safety management method and system for storage chip preparation, belonging to the technical field of chip management. Background Art

[0002] Memory chips play a vital role in modern electronic devices. With the rapid development of the electronics industry, the market demand for memory chips continues to expand. In order to ensure the quality and safety of memory chips, strict safety management of the memory chip preparation process is required.

[0003] The existing safety management of memory chip preparation is mainly achieved by formulating strict operating procedures and quality control standards, determining the safety requirements and quality standards of each link in the memory chip preparation process, and training operators to make them familiar with the operating procedures and quality control standards. During the preparation process, the quality and safety of memory chips are monitored through manual inspection and sampling inspection. However, this method mainly relies on manual operation, which is inefficient and prone to human errors. For the complex memory chip preparation process, it is difficult to achieve comprehensive and real-time safety management, which in turn leads to an increase in the safety risk of memory chip preparation. Therefore, a method that can improve the comprehensiveness of safety management applied to memory chip preparation is needed. Summary of the invention

[0004] The present invention provides a safety management method and system for storage chip preparation, the main purpose of which is to solve the problem of low comprehensiveness of safety management in storage chip preparation.

[0005] To achieve the above object, the present invention provides a security management method for memory chip preparation, comprising:

[0006] Obtain the memory chip under preparation, and query the chip process equipment used in the preparation process of the memory chip, determine the chip manufacturing specification corresponding to the chip process equipment, and formulate the safety warning indicator corresponding to the chip process equipment based on the chip manufacturing specification;

[0007] Collect chip preparation data of the memory chip in the preparation process, analyze the preparation characteristic dimension corresponding to the chip process equipment based on the chip preparation data, calculate the indicator safety factor corresponding to the safety warning indicator based on the preparation characteristic dimension, and evaluate the equipment safety performance corresponding to the chip process equipment based on the indicator safety factor;

[0008] Collecting a chip node image and a chip circuit diagram of the memory chip in the chip process equipment, analyzing chip physical properties corresponding to the memory chip based on the chip node image, analyzing microscopic circuit features corresponding to the memory chip based on the chip circuit diagram, and calculating a quality trust index corresponding to the memory chip in combination with the microscopic circuit features and the chip physical properties;

[0009] Acquire a storage area corresponding to the storage chip, collect storage environment factors corresponding to the storage area, and analyze the storage compatibility of the storage chip in the storage area based on the storage environment factors;

[0010] Based on the device safety performance, the quality trust index, and the storage compatibility, a security management strategy corresponding to the storage chip is formulated. Based on the security management strategy, security management of the storage chip during preparation is performed to obtain a management result.

[0011] Optionally, formulating a safety warning indicator corresponding to the chip process equipment based on the chip manufacturing specification includes:

[0012] Performing character recognition on the chip manufacturing protocol to obtain protocol characters;

[0013] Performing semantic analysis on the specified characters to obtain the meaning of the specified characters;

[0014] Based on the meaning of the protocol characters, identifying the security protocol characters in the protocol characters;

[0015] Extracting key characters from the security specification characters to obtain specification key characters;

[0016] Based on the key characters of the protocol, safety warning indicators corresponding to the chip process equipment are formulated.

[0017] Optionally, analyzing the manufacturing characteristic dimension corresponding to the chip process equipment based on the chip manufacturing data includes:

[0018] Purifying the chip preparation data to obtain purified preparation data;

[0019] Performing label recognition on the purification preparation data to obtain a preparation label;

[0020] calculating the interaction strength coefficients between the preparation labels, and screening out characteristic preparation labels from the preparation labels based on the interaction strength coefficients;

[0021] Based on the characteristic preparation label, the target preparation data is subjected to data screening processing to obtain characteristic preparation data;

[0022] Extracting features from the characteristic preparation data to obtain preparation data features;

[0023] Performing dimension analysis on the fabrication data features to obtain fabrication characteristic dimensions corresponding to the chip process equipment.

[0024] Optionally, the calculating the interaction strength coefficient between the prepared tags includes:

[0025] Quantifying the prepared label to obtain a label quantization value, and calculating a label expected value corresponding to the prepared label based on the label quantization value;

[0026] Combining the label quantization value and the label expectation value, the interaction strength coefficient between the prepared labels is calculated by the following formula:

[0027]

[0028] Where A represents the interaction strength coefficient between the prepared tags, M a Indicates the label quantization value corresponding to the ath label in the prepared label. represents the expected value of the ath tag in the prepared tag, a and a+1 both represent the serial number corresponding to the prepared tag, M a+1 Indicates the label quantization value corresponding to the a+1th label in the prepared label. Indicates the expected value of the label corresponding to the a+1th label in the prepared label.

[0029] Optionally, the calculating, based on the preparation characteristic dimension, an indicator safety factor corresponding to the safety warning indicator includes:

[0030] Standardizing the preparation characteristic dimension to obtain a standard dimension value;

[0031] The dimension weight corresponding to the preparation characteristic dimension is calculated, and the indicator safety factor corresponding to the safety warning indicator is calculated by combining the dimension weight and the standard dimension value through the following formula:

[0032]

[0033] Among them, B represents the indicator safety factor corresponding to the safety warning indicator, E b represents the standard dimension value corresponding to the bth dimension in the preparation characteristic dimension, b represents the serial number of the preparation characteristic dimension, r represents the number of preparation characteristic dimensions, E stdb Represents the standardized safety threshold corresponding to the bth dimension in the preparation characteristic dimension.

[0034] Optionally, analyzing chip physical properties corresponding to the storage chip based on the chip node image includes:

[0035] Performing image optimization processing on the chip node image to obtain an optimized chip image;

[0036] Performing subject extraction processing on the optimized chip image to obtain a subject chip image;

[0037] Identify a chip package outline in the main chip image, and calculate an outline completeness corresponding to the memory chip based on the chip package outline;

[0038] Extracting chip pixel information corresponding to the main chip image, and calculating a physical property value corresponding to the storage chip based on the chip pixel information;

[0039] Based on the physical property value and the outline completeness, a chip physical property corresponding to the storage chip is generated.

[0040] Optionally, the calculating the outline completeness corresponding to the memory chip based on the chip package outline includes:

[0041] Acquire a standard package outline corresponding to the memory chip, and respectively perform vector processing on the chip package outline and the standard package outline to obtain a first outline vector and a second outline vector;

[0042] Based on the first contour vector, calculating the contour perimeter corresponding to the chip package contour to obtain a first contour perimeter;

[0043] Based on the second contour vector, calculating the contour perimeter corresponding to the standard package contour to obtain a second contour perimeter;

[0044] and measuring the contour areas corresponding to the chip package contour and the standard package contour to obtain a first contour area and a second contour area;

[0045] The profile integrity of the memory chip is calculated by the following formula:

[0046]

[0047] Among them, F represents the completeness of the contour corresponding to the memory chip, P1 represents the perimeter of the first contour, P2 represents the perimeter of the second contour, S1 represents the area of ​​the first contour, and S2 represents the area of ​​the second contour.

[0048] Optionally, the calculating the quality trust index corresponding to the memory chip by combining the microscopic circuit features and the chip physical properties includes:

[0049] Querying the standard circuit characteristics and standard physical properties corresponding to the memory chip, and calculating the characteristic difference between the standard circuit characteristics and the microscopic circuit characteristics;

[0050] Calculating the property difference between the standard physical property and the chip physical property;

[0051] Combining the feature difference and the attribute difference, the quality trust index corresponding to the storage chip is calculated by the following formula:

[0052]

[0053] Among them, G represents the quality trust index corresponding to the storage chip, H d represents the feature difference corresponding to the dth feature in the micro circuit feature, N e It represents the attribute difference corresponding to the e-th attribute in the chip physical properties, d represents the serial number corresponding to the micro circuit feature, p represents the number of features of the micro circuit feature, e represents the serial number corresponding to the chip physical property, and u represents the number of attributes of the chip physical property.

[0054] Optionally, analyzing the storage compatibility of the storage chip in the storage area based on the storage environment factor includes:

[0055] Querying chip manufacturing materials corresponding to the memory chip, and analyzing material environmental characteristics corresponding to the chip manufacturing materials;

[0056] Analyzing the environmental factor indicators in the material environmental characteristics, and extracting the associated environmental factors corresponding to the storage chip from the storage environmental factors based on the environmental factor indicators;

[0057] The coupling coefficient between the material environmental characteristic and the associated environmental factor is calculated, and based on the coupling coefficient, the storage compatibility of the storage chip in the storage area is analyzed.

[0058] A security management system applied to storage chip preparation, characterized in that the system comprises:

[0059] A safety warning indicator formulation module is used to obtain the memory chip under preparation, query the chip process equipment used in the preparation process of the memory chip, determine the chip manufacturing specification corresponding to the chip process equipment, and formulate the safety warning indicator corresponding to the chip process equipment based on the chip manufacturing specification;

[0060] An equipment safety performance evaluation module, used to collect chip preparation data of the memory chip in the preparation process, analyze the preparation characteristic dimension corresponding to the chip process equipment based on the chip preparation data, calculate the indicator safety factor corresponding to the safety warning indicator based on the preparation characteristic dimension, and evaluate the equipment safety performance corresponding to the chip process equipment based on the indicator safety factor;

[0061] A quality trust index calculation module, used for collecting chip node images and chip circuit diagrams of the memory chip in the chip process equipment, analyzing chip physical properties corresponding to the memory chip based on the chip node images, analyzing microscopic circuit features corresponding to the memory chip based on the chip circuit diagram, and calculating a quality trust index corresponding to the memory chip in combination with the microscopic circuit features and the chip physical properties;

[0062] A storage compatibility calculation module, used to obtain a storage area corresponding to the storage chip, collect storage environment factors corresponding to the storage area, and analyze the storage compatibility of the storage chip in the storage area based on the storage environment factors;

[0063] The security management module is used to formulate a security management policy corresponding to the storage chip based on the device safety performance, the quality trust index, and the storage compatibility, and based on the security management policy, perform security management of the storage chip during preparation to obtain a management result.

[0064] Compared with the problems described in the background technology, the present invention formulates safety warning indicators corresponding to the chip process equipment based on the chip manufacturing specifications, and can obtain the safety risk quantification standards corresponding to the chip process equipment, thereby laying a foundation for the subsequent calculation of the indicator safety factor corresponding to the safety warning indicator. The present invention analyzes the preparation characteristic dimensions corresponding to the chip process equipment based on the chip preparation data, and can obtain a description of the different preparation-related characteristics of the chip process equipment, thereby improving the calculation accuracy of the indicator safety factor corresponding to the safety warning indicator. The present invention analyzes the chip physical properties corresponding to the memory chip based on the chip node image, and can obtain the physical properties corresponding to the memory chip, thereby increasing the accuracy of the calculation of the indicator safety factor corresponding to the safety warning indicator. The understanding of the physical properties provides a basis for the subsequent calculation of the quality trust index corresponding to the storage chip. The present invention analyzes the storage fit of the storage chip in the storage area based on the storage environment factors, which can effectively evaluate the adaptability and reliability of the storage chip in the storage environment, and provides a basis for the subsequent formulation of the security management strategy corresponding to the storage chip. The present invention formulates the security management strategy corresponding to the storage chip based on the equipment safety performance, the quality trust index, and the storage fit. The combination of multiple indicators can improve the accuracy of the formulation of the security management strategy, and based on the security management strategy, the security management of the storage chip under preparation is performed, thereby improving the comprehensiveness of the security management of the storage chip under preparation. Therefore, the security management method and system applied to the preparation of storage chips proposed in the present invention can improve the comprehensiveness of the security management under the preparation of storage chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 A schematic flow chart of a safety management method for memory chip preparation according to an embodiment of the present invention;

[0066] Figure 2 A functional module diagram for implementing the security management system applied to storage chip preparation provided in one embodiment of the present invention.

[0067] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0068] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0069] The embodiment of the present application provides a security management method for storage chip preparation. The execution subject of the security management method for storage chip preparation includes but is not limited to at least one of the electronic devices such as a server and a terminal that can be configured to execute the method provided by the embodiment of the present application. In other words, the security management method for storage chip preparation can be executed by software or hardware installed in a terminal device or a server device. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0070] Embodiment 1:

[0071] Reference Figure 1 FIG. 1 is a flow chart of a safety management method for memory chip preparation according to an embodiment of the present invention. In this embodiment, the safety management method for memory chip preparation includes:

[0072] S1. Obtain the memory chip under preparation, and query the chip process equipment used in the preparation of the memory chip, determine the chip manufacturing specifications corresponding to the chip process equipment, and formulate safety warning indicators corresponding to the chip process equipment based on the chip manufacturing specifications.

[0073] The present invention formulates safety warning indicators corresponding to the chip process equipment based on the chip manufacturing specifications, and can obtain safety risk quantification standards corresponding to the chip process equipment, thereby laying a foundation for the subsequent calculation of indicator safety factors corresponding to the safety warning indicators.

[0074] It should be explained that the memory chip is an integrated circuit chip for storing data, usually made of semiconductor materials, with a specific storage unit structure and control circuit; the chip process equipment is the equipment used in the processing of the memory chip, such as wafer processing equipment, photolithography equipment, etching equipment, deposition equipment, cleaning equipment and other professional equipment; the chip manufacturing specifications are the operating specifications and technical guidelines of the chip process equipment, such as operating procedures, quality control standards, safety specifications, etc.; the safety warning indicators are the safety risk quantification standards corresponding to the chip process equipment. Exemplarily, the query of the chip process equipment during the preparation of the memory chip can be achieved through human-computer interaction; the chip manufacturing specifications corresponding to the chip process equipment can be determined through the user manual of the equipment.

[0075] In detail, the security warning indicators corresponding to the chip process equipment are formulated based on the chip manufacturing specifications, including:

[0076] Performing character recognition on the chip manufacturing protocol to obtain protocol characters;

[0077] Performing semantic analysis on the specified characters to obtain the meaning of the specified characters;

[0078] Based on the meaning of the protocol characters, identifying the security protocol characters in the protocol characters;

[0079] Extracting key characters from the security specification characters to obtain specification key characters;

[0080] Based on the key characters of the protocol, safety warning indicators corresponding to the chip process equipment are formulated.

[0081] It should be explained that the protocol characters are the character information in the chip manufacturing protocol, the protocol character meaning is the interpretation of the meaning corresponding to the protocol characters, the security protocol characters are the security-related protocol content in the protocol characters, and the protocol key characters are the representative characters in the security protocol characters.

[0082] Furthermore, the character recognition of the chip manufacturing specification can be realized by OCR recognition technology; the semantic analysis of the specification characters can be realized by semantic analysis method; based on the meaning of the specification characters, the safety specification characters in the specification characters are identified, for example, some characters may represent the safe operation process of the equipment, safety parameter restrictions, danger warnings, etc., and these characters can be recognized as safety specification characters; the key character extraction of the safety specification characters can be realized by TF-IDF algorithm; based on the key characters of the specification, the safety warning indicators corresponding to the chip process equipment are formulated, and if the key characters contain content related to the operating temperature of the equipment, the upper and lower temperature limits are set. For example, when the temperature of the chip process equipment exceeds a specific upper limit value (such as 80°C) during operation, a mild warning is issued to remind the operator to pay attention to the temperature change of the equipment; when the temperature continues to rise and exceeds a higher threshold (such as 90°C), a moderate warning is issued, and at this time, it can be considered to reduce the operating power of the equipment or perform local heat dissipation treatment; when the temperature reaches a serious dangerous value (such as 100°C), a severe warning is issued, and the equipment operation is stopped immediately to prevent equipment damage.

[0083] S2. Collect chip preparation data of the memory chip in the preparation project, analyze the preparation characteristic dimension corresponding to the chip process equipment based on the chip preparation data, calculate the indicator safety factor corresponding to the safety warning indicator based on the preparation characteristic dimension, and evaluate the equipment safety performance corresponding to the chip process equipment based on the indicator safety factor.

[0084] The present invention analyzes the preparation characteristic dimensions corresponding to the chip process equipment based on the chip preparation data, so as to obtain a description of different preparation-related characteristics of the chip process equipment, thereby improving the calculation accuracy of the indicator safety factor corresponding to the safety warning indicator.

[0085] It should be explained that the chip preparation data is the processing record data of the memory chip in the preparation process, and the preparation characteristic dimension is the description of the preparation characteristics of the chip process equipment in multiple aspects. Furthermore, the chip preparation data of the memory chip in the preparation process can be realized through various sensors, such as temperature sensors, pressure sensors, flow sensors, current sensors, etc.

[0086] Specifically, the chip preparation data is used to analyze the preparation characteristic dimensions corresponding to the chip process equipment, including:

[0087] Purifying the chip preparation data to obtain purified preparation data;

[0088] Performing label recognition on the purification preparation data to obtain a preparation label;

[0089] calculating the interaction strength coefficients between the preparation labels, and screening out characteristic preparation labels from the preparation labels based on the interaction strength coefficients;

[0090] Based on the characteristic preparation label, performing data screening processing on the target preparation data to obtain characteristic preparation data;

[0091] Extracting features from the characteristic preparation data to obtain preparation data features;

[0092] Performing dimension analysis on the fabrication data features to obtain fabrication characteristic dimensions corresponding to the chip process equipment.

[0093] It should be explained that the purified preparation data is the data obtained after removing the erroneous data in the chip preparation data, the preparation label is the data identifier corresponding to the purified preparation data, the interaction intensity coefficient represents the degree of mutual influence between the preparation labels, the characteristic preparation label is a representative label among the preparation labels, the characteristic preparation data is the data in the target preparation data corresponding to the characteristic preparation label, and the preparation data feature is the specific attribute expression of the characteristic preparation data, such as numerical distribution, change trend, etc.

[0094] Furthermore, the purification processing of the chip preparation data can be implemented by a box plot method; the label recognition of the purified preparation data can be implemented by a label recognition tool, and the label recognition tool is compiled by a scripting language, such as a JS scripting language;

[0095] When the interaction intensity coefficient is greater than a preset coefficient, the characteristic preparation labels in the preparation labels are screened out, and the preset coefficient can be set to 0.8, or can be set according to the actual application scenario; the data screening process of the target preparation data can be implemented by a screening algorithm, such as the K-Means clustering algorithm; the feature extraction of the characteristic preparation data can be implemented by the principal component analysis method; the dimensional analysis of the preparation data features can be implemented by a multidimensional scaling analysis method, such as the classical multidimensional scaling analysis method, based on the distance matrix between the preparation data features, the position of the point is found in the low-dimensional space, so that the distance in the low-dimensional space is as close to the original distance as possible.

[0096] Further, as an optional embodiment of the present invention, the calculating the interaction strength coefficient between the prepared tags includes:

[0097] Quantifying the prepared label to obtain a label quantization value, and calculating a label expected value corresponding to the prepared label based on the label quantization value;

[0098] Combining the label quantization value and the label expectation value, the interaction strength coefficient between the prepared labels is calculated by the following formula:

[0099]

[0100] Where A represents the interaction strength coefficient between the prepared tags, M a Indicates the label quantization value corresponding to the ath label in the prepared label. represents the expected value of the ath tag in the prepared tag, a and a+1 both represent the serial number corresponding to the prepared tag, M a+1 Indicates the label quantization value corresponding to the a+1th label in the prepared label. Indicates the a+1th in the preparation label

[0101] The expected value of the label corresponding to each label.

[0102] It should be explained that the label quantization value is the expression value corresponding to the prepared label, and the label expected value is the average value corresponding to the prepared label. Furthermore, the quantization processing of the prepared label can be achieved through a coding algorithm, such as binary coding; the calculation of the label expected value corresponding to the prepared label can be achieved through the arithmetic mean method.

[0103] The present invention calculates the indicator safety factor corresponding to the safety warning indicator based on the preparation characteristic dimension, and the safety level corresponding to the safety warning indicator can be understood through the indicator safety factor. If the indicator safety factor is high, it means that the aspect represented by the indicator is in a relatively safe state and the risk is low. For example, in chip preparation, if the indicator safety factor of a temperature-related safety warning indicator is high, it means that the current temperature is within a reasonable and safe range, and it is unlikely that the preparation process will fail or have adverse consequences due to temperature problems.

[0104] Specifically, the calculation of the indicator safety factor corresponding to the safety warning indicator based on the preparation characteristic dimension includes:

[0105] Standardizing the preparation characteristic dimension to obtain a standard dimension value;

[0106] The dimension weight corresponding to the preparation characteristic dimension is calculated, and the indicator safety factor corresponding to the safety warning indicator is calculated by combining the dimension weight and the standard dimension value through the following formula:

[0107]

[0108] Among them, B represents the indicator safety factor corresponding to the safety warning indicator, E b represents the standard dimension value corresponding to the bth dimension in the preparation characteristic dimension, b represents the serial number of the preparation characteristic dimension, r represents the number of preparation characteristic dimensions, E stdbRepresents the standardized safety threshold corresponding to the bth dimension in the preparation characteristic dimension.

[0109] It should be explained that the standard dimension value is the expression value obtained after eliminating the differences between the preparation characteristic dimensions. The standardization process eliminates the influence of different dimensional dimensions, making the data of different dimensions comparable. The dimension weight represents the importance corresponding to the preparation characteristic dimension. The standardized safety threshold is a standard value for measuring whether the preparation characteristic dimension is safe. Furthermore, the standardization process of the preparation characteristic dimension can be achieved through the Z-score standardization method; the calculation of the dimension weight corresponding to the preparation characteristic dimension can be achieved through the hierarchical analysis method.

[0110] The present invention evaluates the equipment safety performance corresponding to the chip process equipment based on the indicator safety factor, so as to understand the equipment operation reliability of the chip process equipment, thereby laying a foundation for the subsequent formulation of the security management strategy corresponding to the storage chip. It should be explained that the equipment safety performance represents the corresponding operation reliability of the chip process equipment.

[0111] For example, a higher indicator safety factor (such as close to 1): it is believed that the equipment has good safety performance in the current state, such as the exposure intensity, alignment accuracy and temperature stability of the lithography machine are generally close to the safety threshold, the equipment operation is relatively reliable, and the risk of failure is relatively low. Specifically, the exposure intensity fluctuates within an acceptable range and will not have a significant impact on the lithography effect of the chip; the alignment accuracy can meet the high-precision requirements of chip manufacturing and ensure the accurate alignment of each circuit layer; the temperature stability is good and will not cause deviations in the lithography process due to temperature changes. A lower indicator safety factor: If the indicator safety factor is low, for example, it means that there are major problems with the safety performance of the equipment, which may mean that the exposure intensity is unstable and exceeds the safety range, resulting in over- or under-exposure of some areas of the chip; poor alignment accuracy may cause errors in the circuit connection of the chip; poor temperature stability may cause changes in the performance of the photoresist and affect the quality of the chip.

[0112] S3. Collect the chip node image and chip circuit diagram of the storage chip in the chip process equipment, analyze the chip physical properties corresponding to the storage chip based on the chip node image, analyze the micro circuit characteristics corresponding to the storage chip based on the chip circuit diagram, and calculate the quality trust index corresponding to the storage chip by combining the micro circuit characteristics and the chip physical properties.

[0113] The present invention analyzes the chip physical properties corresponding to the storage chip based on the chip node image, thereby obtaining the physical characteristics corresponding to the storage chip, increasing the understanding of the physical properties of the storage chip, and providing a basis for subsequent calculation of the quality trust index corresponding to the storage chip.

[0114] It should be explained that the chip node image is an image of the memory chip after the last process in the chip process equipment is completed and before the process of the next device begins, the chip circuit diagram is the circuit design blueprint and functional logic expression corresponding to the memory chip, and the chip physical properties are the physical properties corresponding to the memory chip. Furthermore, the chip node image of the memory chip in the chip process equipment can be collected by an industrial camera, and the chip circuit diagram of the memory chip in the chip process equipment can be realized by a scanning electron microscope.

[0115] In detail, analyzing the chip physical properties corresponding to the storage chip based on the chip node image includes:

[0116] Performing image optimization processing on the chip node image to obtain an optimized chip image;

[0117] Performing subject extraction processing on the optimized chip image to obtain a subject chip image;

[0118] Identify a chip package outline in the main chip image, and calculate an outline completeness corresponding to the memory chip based on the chip package outline;

[0119] Extracting chip pixel information corresponding to the main chip image, and calculating a physical property value corresponding to the storage chip based on the chip pixel information;

[0120] Based on the physical property value and the outline completeness, a chip physical property corresponding to the storage chip is generated.

[0121] It should be explained that the optimized chip image is the image obtained after the chip node image is optimized, such as noise reduction, contrast enhancement and other processing; the main chip image is the image obtained after the background image in the optimized chip image is removed; the chip package outline is the appearance shape corresponding to the chip in the main chip image; the outline completeness indicates the corresponding degree of integrity of the storage chip; the chip pixel information is various information about the chip in the main chip image; the physical property value is a quantifiable feature description corresponding to the storage chip, such as the size parameters, length, width, thickness, etc. of the chip.

[0122] Furthermore, the image optimization processing of the chip node image can be achieved through image enhancement methods, such as contrast enhancement methods, mean filtering algorithms and color enhancement methods; the main body extraction processing of the optimized chip image can be achieved through a threshold segmentation method; the recognition of the chip package contour in the main chip image can be achieved through an edge detection algorithm, such as the Canny edge detection algorithm; the extraction of chip pixel information corresponding to the main chip image can be achieved through a convolutional neural network, such as a U-type network, which is a convolutional neural network architecture, the main feature of which is the use of an encoder-decoder structure and jump connections; based on the chip pixel information, the physical property value corresponding to the storage chip is calculated, such as the length of the chip pixel information is L pixels, the width is W pixels, and the ratio between the pixel and the actual size is known to be 1 pixel corresponding to k millimeters, then the actual length of the chip = L×k millimeters, the actual width = W×k millimeters, the chip thickness is R pixels, and according to the proportional relationship, the actual thickness of the chip = R×k millimeters; the physical property value and the contour integrity are used as the chip physical properties corresponding to the storage chip.

[0123] Further, as an optional embodiment of the present invention, the calculating the outline completeness corresponding to the memory chip based on the chip package outline includes:

[0124] Acquire a standard package outline corresponding to the memory chip, and respectively perform vector processing on the chip package outline and the standard package outline to obtain a first outline vector and a second outline vector;

[0125] Based on the first contour vector, calculating the contour perimeter corresponding to the chip package contour to obtain a first contour perimeter;

[0126] Based on the second contour vector, calculating the contour perimeter corresponding to the standard package contour to obtain a second contour perimeter;

[0127] and measuring the contour areas corresponding to the chip package contour and the standard package contour to obtain a first contour area and a second contour area;

[0128] The profile integrity of the memory chip is calculated by the following formula:

[0129]

[0130] Among them, F represents the completeness of the contour corresponding to the memory chip, P1 represents the perimeter of the first contour, P2 represents the perimeter of the second contour, S1 represents the area of ​​the first contour, and S2 represents the area of ​​the second contour.

[0131] It should be explained that the standard package outline is the ideal outline corresponding to the memory chip, the first outline vector and the second outline vector are the digital feature representations corresponding to the chip package outline and the standard package outline respectively, the first outline perimeter is the outer length corresponding to the chip package outline, the second outline perimeter is the outer length corresponding to the standard package outline, and the first outline area and the second outline area are the sizes of the areas covered on the planes corresponding to the chip package outline and the standard package outline respectively.

[0132] Furthermore, the acquisition of the standard package contour corresponding to the storage chip can be achieved through the official documents of the chip manufacturer; the vectorization processing of the chip package contour and the standard package contour can be achieved through the Fourier descriptor method; the distance value between the first contour vectors is calculated, which is the contour perimeter corresponding to the chip package contour, and the first contour perimeter is obtained; the distance value between the second contour vectors is calculated, which is the contour perimeter corresponding to the standard package contour, and the second contour perimeter is obtained; the measurement of the contour area corresponding to the chip package contour and the standard package contour can be achieved through the pixel counting method, which binarizes the image so that the pixel value inside the contour is 1 and the pixel value outside is 0, and the number of pixels with a pixel value of 1 in the image is counted, and this number is equal to the area of ​​the contour, thereby obtaining the first contour area and the second contour area.

[0133] The present invention analyzes the microscopic circuit features corresponding to the memory chip based on the chip circuit diagram, thereby providing an in-depth understanding of the specific characteristic performance of the memory chip. Furthermore, by combining the microscopic circuit features with the physical properties of the chip, the quality trust index corresponding to the memory chip is calculated, and the quality reliability of the memory chip can be understood through the quality trust index.

[0134] It should be explained that the microscopic circuit characteristics are the manifestation of the intrinsic essential properties corresponding to the memory chip, such as the type and size of transistors, the wiring layout of circuits, the structure and organization of storage units, the transmission and processing mechanism of signals, etc., which are all specific manifestations of microscopic circuit characteristics as the intrinsic essential properties of memory chips. The quality trust index represents the quality reliability of the memory chip. Furthermore, based on the chip circuit diagram, the microscopic circuit characteristics corresponding to the memory chip are analyzed, such as observing the surface morphology of the memory chip, the layout and connection method of metal lines, the shape and size of components such as transistors and capacitors. Image analysis software can be used to measure and analyze microscope images, such as measuring the width, spacing and length of the lines. By comparing images of different areas, the unevenness and defects of the microstructure can be found, such as line breakage, component damage or impurity contamination, so as to obtain the microscopic circuit characteristics corresponding to the memory chip.

[0135] Specifically, the combining the microscopic circuit features and the chip physical properties to calculate the quality trust index corresponding to the memory chip includes:

[0136] Querying the standard circuit characteristics and standard physical properties corresponding to the memory chip, and calculating the characteristic difference between the standard circuit characteristics and the microscopic circuit characteristics;

[0137] Calculating the property difference between the standard physical property and the chip physical property;

[0138] Combining the feature difference and the attribute difference, the quality trust index corresponding to the storage chip is calculated by the following formula:

[0139]

[0140] Among them, G represents the quality trust index corresponding to the storage chip, H d represents the feature difference corresponding to the dth feature in the micro circuit feature, N e It represents the attribute difference corresponding to the e-th attribute in the chip physical properties, d represents the serial number corresponding to the micro circuit feature, p represents the number of features of the micro circuit feature, e represents the serial number corresponding to the chip physical property, and u represents the number of attributes of the chip physical property.

[0141] It should be explained that the standard circuit characteristics and the standard physical properties are respectively the ideal reference state and quality judgment benchmark of the memory chip, the characteristic difference degree indicates the difference degree between the standard circuit characteristics and the microscopic circuit characteristics, and the property difference degree indicates the difference degree between the standard physical properties and the chip physical properties. Furthermore, the query of the standard circuit characteristics and standard physical properties corresponding to the memory chip can be achieved through the official website of the chip manufacturer; the characteristic difference between the standard circuit characteristics and the microscopic circuit characteristics is calculated, and the characteristic difference is divided by the standard circuit characteristics to obtain the characteristic difference degree; the calculation principle of the property difference degree is the same as that of the characteristic difference degree, which will not be elaborated here.

[0142] S4. Acquire a storage area corresponding to the storage chip, collect storage environment factors corresponding to the storage area, and analyze the storage compatibility of the storage chip in the storage area based on the storage environment factors.

[0143] The present invention can effectively evaluate the adaptability and reliability of the storage chip in the storage environment by analyzing the storage fit of the storage chip in the storage area based on the storage environment factors, and provides a basis for the subsequent formulation of security management strategies corresponding to the storage chip. It should be explained that the storage area is the physical storage space corresponding to the storage chip, and the storage environment factors are the specific environmental parameters corresponding to the storage area, such as temperature, humidity, air pressure and other factors and values. The storage area corresponding to the storage chip can be obtained through manual investigation. Furthermore, the collection of storage environment factors corresponding to the storage area can be achieved through an environmental monitoring system. The environmental monitoring system is composed of multiple sensor nodes, and transmits data to a central monitoring station through a wireless network or a wired connection.

[0144] In detail, analyzing the storage compatibility of the storage chip in the storage area based on the storage environment factor includes:

[0145] Querying chip manufacturing materials corresponding to the memory chip, and analyzing material environmental characteristics corresponding to the chip manufacturing materials;

[0146] Analyzing the environmental factor indicators in the material environmental characteristics, and extracting the associated environmental factors corresponding to the storage chip from the storage environmental factors based on the environmental factor indicators;

[0147] The coupling coefficient between the material environmental characteristic and the associated environmental factor is calculated, and based on the coupling coefficient, the storage compatibility of the storage chip in the storage area is analyzed.

[0148] It should be explained that the chip manufacturing material is the basic material corresponding to the memory chip, and the material environmental characteristics are the environment-specific properties corresponding to the chip manufacturing material, such as the material's sensitivity to temperature changes, hygroscopicity and moisture resistance to humidity, adaptability to changes in air pressure, shielding and sensitivity to electromagnetic interference, etc. The environmental factor index is the environment type in the material environmental characteristics, the associated environmental factor is the environmental indicator in the storage environmental factor that is related to the memory chip, and the coupling coefficient represents the degree of correlation between the material environmental characteristics and the associated environmental factors.

[0149] Furthermore, the query of the chip manufacturing material corresponding to the storage chip can be realized through the chip product data manual; the material environmental characteristics corresponding to the chip manufacturing material can be obtained by analyzing the experimental test data of the chip; the corresponding coupling coefficient can be obtained by calculating the ratio between the value corresponding to the material environmental characteristics and the value of the associated environmental factor. For example, in terms of material environmental characteristics, for example, the resistance change characteristic of the material at a specific temperature is an important indicator. When the temperature is 25°C, the resistance value of the material is 100 ohms. As the temperature rises, at 35°C, the resistance value becomes 120 ohms. The associated environmental factor is the temperature of the storage area. After measurement, the temperature change range of the storage area is between 20°C and 40°C. Then, the calculation Calculate the coupling coefficient between the environmental characteristics of the material and the temperature, an associated environmental factor. First, calculate the ratio of the material resistance change value to the temperature change value. The resistance change value is 120 ohms-100 ohms=20 ohms, and the temperature change value is 35℃-25℃=10℃. The coupling coefficient=resistance change value / temperature change value=20 ohms / 10℃=2 ohms / ℃; sum the coupling coefficients to obtain a total coupling coefficient value. According to the total coupling coefficient value, analyze the storage compatibility of the memory chip in the storage area. If the total coupling coefficient value is 0.8, it indicates that the storage compatibility is high. If the total coupling coefficient value is 0.5, it indicates that the storage compatibility is medium. If the total coupling coefficient value is less than 0.5, it indicates that the storage compatibility is low.

[0150] S5. Based on the device safety performance, the quality trust index, and the storage compatibility, formulate a security management strategy corresponding to the storage chip, and based on the security management strategy, perform security management of the storage chip during preparation to obtain a management result.

[0151] The present invention formulates a security management strategy corresponding to the storage chip based on the device safety performance, the quality trust index, and the storage compatibility. Combining multiple indicators can improve the accuracy of the formulation of the security management strategy, and based on the security management strategy, the security management of the storage chip during preparation is performed, thereby improving the comprehensiveness of the security management of the storage chip during preparation. It should be explained that the security management strategy is a specific method of security management corresponding to the storage chip. Furthermore, the formulation steps of the security management strategy corresponding to the storage chip are: assuming that the device safety performance, quality trust index and storage compatibility of the storage chip are high, the existing strict physical security protection measures are maintained, and equipment safety inspections and maintenance are performed regularly to ensure that the device casing, interface, etc. are not damaged, and to prevent external force damage from affecting the storage chip. At the same time, we will continue to optimize access control permissions to prevent unauthorized access, maintain current production quality control standards, work closely with suppliers, obtain the latest industry technology and quality improvement information in a timely manner, conduct regular performance tests on storage chips to ensure that their performance is always at a high level, and continue to monitor the temperature, humidity and other factors of the storage environment to ensure that the environment is stable within a range suitable for storage chips. The frequency of adjusting the storage environment can be appropriately reduced, but an emergency response mechanism still needs to be established to cope with possible sudden environmental changes. If the device safety performance of the storage chip is low, the quality trust index is low, and the storage fit is low, then immediately strengthen physical security protection and increase Monitor equipment, improve the robustness of equipment casings, re-evaluate access control strategies, strengthen user identity authentication and authorization management, prevent data leaks and malicious attacks, comprehensively review production processes, identify links that may affect quality and make improvements, increase the frequency and strictness of quality inspections on storage chips, work with suppliers to analyze the root causes of quality problems and develop solutions, comprehensively optimize the storage environment, install environmental conditioning equipment, monitor environmental factors such as temperature and humidity in real time, consider replacing storage chips that are more suitable for the current storage environment or taking special protective measures, such as using moisture-proof and shock-proof packaging, etc., in order to generate a security management strategy corresponding to the storage chip.

[0152] Compared with the problems described in the background technology, the present invention formulates safety warning indicators corresponding to the chip process equipment based on the chip manufacturing specifications, and can obtain the safety risk quantification standards corresponding to the chip process equipment, thereby laying a foundation for the subsequent calculation of the indicator safety factor corresponding to the safety warning indicator. The present invention analyzes the preparation characteristic dimensions corresponding to the chip process equipment based on the chip preparation data, and can obtain a description of the different preparation-related characteristics of the chip process equipment, thereby improving the calculation accuracy of the indicator safety factor corresponding to the safety warning indicator. The present invention analyzes the chip physical properties corresponding to the memory chip based on the chip node image, and can obtain the physical properties corresponding to the memory chip, thereby increasing the accuracy of the calculation of the indicator safety factor corresponding to the safety warning indicator. The understanding of the physical properties provides a basis for the subsequent calculation of the quality trust index corresponding to the storage chip. The present invention analyzes the storage fit of the storage chip in the storage area based on the storage environment factors, which can effectively evaluate the adaptability and reliability of the storage chip in the storage environment, and provides a basis for the subsequent formulation of the security management strategy corresponding to the storage chip. The present invention formulates the security management strategy corresponding to the storage chip based on the equipment safety performance, the quality trust index, and the storage fit. The combination of multiple indicators can improve the accuracy of the formulation of the security management strategy, and based on the security management strategy, the security management of the storage chip under preparation is performed, thereby improving the comprehensiveness of the security management of the storage chip under preparation. Therefore, the security management method applied to the preparation of storage chips proposed in the present invention improves the comprehensiveness of the security management under the preparation of storage chips.

[0153] Embodiment 2:

[0154] like Figure 2 1 is a functional module diagram of a security management system for storage chip preparation provided by an embodiment of the present invention.

[0155] The security management system 100 for storage chip preparation described in the present invention can be installed in an electronic device. According to the functions implemented, the security management system 100 for storage chip preparation can include a security early warning index formulation module 101, an equipment safety performance evaluation module 102, a quality trust index calculation module 103, a storage fit calculation module 104 and a security management module 105. The module described in the present invention can also be called a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0156] In this embodiment, the functions of each module / unit are as follows:

[0157] The safety warning indicator formulation module 101 is used to obtain the memory chip under preparation, query the chip process equipment of the memory chip during the preparation process, determine the chip manufacturing specification corresponding to the chip process equipment, and formulate the safety warning indicator corresponding to the chip process equipment based on the chip manufacturing specification;

[0158] The equipment safety performance evaluation module 102 is used to collect chip preparation data of the memory chip in the preparation process, analyze the preparation characteristic dimension corresponding to the chip process equipment based on the chip preparation data, calculate the indicator safety factor corresponding to the safety warning indicator based on the preparation characteristic dimension, and evaluate the equipment safety performance corresponding to the chip process equipment based on the indicator safety factor;

[0159] The quality trust index calculation module 103 is used to collect the chip node image and chip circuit diagram of the memory chip in the chip process equipment, analyze the chip physical properties corresponding to the memory chip based on the chip node image, analyze the micro circuit features corresponding to the memory chip based on the chip circuit diagram, and calculate the quality trust index corresponding to the memory chip by combining the micro circuit features and the chip physical properties;

[0160] The storage compatibility calculation module 104 is used to obtain the storage area corresponding to the storage chip, collect storage environment factors corresponding to the storage area, and analyze the storage compatibility of the storage chip in the storage area based on the storage environment factors;

[0161] The security management module 105 is used to formulate a security management policy corresponding to the storage chip based on the device safety performance, the quality trust index, and the storage compatibility, and to perform security management of the storage chip during preparation based on the security management policy to obtain a management result.

[0162] In detail, each module described in a security management system 100 for storage chip preparation described in the embodiment of the present application is used in the same manner as described above. Figure 1 The technical means described in the safety management method applied to the preparation of memory chips are the same and can produce the same technical effects, which will not be repeated here.

[0163] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A security management method for storage chip preparation, characterized in that: The method comprises: Obtain the memory chip under preparation, and query the chip process equipment used in the preparation process of the memory chip, determine the chip manufacturing specification corresponding to the chip process equipment, and formulate the safety warning indicator corresponding to the chip process equipment based on the chip manufacturing specification; Collect chip preparation data of the memory chip in the preparation process, analyze the preparation characteristic dimension corresponding to the chip process equipment based on the chip preparation data, calculate the indicator safety factor corresponding to the safety warning indicator based on the preparation characteristic dimension, and evaluate the equipment safety performance corresponding to the chip process equipment based on the indicator safety factor; Collecting a chip node image and a chip circuit diagram of the memory chip in the chip process equipment, analyzing chip physical properties corresponding to the memory chip based on the chip node image, analyzing microscopic circuit features corresponding to the memory chip based on the chip circuit diagram, and calculating a quality trust index corresponding to the memory chip in combination with the microscopic circuit features and the chip physical properties; Acquire a storage area corresponding to the storage chip, collect storage environment factors corresponding to the storage area, and analyze the storage compatibility of the storage chip in the storage area based on the storage environment factors; Based on the device safety performance, the quality trust index, and the storage compatibility, a security management strategy corresponding to the storage chip is formulated. Based on the security management strategy, security management of the storage chip during preparation is performed to obtain a management result.

2. The security management method for storage chip preparation according to claim 1, characterized in that: The step of formulating safety warning indicators corresponding to the chip process equipment based on the chip manufacturing specification includes: Performing character recognition on the chip manufacturing protocol to obtain protocol characters; Performing semantic analysis on the specified characters to obtain the meaning of the specified characters; Based on the meaning of the protocol characters, identifying the security protocol characters in the protocol characters; Extracting key characters from the security specification characters to obtain specification key characters; Based on the key characters of the protocol, safety warning indicators corresponding to the chip process equipment are formulated.

3. The security management method for storage chip preparation according to claim 1, characterized in that: The step of analyzing the manufacturing characteristic dimension corresponding to the chip process equipment based on the chip manufacturing data includes: Purifying the chip preparation data to obtain purified preparation data; Performing label recognition on the purification preparation data to obtain a preparation label; calculating the interaction strength coefficients between the preparation labels, and screening out characteristic preparation labels from the preparation labels based on the interaction strength coefficients; Based on the characteristic preparation label, the target preparation data is subjected to data screening processing to obtain characteristic preparation data; Extracting features from the characteristic preparation data to obtain preparation data features; Performing dimension analysis on the fabrication data features to obtain fabrication characteristic dimensions corresponding to the chip process equipment.

4. The security management method for storage chip preparation as claimed in claim 3, characterized in that: The calculating the interaction strength coefficient between the prepared tags comprises: Quantifying the prepared label to obtain a label quantization value, and calculating a label expected value corresponding to the prepared label based on the label quantization value; Combining the label quantization value and the label expectation value, the interaction strength coefficient between the prepared labels is calculated by the following formula: Where A represents the interaction strength coefficient between the prepared tags, M a Indicates the label quantization value corresponding to the ath label in the prepared label. represents the expected value of the ath tag in the prepared tag, a and a+1 both represent the serial number corresponding to the prepared tag, M a+1 Indicates the label quantization value corresponding to the a+1th label in the prepared label. Indicates the expected value of the label corresponding to the a+1th label in the prepared label.

5. The security management method for storage chip preparation according to claim 1, characterized in that: The step of calculating the indicator safety factor corresponding to the safety warning indicator based on the preparation characteristic dimension includes: Standardizing the preparation characteristic dimension to obtain a standard dimension value; The dimension weight corresponding to the preparation characteristic dimension is calculated, and the indicator safety factor corresponding to the safety warning indicator is calculated by combining the dimension weight and the standard dimension value through the following formula: Among them, B represents the indicator safety factor corresponding to the safety warning indicator, E b represents the standard dimension value corresponding to the bth dimension in the preparation characteristic dimension, b represents the serial number of the preparation characteristic dimension, r represents the number of preparation characteristic dimensions, E stdb Represents the standardized safety threshold corresponding to the bth dimension in the preparation characteristic dimension.

6. The security management method for storage chip preparation according to claim 1, characterized in that: The analyzing the chip physical properties corresponding to the storage chip based on the chip node image includes: Performing image optimization processing on the chip node image to obtain an optimized chip image; Performing subject extraction processing on the optimized chip image to obtain a subject chip image; Identify a chip package outline in the main chip image, and calculate an outline completeness corresponding to the memory chip based on the chip package outline; Extracting chip pixel information corresponding to the main chip image, and calculating a physical property value corresponding to the storage chip based on the chip pixel information; Based on the physical property value and the outline completeness, a chip physical property corresponding to the storage chip is generated.

7. The security management method for storage chip preparation as claimed in claim 6, characterized in that: The calculating the outline completeness corresponding to the memory chip based on the chip package outline includes: Acquire a standard package outline corresponding to the memory chip, and respectively perform vector processing on the chip package outline and the standard package outline to obtain a first outline vector and a second outline vector; Based on the first contour vector, calculating the contour perimeter corresponding to the chip package contour to obtain a first contour perimeter; Based on the second contour vector, calculating the contour perimeter corresponding to the standard package contour to obtain a second contour perimeter; and measuring the contour areas corresponding to the chip package contour and the standard package contour to obtain a first contour area and a second contour area; The profile integrity of the memory chip is calculated by the following formula: Among them, F represents the completeness of the contour corresponding to the memory chip, P1 represents the perimeter of the first contour, P2 represents the perimeter of the second contour, S1 represents the area of ​​the first contour, and S2 represents the area of ​​the second contour.

8. The security management method for storage chip preparation as claimed in claim 1, characterized in that: The calculating the quality trust index corresponding to the memory chip by combining the microscopic circuit features and the chip physical properties includes: Querying the standard circuit characteristics and standard physical properties corresponding to the memory chip, and calculating the characteristic difference between the standard circuit characteristics and the microscopic circuit characteristics; Calculating the property difference between the standard physical property and the chip physical property; Combining the feature difference and the attribute difference, the quality trust index corresponding to the storage chip is calculated by the following formula: Among them, G represents the quality trust index corresponding to the storage chip, H d represents the feature difference corresponding to the dth feature in the micro circuit feature, N e represents the attribute difference corresponding to the e-th attribute in the chip physical properties, d represents the serial number corresponding to the micro circuit feature, p represents the feature number of the micro circuit feature, e represents the serial number corresponding to the chip physical property, and u represents the attribute number of the chip physical property.

9. The security management method for storage chip preparation according to claim 1, characterized in that: The analyzing the storage compatibility of the storage chip in the storage area based on the storage environment factor includes: Querying chip manufacturing materials corresponding to the memory chip, and analyzing material environmental characteristics corresponding to the chip manufacturing materials; Analyzing the environmental factor indicators in the material environmental characteristics, and extracting the associated environmental factors corresponding to the storage chip from the storage environmental factors based on the environmental factor indicators; The coupling coefficient between the material environmental characteristic and the associated environmental factor is calculated, and based on the coupling coefficient, the storage compatibility of the storage chip in the storage area is analyzed.

10. A security management system used in the preparation of storage chips, characterized in that: The system comprises: A safety warning indicator formulation module is used to obtain the memory chip under preparation, query the chip process equipment used in the preparation process of the memory chip, determine the chip manufacturing specification corresponding to the chip process equipment, and formulate the safety warning indicator corresponding to the chip process equipment based on the chip manufacturing specification; An equipment safety performance evaluation module, used to collect chip preparation data of the memory chip in the preparation process, analyze the preparation characteristic dimension corresponding to the chip process equipment based on the chip preparation data, calculate the indicator safety factor corresponding to the safety warning indicator based on the preparation characteristic dimension, and evaluate the equipment safety performance corresponding to the chip process equipment based on the indicator safety factor; A quality trust index calculation module, used for collecting chip node images and chip circuit diagrams of the memory chip in the chip process equipment, analyzing chip physical properties corresponding to the memory chip based on the chip node images, analyzing microscopic circuit features corresponding to the memory chip based on the chip circuit diagram, and calculating a quality trust index corresponding to the memory chip in combination with the microscopic circuit features and the chip physical properties; A storage compatibility calculation module, used to obtain a storage area corresponding to the storage chip, collect storage environment factors corresponding to the storage area, and analyze the storage compatibility of the storage chip in the storage area based on the storage environment factors; The security management module is used to formulate a security management policy corresponding to the storage chip based on the device safety performance, the quality trust index, and the storage compatibility, and based on the security management policy, perform security management of the storage chip during preparation to obtain a management result.

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