Full-chip power supply network design method

Abstract

The invention discloses a full-chip power supply network design method, which comprises the following steps of: 1, analyzing power consumption, and respectively calculating maximum transient power consumption and average power consumption of a chip under different application conditions; 2, estimating parameters of the power supply network, and estimating the parameters of the power supply network so as to provide reference design for the power supply network; 3, designing a power supply network, namely determining the density of the power supply network, the number of power supply IOs and selecting the style of a power supply rail; and step 4, analyzing network grid points. The full-chip power supply network is optimally designed, so that the chip area occupied by the power supply network is minimum on the premise of ensuring that voltage drop and electromigration are within ideal ranges, unlimited congestion is not caused, the adaptability of the power supply network and a chip is improved, the area of the full-chip power supply network is smaller than that of a uniform distribution method, and the power supply network can be applied to the power supply network. And the working life of the chip is greatly prolonged.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply network design, and more specifically to a full-chip power supply network design method. Background Art

[0002] With the continuous development of integrated circuit technology, the power consumption of chips is also increasing. The optimized design of the power supply network is extremely important for the performance and stability of the chip. As one of the core parts of the chip, the power supply network must meet its high power consumption requirements while ensuring the performance and stability of the chip. Therefore, optimizing the design of the new power supply network can effectively improve the performance and stability of the chip and provide technical support for its promotion in the application field. It is necessary to analyze the power supply network of the entire chip, find out the existing problems, optimize the design of the power supply network of the entire chip, and improve stability and efficiency.

[0003] In the prior art, the resistance and inductance in the power supply network will cause voltage drop when current passes through, affecting the power supply voltage of various parts of the chip. The noise in the power supply network also affects the normal operation of other modules, making it difficult to evaluate its noise situation. The chip power consumption analysis capability is lagging behind, the layout area occupied by the power supply network is high, and the energy consumption analysis capability is lagging behind. Summary of the invention

[0004] In view of the deficiencies of the above-mentioned technologies, the present invention discloses a full-chip power supply network design method, which optimizes the design of the full-chip power supply network to ensure that the voltage drop and electromigration are within the ideal range, minimizes the chip area occupied by the power supply network, does not cause unlimited congestion, and improves the compatibility of the power supply network with the chip.

[0005] A full-chip power network design method, the method comprising:

[0006] Step 1: Power consumption analysis: Use RTL-level simulation technology to calculate the maximum transient power consumption and average power consumption of the chip under different application conditions.

[0007] Step 2: Estimation of power network parameters: Estimation of power network parameters through electromagnetic model, so as to provide reference design for the power network;

[0008] Step 3: Designing the power network, including determining the density of the power network, the number of power IOs, and selecting the style of the power rail;

[0009] Step 4: Use network topology analysis technology to analyze the network grid and obtain a power integrity report, mainly for voltage drop and electromigration analysis.

[0010] Further, the power consumption analysis includes RTL level power consumption analysis and gate circuit level power consumption analysis;

[0011] The RTL-level power analysis uses a spreadsheet analysis to find the best power-conscious library and design architecture. After the library is selected, the design compiler and power compiler are used instead of the spreadsheet to provide data to the spreadsheet. In order to use the spreadsheet analysis method, the number and activity level of each type of library unit are estimated, and the energy consumed by each type of unit when switching is obtained. The internal power consumption formula of each type of unit in a module is:

[0012] (1)

[0013] In formula (1), For the power consumption speed ratio, the power consumption of all different types of units in a module is added together to obtain an estimate of the total internal dynamic power consumption of this module. Before synthesis, the number of gates is estimated based on the selected architecture and the understanding of the design itself;

[0014] The gate level power consumption analysis is to obtain accurate power consumption estimation value from the power compiler according to the actual number of gates and the activity obtained by simulation after the RTL level power consumption analysis is completed. In VCS, the same instructions as the RTL level power consumption analysis are used to generate SAIF files. The physical compiler tool uses instructions to improve the accuracy of the load after physical optimization. The instructions generate SPEF files annotated with Steiner paths and parasitic resistance and capacitance estimation values. After the layout is completed, the simulation can generate a value transformation dump file for basic power analysis. The value transformation dump file records the value that becomes a signal value during the simulation process and provides information on the node activity, structural data system connectivity, path delay, timing and time of the design.

[0015] Furthermore, the estimation of the power network parameters includes determining the number and position of PADs and calculating the line width spacing of the power grid within the chip;

[0016] The number and location of PG units. In the package design, PAD forms a PAD ring around the internal logic of the chip, and PG units should be distributed in pairs. According to the power consumption and operating voltage of the chip, the total current is estimated as follows:

[0017] (2)

[0018] In formula (2), is the total current inside the chip, is the total power consumption inside the chip, is the total voltage inside the chip, The chip power consumption analysis tool is used to obtain that PAD represents the IO unit of the chip. The formula for determining the number of PADs and the required power supply is:

[0019] (3)

[0020] In formula (3), is the minimum value of the current passing through, M is the minimum number of PG units allowed by the design. When PAD resources allow, place more PG units to reduce the resistance voltage drop effect, reduce the parasitic inductance on the power connection line, and reduce the voltage fluctuation caused by instantaneous current changes;

[0021] According to the silicon area of ​​the chip and the overall power consumption of the chip, the average power consumption per unit area of ​​the silicon chip is:

[0022] (4)

[0023] In formula (4), is the total power consumption of the internal logic, is the average power consumption per unit area of ​​silicon wafer, For the total area of ​​the silicon wafer, the formula for estimating the average current consumed by a fixed length of standard cell row is:

[0024] (5)

[0025] In formula (5), i is the length of The power consumed by the standard cell row is W, and the height of the standard cell row is W. In practical applications, the length of each standard cell row is between tens and hundreds of microns. The length of n series is The voltage drop formula on the power rail is:

[0026] (6)

[0027] In formula (6), I m represents the current on the mth long standard cell row, and R represents the length The resistance on the metal power rail, R, is derived from the process parameters, and the current formula on the mth standard cell row is:

[0028] (7)

[0029] In formula (7), i is the length of The power consumed by the standard cell row, n represents the number of series lengths, then the final n series lengths are The voltage drop formula on the power rail is:

[0030] (8)

[0031] The power rail inside the chip is bidirectional. The spacing between the power supply networks is determined. After the average power consumption is calculated, the calculated value is multiplied by a coefficient to obtain the peak power consumption, and the coefficient is 1.5.

[0032] Furthermore, the chip power network design topology optimization method:

[0033] 1) Problem description: According to the structural characteristics of the low-level chip power network, the power rail spacing is the height of the standard unit. The chip power network design topology optimization is aimed at the high-level chip power network. Under the premise of ensuring that there is no voltage drop violation in the chip power network, the layout area occupied by the power network is reduced. The constraint objective function is:

[0034] (9)

[0035] In formula (9), G pall For the updated power network topology diagram, G k G pall The k-th topological graph in the table has the following constraints: , E k is the topological graph G k The edge set in E H For E k The edge set in the high-level chip power network, and w j For edge e j The length and width of the corresponding power point segment, ΔV is the node voltage drop, and its value is the difference between the ideal power supply voltage and the node voltage;

[0036] 2) Topology update. During the topology update of the chip power network, new power lines are constantly inserted. The edges in the virtual network will gradually be replaced by different types of power lines. j The weight w j Defined as:

[0037] (10)

[0038] In formula (10), w j is the virtual edge e j The weight of h is the height of the high-level chip power network, E H For E k The edge set in the high-level chip power network, R Lj Indicates the voltage of the high-level chip power network;

[0039] After the chip power network topology is generated, the power network is analyzed and the analysis result is compared with the constraint condition (9) to obtain an approximate optimal solution based on this type of topology, and the objective function is achieved while satisfying the constraint condition.

[0040] Furthermore, the architecture design of the full-chip power supply network includes: multiple metal layers, the multiple metal layers include a first metal layer and a second metal layer, and the power supply network design method is:

[0041] A first power line and a first ground line arranged in parallel along a first direction on a first metal layer of the full-chip power network;

[0042] A second power line and a second ground line are arranged in parallel along a second direction on the second metal layer of the full-chip power network, wherein the first direction is perpendicular to the second direction;

[0043] The first power line and the second power line are connected at the overlapping point by a through hole, the first ground line and the second ground line are connected at the overlapping points by a through hole, the length of the second power line is less than the threshold of the length of the first power line, there is no overlapping point between the second power line and the first ground line, the length of the second ground line is less than the threshold of the length of the second ground line, and there is no overlapping point between the second ground line and the first power line.

[0044] Furthermore, in the chip, the wiring layer used is implemented by metal M4 and via V3. A layer of M4 is added in the vertical direction with a width of 2μm for power supply and ground line spacing of 20μm and a group spacing of 50μm, so that the power supply spacing of the entire network standard unit is reduced, avoiding congestion in an area less than 2mm*2mm in length*width.

[0045] Furthermore, the full-chip power network further includes other metal layers located above the second metal layer;

[0046] The other metal layers are used to lay out metal lines based on preset wiring rules.

[0047] Positive beneficial effects:

[0048] By optimizing the design of the full-chip power supply network, the chip area occupied by the power supply network is minimized while ensuring that the voltage drop and electromigration are within the ideal range, and will not cause unlimited congestion, thereby improving the compatibility of the power supply network with the chip. As a result, the area of ​​the full-chip power supply network is smaller than that of the uniform distribution method, with good resource utilization, which is suitable for the application needs of the ever-expanding scale of the full-chip power supply network. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0050] Figure 1 A schematic diagram of an SRAM power ring expansion structure of a full-chip power network design method of the present invention;

[0051] Figure 2 A comparison diagram of voltage drop distribution before optimization and voltage drop distribution after optimization in a full-chip power network design method of the present invention;

[0052] Figure 3 A virtual network diagram established in a full-chip power network design method of the present invention;

[0053] Figure 4 The initialization network diagram is established in a full-chip power supply network design method of the present invention. DETAILED DESCRIPTION

[0054] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0055] like Figure 1 As shown, a full-chip power network design method includes:

[0056] Step 1: Power consumption analysis: Use RTL-level simulation technology to calculate the maximum transient power consumption and average power consumption of the chip under different application conditions.

[0057] In a further technical embodiment, power consumption analysis is a key step in integrated circuit design, which helps to evaluate the energy consumption performance of the chip under different application scenarios. Power consumption analysis is performed using RTL level simulation technology to provide power consumption estimation of the chip at the behavioral level. The following is a method for calculating the maximum transient power consumption and average power consumption of the chip under different application scenarios using RTL level simulation technology:

[0058] Maximum transient power consumption analysis:

[0059] 1. Behavioral level simulation:

[0060] Simulation is performed using RTL code written in hardware description language (HDL) to simulate the behavior of the chip in a specific application scenario.

[0061] 2. Event-driven simulation:

[0062] During the simulation, all events that occur within the clock cycle are recorded, including data transfer, register update, instruction execution, etc.

[0063] 3. Power consumption calculation:

[0064] For each event, the corresponding power consumption is calculated, including dynamic power consumption (related to switching activities) and static power consumption (related to holding states).

[0065] 4. Transient power consumption peak calculation:

[0066] During the simulation, the maximum power consumption value of each clock cycle or event is recorded.

[0067] Average power consumption analysis:

[0068] 1. Power consumption statistics:

[0069] Statistics the power consumption of all clock cycles or events during the entire simulation process.

[0070] 2. Average power consumption calculation:

[0071] Divide the total power consumption by the simulation time or the number of clock cycles to get the average power consumption.

[0072] Specific steps:

[0073] 1. Write and compile RTL code: Convert the chip's behavioral description into HDL code and compile it into a form that can be simulated.

[0074] 2. Set up the simulation environment: configure the simulation tools, including clock frequency, simulation time, stimulus signal, etc.

[0075] 3. Run simulation: Execute the simulation and record all events and power consumption data during the simulation.

[0076] 4. Power consumption analysis:

[0077] Use a power analysis tool or a custom script to calculate transient peak and average power consumption.

[0078] 5. Result verification: Compare the simulation results with the power consumption data of the actual chip to verify the accuracy of the simulation.

[0079] Through RTL-level simulation technology, designers can evaluate power consumption in the early stages of chip design, and then optimize it in the subsequent design process to reduce chip energy consumption and improve energy efficiency.

[0080] RTL level simulation technology (Register Transfer Level Simulation) is an important part of digital circuit design. It is a behavioral level simulation method used to verify and test the functional correctness of digital systems in the early stages of circuit design. The following is a detailed explanation of RTL level simulation technology:

[0081] RTL level simulation technology definition:

[0082] RTL level simulation is performed at the register transfer level, which describes the behavior of digital circuits without involving specific logic gate level details. At the RTL level, designers use hardware description languages ​​(HDL) such as Verilog or VHDL to write the behavior description of the circuit.

[0083] Features of RTL-level simulation:

[0084] 1. Behavioral description: RTL-level simulation focuses on the behavior of the circuit rather than the specific implementation details of the circuit.

[0085] 2. Abstraction level: It provides a higher level of abstraction than gate-level simulation, allowing designers to start verifying the design earlier.

[0086] 3. Early verification: Functional verification is performed before the specific implementation details of the circuit are determined.

[0087] 4. Simulation speed: Due to the higher level of abstraction, RTL-level simulation is usually faster than gate-level simulation.

[0088] 5. Reusability: RTL level codes are reused for different implementations as they do not depend on specific hardware details.

[0089] Steps for RTL level simulation:

[0090] 1. Writing HDL code: Designers write the behavioral description of the circuit using an HDL language such as Verilog or VHDL.

[0091] 2. Simulation environment settings: Configure simulation tools, including defining clocks, stimulus signals, test vectors, etc.

[0092] 3. Run Simulation: Perform a simulation to observe whether the circuit behaves as expected.

[0093] 4. Analyze results: Check the simulation results to verify the functional correctness of the circuit.

[0094] 5. Debug and optimize: Debug and optimize the design based on the simulation results.

[0095] Applications of RTL-level simulation:

[0096] Functional Verification: Ensure that the design meets the functional requirements.

[0097] Performance Evaluation: Evaluate the performance of the design under different operating conditions.

[0098] Power Analysis: Predict and estimate the power consumption of a design.

[0099] Resource Utilization Analysis: Evaluate the logic resources required for your design.

[0100] Timing Analysis: Ensure that the design meets timing requirements.

[0101] Tools for RTL-level simulation:

[0102] Simulation software: such as ModelSim, Vivado Simulator, QuestaSim, etc.

[0103] Power consumption analysis tools: such as Cadence Spectre, Synopsys VCS, etc.

[0104] Through RTL-level simulation, designers can discover and correct potential design errors before the specific implementation of the circuit, thereby improving design quality and efficiency.

[0105] Step 2: Estimation of power network parameters: Estimation of power network parameters through electromagnetic model, so as to provide reference design for the power network;

[0106] In this step, the estimation of power network parameters is crucial to ensure the power integrity of the integrated circuit (IC). Estimating the power network parameters through electromagnetic models helps designers optimize the power network design and improve the performance and reliability of the system. Estimating the power network parameters through electromagnetic models provides a scientific basis for the power network and helps designers create efficient and stable power network designs.

[0107] Step 3: Designing the power network, including determining the density of the power network, the number of power IOs, and selecting the style of the power rail;

[0108] Step 4: Use network topology analysis technology to analyze the network grid and obtain a power integrity report, mainly for voltage drop and electromigration analysis.

[0109] In addition, the power network design includes power consumption analysis, power network pre-assessment, power network distribution estimation, and power integrity analysis. The quality of power design is based on two aspects: power integrity and power network area. Increasing the density of the power network can improve the voltage drop and electromigration effect of the chip, but it will lead to an increase in the chip area, thereby increasing the cost of the chip, and requiring multiple iterations of the chip power network.

[0110] As a further embodiment of the present invention, the power consumption analysis includes RTL level power consumption analysis and gate circuit level power consumption analysis;

[0111] The RTL-level power analysis uses a spreadsheet analysis to find the best power-conscious library and design architecture. After the library is selected, the design compiler and power compiler are used instead of the spreadsheet to provide data to the spreadsheet. In order to use the spreadsheet analysis method, the number and activity level of each type of library unit are estimated, and the energy consumed by each type of unit when switching is obtained. The internal power consumption formula of each type of unit in a module is:

[0112] (1)

[0113] In formula (1), For the power consumption speed ratio, the power consumption of all different types of units in a module is added together to obtain an estimate of the total internal dynamic power consumption of this module. Before synthesis, the number of gates is estimated based on the selected architecture and the understanding of the design itself;

[0114] The gate circuit level power consumption analysis is to obtain accurate power consumption estimation values ​​from the power compiler according to the actual number of gates and the activities obtained by simulation after the RTL level power consumption analysis is completed. In VCS, the same instructions as the RTL level power consumption analysis are used to generate SAIF files. The physical compiler tool uses instructions to improve the accuracy of the load after physical optimization. The instructions generate a SPEF file annotated with Steiner paths and parasitic resistance and capacitance estimation values. After the layout is completed, the simulation can generate a value transformation dump file for basic power analysis. The value transformation dump file records the value that becomes a signal value during the simulation process and provides information on the node activities, structural data system connectivity, path delay, timing and time of the design.

[0115] One of the instructions was changed to:

[0116] $set_gate_level_monitoring ("on");

[0117] The physics compiler tool uses the write parasitics -distributed directive after physics optimization to improve the accuracy of loads.

[0118] In the above specific embodiment, in the RTL level power consumption analysis, the power compiler provides a power estimation function, which uses SAIF files to define libraries and constraints, and annotates the design for power consumption estimation. After the power compiler calculates the internal power consumption, it compares the power consumption of different design solutions, but is not used to predict the actual power consumption of the chip. The approximate estimation at the RTL level can indeed provide reference opinions on the feasibility of chip design in the early stage. The estimation result obtained by using the estimation method of the power compiler is:

[0119] Table 1 Estimation results obtained using the spreadsheet method

[0120] Box 1: (frequency 100MHz) Gate type A=100 Activity=0.25 μm / MHz=5 Gate type A=130 Activity=0.05 μm / MHz=13 Gate type A=55 Activity=0.1 μm / MHz=18

[0121] As can be seen from Table (1), the RTL level power consumption can be quickly estimated using the spreadsheet method. This estimation is mainly based on the default switching action of the uncommented port. Each rising edge has a 1 / 4 probability of reversal. This value is applied and transmitted throughout the module.

[0122] As a further embodiment of the present invention, the estimation of the power network parameters includes determining the number and position of PADs and calculating the line width spacing of the power grid within the chip;

[0123] The number and location of PG units. In the package design, PAD forms a PAD ring around the internal logic of the chip, and PG units should be distributed in pairs. According to the power consumption and operating voltage of the chip, the total current is estimated as follows:

[0124] (2)

[0125] In formula (2), is the total current inside the chip, is the total power consumption inside the chip, is the total voltage inside the chip, The chip power consumption analysis tool is used to obtain that PAD represents the IO unit of the chip. The formula for determining the number of PADs and the required power supply is:

[0126] (3)

[0127] In formula (3), is the minimum value of the current passing through, M is the minimum number of PG units allowed by the design. When PAD resources allow, place more PG units to reduce the resistance voltage drop effect, reduce the parasitic inductance on the power connection line, and reduce the voltage fluctuation caused by instantaneous current changes;

[0128] According to the silicon area of ​​the chip and the overall power consumption of the chip, the average power consumption per unit area of ​​the silicon chip is:

[0129] (4)

[0130] In formula (4), is the total power consumption of the internal logic, is the average power consumption per unit area of ​​silicon wafer, For the total area of ​​the silicon wafer, the formula for estimating the average current consumed by a fixed length of standard cell row is:

[0131] (5)

[0132] In formula (5), i is the length of The power consumed by the standard cell row is W, and the height of the standard cell row is W. In practical applications, the length of each standard cell row is between tens and hundreds of microns. The length of n series is The voltage drop formula on the power rail is:

[0133] (6)

[0134] In formula (6), I m represents the current on the mth long standard cell row, and R represents the length The resistance on the metal power rail, R, is derived from the process parameters, and the current formula on the mth standard cell row is:

[0135] (7)

[0136] In formula (7), i is the length of The power consumed by the standard cell row, n represents the number of series lengths, then the final n series lengths are The voltage drop formula on the power rail is:

[0137] (8)

[0138] The power rail inside the chip is bidirectional. The spacing between the power supply networks is determined. After the average power consumption is calculated, the calculated value is multiplied by a coefficient to obtain the peak power consumption, and the coefficient is 1.5.

[0139] The layout of the full-chip power network must be completed before all existing network wiring, and then the clock network and general signal network are arranged. Any physical changes will lead to significant changes in its performance. The width of the power line must be customized, and cannot be uniformly set by software like other interconnects. At the same time, the power network is most closely connected with the modules on the chip, and its power domain and peak current are mainly considered. Since the core address in the chip has a large power consumption density, the current density on the power trunk is larger than the estimated value, and a large voltage drop will be generated on the power trunk. The current density on the power trunk cannot be accurately calculated in the evaluation stage, so the voltage drop on the core power ring is controlled at a low level through computer processing.

[0140] It should be noted that when calculating, after the spacing of the power grid is determined, its width is quickly determined based on the average load and process parameters of each metal line, and the peak power consumption is used as the basis for estimation to avoid serious impact on the performance of the power network due to excessive local and instantaneous power consumption.

[0141] When performing power consumption calculations, the SAIF file is an ASCII format file that contains circuit switch activity information and has the following advantages: compared to the VCD format, the format is more compact; it has complete switch information; it has excellent ease of use and practicality; and VCD is a standard Verilog waveform file that records the time and level information of any variable changes. This file is generated by simulation. Since the switch activity information provided in the VCD file is dynamic, during the processing, different information obtained under the working conditions at different stages of the simulation process is extracted.

[0142] During the power consumption analysis process, all units in the design need to be treated as standard units and processed uniformly, including calculations and obtaining other power consumption parts from the power consumption model, and finally recording the results; for the power consumption definition information of certain units, these power consumption values ​​need to overwrite the corresponding data in the original record, and finally record the results. After the power consumption analysis is completed, the analysis results must be checked and checked using instructions, which can reflect the analysis results and save time in subsequent analysis processes.

[0143] As a further embodiment of the present invention, a chip power network design topology optimization method is as follows:

[0144] 1) Problem description: According to the structural characteristics of the low-level chip power network, the power rail spacing is the height of the standard unit. The chip power network design topology optimization is aimed at the high-level chip power network. Under the premise of ensuring that there is no voltage drop violation in the chip power network, the layout area occupied by the power network is reduced. The constraint objective function is:

[0145] (9)

[0146] In formula (9), G pall For the updated power network topology diagram, G k G pall The k-th topological graph in the table has the following constraints: , E k is the topological graph G k The edge set in E H For E k The edge set in the high-level chip power network, and w j For edge e j The length and width of the corresponding power point segment, ΔV is the node voltage drop, and its value is the difference between the ideal power supply voltage and the node voltage;

[0147] 2) Topology update. During the topology update of the chip power network, new power lines are constantly inserted. The edges in the virtual network will gradually be replaced by different types of power lines. j The weight w j Defined as:

[0148] (10)

[0149] In formula (10), w j is the virtual edge e j The weight of h is the height of the high-level chip power network, E H For E k The edge set in the high-level chip power network, R Lj Indicates the voltage of the high-level chip power network;

[0150] After the chip power network topology is generated, the power network is analyzed and the analysis result is compared with the constraint condition (9) to obtain an approximate optimal solution based on this type of topology, and the objective function is achieved while satisfying the constraint condition.

[0151] In the above specific embodiment, the topology optimization method is compared with the uniform distribution method commonly used in engineering time. The experimental objects are five full-chip power networks of different sizes. The larger the number, the larger the scale. The physical parameter value is 0.23μm, the operating voltage is 1.5V, and the maximum voltage drop allowed is 10%, that is, 0.15V. The experimental data is:

[0152] Table 2 Area comparison experimental data table

[0153]

[0154] As can be seen from Table (2), the topology optimization method of the full-chip power supply occupies less wiring resources while ensuring the voltage drop requirement of the power supply network. It saves a maximum of 20.15% of the power supply area compared to the uniform distribution method, and an average of 8.95%. Moreover, the optimization performance improves with the increase of the scale of the full-chip power supply network, and thus the full-chip power supply network can be optimized.

[0155] In addition, the evaluation of the design quality of the full-chip power network must wait until the standard cell layout is completed and obtained through power grid analysis. If the power network design is unreasonable, the modification cycle will be long. In order to reduce the number of iterations and shorten the design cycle, it is necessary to estimate the full-chip power network beforehand. Standard cells should be placed within the internal logic range and outside the internal space, and power lines should be arranged in these places to extend the full-chip power network to each standard cell.

[0156] As a further embodiment of the present invention, the architecture design of the full-chip power network includes: multiple metal layers, the multiple metal layers include a first metal layer and a second metal layer, and the power network design method is:

[0157] A first power line and a first ground line arranged in parallel along a first direction on a first metal layer of the full-chip power network;

[0158] A second power line and a second ground line are arranged in parallel along a second direction on the second metal layer of the full-chip power network, wherein the first direction is perpendicular to the second direction;

[0159] The first power line and the second power line are connected at the overlapping point by a through hole, the first ground line and the second ground line are connected at the overlapping points by a through hole, the length of the second power line is less than the threshold of the length of the first power line, there is no overlapping point between the second power line and the first ground line, the length of the second ground line is less than the threshold of the length of the second ground line, and there is no overlapping point between the second ground line and the first power line.

[0160] As a further embodiment of the present invention, in the chip, the wiring layer used is implemented by metal M4 and via V3, and a layer of M4 is added in the vertical direction, with a width of 2μm for power supply and ground line spacing of 20μm, and a group spacing of 50μm, so that the power supply spacing of the entire network standard unit is reduced, avoiding congestion within an area less than 2mm*2mm in length*width.

[0161] As a further embodiment of the present invention, the full-chip power network further includes other metal layers located above the second metal layer;

[0162] The other metal layers are used to lay out metal lines based on preset wiring rules.

[0163] It should be noted that the wiring rules for the first metal layer and the second metal layer provided in the present invention only provide a wiring rule for adjacent metal layers, and do not limit the specific positions of the first metal layer and the second metal layer in the power supply network. Any physical routing between adjacent metal layers with similar scenarios can adopt the technical solution of this application.

[0164] In a specific embodiment, the second power line and the second ground line are arranged in a segmented manner. The second power line only needs to be arranged at the place where it is connected to the first power line, and the second ground line needs to be arranged at the place where it is connected to the first ground line. Compared with the through-layout method in the second direction, the wiring redundancy is greatly reduced, thereby saving the winding resources of the second metal layer, releasing the occupied second metal layer space, and making the placement of the standard unit block more flexible. At the same time, the other metal layers of the power network arrange metal wires based on preset wiring rules. Therefore, in addition to the above-mentioned first metal layer and second metal layer, the power network may also include other metal layers, and the wiring rules of other metal layers may follow the existing wiring rules, and may also adopt the wiring rules of the first metal layer and the second metal layer in this application.

[0165] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that these specific embodiments are only illustrative, and those skilled in the art may omit, replace, and change the details of the above methods and systems in various ways without departing from the principles and essence of the present invention. For example, merging the above method steps so as to perform substantially the same functions in substantially the same manner to achieve substantially the same results is within the scope of the present invention. Therefore, the scope of the present invention is limited only by the appended claims.

Claims

1. A full-chip power network design method, characterized in that: Methods include: Step 1: Power consumption analysis: use RTL-level simulation technology to calculate the maximum transient power consumption and average power consumption of the chip under different application conditions; Step 2: Estimation of power network parameters: Estimation of power network parameters through electromagnetic model to provide reference design for the power network; Step 3: Designing the power network, including determining the density of the power network, the number of power IOs, and selecting the style of the power rail; Step 4: Use network topology analysis technology to analyze the network grid and obtain a power integrity report, mainly for voltage drop and electromigration analysis.

2. The full-chip power network design method according to claim 1, characterized in that: The power consumption analysis includes RTL level power consumption analysis and gate circuit level power consumption analysis; The RTL-level power analysis uses a spreadsheet analysis to find the best power-conscious library and design architecture. After the library is selected, the design compiler and power compiler are used instead of the spreadsheet to provide data to the spreadsheet. In order to use the spreadsheet analysis method, the number and activity level of each type of library unit are estimated, and the energy consumed by each type of unit when switching is obtained. The internal power consumption formula of each type of unit in a module is: （1） In formula (1), For the power consumption speed ratio, the power consumption of all different types of units in a module is added together to obtain an estimate of the total internal dynamic power consumption of this module. Before synthesis, the number of gates is estimated based on the selected architecture and the understanding of the design itself; The gate circuit level power consumption analysis is to obtain accurate power consumption estimation values ​​from the power compiler according to the actual number of gates and the activities obtained by simulation after the RTL level power consumption analysis is integrated. In VCS, the same instructions as the RTL level power consumption analysis are used to generate SAIF files. The physical compiler tool uses instructions to improve the accuracy of the load after physical optimization. The instructions generate SPEF files that annotate the Steiner path and the estimated values ​​of parasitic resistance and capacitance. After the layout is completed, the simulation can generate a value transformation dump file for basic power analysis. The value transformation dump file records the value that becomes a signal value during the simulation process and provides the node activity, structural data system connectivity, path delay, timing and time information of the design.

3. The full-chip power network design method according to claim 1, characterized in that: The estimation of the power network parameters includes the determination of the number and position of PADs and the calculation of the line width spacing of the power grid within the chip; The number and location of PG units. In the package design, PAD forms a PAD ring around the internal logic of the chip, and PG units should be distributed in pairs. According to the power consumption and operating voltage of the chip, the total current is estimated as follows: （2） In formula (2), is the total current inside the chip, is the total power consumption inside the chip, is the total voltage inside the chip, The chip power consumption analysis tool is used to obtain that PAD represents the IO unit of the chip. The formula for determining the number of PADs and the required power supply is: （3） In formula (3), is the minimum value of the current passing through, M is the minimum number of PG units allowed by the design. When PAD resources allow, place more PG units to reduce the resistance voltage drop effect, reduce the parasitic inductance on the power connection line, and reduce the voltage fluctuation caused by instantaneous current changes; According to the silicon area of ​​the chip and the overall power consumption of the chip, the average power consumption per unit area of ​​the silicon chip is: （4） In formula (4), is the total power consumption of the internal logic, is the average power consumption per unit area of ​​silicon wafer, For the total area of ​​the silicon wafer, the formula for estimating the average current consumed by a fixed length of standard cell row is: （5） In formula (5), i is the length of The power consumed by the standard cell row is W, and the height of the standard cell row is W. In practical applications, the length of each standard cell row is between tens and hundreds of microns. The length of n series is The voltage drop formula on the power rail is: （6） In formula (6), I m represents the current on the mth long standard cell row, and R represents the length The resistance on the metal power rail, R, is derived from the process parameters, and the current formula on the mth standard cell row is: （7） In formula (7), i is the length of The power consumed by the standard cell row, n represents the number of series lengths, then the final n series lengths are The voltage drop formula on the power rail is: （8） The power rail inside the chip is bidirectional. The spacing between the power supply networks is determined. After the average power consumption is calculated, the calculated value is multiplied by a coefficient to obtain the peak power consumption, and the coefficient is 1.

5.

4. The full-chip power network design method according to claim 1, characterized in that: Chip power network design topology optimization method: 1) Problem description: According to the structural characteristics of the low-level chip power network, the power rail spacing is the height of the standard unit. The chip power network design topology optimization is aimed at the high-level chip power network. Under the premise of ensuring that there is no voltage drop violation in the chip power network, the layout area occupied by the power network is reduced. The constraint objective function is: （9） In formula (9), G pall For the updated power network topology diagram, G k G pall The k-th topological graph in the table has the following constraints: , E k is the topological graph G k The edge set in E H For E k The edge set in the high-level chip power network, and w j For edge e j The length and width of the corresponding power point segment, ΔV is the node voltage drop, and its value is the difference between the ideal power supply voltage and the node voltage; 2) Topology update. During the topology update of the chip power network, new power lines are constantly inserted. The edges in the virtual network will gradually be replaced by different types of power lines. j The weight w j Defined as: （10） In formula (10), w j is the virtual edge e j The weight of h is the height of the high-level chip power network, E H For E k The edge set in the high-level chip power network, R Lj Represents the voltage of the high-level chip power network.

5. The full-chip power network design method according to claim 4, characterized in that: After the chip power network topology is generated, the power network is analyzed and the analysis result is compared with the constraint condition (9) to obtain an approximate optimal solution based on this type of topology, and the objective function is achieved while satisfying the constraint condition.

6. The full-chip power network design method according to claim 5, characterized in that: The architecture design of the full-chip power supply network includes: multiple metal layers, the multiple metal layers include a first metal layer and a second metal layer, and the power supply network design method is: A first power line and a first ground line arranged in parallel along a first direction on a first metal layer of the full-chip power network; A second power line and a second ground line are arranged in parallel along a second direction on the second metal layer of the full-chip power network, and the first direction is perpendicular to the second direction.

7. A full-chip power network design method according to claim 6, characterized in that: The first power line and the second power line are connected at the overlapping point by a through hole, the first ground line and the second ground line are connected at the overlapping points by a through hole, the length of the second power line is less than the threshold of the length of the first power line, there is no overlapping point between the second power line and the first ground line, the length of the second ground line is less than the threshold of the length of the second ground line, and there is no overlapping point between the second ground line and the first power line.

8. The full-chip power network design method according to claim 7, characterized in that: In the chip, the wiring layer used is implemented by metal M4 and via V3. An M4 layer is added in the vertical direction with a width of 2μm for power supply and ground line spacing of 20μm and a group spacing of 50μm.

9. The full-chip power network design method according to claim 8, characterized in that: The full-chip power network also includes other metal layers located above the second metal layer.

10. A full-chip power network design method according to claim 9, characterized in that: The other metal layers are used to lay out metal lines based on preset wiring rules.

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