Signal integrity analysis and optimization method considering electrothermal coupling and parasitic effect in artificial intelligence chip

Abstract

The invention discloses a signal integrity analysis and optimization method considering electrothermal coupling and parasitic effect in an artificial intelligence chip. According to the method, aiming at a random resistive memory cross array in an artificial intelligence chip, an RRAM compact model is combined to research the influence of device electrothermal coupling and parasitic effect on signal integrity in the cross array, evaluation analysis is carried out, and an optimization scheme is provided. Comprising the following steps: (1) based on a compact model of an RRAM device, establishing an equivalent thermal circuit network to represent an electrothermal coupling effect of a device in a cross array; (2) establishing an interconnection line equivalent circuit model containing parasitic resistance, capacitance and inductance, and extracting parasitic parameters in the model by adopting a partial element equivalent circuit (PEEC) method; (3) analyzing a simulation result, and realizing signal integrity evaluation considering electrothermal coupling, parasitic effect and the like; and (4) proposing an optimization scheme for the problems of parasitic voltage drop and leakage path. The method has important application value in random resistive memories and neuromorphic brain-like chips.

Description

Technical Field

[0001] The present invention relates to the field of random resistive memory crossbar array and signal integrity modeling and simulation, and relates to a signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects in an artificial intelligence chip. Background Art

[0002] Theoretically, as the integration density of RRAM crossbar arrays increases, the reduction in device size and spacing will bring about two key problems: thermal crosstalk and parasitic effects. Due to the electrothermal effect, the heat generated in the unit will have a negative impact on the stability and reliability of adjacent units. In addition, the parasitic effects between the interconnections in the crossbar array may cause various signal integrity issues, including parasitic voltage drops, crosstalk between neighbors, and sneak paths. These problems directly affect the system calculation accuracy when the RRAM crossbar array is used as a computing unit. Therefore, it is necessary to model the electrothermal coupling and parasitic effects in the random resistive memory crossbar array to study the integrity issues in the array.

[0003] At present, the modeling and simulation based on the electrothermal coupling effect of devices are mainly carried out through commercial software or finite element method. The simulation efficiency is low when solving large-scale cross arrays, and the compact models of many devices only consider the self-heating effect inside the device and ignore the thermal crosstalk between devices in the array. In addition, the current parasitic circuit models based on cross arrays mostly use commercial software such as ANSYS Q3D and ANSYS HFSS, and the simulation efficiency of parasitic effects in solving large-scale cross arrays is also low. Therefore, it is very necessary to model and analyze the electrothermal coupling and parasitic effects in random resistive memory cross arrays from the circuit perspective. At present, there is almost no circuit model that comprehensively considers electrothermal effects and parasitic effects in random resistive memory cross arrays.

[0004] In recent years, there have been many studies and reports on the optimization of parasitic voltage drops and leakage paths. For example, for neural network calculations, voltage compensation is achieved by changing the weight value to map the resistance value in the memory during offline learning, or the voltage drop effect of the intermediate unit is alleviated by stimulating the two ends separately; the resistance state reading in the presence of leakage paths can be achieved through three write schemes or grounding, or complex circuit connection schemes. However, the currently available solutions to the parasitic voltage drop problem are limited to complex algorithm modifications and specific application scenarios, and the reading solution to solve the sneak path problem in the crossbar array is limited by power consumption, number of writes, and circuit connection complexity. Therefore, a more efficient solution is needed to alleviate the parasitic voltage drop and sneak path problems. The present invention is based on a general compact model of the device, constructs an equivalent thermal circuit network through thermal resistance and thermal capacitance, then establishes a parasitic model of interconnect lines including parasitic resistance, capacitance and inductance, and uses a partial component equivalent circuit method to achieve efficient extraction of parasitic parameters. It further provides a signal integrity analysis of random resistive memory cross arrays in artificial intelligence chips that considers electrothermal coupling and parasitic effects, and an optimization scheme for parasitic voltage drops and leakage paths. This method is applicable to random resistive memory cross array structures of any scale. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention provides a signal integrity analysis and optimization method taking into account electrothermal coupling and parasitic effects in an artificial intelligence chip.

[0006] The technical solution adopted by the present invention is as follows:

[0007] A signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects in an artificial intelligence chip mainly includes:

[0008] Based on the compact model of random resistive RAM (RRAM), an equivalent thermal circuit network was established using thermal resistance and thermal capacitance to characterize the electrothermal effect of the devices in the crossbar array.

[0009] The parasitic equivalent circuit model between interconnects in the crossbar array is established using parasitic resistance, capacitance and inductance elements, and the parasitic element values ​​are solved using the partial element equivalent circuit method;

[0010] Based on the above-mentioned comprehensive circuit model considering electrothermal coupling and parasitic effects, further, circuit simulation software such as SPICE is used to perform signal integrity analysis on, for example, a 1MB (1024×1024) crossbar array memory, and then evaluate the influencing factors of performance such as thermal crosstalk, parasitic voltage drop, parasitic crosstalk, leakage current, etc.; thereby guiding optimization.

[0011] In the above technical solution, further, a compact model of the memory is established based on the change of the conductive filaments, the electric power of the RRAM and the control element is calculated as the heat source according to the compact model, the thermal resistance and thermal capacitance of the device are calculated to obtain the equivalent thermal circuit model, the heat source is coupled to the equivalent thermal circuit network, and the temperature distribution of the device is calculated, the temperature is coupled to the compact model of the memory to update the electrical characteristics to obtain the updated electric power, and the above process is iterated until convergence is achieved.

[0012] Furthermore, an RLC parasitic circuit model of the interconnects in the crossbar array is established, including the parasitic resistance of the interconnects, the ground capacitance and mutual capacitance of the interconnects, and the self-inductance and mutual inductance between the interconnects. The parasitic resistance, parasitic capacitance and parasitic inductance parameter values ​​are calculated using the partial component equivalent circuit method.

[0013] Furthermore, when calculating the parasitic capacitance and parasitic inductance parameters using the partial element equivalent circuit method, the discrete interconnects are divided into several rectangular blocks, i.e., block units, and only the outer four surfaces of the interconnects of each rectangular block are considered in the capacitance and inductance calculations;

[0014] Furthermore, based on the above integrity analysis, optimization can be performed for the parasitic voltage drop problem and the leakage path problem; for the parasitic voltage drop, the voltage drop and the storage position of the device can be fitted and analyzed to further correct and compensate for the parasitic voltage drop in the array; for the leakage path problem, a new current reading method under the leakage path can be set, and a method combining setting a reference unit and grounding can be used to achieve correct identification of the resistance state of the storage device.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] 1. The present invention provides a signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects in an artificial intelligence chip. Compared with the traditional finite element method, this method can simultaneously simulate the temperature distribution in the device, thermal crosstalk between devices, parasitic voltage drop and adjacent crosstalk, leakage path current, etc., to evaluate the comprehensive impact of signal integrity issues on computing performance. It has guiding significance for further improving the computing performance of the system and has important application value in random resistive memory and neuromorphic computing chips.

[0017] 2. In the present invention, an equivalent thermal circuit network is used to characterize the electrothermal coupling effect of the device, and a partial component equivalent circuit method is used to solve the parasitic parameters. Modeling efficiency and simulation speed can be greatly improved through circuit-level modeling.

[0018] 3. The present invention adopts a method combining fitting and testing to achieve effective correction and compensation of parasitic voltage drop, and optimizes the leakage path problem by combining setting a reference unit with grounding, thereby achieving accurate storage state identification. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.

[0020] Figure 1 A typical random resistive memory crossbar array structure is provided for the present invention. The array scale in the figure is 3×3. The non-ideal effects in the array include random noise, thermal crosstalk, IR voltage drop, crosstalk and sneak path.

[0021] Figure 2 A flow chart of a signal integrity modeling simulation and optimization scheme considering electrothermal and parasitic effects in a random resistive memory crossbar array provided by the present invention;

[0022] Figure 3 The equivalent thermal circuit model diagram of the resistor-diode series structure (1D1R) unit with thermal resistance and thermal capacitance provided by the present invention, the red part represents the thermal resistance in the vertical direction, the black part corresponds to the lateral thermal resistance and capacitance on the right side of the 1D1R battery, and the lateral thermal resistance and capacitance in the front-to-back and left directions are the same as those on the right side;

[0023] Figure 4 The parasitic equivalent circuit model containing parasitic resistance, capacitance and inductance provided by the present invention. (a) is the parasitic equivalent circuit of the interconnection line in the array, (b) is a schematic diagram of the discrete interconnection line as three rectangular blocks when the partial element equivalent circuit method is used, and only four surfaces of each rectangular block are considered in the calculation of capacitance and inductance;

[0024] Figure 5 1D1R unit in the embodiment of the present invention is a temperature distribution when the unit is working, wherein (a) is the temperature distribution of the unit 1D1R in COMSOL, and (b) is the relationship between the equivalent thermal circuit and the change of the center temperature of the memory in COMSOL with the power consumption;

[0025] Figure 6 1 is the thermal crosstalk of the array under the worst condition in the embodiment of the present invention, wherein (a) is a schematic diagram of the array under the worst condition, and (b) is the relationship between the thermal crosstalk and the device spacing and device size;

[0026] Figure 71 is the relationship between the voltage and the device position under different numbers of low-resistance units and low-resistance values ​​in the embodiment of the present invention, wherein (a) is the relationship between the voltage and the device position under different resistance values, and (b) is the relationship between the voltage and the device position under different numbers of low-resistance units;

[0027] Figure 8 1 is the variation of parasitic crosstalk between adjacent cells with input pulses in an embodiment of the present invention, wherein (a) is the variation relationship of crosstalk between cells in different columns in adjacent rows with time, and (b) is the variation relationship of parasitic crosstalk between cells in the last column of the three adjacent rows closest to the input row with time;

[0028] Fig. 9 1 is the relationship between the array leakage current and the array size in the embodiment of the present invention.

[0029] Fig.10 It is the error when voltage correction is performed based on the exponential relationship between voltage drop and device position fitting under different numbers of low-resistance state units in the embodiment of the present invention.

[0030] Fig.11 Schematic diagram of a current reading scheme combining a reference column and grounding in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0032] A typical random resistive memory crossbar array structure is selected, and the 1D1R unit is taken as an example. The signal integrity modeling and analysis method considering electrothermal coupling and parasitic effects in the array is described in a comprehensive and detailed manner. The optimization scheme of parasitic voltage drop and leakage path is introduced. It is suitable for neural computing systems or artificial intelligence chips such as memories and brain-like chips composed of random resistive memory crossbar array structures.

[0033] According to a specific embodiment of the present invention, a signal integrity modeling and analysis method considering electrothermal coupling and parasitic effects in a random resistive memory crossbar array comprises the following steps:

[0034] Step 1: Based on the 1D1R compact model, the electrical power of the RRAM and the diode is calculated, and coupled to the equivalent thermal circuit network as a heat source to calculate the temperature distribution of the device; the temperature is coupled to the compact model of the 1D1R unit to update the electrical characteristics, and these iterative processes continue until convergence is achieved, where the boundary conditions of the equivalent thermal circuit network are set to room temperature (300K). The governing equations of the solution process are listed in Table 1.

[0035] Step 2: Establish an equivalent circuit model of interconnects in the array containing parasitic resistance, capacitance and inductance, including the self-parasitic resistance of the interconnects, the capacitance to ground and mutual capacitance between interconnects, the self-inductance and mutual inductance between interconnects, and calculate the parasitic parameter values ​​using the partial component equivalent circuit method. The control equations of the solution process are listed in Table 1. The model based on the thermal circuit network and the parasitic circuit model can simultaneously analyze the overall impact of signal integrity issues such as electrothermal coupling and parasitic effects on the computing accuracy of neuromorphic chips during device operation.

[0036] Step 3: Signal integrity analysis. Implement steps 1 and 2 in the circuit simulation software SPICE and simulate them. The simulation results can obtain the array's thermal crosstalk, parasitic voltage drop, parasitic neighbor crosstalk, and leakage current.

[0037] Step 4: Based on the analysis of step 3, the relationship between the voltage drop and the device position in the simulation results is studied, and an exponential relationship is fitted. The fitting parameters are accurately solved by combining the test, so as to accurately correct the voltage drop at different device positions; in addition, by setting the reference unit in combination with the grounding, the resistance state under the leakage path can be correctly identified. The control equations of the model are listed in Table 1.

[0038] Table 1 Control equations in the model

[0039]

[0040]

[0041] The symbols and terms used in this paper are shown in Table 2.

[0042] Table 2 Symbols and terms used in this paper

[0043]

[0044]

[0045]

[0046] like Figure 2As shown, a signal integrity modeling and simulation flow chart of the random resistive memory crossbar array in the artificial intelligence chip is provided. First, the electric power of the RRAM and the diode is calculated as the heat source based on the 1D1R compact model (Formula 1-5). All fitting parameters in the compact model are determined by fitting according to the experimental voltage-current curve.

[0047] Step 2: Calculate the thermal resistance and thermal capacitance of the device (Equations 6-8), couple the heat source to the equivalent thermal circuit network to calculate the temperature distribution of the device; couple the temperature to the compact model of the 1D1R unit to update the electrical properties, and these iterative processes continue until convergence is achieved, where the boundary conditions of the equivalent thermal circuit network are set to room temperature (300K). The governing equations of the solution process are listed in Table 1.

[0048] Step 3: Establish the RLC parasitic circuit model of the interconnection lines in the array, including the parasitic resistance of the interconnection lines, the capacitance to ground and mutual capacitance of the interconnection lines, the self-inductance and mutual inductance between the interconnection lines, and use the partial element equivalent circuit method to calculate the parasitic resistance (Equation 9), parasitic capacitance (Equations 10-13) and parasitic inductance (Equation 14) parameter values. The control equations of the solution process are listed in Table 1.

[0049] Step 4: Signal integrity analysis. Implement steps 1 and 2 in the circuit simulation software SPICE and simulate them. The simulation results can obtain the array's thermal crosstalk, parasitic voltage drop, parasitic crosstalk, and leakage path. Furthermore, based on the relationship between the voltage drop and the device position in the circuit simulation, an exponential fit is performed (Equations 15-16). Combined with the test to solve the fitting parameters, the voltage drop at different device positions can be accurately corrected; in addition, by setting the reference unit in combination with the grounding method (Equations 17-18), the resistance state under the leakage path can be correctly identified. The control equations of the model are listed in Table 1.

[0050] like Figure 3 As shown, the equivalent thermal circuit network of the 1D1R unit composed of thermal resistance and thermal capacitance in the vertical and right horizontal directions in step 2 is provided. The red part represents the thermal resistance in the vertical direction, and the black part corresponds to the thermal resistance and capacitance in the horizontal direction on the right side of the 1D1R unit. The horizontal thermal resistance and capacitance in the front and back and left directions are the same as above.

[0051] for Figure 3 The relevant parameters used in the simulation of the example are listed in Table 3.

[0052] Table 3 Relevant parameters for thermal resistance calculation

[0053] Parameter (unit) value <![CDATA[d CF (nm)]]> 80 <![CDATA[d diode (nm)]]> 50 <![CDATA[r CF (nm)]]> 8 <![CDATA[r diode (nm)]]> 40 <![CDATA[k CF (w / (m·k))]]> 0.5 <![CDATA[k diode (w / (m·k))]]> 22 <h2 style=";text-align:left;direction:ltr"><![CDATA[c <h2 style=";text-align:left;direction:ltr"> CF <h2 style=";text-align:left;direction:ltr"> (J / (kg·k))]]><h2 style=";text-align:left;direction:ltr"> 445 <h2 style=";text-align:left;direction:ltr"><![CDATA[c <h2 style=";text-align:left;direction:ltr"> diode <h2 style=";text-align:left;direction:ltr"> (J / (kg·k))]]><h2 style=";text-align:left;direction:ltr"> 710 <![CDATA[ρ CF (kg / m 3 )]]> <![CDATA[8.9×10 3 ]]> <![CDATA[ρ diode (kg / m 3 )]]> <![CDATA[4.17×10 3 ]]>

[0054] like Figure 4The figure shows the equivalent parasitic circuit model in the crossbar switch array. The parasitic elements in the model include the parasitic resistance (R) of the word line and the bit line, the self-inductance (L sw , L sb ) and self capacitance (C sw , C sb ), the mutual inductance between adjacent word lines and adjacent bit lines (L mw , L mb ) and mutual capacitance (C mw , C mb ), the mutual capacitance between the word line and the bit line (C mwb ).

[0055] for Figure 4 The relevant parameters are listed in Table 4.

[0056] Table 4 Interconnect wire dimensions and parasitic parameter values

[0057]

[0058]

[0059] Figure 5 The center temperature of the thermal node n1 calculated by COMSOL and the thermal circuit network is almost consistent with the change of CF power consumption, which verifies the accuracy of the device equivalent thermal circuit; Figure 6 The relationship between the thermal crosstalk of the 1D1R unit under the worst-case operation and the device spacing and size. As the device spacing decreases, the thermal crosstalk becomes more serious, and the thermal crosstalk changes more dramatically within 50nm of the device spacing. In addition, due to different thermal resistances, the size of the diode also has a significant impact on the thermal crosstalk. Figure 7 This is the relationship between the voltage of the array and the position of the device under different numbers of low-resistance units and low-resistance values. It can be seen that the resistance of the high-resistance unit has little effect on the parasitic voltage drop, while the resistance of the low-resistance unit has a greater impact on the parasitic voltage drop. In addition, when all units are in the high-resistance unit state, the voltage drop trend is relatively slow, and the bias voltage of the 1024th unit only drops by 32%. As the number of low-resistance units increases, the trend of parasitic voltage drop deteriorates sharply. Figure 8 The relationship between parasitic crosstalk between adjacent rows and columns in the array and the input pulse is shown in Figure 2. The larger the array, the more serious the crosstalk between adjacent rows or columns will be due to the series-parallel relationship between parasitic capacitance and inductance. Figure 5-8 The relevant parameters used in the simulation of the example are listed in Table 4.

[0060] Fig. 9Because the leakage current varies with array size, the sneak current will increase with the array size, making it increasingly difficult to identify the resistance state of the selected cell. In addition, the sneak path current when all cells are in the low resistance state is significantly higher than when all cells are in the high resistance state. Fig.10 is the error of voltage correction based on the exponential relationship between voltage drop and device position fitting under different numbers of low-resistance units, in V read =350mV, the voltage correction error under different numbers of low-resistance units is within 10mV. Fig.10 The relevant parameters used in the simulation of the example are listed in Table 5. Fig.11 Schematic diagram of a current reading scheme using a reference column combined with grounding.

[0061] Table 5 Exponential fitting relationship parameters of parasitic voltage drop and device position

[0062]

[0063] Combined with the simulation results of signal integrity, it can be seen that thermal crosstalk and parasitic effects between devices will cause great interference to signal transmission and detection. In the future, there is still a lot of room for optimization in terms of device structure and circuit design, and more efficient signal integrity optimization and calibration schemes are worth exploring. The signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects in an artificial intelligence chip provided by the present invention has important application value in random resistive memory and neuromorphic brain-like chips.

[0064] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects in an artificial intelligence chip, characterized in that: include: For random resistive memory crossbar arrays in artificial intelligence chips, an equivalent thermal circuit network is established based on the compact model of random resistive memory devices (RRAM) to characterize the electrothermal coupling effect of devices in the crossbar array; The parasitic equivalent circuit model between interconnects in the crossbar array is established using parasitic resistance, capacitance, and inductance elements, and the partial element equivalent circuit method is used to solve the parasitic element values; Taking into account the electrothermal coupling and parasitic effects, based on the equivalent thermal circuit network and the parasitic equivalent circuit model, the signal integrity analysis of the cross-array memory is performed using circuit simulation software to evaluate the influencing factors and changing laws of thermal crosstalk, parasitic voltage drop, parasitic adjacent crosstalk, and leakage current to guide the optimization.

2. The signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects in an artificial intelligence chip according to claim 1, characterized in that: A compact model of the memory is established based on the changes in the conductive filaments. The electric power of the RRAM and the control element is calculated according to the compact model as the heat source. The thermal resistance and thermal capacitance of the device are calculated to obtain the equivalent thermal circuit model. The heat source is coupled to the equivalent thermal circuit network to calculate the temperature distribution of the device. The temperature is coupled to the compact model of the memory to update the electrical characteristics to obtain the updated electric power. The above process is iterated until convergence is achieved, where the boundary condition of the equivalent thermal circuit network is set to room temperature, i.e. 300K.

3. The signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects in an artificial intelligence chip according to claim 2, characterized in that: The change of conductive filaments over time in the memory compact model is as follows: Among them, g is the distance between the conductive filament and the electrode, v0 is the fitting parameter, and E a is the activation energy, k is the Boltzmann constant, T CF is the temperature of the conductive filament, T CF =T0+ΔT, T0 is room temperature, ΔT is the temperature change, γ is the field enhancement factor, γ=γ0-β·g 3 , γ0 and β are fitting parameters, a0 is the effective jump distance, t ox is the thickness of the oxide layer, q is the elementary charge, and V is the potential; The current equation of the device: I0, g0, and V0 are all fitting parameters.

4. The signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects in an artificial intelligence chip according to claim 1, characterized in that: An RLC parasitic circuit model of interconnects in a crossbar array is established, including the parasitic resistance of the interconnects, the ground capacitance and mutual capacitance of the interconnects, and the self-inductance and mutual inductance between the interconnects. The parasitic resistance, parasitic capacitance and parasitic inductance parameter values ​​are calculated using the partial component equivalent circuit method.

5. The signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects in an artificial intelligence chip according to claim 4, characterized in that: The parasitic resistance R of the interconnect is: ρ is the mass density of the interconnect, l is the length of the interconnect, and s is the cross-sectional area of ​​the interconnect; The parasitic capacitance and parasitic inductance parameters are calculated using the partial component equivalent circuit method. When the partial component equivalent circuit method is used, the discrete interconnects are divided into several rectangular blocks, i.e., block units. In the calculation of capacitance and inductance, only the four outer surfaces of the interconnects of each rectangular block are considered, including: [Cs]=[P] -1 Among them, C s is the interconnect short-circuit capacitance matrix, P is the potential coefficient matrix, and the elements in the matrix are: ε is the dielectric constant, S i , S j is the plane area in the block unit of the interconnection line, g(r,r′) is the scalar Green's function, r is the source point coordinate, and r′ is the target point coordinate; For any three adjacent rectangular blocks a, b and c obtained by discretizing word lines or bit lines, the outer surfaces of the four interconnects in rectangular block a are defined as surfaces 1 to 4, the outer surfaces of the four interconnects in rectangular block b are defined as surfaces 5 to 8, and the outer surfaces of the four interconnects in rectangular block c are defined as surfaces 9 to 12. The capacitance matrix formula is: Among them, Cs aa , Cs bb , Cs cc is the self-capacitance between the interconnection lines, Cs ab , Cs bc , Cs ac , Cs ba , Cs cb , Cs ca is the mutual capacitance between the interconnection block units, Cs ij is the capacitance between the block units of the interconnects; The self-capacitance and mutual capacitance corresponding to the three rectangular blocks are: For any two rectangular blocks: Among them, L ij is the parasitic inductance between the two rectangular blocks i and j, μ0 is the magnetic permeability of vacuum, a i and a j are the cross-sectional areas perpendicular to the signal transmission direction in the two rectangular blocks, l i and l j are the lengths of the two rectangular blocks along the signal transmission direction, V i and V j are the volumes of the two rectangular blocks respectively.

6. The signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects in an artificial intelligence chip according to claim 1, characterized in that: In view of the parasitic voltage drop problem, the voltage drop and the storage position of the device are analyzed by fitting the relationship, so as to further correct and compensate the parasitic voltage drop in the array; the fitting relationship can adopt any of the following: V d =V read yes -pn Among them, V d is the parasitic voltage drop, p1, p2, p3, and p are all fitting parameters, V read is the read voltage, and n is the device position.

7. The signal integrity analysis and optimization method considering electrothermal coupling and parasitic effects in an artificial intelligence chip according to claim 1, characterized in that: To solve the leakage path problem, a method combining setting a reference unit and grounding is used to correctly identify the resistance state of the memory device. The current reading method under the leakage path is: I j =Is j +Ir j Among them, I j Is is the output current of the j-th column unit, j is the leakage current of the j-th column unit, Ir j Read the current for the jth column cell, I sum is the total leakage current, which is the sum of the first n-2 columns.

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