Auxiliary inspection method for PCB test
By creating a via structure for testing in the PCB design file and defining a prohibited wiring area, the problem of low detection efficiency of PCB test point signal connection in the prior art is solved, which improves the testing efficiency and reduces the workload of manual inspection.
Patent Information
- Application Number
- CN202411548155.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-14
AI Technical Summary
In the prior art, the PCB test point signal connection detection efficiency is low, mainly due to manual confirmation of whether the upper and lower vias of the test point are connected to other unnecessary layer structures, resulting in trivial and inefficient operation.
Based on the original PCB design file, a via generation program is used to create a via structure specifically for testing, and a prohibited wiring area is defined to limit the layer structure of the test point connection, thereby avoiding manual review.
It improves PCB testing efficiency, reduces manual inspection workload, makes the operation of testers more convenient, and realizes collective management of test point via structures.
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of PCB testing, and more particularly to an auxiliary inspection method for PCB testing. Background Art
[0002] PCB, or printed circuit board, is an important component of electronic devices. It provides a basic platform for electrical connections between electronic components. PCB consists of an insulating substrate, a copper foil layer, a solder mask layer, a silk screen layer, etc. The copper foil is etched to form a circuit pattern to connect various electronic components such as resistors, capacitors, transistors, integrated circuits, etc. After years of application and technological development, PCB has extended to a multi-layer board structure. Multi-layer PCB can achieve denser wiring in a limited space, accommodate more electronic components and more complex circuit designs, thereby improving the integration of the system. In addition, multi-layer PCB can effectively shield interference between signal layers, reduce noise, and improve signal quality by designing a dedicated ground plane (Ground Plane, referred to as GND) and power plane (Power Plane).
[0003] In actual design and production, after the PCB layout design is completed, a series of inspections and tests need to be performed on the PCB to verify whether the PCB meets the design requirements and whether it can work properly in the actual application environment. For the test of multi-layer boards, since most of the signals of multi-layer boards are GND signals, when testing a certain point, this point is connected to the test connector. In this process, it is necessary to start from the test point, lead out the vias at both ends of the test point through a specific layer and connect the test connector. In addition, it is also necessary to avoid the situation where other non-test requirement layers have no connection at the test point.
[0004] In the prior art, after the upper and lower vias of the test point are connected to the test connector, confirming whether the test point is connected on other layers is basically done manually, which is not only cumbersome and complicated in operation, but also inefficient and consumes a lot of manpower. Summary of the invention
[0005] In order to overcome the disadvantage of low efficiency of signal connection detection of test points in the prior art, the present invention provides an auxiliary inspection method for PCB testing.
[0006] The technical solution of the present invention is as follows:
[0007] An auxiliary inspection method for PCB testing,
[0008] Get the via generation program,
[0009] The via generation program defines the via data structure and clarifies the various characteristic attributes of the via.
[0010] The via generation program defines the data structure of the prohibited wiring area and clarifies the various characteristic attributes of the prohibited wiring area.
[0011] The via generation program defines the functions of via objects and the functions of adding prohibited wiring areas.
[0012] The via generation program interacts with the user to obtain the characteristic attribute information of the via and the forbidden wiring area.
[0013] The via generator creates via objects and adds keep-out zones.
[0014] The vias are connected to the inspector.
[0015] For the test of test points, the traditional operation is to use the existing via structure located at the upper and lower ends of the test point, connect it to the inspector, so that the inspection object is only the test point, wherein it is necessary to ensure that the two ends of the via structure are not connected to other layer structures. The present invention, on the basis of the original PCB design file, uses a via generation program to create a via structure specifically for testing. Starting from setting this via structure, the characteristic attribute definition of the via structure creates a via, and at the same time defines the forbidden wiring area to which the via structure belongs. The layer to which the via structure is forbidden to connect is set through the forbidden wiring area, so that the via structure is independent and not connected to other layer structures unrelated to the test point. In this way, the created via structure becomes a new functional structure for test point testing, and the forbidden wiring area set by it is used to limit the layer structure connected to the test point, thereby avoiding the workload of manually checking whether the upper and lower via structures of the test point are connected to other unnecessary layer structures, thereby improving work efficiency.
[0016] In the above-mentioned auxiliary inspection method for PCB testing, the characteristic attributes of the via include the position of the via, the geometric size of the via, the mechanical properties of the via, the connection relationship between the via and the power / ground plane, the stacking structure of the via and the electrical properties of the via.
[0017] Furthermore, the characteristic attributes of the via include an X coordinate of the via, a Y coordinate of the via, a diameter of the via, a drilling diameter of the via, and a list of layers penetrated by the via.
[0018] In the above-mentioned auxiliary inspection method for PCB testing, the characteristic attributes of the forbidden wiring area include the center X coordinate of the forbidden wiring area, the center Y coordinate of the forbidden wiring area, the radius of the forbidden wiring area and the layer to which the forbidden wiring area belongs.
[0019] In the above-mentioned auxiliary inspection method for PCB testing, the characteristic attributes of the forbidden wiring area include the lower left corner X coordinate of the forbidden wiring area, the lower left corner Y coordinate of the forbidden wiring area, the upper right corner X coordinate of the forbidden wiring area, the upper right corner Y coordinate of the forbidden wiring area and the layer to which the forbidden wiring area belongs.
[0020] In the above-mentioned auxiliary inspection method for PCB testing, when setting the layer to which the prohibited wiring area belongs, the number of layers of the PCB design file is obtained, each layer is traversed, and the prohibited wiring area of the via is set.
[0021] Furthermore, the user interaction interface of the via includes a prohibited wiring area check box. When the prohibited wiring area check box is checked, the layer structure traversal program is triggered, and a window containing a layer structure selection requirement information column pops up. The layer structure traversal program obtains the required connection layer information according to the information in the layer structure selection requirement information column. The layer structure traversal program traverses all layer structures and sets the set prohibited wiring area for all layers without required connection layer information according to the required connection layer information.
[0022] In the above-mentioned auxiliary inspection method for PCB testing, the name content of the via object includes an identification indicating that the object is a via, the diameter of the via, the test purpose of the via, the area where the via is set, and the number of layers penetrated by the via.
[0023] The above-mentioned auxiliary inspection method for PCB testing obtains a highlighting program, selects a color and a device type, and locks a certain via structure or a certain type of via structure according to the test requirements, runs the highlighting program, and highlights the corresponding via structure.
[0024] In the above-mentioned auxiliary inspection method for PCB testing, the characteristic attributes of the via are set, and the ApplyHighSpeedViaDefinition function is used to write the via definition content into the design database, and the via structure is stored in the via database in the PCB design file.
[0025] The present invention according to the above scheme has the beneficial effect that:
[0026] 1. Additional via structures for testing are set up without affecting the original via structures, thus avoiding misoperation and mismodification. It is also conducive to the collective management of the test via structures, making the operation more convenient for testers.
[0027] 2. Highlighting the via structure used for testing is conducive to capturing, observing and viewing the setting position and distribution of the via structure in the existing PCB design file, making it convenient for testers to view.
[0028] 3. The set via structure directly uses the prohibited wiring area to replace the existing vias in the original PCB design file, and uses the set vias in the prohibited wiring area to replace the original manual inspection, which reduces the inspection workload of a large number of testers and improves work efficiency. DETAILED DESCRIPTION
[0029] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0030] An auxiliary inspection method for PCB testing, obtaining a via generation program, defining a via data structure, clarifying various characteristic attributes of the via, defining a data structure of a prohibited wiring area, clarifying various characteristic attributes of the prohibited wiring area, defining a function of a via object and a function of adding a prohibited wiring area, the via generation program interacts with a user, obtaining characteristic attribute information of the via and the prohibited wiring area, creating a via object and adding a prohibited wiring area, and connecting the via to a checker.
[0031] The characteristic attributes of the via include the location of the via, the geometric size of the via, the mechanical properties of the via, the connection relationship between the via and the power / ground plane, the stacking structure of the via, and the electrical properties of the via.
[0032] The characteristic attributes of the via include the X coordinate of the via, the Y coordinate of the via, the diameter of the via, the drilling diameter of the via, and the list of layers penetrated by the via.
[0033] For the test of test points, the traditional operation is to use the existing via structure located at the upper and lower ends of the test point, connect it to the inspector, so that the inspection object is only the test point, wherein it is necessary to ensure that the two ends of the via structure are not connected to other layer structures. The present invention, on the basis of the original PCB design file, uses a via generation program to create a via structure specifically for testing. Starting from setting this via structure, the characteristic attribute definition of the via structure creates a via, and at the same time defines the forbidden wiring area to which the via structure belongs. The layer to which the via structure is forbidden to connect is set through the forbidden wiring area, so that the via structure is independent and not connected to other layer structures unrelated to the test point. In this way, the created via structure becomes a new functional structure for test point testing, and the forbidden wiring area set by it is used to limit the layer structure connected to the test point, thereby avoiding the workload of manually checking whether the upper and lower via structures of the test point are connected to other unnecessary layer structures, thereby improving work efficiency.
[0034] In this embodiment, a via generation program is obtained, and the via generation program defines a class to generate a via object. The via generation program constructs a function HighSpeedViaCreator, which is a via generation function, and then destructs the function HighSpeedViaCreator to enter the running program of creating a via function CreateHighSpeedVia.
[0035] The process content of CreateHighSpeedVia function is as follows:
[0036] Initialize the via creation parameters InitializeHighSpeedViaParameters, and the PCB design software reads the design rule check (DRC) parameters, such as reading the default via diameter, drilling size, etc. from the PCB design file, using the readDesignRuleCheckParameters function. The main purpose of the readDesignRuleCheckParameters function is to read the DRC parameters from the design file or configuration file and store these parameters in a structure for use in the subsequent via structure creation process to ensure that the via structure design complies with the design rules, thereby improving the reliability and manufacturability of the design. In actual implementation, the specific data reading method will be adjusted according to the Allegro API and file format. After reading the readDesignRuleCheckParameters function, use the loadDefaultOrConfiguredValues function to set the default value or load the value from the configuration file.
[0037] After the configuration file is confirmed, the via creation process begins, and the via creation process begins through the CreateViaStructure function. Specifically, it includes setting the position of the via, and determining the position of the via by running the SetViaPosition(double x, double y) function, where double x is the X coordinate of the via and double y is the Y coordinate of the via; it includes setting the geometric dimensions of the via, and setting the via diameter through the SetViaDiameter function, and setting the drilling size through the SetDrillSize function; it includes setting the mechanical properties of the via, and setting the plating material of the via through the SetPlatingMaterial function, and setting the thermal design options of the via through the SetThermalDesignOptions function; it includes setting the connection between the via and the power / ground plane, and confirming the via plane through the ConnectViaToPlane function; it includes setting the stacking of the via, and configuring the via stacking structure through ConfigureViaStackup; it includes setting the electrical properties of the via, and setting the impedance of the via through SetImpedance.
[0038] In a specific embodiment, SetViaDiameter(10) indicates setting the via diameter to 10 mil.
[0039] In a specific embodiment, SetDrillSize(6) indicates setting the drill size to 6 mil.
[0040] In a specific embodiment, SetRoutingExclusionZone(20) indicates setting the diameter of the exclusion zone around the via to 20 mil.
[0041] In a specific embodiment, SetLayerExclusionZones(20) indicates setting the size of the prohibited routing area of the via in different layers to 20 mil.
[0042] In a specific embodiment, SetImpedance(50) indicates setting the impedance of the via to 50 ohms.
[0043] In a specific embodiment, SetPlatingMaterial("Copper" indicates setting the plating material of the via hole to copper.
[0044] In a specific embodiment, ConnectViaToPlane("GND") represents / connects a via to a ground plane.
[0045] For the characteristic attributes of the via's X coordinate, the via's Y coordinate, the via's diameter, the via's drilling diameter, and the via's penetration layer list, the CreateHighSpeedVia function's settings include the via's X coordinate, the via's Y coordinate, the via's diameter, the via's drilling diameter, and the via's penetration layer list, but the via's X coordinate and the via's Y coordinate are manually input or selected before running. In one embodiment, the content is manually obtained in the program running interface or through the user interaction interface double x = 100.0 double y = 200.0
[0046] creator.CreateHighSpeedVia(x,y), so as to determine the center coordinates of the via as (100.0,200.0)
[0047] The characteristic attributes of the keep-out area include the center X coordinate of the keep-out area, the center Y coordinate of the keep-out area, the radius of the keep-out area, and the layer to which the keep-out area belongs.
[0048] The characteristic attributes of the keep-out area include the lower left corner X coordinate of the keep-out area, the lower left corner Y coordinate of the keep-out area, the upper right corner X coordinate of the keep-out area, the upper right corner Y coordinate of the keep-out area and the layer to which the keep-out area belongs.
[0049] If the characteristic attributes of the forbidden routing zone include the center X coordinate of the forbidden routing zone, the center Y coordinate of the forbidden routing zone, the radius of the forbidden routing zone and the layer to which the forbidden routing zone belongs, then the shape of the forbidden routing zone is a circle, the center of which overlaps with the center of the via, and the size of the forbidden routing area around the via (that is, the diameter of the circle) is set through the SetRoutingExclusionZone function through function restrictions.
[0050] If the characteristic attributes of the forbidden wiring area include the lower left corner X coordinate of the forbidden wiring area, the lower left corner Y coordinate of the forbidden wiring area, the upper right corner X coordinate of the forbidden wiring area, the upper right corner Y coordinate of the forbidden wiring area and the layer to which the forbidden wiring area belongs, then the shape of the forbidden wiring area is a rectangle, the center of which is the center of the via, and the coordinates of the four corners are
[0051] CreateRectangularExclusionZone(double x1,double y1,double x2,doubley2) to confirm.
[0052] When setting the layer to which the prohibited routing area belongs, obtain the number of layers in the PCB design file, traverse each layer, and set the prohibited routing area of the via.
[0053] The user interaction interface of the via includes a prohibited wiring area check box. When the prohibited wiring area check box is checked, the layer structure traversal program is triggered, and a window containing a layer structure selection requirement information column is popped up. The layer structure traversal program obtains the required connection layer information according to the information in the layer structure selection requirement information column. The layer structure traversal program traverses all layer structures and sets the set prohibited wiring area for all layers that are not required connection layer information according to the required connection layer information.
[0054] Specifically, the function layerCount is set so that int layerCount = allegro_get_layer_count obtains the number of layers of the PCB design file, and then the loop function for is used to traverse all the obtained layers. The name of each layer is obtained to specify the specific layer when setting the prohibited wiring area. The prohibited wiring area of the via is set for each layer to ensure that wiring will not be done around the via on this layer.
[0055] Through the check box of the prohibited wiring area in the user interaction interface, the user sets the characteristic attributes of the prohibited wiring area for the via structure, and at the same time triggers the start of the layer structure traversal program and the window containing the layer structure selection requirement information bar. The user selects the layer that needs to be connected (that is, needs to be connected during testing) in the layer structure selection requirement information bar. After obtaining this information, the layer structure traversal program traverses all layer structures, and then excludes the layers that need to be connected, and sets prohibited wiring areas for all other layers.
[0056] The name of the via object includes an identifier indicating that the object is a via, the diameter of the via, the test purpose of the via, the area where the via is set, and the number of layers that the via penetrates.
[0057] After creating a via, when performing subsequent checker connection operations, in order to quickly find the required via in the via database of the PCB design file, when naming the via, the identifier indicating that the object is a via, the diameter of the via, the test purpose of the via, the area where the via is set, and the number of layers the via penetrates are all placed in the name of the via so that it can be quickly found.
[0058] Specifically, the identifier indicating that the object is a via is used to clearly indicate that it is a via, not some other type of object (such as a pad, component, etc.); setting the diameter of the via facilitates identification of the physical size of the via, which helps in selecting appropriate tools and equipment during the design and testing process; the test purpose of the via is used to clarify the purpose of the via, such as for signal transmission, power distribution, grounding, etc., which helps in selecting the correct via for different test points during testing; setting the area of the via is used to identify the PCB area where the via is located, which helps in quick positioning in complex multi-area designs; the number of layers penetrated by the via is used to clarify the number of layers connected by the via, which helps in quick identification of the connection status of the via in multi-layer board designs.
[0059] Get the highlighting program, select the color and device type, and lock a certain via structure or a certain type of via structure according to the test requirements, run the highlighting program, and highlight the corresponding via structure.
[0060] The design process by designers or the testing process by testers is basically realized through PCB design graphics. On this basis, if the vias and the prohibited wiring areas around them are marked, it will be easier to distinguish them. Therefore, a highlighting program is set to display the vias and their prohibited wiring areas.
[0061] After the feature attributes of the via are set, use the ApplyHighSpeedViaDefinition function to write the via definition content into the design database and store the via structure into the via database in the PCB design file.
[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A PCB test auxiliary inspection method, characterized in that: Get the via generation program, The via generation program defines the via data structure and clarifies the various characteristic attributes of the via. The via generation program defines the data structure of the prohibited wiring area and clarifies the various characteristic attributes of the prohibited wiring area. The via generation program defines the functions of via objects and the functions of adding prohibited wiring areas. The via generation program interacts with the user to obtain the characteristic attribute information of the via and the forbidden wiring area. The via generator creates via objects and adds keep-out zones. The vias are connected to the inspector.
2. According to the auxiliary inspection method for PCB testing described in claim 1, it is characterized in that: The characteristic attributes of the via include the location of the via, the geometric size of the via, the mechanical properties of the via, the connection relationship between the via and the power / ground plane, the stacking structure of the via, and the electrical properties of the via.
3. According to the auxiliary inspection method for PCB testing described in claim 2, it is characterized in that: The characteristic attributes of the via include the X coordinate of the via, the Y coordinate of the via, the diameter of the via, the drilling diameter of the via, and the list of layers penetrated by the via.
4. According to the auxiliary inspection method for PCB testing described in claim 1, it is characterized in that: The characteristic attributes of the keep-out area include the center X coordinate of the keep-out area, the center Y coordinate of the keep-out area, the radius of the keep-out area, and the layer to which the keep-out area belongs.
5. According to the auxiliary inspection method for PCB testing described in claim 1, it is characterized in that: The characteristic attributes of the keep-out area include the lower left corner X coordinate of the keep-out area, the lower left corner Y coordinate of the keep-out area, the upper right corner X coordinate of the keep-out area, the upper right corner Y coordinate of the keep-out area and the layer to which the keep-out area belongs.
6. According to the auxiliary inspection method for PCB testing described in claim 1, it is characterized in that: When setting the layer to which the prohibited routing area belongs, obtain the number of layers in the PCB design file, traverse each layer, and set the prohibited routing area of the via.
7. The auxiliary inspection method for PCB testing according to claim 6, characterized in that: The user interaction interface of the via includes a prohibited wiring area check box. When the prohibited wiring area check box is checked, the layer structure traversal program is triggered, and a window containing a layer structure selection requirement information column is popped up. The layer structure traversal program obtains the required connection layer information according to the information in the layer structure selection requirement information column. The layer structure traversal program traverses all layer structures and sets the set prohibited wiring area for all layers that are not required connection layer information according to the required connection layer information.
8. According to the auxiliary inspection method for PCB testing described in claim 1, it is characterized in that: The name of the via object includes an identifier indicating that the object is a via, the diameter of the via, the test purpose of the via, the area where the via is set, and the number of layers that the via penetrates.
9. The auxiliary inspection method for PCB testing according to claim 1, characterized in that: Get the highlighting program, select the color and device type, and lock a certain via structure or a certain type of via structure according to the test requirements, run the highlighting program, and highlight the corresponding via structure.
10. The auxiliary inspection method for PCB testing according to claim 1, characterized in that: After the feature attributes of the via are set, use the ApplyHighSpeedViaDefinition function to write the via definition content into the design database and store the via structure into the via database in the PCB design file.