Memristive pulse neural network system and method

Abstract

The invention discloses a memristive pulse neural network system and method, and belongs to the technical field of artificial intelligence. According to the memristor pulse neural network system provided by the invention, the synaptic structure of a biological neural network is accurately simulated by connecting the same-stage memristors in series by applying a bionic design concept; based on a positive and negative Hertz plasticity rule, a self-adaptive learning mechanism is realized, and a calculation function in memory and calculation integrated performance of the memristor is enhanced; and a cascade extensible control architecture combining master control and slave control is adopted, so that the system is endowed with high expansibility. According to the requirement of a specific task, a user can flexibly adjust the scale of the neural network to realize infinite magnitude cascade extension, so that various complex scenes can be easily coped with. Besides, the built-in ADC acquisition module provides a real-time feedback mechanism, so that the monitoring precision of the system can be improved, the response speed can be increased, and precious data support is provided for optimization and adjustment of the system.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to a memristor pulse neural network system and method. Background Art

[0002] With the rapid advancement of AI technology, especially in the training and reasoning of large-scale neural networks and deep learning models, the computing power requirements and energy efficiency of computer systems are facing severe challenges. The traditional von Neumann architecture leads to the "storage wall" problem due to the separation of computing and storage, which hinders the improvement of computing power and increases energy consumption, becoming a key bottleneck for the efficient operation of AI models. Faced with the urgent need for high-performance computing in AI applications, the limitations of the von Neumann architecture are highlighted. In order to solve this problem, the technical concept based on storage and computing integration has rapidly emerged. Memristors have attracted much attention as the core components of the storage and computing integrated architecture. They can carry storage and computing functions at the same time and avoid performance bottlenecks.

[0003] Memristors have shown great potential in building new computing architectures with their excellent parallel computing capabilities and ultra-high storage density. In stark contrast to traditional computing systems, memristors can directly perform matrix operations in neural networks, which is undoubtedly a great boon for large-scale parallel computing tasks. In addition, memristors can not only significantly reduce the frequency and energy consumption of data transmission, but also greatly improve computing efficiency at the hardware level, perfectly meeting the dual needs of future artificial intelligence applications for high-performance computing and low power consumption.

[0004] In this context, HP Labs proposed an innovative memristor-based Crossbar architecture. This architecture cleverly adopts a cross-connected grid design and cleverly arranges memristors at the intersections of the grid, thereby achieving parallel execution of computing and storage at the same physical location. Compared with the von Neumann architecture, the Crossbar architecture achieves a deep fusion of computing and storage through the clever use of memristors, greatly reducing the frequent transmission of data between computing units and storage units, and effectively weakening the "storage wall" effect in the von Neumann architecture. This groundbreaking architecture has unique advantages in building pulse neural networks, and can handle massive parallel computing tasks with extremely low power consumption and excellent performance, showing broad application prospects in the field of neuromorphic computing.

[0005] However, it is worth noting that the existing Crossbar architecture focuses more on the storage function of the memristor in practical applications. Current implementation plans often use traditional control methods to manage these new neural network architectures, and the weight assignment in the network still relies on the decision-making of traditional computers. Although this approach has improved computing efficiency to a certain extent, it has not fully explored the unique advantages of memristor storage and computing integration, especially in terms of energy consumption optimization, there is still much room for improvement. Summary of the invention

[0006] The purpose of the present invention is to provide a memristor pulse neural network system and method to overcome the problem that the neural network architecture using memristors in the prior art focuses on storage functions while ignoring its computing potential, resulting in limited room for improvement in energy consumption optimization.

[0007] The present invention solves the above technical problems through the following technical solutions: A memristor pulse neural network system includes a driving source module, including a positive driving source, a directional driving source and a negative driving source, which is used to switch the state of the memristor pulse neural network system; A memristor pulse neural network, comprising at least one input memristor group and at least one bias memristor group, wherein the input memristor group is formed by connecting a plurality of first basic structures in parallel, wherein the first basic structure is a pair of positive input memristors connected in series at the same level, and each positive input memristor connected in series at the same level is provided with an independent switch; the bias memristor group is formed by connecting a plurality of second basic structures in parallel, wherein the second basic structure is a pair of reverse biased memristors connected in series at the same level, and each reverse biased memristor connected in series at the same level is provided with an independent switch; a positive driving source is connected to the positive end of the first basic structure and the negative end of the second basic structure, a directional driving source is connected to the series node of the first basic structure and the second basic structure, a negative driving source is connected to the positive end of the first basic structure and the negative end of the second basic structure, and switches are provided on both the first basic structure and the second basic structure; Each input memristor group or bias memristor group is connected to a control module to form a cascaded memristor pulse neural network control module; The control module includes a single-chip microcomputer, an SPI communication interface module and a visualization module are connected to the single-chip microcomputer, a GPIO control port of the single-chip microcomputer is connected to the memristor of the memristive pulse neural network, a slave SPI communication interface of this level is used to connect to the main SPI communication interface of the upper-level control module, the main SPI communication interface of this level is used to connect to the slave SPI communication interface of the next-level control module, and the visualization module is used to display the system control process and results; One of the control modules is a main control module, which is also connected to an ADC acquisition module, an SD card storage module and an analog switch, and the slave SPI communication interface of the main control module is connected to the master SPI communication interface of the host computer, wherein the ADC acquisition module is used to collect the output voltage of the series node ,The SD card storage module is used to store the network training process data and classification result data, and the analog switch is used to control the driving source module; The host computer is used to interact with the main control module and provide guidance for the training of the memristor pulse neural network; An external power supply is used to drive the memristor and control module of the memristive pulse neural network.

[0008] Further, when the state of the memristor pulse neural network system is a state of increasing the weight of the positive-end memristor, the positive driving source is a positive voltage, the directional driving source is a negative voltage, and the negative driving source is a negative voltage; When the state of the memristor pulse neural network system is the network result state under output weighting, the positive driving source is a positive voltage, the directional driving source is a floating state, and the negative driving source is a negative voltage; When the state of the memristor pulse neural network system is to increase the weight of the negative-end memristor, the positive driving source is a positive voltage, the directional driving source is a positive voltage, and the negative driving source is a negative voltage; When the state of the memristor pulse neural network system is the off initial state, the positive driving source is a positive voltage, the directional driving source is a positive voltage, and the negative driving source is a positive voltage.

[0009] Furthermore, the memristor is a physical memristor or an analog memristor, and the memristor pulse neural network system also includes a multi-level power management module for gradually stepping down the +24V power supply provided by an external power supply, and the output covers voltage levels of ±15V, ±2.5V, 5V and 3.3V, which is adapted to the power drive of the memristor and the control module.

[0010] Furthermore, an optocoupler isolation module and a level conversion module are sequentially arranged between the GPIO control port of the single-chip microcomputer and the memristor, wherein the optocoupler isolation module is used to realize isolation protection, and the level conversion module is used to convert the level of the output signal of the optocoupler isolation module to adapt to the control requirements of the memristor pulse neural network.

[0011] A control method for a memristor pulse neural network system, based on the above-mentioned memristor pulse neural network system, the control method of the main control module specifically includes the following steps: S1, initialize the main control module, ADC acquisition module, SD card storage module and analog switch; S2, receiving the host computer instruction, determining whether to start the memristor pulse neural network system, if the determination is yes, executing step S3; if the determination is no, repeating step S2; S3, numbering the main control module and transmitting it to the next level control module, the number is 0; S4, determine whether the control module is the last level control module, if it is not, execute step S5; if it is yes, execute step S6; S5, continue to wait for the ready signal of the next level control module until the signal is received, and then execute step S6; S6. Apply for MCU memory space to increase the network training speed; S7, control the positive driving source to positive voltage, the directional driving source to floating state, the negative driving source to negative voltage, and collect the output voltage , as the initialization classification reference voltage, create a result storage file for storing network training process data and classification result data; S8, communicate with the host computer to obtain the pulse data set to be output, and determine whether the control module is the last level control module. If the determination is no, execute step S9; if the determination is yes, execute step S10; S9, sending the pulse data that needs to be output in the current round Q to the next level control module; continue to wait for the ready signal of the next level control module until the signal is received, and then execute step S10; S10, numbering the memristors according to the pulse data of the current round Q, and combining the self-numbering of the control module to determine the memristors that need to be controlled to be turned on in the current round Q, and judging whether the label of the pulse data is 0, if it is judged to be no, then executing the supervised learning process, and then entering step S11; if it is judged to be yes, then executing the unsupervised learning process, and then entering step S11; S11, obtaining the classification result of the memristor pulse neural network, performing visualization processing, and feeding back the current classification result to the host computer; judging whether the pulse data of the current round is the last set of data in the pulse data set, if the judgment is yes, executing step S13; if the judgment is no, executing step S9; S12. Storing the network training process data and the classification result data in a pre-created result storage file.

[0012] Furthermore, the labels of the pulse data include -1, 0 and 1, wherein -1 indicates that the group of pulse data is classified as a negative class; 1 indicates that the group of pulse data is classified as a positive class; and 0 indicates that the group of pulse data is not classified.

[0013] Furthermore, the control method of the non-main control module specifically includes the following steps: Step B1: Initializing the non-main control module, initializing the external interrupt of the non-main control module, for receiving the synchronization signal of the main control module; Step B2: Determine whether the number of the upper-level control module is received. If it is determined to be yes, execute step B3; if it is determined to be no, repeat step B2; Step B3: add 1 to the received number as the number of this module, and determine whether this module is the last-level control module. If it is not, execute step B4; if it is yes, execute and go to step B5; Step B4: try to pass the number to the next level control module, and continue to wait for the ready signal of the next level control module until the signal is received, and then execute step B5; Step B5: Transmit a ready signal to the upper level control module; clear the suspend register, set and enable the external interrupt to receive the synchronization signal of the main control module; initialize and turn on all memristors controlled by this module, and cooperate with the main control module to collect the initialization classification reference voltage; Step B6: Turn off all memristors, start communication reception, and set external interrupts to disable to prevent interruptions from interrupting the communication process and causing system errors; Step B7: Determine whether the pulse data of the current round is received. If it is determined to be yes, execute step B8; if it is determined to be no, repeat step B7; Step B8: Determine whether this module is the last level control module. If it is not, execute step B9; if it is yes, execute and transfer to step B10; Step B9: Send pulse data to the next level control module, and continue to wait for the ready signal of the next level control module until the signal is received, and then execute step B10; Step B10: According to the pulse data of the current round and the number of the current module, determine the memristor that needs to be controlled to be turned on in the current round, turn off the communication reception, set to enable the external interrupt, used to receive the synchronization signal of the main control module, and send a ready signal to the upper-level control module; Step B11: Determine whether the module triggers the first external interrupt. If it is, execute step B12; if it is not, repeat step B11. Step B12: Turn on the corresponding memristor and write the current round pulse information; Step B13: Determine whether the module triggers the second external interrupt. If it is, execute step B14; if it is not, repeat step B13. Step B14: Turning on the corresponding memristor and waiting for the main control module to collect the classification result of the memristor pulse neural network in this round; Step B15: After the main control module collects the data, it determines whether the module triggers the third external interrupt. If it is determined to be yes, step B16 is executed; if it is determined to be no, step B15 is repeated. Step B16: Turn off the corresponding memristor, set the external interrupt to be disabled to avoid interruption of the communication process causing system errors, start communication reception, and execute step B7.

[0014] Further, when the supervised learning process is performed in step S10, the step S11 of obtaining the classification result of the memristor pulse neural network specifically includes the following steps: Step C1: Determine whether the label of the pulse data is 1. If it is, execute step C2; if it is not, execute step C3; Step C2: The pulse neural network classification result is obtained as a positive class, the positive driving source is controlled to be a positive voltage, the directional driving source is controlled to be a negative voltage, the negative driving source is controlled to be a negative voltage, the upper half memristor between the positive driving source and the directional driving source is controlled to be turned on, and step C4 is executed; Step C3: The pulse neural network classification result is obtained as a negative class, the positive driving source is controlled to be a positive voltage, the directional driving source is controlled to be a positive voltage, the negative driving source is controlled to be a negative voltage, the lower half memristor between the directional driving source and the negative driving source is controlled to be turned on, and step C4 is executed; Step C4: the main control module generates a synchronization signal, triggers the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

[0015] Furthermore, when step S10 performs an unsupervised learning process, step S11 of obtaining the classification result of the memristor pulse neural network specifically includes the following steps: Step D1: Obtain the classification result of the last round of memristor pulse neural network and collect the output voltage of the last round; Step D2: Determine whether the output voltage of the previous round is greater than the initialization classification reference voltage. If it is determined to be yes, execute step D3; if it is determined to be no, execute step D6; Step D3: When the pulse neural network classification result is positive, the positive driving source is controlled to be a positive voltage, the directional driving source is controlled to be a negative voltage, and the negative driving source is controlled to be a negative voltage, and the upper half memristor between the positive driving source and the directional driving source is controlled to be turned on, and step D5 is executed; Step D4: The classification result of the pulse neural network is obtained as a negative class, the positive driving source is controlled to be a positive voltage, the directional driving source is controlled to be a positive voltage, the negative driving source is controlled to be a negative voltage, the negative end memristor of the lower half memristor between the directional driving source and the negative driving source is controlled to be turned on, and step D5 is executed; Step D5: The main control module generates a synchronization signal, triggers the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

[0016] Furthermore, the method further comprises the following steps: Step E1: The main control module generates a synchronization signal, triggers the second external interrupt of the non-control module, turns on the corresponding memristor, controls the positive driving source to be a positive voltage, the directional driving source to be a zero voltage, and the negative driving source to be a negative voltage; Step E2: Collect the output voltage of the series node through the ADC acquisition module , the corresponding memristor is disconnected, the main control module generates a synchronization signal, triggers the third external interrupt of the non-control module, and executes step S11.

[0017] Compared with the prior art, the positive and progressive effects of the present invention are: The memristor pulse neural network system provided by the present invention uses the bionic design concept to accurately simulate the synaptic structure of the biological neural network by connecting the same-level memristor pairs in series. Based on the positive and negative Hebbian plasticity rules, the system realizes an adaptive learning mechanism, strengthens the computing function in the storage and computing performance of the memristor, improves the learning efficiency of the neural network, and enables it to maintain excellent stability and excellent generalization ability under different working conditions, and is particularly good at processing binary classification tasks; the cascaded scalable control architecture combining the master control and the slave control is adopted to give the system a high degree of scalability. According to the needs of specific tasks, users can flexibly adjust the scale of the neural network to achieve unlimited cascade expansion, so as to easily cope with various complex scenarios. In addition, the built-in ADC acquisition module provides a real-time feedback mechanism, which can improve the accuracy of experimental monitoring, speed up the response speed, and provide valuable data support for the optimization and adjustment of the experiment; the modular design concept is adopted, so that the system has good compatibility and flexibility, and can easily adapt to various types of memristors. No matter what kind of manufacturing process or packaging form, suitable application scenarios can be found in the system, which is suitable for various scenarios in teaching and scientific research experiments.

[0018] Furthermore, the multi-level power management module can stably step down the +24V power supply provided by the analog switch to multiple voltage levels, so that the system can flexibly adapt to different types of memristors to meet power drive requirements, avoid system failures or performance degradation caused by voltage fluctuations or instability, and help improve system stability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings in the specification are used to provide further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0020] Figure 1 This is a schematic diagram of the structure of the memristor pulse neural network system; Figure 2 Detailed schematic diagram of independent switches in a memristor pulse neural network system; Figure 3 This is a schematic diagram of the module structure of the memristor pulse neural network system; Figure 4 It is a schematic diagram of the structure of a multi-level power management module; Figure 5 It is a structural diagram of an optocoupler isolation module and a level conversion module; Figure 6 Flow chart of the main control module; Figure 7 It is a flowchart of a non-main control module; Figure 8 Flowchart of supervised learning for the main control module; Fig. 9 Flowchart of unsupervised learning for the main control module.

[0021] Among them, 1 is a positive driving source; 2 is a directional driving source; 3 is a negative driving source; 4 is an input memristor group; 5 is a bias memristor group; 6 is a cascaded memristor pulse neural network control module; 7 is a host computer; 41 is an independent switch for a positive input memristor of the same level; 42 is a positive input memristor of the same level; 51 is a reverse bias memristor of the same level; 52 is an independent switch for a reverse bias memristor of the same level; 61 is an MCU; 62 is a GPIO control port; 63 is an SPI communication interface module; and 64 is an ADC acquisition module. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below in conjunction with specific embodiments, which are intended to explain the present invention rather than to limit it.

[0023] A memristor pulse neural network system comprises a driving source module, including a positive driving source 1, a directional driving source 2 and a negative driving source 3, for switching the state of the memristor pulse neural network system; A memristor pulse neural network comprises at least one input memristor group 4 and at least one bias memristor group 5, wherein the input memristor group 4 is formed by connecting a plurality of first basic structures in parallel, wherein the first basic structure is a pair of positive input memristors 42 connected in series at the same level, and each positive input memristor 42 at the same level is provided with an independent switch 41; the bias memristor group 5 is formed by connecting a plurality of second basic structures in parallel, wherein the second basic structure is a pair of reverse biased memristors 51 connected in series at the same level, and each reverse biased memristor 51 at the same level is provided with an independent switch 52; a positive driving source 1 is connected to the positive end of the first basic structure and the negative end of the second basic structure, a directional driving source 2 is connected to the series node of the first basic structure and the second basic structure, a negative driving source 3 is connected to the positive end of the first basic structure and the negative end of the second basic structure, and switches are provided on both the first basic structure and the second basic structure; Each input memristor group 4 or bias memristor group 5 is connected to a control module to form a cascaded memristor pulse neural network control module 6; The control module includes a single-chip microcomputer, the single-chip microcomputer is connected to an SPI communication interface module 63 and a visualization module, the GPIO control port 62 of the single-chip microcomputer is connected to the memristor of the memristive pulse neural network, the slave SPI communication interface of this level is used to connect to the master SPI communication interface of the upper-level control module, the master SPI communication interface of this level is used to connect to the slave SPI communication interface of the next-level control module, and the visualization module is used to display the system control process and results; One of the control modules is a main control module, which is also connected to an ADC acquisition module 64, an SD card storage module and an analog switch, and the slave SPI communication interface of the main control module is connected to the master SPI communication interface of the host computer 7, wherein the ADC acquisition module 64 is used to collect the output voltage of the series node ,The SD card storage module is used to store the network training process data and classification result data, and the analog switch is used to control the driving source module; The host computer 7 is used to interact with the main control module and provide guidance for the training of the memristor pulse neural network; An external power supply is used to drive the memristor and control module of the memristive pulse neural network.

[0024] In the following, for the convenience of description, other control modules other than the main control module are referred to as non-main control modules.

[0025] See also Figure 1~2 The basic structure of the memristor pulse neural network system is a synaptic structure composed of a pair of memristors of the same level connected in series. The two memristors represent the competing energy dissipation paths in the positive and negative Hebbian plasticity rules. The conductance of each memristor represents the dissipation rate, and the conductance difference reflects the connection weight of the synapse. When the positive driving source 1 and the negative driving source 3 apply symmetrical voltages respectively When the output voltage on the network center line driven by directional drive source 2 is That is, it reflects the state of the synapse. When , it indicates that the dissipation path represented by the positive end memristor has an absolute advantage, and vice versa, it indicates that the dissipation path represented by the negative end memristor has an advantage. When the positive end memristor has an advantage, according to the voltage division principle, it can be seen that the voltage applied to the positive end is less than the negative end voltage, making the former's conductivity increase rate lower than the latter, which is basically similar to the anti-Hebbian process. By connecting the basic synaptic structure in parallel, the most basic pulse neural network architecture can be obtained. Each synapse in the network will have its own weight. According to Kirchhoff's law, when the positive drive source 1 and the negative drive source 3 apply symmetrical voltages respectively When the output voltage of the network neutral line driven by directional drive source 2 is satisfy (1) in and Respectively represent The conductance of the positive and negative memristors connected to the network through switches. It can be seen that the classification result of the network is directly related to the synaptic weights of all connected networks. In addition to the normal input memristor, the network introduces a bias memristor with the same structure and opposite polarity to simulate the bias in linear neuron operations, while introducing a factor that antagonizes the main learning process to avoid overfitting.

[0026] Specifically, when the state of the memristor pulse neural network system is to increase the weight state of the positive-end memristor, the positive driving source 1 is a positive voltage, the directional driving source 2 is a negative voltage, and the negative driving source 3 is a negative voltage; When the state of the memristor pulse neural network system is the network result state under output weighting, the positive driving source 1 is a positive voltage, the directional driving source 2 is a floating state, and the negative driving source 3 is a negative voltage; When the state of the memristor pulse neural network system is to increase the weight of the negative-end memristor, the positive driving source 1 is a positive voltage, the directional driving source 2 is a positive voltage, and the negative driving source 3 is a negative voltage; When the state of the memristor pulse neural network system is the off initial state, the positive driving source 1 is a positive voltage, the directional driving source 2 is a positive voltage, and the negative driving source 3 is a positive voltage.

[0027] Specifically, the memristor is a physical memristor or an analog memristor, and the memristor pulse neural network system also includes a multi-level power management module, see Figure 4 , used to step down the +24V power supply provided by the external power supply, and the output covers voltage levels such as ±15V, ±2.5V, 5V and 3.3V, which is suitable for the power drive of the memristor and control module. Figure 5 , because the voltage driving levels of different submodules in the memristor pulse neural network module are inconsistent, and if the memristor simulator built based on active devices is selected as the basic unit of the neural network in the system, the power supply circuit needs to provide multiple power drives with different voltage levels. The multi-level power management module controls each level of power through a multi-level power management controller, and controls the external power input with a working voltage level of +24V according to the idea of ​​step-by-step voltage reduction. The output covers voltage levels such as ±15V, ±2.5V, 5V and 3.3V to ensure the normal operation of each module and the stable operation of the system. The characteristics of the memristor pulse neural network determine that the module cannot share the same ground with the control module, so the optocoupler isolation module is used for isolation protection between the GPIO and the memristor module, and the level conversion module converts the output signal of the optocoupler isolation module to adapt to the control requirements of the memristor module. The selected high-speed optocoupler chip 6N137 has a transmission rate of up to 10Mbit / s, which meets the high-speed requirements of the system.

[0028] Specifically, an optocoupler isolation module and a level conversion module are arranged in sequence between the GPIO control port 62 of the single-chip microcomputer and the memristor, wherein the optocoupler isolation module is used to realize isolation protection, and the level conversion module is used to convert the level of the output signal of the optocoupler isolation module to adapt to the control requirements of the memristor pulse neural network.

[0029] See also Figure 3As a specific embodiment of the present invention, the memristor pulse neural network module includes eight pairs of memristor groups, which are mounted on a voltage bus driven by three driving sources and are uniformly powered by an external power supply and a multi-level power management module to support the module's on / off control function. The optocoupler isolation module and the level conversion module are used to isolate the memristor pulse neural network module from the control module to ensure system safety.

[0030] The control module is composed of a main control module and a non-main control module, and the two realize independent on-off control of each memristor through a GPIO interface and an optical coupling isolation module. The main and non-main control modules are respectively equipped with SPI communication modules for realizing high-speed data transmission and reception, and the identity of the master and slave modules is identified through an independent identity judgment module. The system also integrates an independent visualization module to realize the visualization display of the system control process. Compared with the non-main control module, the main control module adds an analog switch control module, an SD card storage module and an ADC acquisition module 64. The analog switch control module is externally connected to a symmetrical power supply and a zero potential point, and realizes the dynamic switching of the three driving source functions by logically controlling the gating of the analog switch. The specific driving source function status is shown in the driving source state function corresponding table. The ADC acquisition module 64 is directly connected to the network center line driven by the directional driving source 2, and is used to collect data in the network training process in real time. After the training is completed, all process data and final results will be saved through the SD card storage module. The main control module communicates directly with the host computer 7, receives experimental guidance and realizes the real-time control of the system by the host computer 7. In actual implementation, the MCU61 of the control module has a relatively high main frequency, ensuring that the reading time of the pulse neural network is within 1~100us and the communication time between modules is within 1ms.

[0031] Table 1 Drive source status function correspondence table

[0032] See also Figure 6 Based on the same inventive concept, the present application provides a control method for a memristor pulse neural network system. Based on the above memristor pulse neural network system, the control method of the main control module specifically includes the following steps: S1, initializing the main control module, ADC acquisition module 64, SD card storage module and analog switch; S2, receiving the instruction from the host computer 7, determining whether to start the memristor pulse neural network system, if it is determined to be yes, executing step S3; if it is determined to be no, repeating step S2; S3, numbering the main control module and transmitting it to the next level control module, the number is 0; S4, determine whether the control module is the last level control module, if it is not, execute step S5; if it is yes, execute step S6; S5, continue to wait for the ready signal of the next level control module until the signal is received, and then execute step S6; S6. Apply for MCU memory space to increase the network training speed; S7, control the positive driving source to positive voltage, the directional driving source to floating state, the negative driving source to negative voltage, and collect the output voltage , as the initialization classification reference voltage, create a result storage file for storing network training process data and classification result data; S8, communicate with the host computer to obtain the pulse data set to be output, and determine whether the control module is the last level control module. If the determination is no, execute step S9; if the determination is yes, execute step S10; S9, sending the pulse data that needs to be output in the current round Q to the next level control module; continue to wait for the ready signal of the next level control module until the signal is received, and then execute step S10; S10, numbering the memristors according to the pulse data of the current round Q, and combining the self-numbering of the control module to determine the memristors that need to be controlled to be turned on in the current round Q, and judging whether the label of the pulse data is 0, if it is judged to be no, then executing the supervised learning process, and then entering step S11; if it is judged to be yes, then executing the unsupervised learning process, and then entering step S11; S11, obtaining the classification result of the memristor pulse neural network, performing visualization processing, and feeding back the current classification result to the host computer; judging whether the pulse data of the current round is the last set of data in the pulse data set, if the judgment is yes, executing step S13; if the judgment is no, executing step S9; S12. Storing the network training process data and the classification result data in a pre-created result storage file.

[0033] Specifically, the labels of the pulse data include three types: -1, 0 and 1, wherein -1 indicates that the group of pulse data is classified as a negative class; 1 indicates that the group of pulse data is classified as a positive class; and 0 indicates that the group of pulse data is not classified.

[0034] For details, see Figure 7 The control method of the non-main control module specifically includes the following steps: Step B1: Initializing the non-main control module, initializing the external interrupt of the non-main control module, for receiving the synchronization signal of the main control module; Step B2: Determine whether the number of the upper-level control module is received. If it is determined to be yes, execute step B3; if it is determined to be no, repeat step B2; Step B3: add 1 to the received number as the number of this module, and determine whether this module is the last-level control module. If it is not, execute step B4; if it is yes, execute and go to step B5; Step B4: try to pass the number to the next level control module, and continue to wait for the ready signal of the next level control module until the signal is received, and then execute step B5; Step B5: Transmit a ready signal to the upper level control module; clear the suspend register, set and enable the external interrupt to receive the synchronization signal of the main control module; initialize and turn on all memristors controlled by this module, and cooperate with the main control module to collect the initialization classification reference voltage; Step B6: Turn off all memristors, start communication reception, and set external interrupts to disable to prevent interruptions from interrupting the communication process and causing system errors; Step B7: Determine whether the pulse data of the current round is received. If it is determined to be yes, execute step B8; if it is determined to be no, repeat step B7; Step B8: Determine whether this module is the last level control module. If it is not, execute step B9; if it is yes, execute and transfer to step B10; Step B9: Send pulse data to the next level control module, and continue to wait for the ready signal of the next level control module until the signal is received, and then execute step B10; Step B10: According to the pulse data of the current round and the number of the current module, determine the memristor that needs to be controlled to be turned on in the current round, turn off the communication reception, set to enable the external interrupt, used to receive the synchronization signal of the main control module, and send a ready signal to the upper-level control module; Step B11: Determine whether the module triggers the first external interrupt. If it is, execute step B12; if it is not, repeat step B11. Step B12: Turn on the corresponding memristor and write the current round pulse information; Step B13: Determine whether the module triggers the second external interrupt. If it is, execute step B14; if it is not, repeat step B13. Step B14: Turning on the corresponding memristor and waiting for the main control module to collect the classification result of the memristor pulse neural network in this round; Step B15: After the main control module collects the data, it determines whether the module triggers the third external interrupt. If it is determined to be yes, step B16 is executed; if it is determined to be no, step B15 is repeated. Step B16: Turn off the corresponding memristor, set the external interrupt to be disabled to avoid interruption of the communication process causing system errors, start communication reception, and execute step B7.

[0035] For details, see Figure 8 When the supervised learning process is performed in step S10, the step S11 of obtaining the classification result of the memristor pulse neural network specifically includes the following steps: Step C1: Determine whether the label of the pulse data is 1. If it is, execute step C2; if it is not, execute step C3; Step C2: The pulse neural network classification result is positive, the positive driving source 1 is controlled to be a positive voltage, the directional driving source 2 is controlled to be a negative voltage, the negative driving source 3 is controlled to be a negative voltage, the upper half memristor between the positive driving source 1 and the directional driving source 2 is controlled to be turned on, and step C4 is executed; Step C3: The pulse neural network classification result is obtained as a negative class, the positive driving source 1 is controlled to be a positive voltage, the directional driving source 2 is controlled to be a positive voltage, the negative driving source 3 is controlled to be a negative voltage, the lower half memristor between the directional driving source 2 and the negative driving source 3 is controlled to be turned on, and step C4 is executed; Step C4: the main control module generates a synchronization signal, triggers the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

[0036] For details, see Fig. 9 When step S10 performs the unsupervised learning process, step S11 of obtaining the classification result of the memristor pulse neural network specifically includes the following steps: Step D1: Obtain the classification result of the last round of memristor pulse neural network and collect the output voltage of the last round; Step D2: Determine whether the output voltage of the previous round is greater than the initialization classification reference voltage. If it is determined to be yes, execute step D3; if it is determined to be no, execute step D6; Step D3: The pulse neural network classification result is obtained as a positive class, the positive driving source 1 is controlled to be a positive voltage, the directional driving source 2 is controlled to be a negative voltage, the negative driving source 3 is controlled to be a negative voltage, the upper half memristor between the positive driving source 1 and the directional driving source 2 is controlled to be turned on, and step D5 is executed; Step D4: The pulse neural network classification result is obtained as a negative class, the positive driving source 1 is controlled to be a positive voltage, the directional driving source 2 is controlled to be a positive voltage, the negative driving source 3 is controlled to be a negative voltage, the negative end memristor of the lower half memristor between the directional driving source 2 and the negative driving source 3 is controlled to be turned on, and step D5 is executed; Step D5: The main control module generates a synchronization signal, triggers the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

[0037] Specifically, see 8~9, which also includes the following steps: Step E1: The main control module generates a synchronization signal, triggers the second external interrupt of the non-control module, turns on the corresponding memristor, controls the positive driving source 1 to be a positive voltage, the directional driving source 2 to be a zero voltage, and the negative driving source 3 to be a negative voltage; Step E2: Collect the output voltage of the series node through the ADC acquisition module 64 , turn off the corresponding memristor, the main control module generates a synchronization signal, triggers the third external interrupt of the non-control module, and executes step S11.

[0038] The memristor pulse neural network system provided in this application adopts a cascaded scalable control architecture combining master control and slave control, and each non-master control module independently manages the on-off operation of multiple pairs of input memristor pairs or bias memristor pairs. The main control board directly controls the real-time state of the drive source group through analog switches, manages the three drive buses in the pulse neural network, and uses the ADC acquisition module to monitor the median voltage in the network in real time, and transmits the feedback signal to the host computer to assist it in making accurate decisions. The minimum configuration of the system only requires a host computer responsible for decision-making and a main control board, and the non-master control modules can be flexibly cascaded according to the actual needs of the neural network to achieve unlimited expansion.

[0039] By simulating the synaptic structure of biological neural networks through bionic design and realizing adaptive learning based on positive and negative Hebbian plasticity rules, the present invention further strengthens the computing function of the memristor's integrated storage and computing performance, significantly improves learning efficiency, and maintains excellent stability and generalization ability under different working conditions. The high scalability of the master-slave cascade control architecture allows the network scale to be flexibly adjusted according to actual needs. The real-time feedback mechanism of the ADC module greatly improves the experimental accuracy and response speed, while the modular design ensures the compatibility and flexibility of the system.

[0040] In practical applications, this system is compatible with various types and manufacturing processes of memristors or memristor simulators, such as active device memristor simulator modules, 16P packaged memristor modules, 32P packaged memristor modules, etc. These modules, as the core units of the system, participate in the construction and operation of neural networks. By integrating different types of memristors or simulators, the system can achieve diversified expansion and performance optimization of pulse neural network functions, showing strong applicability and generalization.

[0041] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A memristor pulse neural network system, characterized in that: include A driving source module, comprising a positive driving source (1), a directional driving source (2) and a negative driving source (3), for switching the state of the memristor pulse neural network system; A memristor pulse neural network comprises at least one input memristor group (4) and at least one bias memristor group (5), wherein the input memristor group (4) is formed by connecting a plurality of first basic structures in parallel, wherein the first basic structure is a pair of same-level positive-connected input memristors (42) connected in series, and each of the same-level positive-connected input memristors (42) is provided with an independent switch (41); the bias memristor group (5) is formed by connecting a plurality of second basic structures in parallel, wherein the second basic structure is a pair of same-level reverse-connected bias memristors (51) connected in series, and each of the same-level reverse-connected bias memristors (51) is provided with an independent switch (52); a positive drive source (1) is connected to the positive end of the first basic structure and the negative end of the second basic structure, a directional drive source (2) is connected to the series node of the first basic structure and the second basic structure, and a negative drive source (3) is connected to the positive end of the first basic structure and the negative end of the second basic structure, and switches are provided on both the first basic structure and the second basic structure; Each input memristor group (4) or bias memristor group (5) is connected to a control module to form a cascaded memristor pulse neural network control module (6); The control module comprises a single-chip computer, the single-chip computer is connected to an SPI communication interface module (63) and a visualization module, the GPIO control port (62) of the single-chip computer is connected to the memristor of the memristive pulse neural network, the slave SPI communication interface of this level is used to connect to the master SPI communication interface of the previous level control module, the master SPI communication interface of this level is used to connect to the slave SPI communication interface of the next level control module, and the visualization module is used to display the system control process and results; One of the control modules is a main control module, the main control module is also connected to an ADC acquisition module (64), an SD card storage module and an analog switch, and a slave SPI communication interface of the main control module is connected to a master SPI communication interface of a host computer (7), wherein the ADC acquisition module (64) is used to acquire the output voltage of the series node ,The SD card storage module is used to store the network training process data and classification result data, and the analog switch is used to control the driving source module; A host computer (7) is used to interact with the main control module and provide guidance for the training of the memristor pulse neural network; An external power supply is used to drive the memristor and control module of the memristive pulse neural network.

2. A memristor pulse neural network system according to claim 1, characterized in that: When the state of the memristor pulse neural network system is to increase the weight of the positive-end memristor, the positive driving source (1) is a positive voltage, the directional driving source (2) is a negative voltage, and the negative driving source (3) is a negative voltage; When the state of the memristor pulse neural network system is the network result state under output weighting, the positive driving source (1) is a positive voltage, the directional driving source (2) is in a floating state, and the negative driving source (3) is a negative voltage; When the state of the memristor pulse neural network system is to increase the weight of the negative-end memristor, the positive driving source (1) is a positive voltage, the directional driving source (2) is a positive voltage, and the negative driving source (3) is a negative voltage; When the state of the memristor pulse neural network system is the off initial state, the positive driving source (1) is a positive voltage, the directional driving source (2) is a positive voltage, and the negative driving source (3) is a positive voltage.

3. A memristor pulse neural network system according to claim 1, characterized in that: The memristor is a physical memristor or an analog memristor. The memristor pulse neural network system also includes a multi-level power management module for gradually stepping down the +24V power supply provided by an external power supply. The output covers voltage levels of ±15V, ±2.5V, 5V and 3.3V, which is suitable for the power drive of the memristor and the control module.

4. The memristor pulse neural network system according to claim 1, characterized in that: An optocoupler isolation module and a level conversion module are sequentially arranged between the GPIO control port (62) of the single-chip computer and the memristor, wherein the optocoupler isolation module is used to realize isolation protection, and the level conversion module is used to perform level conversion on the output signal of the optocoupler isolation module to adapt to the control requirements of the memristor pulse neural network.

5. A control method for a memristor pulse neural network system, characterized in that: Based on the memristor pulse neural network system described in claim 1, the control method of the main control module specifically includes the following steps: S1, initializing the main control module, the ADC acquisition module (64), the SD card storage module and the analog switch; S2, receiving the instruction from the host computer (7), determining whether to start the memristor pulse neural network system, if the determination is yes, executing step S3; if the determination is no, repeating step S2; S3, numbering the main control module and transmitting it to the next level control module, the number is 0; S4, determine whether the control module is the last level control module, if it is not, execute step S5; if it is yes, execute step S6; S5, continue to wait for the ready signal of the next level control module until the signal is received, and then execute step S6; S6. Apply for MCU memory space to increase the network training speed; S7, control the positive drive source (1) to a positive voltage, the directional drive source (2) to a floating state, the negative drive source (3) to a negative voltage, and collect the output voltage , as the initialization classification reference voltage, create a result storage file for storing network training process data and classification result data; S8, communicating with the host computer (7), obtaining the pulse data set to be output, and determining whether the control module is the last level control module. If the determination is no, executing step S9; if the determination is yes, executing step S10; S9, sending the pulse data that needs to be output in the current round Q to the next level control module; continue to wait for the ready signal of the next level control module until the signal is received, and then execute step S10; S10, numbering the memristors according to the pulse data of the current round Q, and combining the self-numbering of the control module to determine the memristors that need to be controlled to be turned on in the current round Q, and judging whether the label of the pulse data is 0, if it is judged to be no, then executing the supervised learning process, and then entering step S11; if it is judged to be yes, then executing the unsupervised learning process, and then entering step S11; S11, obtaining the classification result of the memristor pulse neural network, performing visualization processing, and feeding back the current classification result to the host computer (7); determining whether the pulse data of the current round is the last set of data in the pulse data set, if the determination is yes, executing step S13; if the determination is no, executing step S9; S12. Storing the network training process data and the classification result data in a pre-created result storage file.

6. The control method of a memristor pulse neural network system according to claim 5, characterized in that: The labels of the pulse data include -1, 0 and 1, wherein -1 indicates that the group of pulse data is classified as a negative class; 1 indicates that the group of pulse data is classified as a positive class; and 0 indicates that the group of pulse data is not classified.

7. The control method of a memristor pulse neural network system according to claim 5, characterized in that: The control method of the non-main control module specifically includes the following steps: Step B1: Initializing the non-main control module, initializing the external interrupt of the non-main control module, for receiving the synchronization signal of the main control module; Step B2: Determine whether the number of the upper-level control module is received. If it is determined to be yes, execute step B3; if it is determined to be no, repeat step B2; Step B3: add 1 to the received number as the number of this module, and determine whether this module is the last-level control module. If it is not, execute step B4; if it is yes, execute and go to step B5; Step B4: try to pass the number to the next level control module, and continue to wait for the ready signal of the next level control module until the signal is received, and then execute step B5; Step B5: Transmit a ready signal to the upper level control module; clear the suspend register, set and enable the external interrupt to receive the synchronization signal of the main control module; initialize and turn on all memristors controlled by this module, and cooperate with the main control module to collect the initialization classification reference voltage; Step B6: Turn off all memristors, start communication reception, and set external interrupts to disable to prevent interruptions from interrupting the communication process and causing system errors; Step B7: Determine whether the pulse data of the current round is received. If it is determined to be yes, execute step B8; if it is determined to be no, repeat step B7; Step B8: Determine whether this module is the last level control module. If it is not, execute step B9; if it is yes, execute and transfer to step B10; Step B9: Send pulse data to the next level control module, and continue to wait for the ready signal of the next level control module until the signal is received, and then execute step B10; Step B10: According to the pulse data of the current round and the number of the current module, determine the memristor that needs to be controlled to be turned on in the current round, turn off the communication reception, set to enable the external interrupt, used to receive the synchronization signal of the main control module, and send a ready signal to the upper-level control module; Step B11: Determine whether the module triggers the first external interrupt. If it is, execute step B12; if it is not, repeat step B11. Step B12: Turn on the corresponding memristor and write the current round pulse information; Step B13: Determine whether the module triggers the second external interrupt. If it is, execute step B14; if it is not, repeat step B13. Step B14: Turning on the corresponding memristor and waiting for the main control module to collect the classification result of the memristor pulse neural network in this round; Step B15: After the main control module collects the data, it determines whether the module triggers the third external interrupt. If it is determined to be yes, step B16 is executed; if it is determined to be no, step B15 is repeated. Step B16: Turn off the corresponding memristor, set the external interrupt to be disabled to avoid interruption of the communication process causing system errors, start communication reception, and execute step B7.

8. The control method of a memristor pulse neural network system according to claim 5, characterized in that: When the supervised learning process is performed in step S10, obtaining the classification result of the memristor pulse neural network in step S11 specifically includes the following steps: Step C1: Determine whether the label of the pulse data is 1. If it is, execute step C2; if it is not, execute step C3; Step C2: The pulse neural network classification result is obtained as a positive class, the positive driving source (1) is controlled to be a positive voltage, the directional driving source (2) is controlled to be a negative voltage, the negative driving source (3) is controlled to be a negative voltage, the upper half memristor between the positive driving source (1) and the directional driving source (2) is controlled to be turned on, and step C4 is executed; Step C3: The classification result of the pulse neural network is obtained as a negative class, the positive driving source (1) is controlled to be a positive voltage, the directional driving source (2) is controlled to be a positive voltage, the negative driving source (3) is controlled to be a negative voltage, the lower half memristor between the directional driving source (2) and the negative driving source (3) is controlled to be turned on, and step C4 is executed; Step C4: the main control module generates a synchronization signal, triggers the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

9. The control method of a memristor pulse neural network system according to claim 5, characterized in that: When step S10 performs the unsupervised learning process, step S11 of obtaining the classification result of the memristor pulse neural network specifically includes the following steps: Step D1: Obtain the classification result of the last round of memristor pulse neural network and collect the output voltage of the last round; Step D2: Determine whether the output voltage of the previous round is greater than the initialization classification reference voltage. If it is determined to be yes, execute step D3; if it is determined to be no, execute step D6; Step D3: When the classification result of the pulse neural network is positive, the positive driving source (1) is controlled to be a positive voltage, the directional driving source (2) is controlled to be a negative voltage, the negative driving source (3) is controlled to be a negative voltage, the upper half memristor between the positive driving source (1) and the directional driving source (2) is controlled to be turned on, and step D5 is executed; Step D4: The classification result of the pulse neural network is obtained as a negative class, the positive driving source (1) is controlled to be a positive voltage, the directional driving source (2) is controlled to be a positive voltage, the negative driving source (3) is controlled to be a negative voltage, the negative end memristor of the lower half memristor between the directional driving source (2) and the negative driving source (3) is controlled to be turned on, and step D5 is executed; Step D5: The main control module generates a synchronization signal, triggers the first external interrupt of the non-control module, writes pulse data to the memristor pulse neural network, and controls the memristor to be turned on and off.

10. A control method for a memristor pulse neural network system according to claim 8 or 9, characterized in that: The following steps are also included: Step E1: the main control module generates a synchronization signal, triggers the second external interrupt of the non-control module, turns on the corresponding memristor, controls the positive driving source (1) to be a positive voltage, the directional driving source (2) to be a floating state, and the negative driving source (3) to be a negative voltage; Step E2: Collect the output voltage of the series node through the ADC acquisition module (64) , turn off the corresponding memristor, the main control module generates a synchronization signal, triggers the third external interrupt of the non-control module, and executes step S11.

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