Timing controller, display device and image data processing method

Abstract

Disclosed is a time schedule controller, comprising: a clock frequency switching unit for receiving the control signal, and switching the current image to a predetermined vertical blanking time according to the control signal when determining that the vertical blanking time of the current image is greater than the shortest vertical blanking time; generating a switching signal under the clock frequency after the effective display end moment of the current image; the pixel clock signal generation unit is used for receiving the main clock signal and receiving the switching signal under the clock frequency under the condition that the vertical blanking time of the current image is greater than the shortest vertical blanking time; and generating a pixel clock signal having a frequency K times the frequency of the master clock signal in response to the clock frequency switching signal, where 0 < = K < 1. A display device using the timing controller and a method of processing image data using the timing controller are also disclosed.

Description

Technical Field

[0001] The present invention generally relates to a timing controller, and more particularly to a timing controller capable of reducing power consumption, a display device using the timing controller, and a method for processing image data using the timing controller. Background Art

[0002] As information technology develops, the importance of display devices as a connection medium between users and information is being emphasized. For example, the use of display devices such as liquid crystal display devices, organic light emitting display devices, plasma display devices, etc. is increasing.

[0003] In traditional display devices, the image frame rate output by an external host processor (such as a GPU) to a display panel is affected by the load of the host processor itself and fluctuates all the time. When the host processor load is high, the output image frame rate is low, and when the host processor load is low, the output image frame rate is high. When the display panel refresh rate does not match the image frame rate, screen freezes, tearing, and other phenomena will occur, thus affecting the user experience.

[0004] The current technology to solve the mismatch between the image frame rate output by the host processor and the refresh rate of the display panel mainly includes VRR (Variable Refresh Rate) technology. VRR technology controls the image frame rate output by the host processor by scaling the vertical blanking (Vblank) time while keeping the effective display time unchanged. However, since VRR technology only extends the V-blank time, when the image frame rate output by the host processor is low, the frequency of the pixel clock signal generated by the timing controller (TCON) of the display device is still the same as the frequency of the pixel clock signal generated by the timing controller of the display device when the host processor outputs the highest image frame rate, which will cause a significant increase in the useless power consumption of the timing controller. Summary of the invention

[0005] In order to solve the technical problems existing in the above-mentioned prior art, embodiments of the present invention provide a timing controller capable of reducing power consumption, a display device using the timing controller, and a method for processing image data using the timing controller.

[0006] According to one aspect of an embodiment of the present invention, a timing controller is provided that receives a main clock signal and a control signal of a current image from an external host processor, and the timing controller includes: a clock frequency switching unit, for receiving the control signal, and generating a clock frequency switching signal after the effective display end time of the current image when it is determined that the vertical blanking time of the current image is greater than the shortest vertical blanking time according to the control signal; a pixel clock signal generating unit, for receiving the main clock signal, and receiving the clock frequency switching signal when the vertical blanking time of the current image is greater than the shortest vertical blanking time, and generating a pixel clock signal having a frequency K times the frequency of the main clock signal in response to the clock frequency switching signal, wherein 0≤K<1.

[0007] In an example of the timing controller provided in the above aspect, the clock frequency switching unit is also used to generate a clock frequency up-switching signal before the effective display start time of the next image when the vertical bottom blanking time of the current image is greater than the shortest vertical bottom blanking time; the pixel clock signal generating unit is also used to receive the clock frequency up-switching signal when the vertical bottom blanking time of the current image is greater than the shortest vertical bottom blanking time, and generate a pixel clock signal having a frequency of the main clock signal in response to the clock frequency up-switching signal.

[0008] In an example of the timing controller provided in the above aspect, the clock frequency switching unit is also used to generate a clock frequency holding signal according to the control signal when the vertical blanking time of the current image is equal to the shortest vertical blanking time; the pixel clock signal generating unit is also used to receive the clock frequency holding signal when the vertical blanking time of the current image is equal to the shortest vertical blanking time, and generate a pixel clock signal having a frequency of the main clock signal in response to the clock frequency holding signal.

[0009] In an example of the timing controller provided in the above aspect, the timing controller also receives input pixel data of the current image from the external host processor, wherein the timing controller also includes: an image processing unit for generating a scanning control signal, a data control signal and output pixel data of the current image based on the control signal, the input pixel data and a pixel clock signal having a frequency of the main clock signal.

[0010] In an example of the timing controller provided in the above aspect, K is 1 / 2 or 1 / 4 or 1 / 8 or 0.

[0011] According to another aspect of the embodiments of the present invention, a display device is provided including the above-mentioned timing controller.

[0012] According to another aspect of an embodiment of the present invention, a method for processing image data includes: receiving a main clock signal and a control signal of a current image from an external host processor; determining, based on the control signal, that a vertical blanking time of the current image is greater than a minimum vertical blanking time; generating a clock frequency switching signal after the effective display end moment of the current image; and generating a pixel clock signal having a frequency K times that of the main clock signal in response to the clock frequency switching signal, wherein 0≤K<1.

[0013] In an example of the image data processing method provided in the above aspect, the processing method also includes: generating a clock frequency switching signal before the effective display start time of the next image when the vertical blanking time of the current image is greater than the shortest vertical blanking time; and generating a pixel clock signal having a frequency having the frequency of the main clock signal in response to the clock frequency switching signal.

[0014] In an example of the image data processing method provided in the above aspect, the processing method also includes: determining that the vertical blanking time of the current image is equal to the shortest vertical blanking time according to the control signal, and generating a clock frequency holding signal; and generating a pixel clock signal having a frequency having the frequency of the main clock signal in response to the clock frequency holding signal.

[0015] In an example of the image data processing method provided in the above aspect, the processing method also includes: receiving input pixel data of the current image from the external host processor; generating a scanning control signal, a data control signal and output pixel data of the current image according to the control signal, the input pixel data and a pixel clock signal having a frequency of the main clock signal.

[0016] Beneficial effect: According to an embodiment of the present invention, the frequency of the pixel clock signal generated by the timing controller within the effective display time of a frame of image is the same as the frequency of the main clock signal, while the frequency of the pixel clock signal generated during the remaining time of a frame of image except the effective display time (for example, the vertical upper blanking time and the vertical lower blanking time) is lower than the frequency of the main clock signal, which can effectively reduce the power consumption of the timing controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features and advantages of the embodiments of the present invention will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a block diagram of a display device according to an embodiment of the present invention;

[0019] Figure 2is a display state diagram of a display panel in a column direction according to an embodiment of the present invention;

[0020] Figure 3 is a block diagram of a timing controller according to an embodiment of the present invention;

[0021] Figure 4 is a flowchart of a method for processing image data according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following detailed description is provided to help the reader gain a comprehensive understanding of the methods, devices and / or systems described herein. However, after understanding the disclosure of the present invention, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be clear. In addition, for greater clarity and simplicity, descriptions of features known in the art may be omitted.

[0023] The features described herein can be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein have been provided to illustrate only some of the many possible ways to implement the methods, devices, and / or systems described herein, which will be clear after understanding the disclosure of the present invention.

[0024] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more.

[0025] The terms used herein are only used to describe various examples and are not intended to limit the disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms "comprise", "include" and "have" indicate the presence of the described features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which the present invention belongs after understanding the present invention. Unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the present invention, and should not be interpreted in an idealized or overly formal manner.

[0027] Furthermore, in the description of the examples, when it is considered that a detailed description of a well-known related construction or function will cause vague interpretation of the present invention, such a detailed description will be omitted.

[0028] Figure 1is a block diagram of a display device according to an embodiment of the present invention.

[0029] Reference Figure 1 According to an embodiment of the present invention, a display device 100 may include a display panel 110 including a plurality of pixels PX, a scan driver 120 that provides a scan signal SS to the plurality of pixels PX, a data driver 130 that provides a data voltage VD to the plurality of pixels PX, and a timing controller 140 that controls the scan driver 120 and the data driver 130.

[0030] The display panel 110 may include a plurality of scan lines SL1 to SLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX (assuming that n and m are integers greater than or equal to 2). Each of the scan lines SL1 to SLn may extend in a first direction (e.g., a row direction), and each of the data lines DL1 to DLm may extend in a second direction (e.g., a column direction) intersecting the first direction. The scan lines SL1 to SLn and the data lines DL1 to DLm may be insulated from each other. A plurality of pixels PX may be arranged in a region where the scan lines SL1 to SLn and the data lines DL1 to DLm intersect.

[0031] In an embodiment, each of the plurality of pixels PX may include a switching transistor transmitting a data voltage VD in response to a scan signal SS, a storage capacitor storing the data voltage VD transmitted by the switching transistor, a driving transistor generating a driving current based on the data voltage VD stored in the storage capacitor, and a light emitting element emitting light based on the driving current generated by the driving transistor. For example, the light emitting element may include a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting element, and other similar light emitting elements.

[0032] The scan driver 120 may provide the scan signal SS to the plurality of pixels PX through the plurality of scan lines SL1 to SLn based on the scan control signal SCTRL received from the timing controller 140. In an embodiment, the scan driver 120 may sequentially provide the scan signal SS to the plurality of pixels PX in row units.

[0033] The data driver 130 may receive a data control signal DCTRL and output image data ODAT from the timing controller 140. The data driver 130 may provide a data voltage VD to a plurality of pixels PX through a plurality of data lines DL1 to DLm based on the data control signal DCTRL and the output image data ODAT.

[0034] The timing controller 140 may receive input image data IDAT, a main clock signal CLK, and a control signal CTRL from an external host processor. For example, the host processor may be an application processor ("AP"), a graphics processing unit ("GPU"), or a graphics card. In an embodiment, the input image data IDAT may be RGB image data including red image data, green image data, and blue image data. The main clock signal CLK is an external pixel clock signal provided by an external host processor. In addition, the control signal CTRL may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an enable signal DE, etc., but is not limited thereto.

[0035] The timing controller 140 may generate a scan control signal SCTRL, a data control signal DCTRL, and output image data ODAT based on the input image data IDAT and the control signal CTRL. The timing controller 140 may control the operation of the scan driver 120 by providing the scan control signal SCTRL to the scan driver 120, and control the operation of the data driver 130 by providing the output image data ODAT and the data control signal DCTRL to the data driver 130.

[0036] Figure 2 A display state diagram of a display panel in a column direction according to an embodiment of the present invention.

[0037] Reference Figure 2 , when displaying a frame of picture, the display panel 110 according to the embodiment of the present invention mainly includes: a vertical synchronization area V1, a vertical upper invalid row area V2, an effective display area AF and a vertical lower invalid row area V3 in the vertical direction (column direction). Among them, during the display of a frame of picture, the time occupied by the vertical synchronization area V1 and the vertical upper invalid row area V2 is the vertical upper blanking time T1; the time occupied by the vertical lower invalid row area V3 is the vertical lower blanking time T2; the time occupied by the effective display area AF as the effective display of a frame of picture is the effective display time T3, which is equal to the time from the effective display start time T31 to the effective display end time T32.

[0038] Figure 3 is a block diagram of a timing controller according to an embodiment of the present invention.

[0039] Reference Figure 3 , the timing controller 140 according to the embodiment of the present invention may include a clock frequency switching unit 141 , a pixel clock signal generating unit 142 , and an image processing unit 143 .

[0040] The clock frequency switching unit 141 can determine the vertical lower blanking time T2 of the current image based on the main clock signal CLK and the control signal CTRL (specifically, the horizontal synchronization signal Hsync and the enable signal DE in the control signal CTRL) corresponding to the current image input by the external host processor. The clock frequency switching unit 141 can compare the vertical lower blanking time T2 with the shortest vertical lower blanking time. The clock frequency switching unit 141 can generate a clock frequency lower switching signal after the effective display end time T32 corresponding to the current image when it determines that the vertical lower blanking time T2 is greater than or equal to the shortest vertical lower blanking time.

[0041] Here, the shortest vertical blanking time means that: the display panel 110 has a maximum refresh rate (for example, 60 Hz). When the external host processor inputs a signal corresponding to a frame of image to the timing controller 140 at a frame rate corresponding to the highest refresh rate (for example, 60 Hz), the timing controller 140 controls the display panel 110 to display the frame of image at the highest refresh rate according to the corresponding signal. The vertical blanking time corresponding to the frame of image is the shortest vertical blanking time.

[0042] Therefore, when the vertical blanking time T2 of a certain frame of image is less than the shortest vertical blanking time, it means that the external host processor inputs the signal corresponding to the certain frame of image to the timing controller 140 at a frame rate lower than the maximum refresh rate. This is because, in this embodiment, no matter at what frame rate the external host processor inputs the signal corresponding to a frame of image to the timing controller 140, the timing controller 140 drives the display panel 110 to display the frame of image at the highest refresh rate during the effective display time T3 of the display panel 110 displaying the frame of image. In other words, no matter at what frame rate the external host processor inputs the signal corresponding to a frame of image to the timing controller 140, the effective display time T3 of these images is the same.

[0043] The pixel clock signal generating unit 142 may receive a master clock signal CLK corresponding to a current image inputted from an external host processor. When the clock frequency switching unit 141 determines that the vertical lower blanking time T2 is greater than or equal to the shortest vertical lower blanking time, the pixel clock signal generating unit 142 may receive a clock frequency down-switching signal from the clock frequency switching unit 141. The pixel clock signal generating unit 142 generates a pixel clock signal having a frequency K times the frequency of the master clock signal CLK in response to the clock frequency down-switching signal, wherein 0≤K<1. For example, K may be 1 / 2 or 1 / 4 or 1 / 8, or even 0.

[0044] In addition, when an external host processor inputs a signal corresponding to a frame of image to the timing controller 140 at any frame rate, in order to ensure that the timing controller 140 drives the display panel 110 to display all images with the same effective display time T3, when the clock frequency switching unit 141 determines that the vertical lower blanking time T2 of the current image is greater than or equal to the shortest vertical lower blanking time, the clock frequency switching unit 141 generates a clock frequency up-switching signal before the effective display time T31 of the next image; the pixel clock signal generating unit 142 can receive the clock frequency up-switching signal from the clock frequency switching unit 141, and generate a pixel clock signal having a frequency of the main clock signal CLK in response to the clock frequency up-switching signal. That is to say, the frequency of the pixel clock signal generated by the pixel clock signal generating unit 142 within the effective display time of a frame image is the same as the frequency of the main clock signal CLK, while the frequency of the pixel clock signal generated by the pixel clock signal generating unit 142 during the remaining time of a frame image except the effective display time (for example, the vertical upper blanking time T1 and the vertical lower blanking time T2) is lower than the frequency of the main clock signal CLK, which can effectively reduce the power consumption of the timing controller 140.

[0045] The image processing unit 143 can generate a scanning control signal SCTRL, a data control signal DCTRL and output image data ODAT of the current image based on the control signal CTRL (vertical synchronization signal Vsync, horizontal synchronization signal Hsync, enable signal DE, etc.) corresponding to the current image input by the external host processor and the pixel clock signal having the frequency of the main clock signal CLK provided by the pixel clock signal generation unit 142.

[0046] Figure 4 is a flowchart of a method for processing image data according to an embodiment of the present invention.

[0047] Reference Figure 4 In step S410, a master clock signal and a control signal of a current image are received from an external host processor.

[0048] Specifically, refer to Figure 3 The clock frequency switching unit 141 can receive a main clock signal CLK and a control signal CTRL (specifically, a horizontal synchronization signal Hsync and an enable signal DE in the control signal CTRL) corresponding to the current image from an external host processor.

[0049] In step S420, it is determined according to the control signal whether the vertical blanking time of the current image is greater than or equal to the shortest vertical blanking time.

[0050] Specifically, refer to Figure 3The clock frequency switching unit 141 determines the vertical lower blanking time T2 of the current image based on the main clock signal CLK and the control signal CTRL corresponding to the current image input by the external host processor. The clock frequency switching unit 141 can compare the vertical lower blanking time T2 with the shortest vertical lower blanking time to determine whether the vertical lower blanking time T2 is greater than the shortest vertical lower blanking time.

[0051] In step S430, a switching signal is generated at a clock frequency after the effective display end time of the current image.

[0052] Specifically, refer to Figure 3 The clock frequency switching unit 141 may generate a clock frequency down-switching signal after the effective display end time T32 corresponding to the current image when it determines that the vertical down-blanking time T2 is greater than or equal to the shortest vertical down-blanking time.

[0053] In step S440 , a pixel clock signal having a frequency K times the frequency of the main clock signal is generated in response to the clock frequency down-switching signal, where 0≤K<1.

[0054] Specifically, refer to Figure 3 , the pixel clock signal generating unit 142 may receive a master clock signal CLK corresponding to the current image inputted based on an external host processor. In the case where the clock frequency switching unit 141 determines that the vertical lower blanking time T2 is greater than or equal to the shortest vertical lower blanking time, the pixel clock signal generating unit 142 may receive a clock frequency down-switching signal from the clock frequency switching unit 141. The pixel clock signal generating unit 142 generates a pixel clock signal having a frequency K times the frequency of the master clock signal CLK in response to the clock frequency down-switching signal, wherein 0≤K<1. For example, K may be 1 / 2 or 1 / 4 or 1 / 8, or even 0.

[0055] Of course, as another embodiment, the clock frequency switching unit 141 may generate a clock frequency holding signal when it determines that the vertical lower blanking time T2 is equal to the shortest vertical lower blanking time. The pixel clock signal generating unit 142 may receive the clock frequency holding signal from the clock frequency switching unit 141, and generate a pixel clock signal having a frequency of the frequency of the master clock signal in response to the clock frequency holding signal.

[0056] In addition, as another embodiment, when an external host processor inputs a signal corresponding to a frame of image to the timing controller 140 at any frame rate, in order to ensure that the timing controller 140 drives the display panel 110 to display all images with the same effective display time T3, when the clock frequency switching unit 141 determines that the vertical lower blanking time T2 of the current image is greater than or equal to the shortest vertical lower blanking time, the clock frequency switching unit 141 generates a clock frequency up-switching signal before the effective display time T31 of the next image; the pixel clock signal generating unit 142 can receive the clock frequency up-switching signal from the clock frequency switching unit 141, and generate a pixel clock signal having a frequency of the main clock signal CLK in response to the clock frequency up-switching signal.

[0057] That is to say, the frequency of the pixel clock signal generated by the pixel clock signal generating unit 142 within the effective display time of a frame image is the same as the frequency of the main clock signal CLK, while the frequency of the pixel clock signal generated by the pixel clock signal generating unit 142 during the remaining time of a frame image except the effective display time (for example, the vertical upper blanking time T1 and the vertical lower blanking time T2) is lower than the frequency of the main clock signal CLK, which can effectively reduce the power consumption of the timing controller 140.

[0058] Further, in Figure 4 After step S440 shown in the figure, the image data processing method according to the embodiment of the present invention may further include: receiving input pixel data of the current image from the external host processor; generating a scan control signal, a data control signal and output pixel data of the current image according to the control signal, the input pixel data and a pixel clock signal having a frequency of the main clock signal. Specifically, continue to refer to Figure 3 The image processing unit 143 can generate a scanning control signal SCTRL, a data control signal DCTRL and output image data ODAT of the current image based on the control signal CTRL (vertical synchronization signal Vsync, horizontal synchronization signal Hsync, enable signal DE, etc.) corresponding to the current image input by the external host processor and the pixel clock signal having the frequency of the main clock signal CLK provided by the pixel clock signal generation unit 142.

[0059] To summarize, the frequency of the pixel clock signal generated by the timing controller according to an embodiment of the present invention within the effective display time of a frame of image is the same as the frequency of the main clock signal, while the frequency of the pixel clock signal generated during the remaining time of a frame of image except the effective display time (for example, the vertical upper blanking time and the vertical lower blanking time) is lower than the frequency of the main clock signal, thereby effectively reducing the power consumption of the timing controller.

[0060] The specific implementation methods of the present invention are described in detail above. Although some embodiments have been shown and described, those skilled in the art should understand that these embodiments may be modified and varied without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents. These modifications and variations should also be within the scope of protection of the claims of the present invention.

Claims

1. A timing controller, characterized in that: Receive a master clock signal and a control signal of a current image from an external host processor, wherein the timing controller comprises: a clock frequency switching unit, configured to receive the control signal and, based on the control signal, generate a clock frequency down-switching signal after the effective display end time of the current image when it is determined that the vertical down-blanking time of the current image is greater than the shortest vertical down-blanking time; A pixel clock signal generating unit is used to receive the main clock signal, and receive the clock frequency switching signal when the vertical blanking time of the current image is greater than the shortest vertical blanking time, and generate a pixel clock signal having a frequency K times the frequency of the main clock signal in response to the clock frequency switching signal, wherein 0≤K<1.

2. The timing controller according to claim 1, characterized in that: The clock frequency switching unit is further used to generate a clock frequency up-switching signal before the effective display start time of the next image when the vertical bottom blanking time of the current image is greater than the shortest vertical bottom blanking time; The pixel clock signal generating unit is also used to receive the clock frequency switching signal when the vertical blanking time of the current image is greater than the shortest vertical blanking time, and generate a pixel clock signal having a frequency of the main clock signal in response to the clock frequency switching signal.

3. The timing controller according to claim 1 or 2, characterized in that: The clock frequency switching unit is further used to generate a clock frequency holding signal according to the control signal when the vertical blanking time of the current image is equal to the shortest vertical blanking time; The pixel clock signal generating unit is also used to receive the clock frequency holding signal when the vertical blanking time of the current image is equal to the shortest vertical blanking time, and generate a pixel clock signal having a frequency of the main clock signal in response to the clock frequency holding signal.

4. The timing controller according to claim 1 or 2, characterized in that: Also receiving input pixel data of the current image from the external host processor, wherein the timing controller further comprises: The image processing unit is used to generate a scanning control signal, a data control signal and output pixel data of a current image according to the control signal, the input pixel data and a pixel clock signal having a frequency of the main clock signal.

5. The timing controller according to claim 1, characterized in that: The K is 1 / 2 or 1 / 4 or 1 / 8 or 0.

6. A display device, characterized in that: A timing controller comprising any one of claims 1 to 5.

7. A method for processing image data, characterized in that: The processing method comprises: Receive a master clock signal and control signals for the current image from an external host processor; Determine, according to the control signal, that the vertical bottom blanking time of the current image is greater than the shortest vertical bottom blanking time; generating a clock frequency switching signal after the effective display end time of the current image; A pixel clock signal having a frequency K times the frequency of the main clock signal is generated in response to the clock frequency down-switching signal, wherein 0≤K<1.

8. The processing method according to claim 7, characterized in that: The processing method also includes: In the case where the vertical blanking time below the current image is greater than the shortest vertical blanking time below, generating a clock frequency up-switching signal before the effective display start time of the next image; A pixel clock signal having a frequency of the main clock signal is generated in response to the clock frequency up-switching signal.

9. The processing method according to claim 7 or 8, characterized in that: The processing method also includes: Determine, according to the control signal, that the vertical blanking time below the current image is equal to the shortest vertical blanking time below, and generate a clock frequency holding signal; A pixel clock signal having a frequency of the master clock signal is generated in response to the clock frequency maintaining signal.

10. The processing method according to claim 7 or 8, characterized in that: The processing method also includes: receiving input pixel data of a current image from the external host processor; A scanning control signal, a data control signal, and output pixel data of a current image are generated according to the control signal, the input pixel data, and a pixel clock signal having a frequency of the main clock signal.

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