Display device

Abstract

The invention discloses a display device comprising at least one data driver, the data driver comprising a data driving module and a buffer control module; the data driving module comprises a plurality of output buffers, and the output buffers are used for transmitting data voltage to data lines corresponding to the data driver when the output buffers are started; the buffer control module is connected with the control ends of the output buffers, and the buffer control module is used for enabling or disabling the corresponding output buffers according to the control signals. The power consumption of the display device can be reduced, and the display effect is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device. Background Art

[0002] With the continuous development of display technology, people have higher and higher requirements on the performance of display devices. At present, existing display devices have the problem of high power consumption. Summary of the invention

[0003] The present invention provides a display device to reduce power consumption of the display device and improve display performance.

[0004] The present invention provides a display device, comprising: at least one data driver, the data driver comprising a data driver module and a buffer control module; the data driver module comprising a plurality of output buffers, the output buffers being used to transmit data voltages to data lines corresponding to the data driver when enabled; the buffer control module being connected to control ends of the plurality of output buffers, the buffer control module being used to enable or disable the output buffers according to a control signal.

[0005] Optionally, the buffer control module includes multiple logic units, the multiple logic units correspond one-to-one to the multiple output buffers, and the control signal includes a first control signal and a second control signal; the first input end of the logic unit is connected to the first control signal, the second input end of the logic unit is connected to the corresponding second control signal, the output end of the logic unit is connected to the control end of the corresponding output buffer, and the logic unit is used to enable the corresponding output buffer when the first control signal and the second control signal are both first level signals, and disable the corresponding output buffer when at least one of the first control signal and the second control signal is a second level signal.

[0006] Optionally, the logic unit includes an AND gate, a first input end of the AND gate serves as a first input end of the logic unit, a second input end of the AND gate serves as a second input end of the logic unit, and an output end of the AND gate serves as an output end of the logic unit.

[0007] Optionally, the display device also includes a timing controller; the timing controller is connected to the buffer control module, and the timing controller is used to output a corresponding control signal according to the display mode and refresh frequency of the display device; wherein different display modes and refresh frequencies correspond to different control signals.

[0008] Optionally, at the same refresh frequency, the timing controller is used to output a control signal according to a display mode of the display device.

[0009] Optionally, in the same display mode, the timing controller is used to output a control signal according to a refresh frequency.

[0010] Optionally, the control signal includes a first control signal and a second control signal; after the timing controller is powered on, the first control signal is a first level signal, and the second control signal is a first level signal and a second level signal that are alternately set in timing.

[0011] Optionally, the display device includes m output buffers. At the same refresh frequency, if the display mode of the display device is light load display, k output buffers among the m output buffers are controlled to be enabled; wherein m is an integer greater than or equal to 2, and k is an integer greater than or equal to 1 and less than m.

[0012] Optionally, the display device includes a display area, in a first time period, the refresh frequency of the display area is a first refresh frequency, and in a second time period, the refresh frequency of the display area is a second refresh frequency; the first refresh frequency is less than the second refresh frequency; in the same display mode, the number of output buffers enabled in the first time period is less than the number of output buffers enabled in the second time period.

[0013] Optionally, when the refresh frequency of the display area is the first refresh frequency, the picture display period of the display device includes at least one hold frame, and the output buffer is closed in the hold frame.

[0014] Optionally, the picture display cycle also includes at least one refresh frame, the refresh frame includes a blank period and a display period, and the buffer control module controls the output buffer to be closed during the blank period and controls the output buffer to be opened during the display period.

[0015] Optionally, at the same refresh rate, if the display mode of the display device is heavy-load display, the output buffers are controlled to be enabled.

[0016] Optionally, the display device includes multiple display partitions, the multiple display partitions include a first display partition and a second display partition, the refresh frequency of the first display partition is a first refresh frequency, the refresh frequency of the second display partition is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency; the display partitions receive data voltages transmitted by corresponding data drivers; under the same display mode, the number of output buffers enabled by the data driver corresponding to the first display partition is less than the number of output buffers enabled by the data driver corresponding to the second display partition.

[0017] Optionally, the data driver also includes a gamma voltage generating module and a filtering module; the gamma voltage generating module includes multiple output terminals, and the gamma voltage generating module is used to generate multiple gamma voltages based on the first reference voltage and the second reference voltage; the input terminal of the filtering module is connected to the gamma voltage generating module, the filtering module includes multiple output terminals, the output terminal of the filtering module corresponds to the output terminal of the gamma voltage generating module, each output terminal of the filtering module is connected to the data driving module, and the filtering module is used to filter each gamma voltage to generate a driving voltage, and output it through the output terminal corresponding to the filtering module.

[0018] Optionally, the multiple output terminals of the gamma voltage generating module include a first reference voltage output terminal and a second reference voltage output terminal; the first reference voltage output terminal is used to output a first reference voltage, and the second reference voltage output terminal is used to output a second reference voltage; the gamma voltage generating module also includes: a plurality of voltage-dividing resistors connected in series between the first reference voltage output terminal and the second reference voltage output terminal; wherein the multiple output terminals of the gamma voltage generating module also include: a plurality of resistor output terminals, and the resistor output terminal is a common terminal between any two adjacent voltage-dividing resistors.

[0019] Optionally, the filtering module includes multiple operational amplifier units and multiple filtering resistors, the input end of each operational amplifier unit is connected to the output end of the gamma voltage generating module in a one-to-one correspondence, the output end of the operational amplifier unit serves as the output end of the filtering module; the filtering resistor is connected to the output end of the operational amplifier unit.

[0020] Optionally, the display device also includes a timing controller, which is connected to the control end of the operational amplifier unit, and the timing controller is used to output an enable signal according to the grayscale and refresh frequency of the current display frame of the display device; wherein different display images and refresh frequencies correspond to different enable signals; the enable signal includes a first enable signal and a second enable signal, the control ends of the first and last operational amplifier units are connected to the first enable signal, and the control ends of the other operational amplifier units are connected to the corresponding second enable signal, the first and last operational amplifier units are used to turn on or off according to the first enable signal, and the other operational amplifier units are used to turn on or off according to the corresponding second enable signal.

[0021] Optionally, at the same refresh frequency, the timing controller is used to output an enable signal according to the gray scale of the current display frame of the display device.

[0022] Optionally, the grayscale of the currently displayed frame image includes a first grayscale, a second grayscale and a third grayscale, wherein the first grayscale is a high grayscale, the second grayscale is a medium grayscale, and the third grayscale is a low grayscale; at the same refresh frequency, when the grayscale of the currently displayed frame image is a low grayscale, all the operational amplifier units are controlled to be turned on; when the grayscale of the currently displayed frame image is a medium grayscale or a high grayscale, the first operational amplifier unit and the last operational amplifier unit are controlled to be turned on.

[0023] Optionally, under the same display screen, the timing controller is used to output an enable signal according to a refresh frequency.

[0024] Optionally, the display device includes a plurality of display partitions, the plurality of display partitions include a first display partition and a second display partition, the refresh frequency of the first display partition is a first refresh frequency, the refresh frequency of the second display partition is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency. The display partitions receive data voltages transmitted by corresponding data drivers; under the same display screen, the number of operational amplifier units enabled by the data driver corresponding to the first display partition is less than the number of operational amplifier units enabled by the data driver corresponding to the second display partition.

[0025] Optionally, the enable signal includes a first enable signal and a second enable signal; after the timing controller is powered on, the first enable signal is a first level signal, and the second enable signal is a first level signal and a second level signal that are alternately set in timing.

[0026] Optionally, the data driver further includes a reference voltage generating module connected to the driving power supply terminal, the reference voltage generating module is connected to the gamma voltage generating module, and the reference voltage generating module is used to generate a first reference voltage and a second reference voltage according to a driving power supply voltage connected to the driving power supply terminal.

[0027] Optionally, the reference voltage generating module includes a first reference voltage generating unit and a second reference voltage generating unit; the first reference voltage generating unit is connected to the driving power supply terminal and the first reference voltage terminal, and is used to generate a first reference voltage according to the driving power supply voltage and a first reference voltage connected to the first reference voltage terminal; the second reference voltage generating unit is connected to the driving power supply terminal and the second reference voltage terminal, and is used to generate a second reference voltage according to the driving power supply voltage and a second reference voltage connected to the second reference voltage terminal; wherein the driving power supply voltage is greater than the first reference voltage, and the first reference voltage is greater than the second reference voltage.

[0028] Optionally, the first reference voltage generating unit includes a first voltage buffer amplifier, and the second reference voltage generating unit includes a second voltage buffer amplifier; the first input terminal of the first voltage buffer amplifier is connected to the first reference voltage terminal, the second input terminal of the first voltage buffer amplifier is connected to its own output terminal, the first power supply terminal of the first voltage buffer amplifier is connected to the driving power supply terminal, the second power supply terminal of the first voltage buffer amplifier is grounded, and the output terminal of the first voltage buffer amplifier provides a first reference voltage; the first input terminal of the second voltage buffer amplifier is connected to the second reference voltage terminal, the second input terminal of the second voltage buffer amplifier is connected to its own output terminal, the first power supply terminal of the second voltage buffer amplifier is connected to the driving power supply terminal, the second power supply terminal of the second voltage buffer amplifier is grounded, and the output terminal of the second voltage buffer amplifier provides a second reference voltage; wherein, the difference between the driving power supply voltage and the first reference voltage is greater than or equal to the preset bias voltage, and the difference between the driving power supply voltage and the second reference voltage is greater than or equal to the preset bias voltage.

[0029] Optionally, the data driving module also includes a register unit, a latch unit and a digital-to-analog conversion unit; the register unit is connected to the latch unit for generating a latch clock signal; the latch unit is connected to the digital-to-analog conversion unit for latching image data according to the latch clock signal; the digital-to-analog conversion unit is connected to the output buffer for converting the latched image data into a data voltage based on multiple driving voltages.

[0030] The display device of the embodiment of the present invention can control the output buffer to enable different numbers in different display scenarios by setting a buffer control module to enable or disable the output buffer according to a control signal, thereby reducing the power consumption of the display device and improving the display performance.

[0031] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a structural schematic diagram of a display device provided by an embodiment of the present invention;

[0034] Figure 2 is a structural schematic diagram of a data driver provided by an embodiment of the present invention;

[0035] Figure 3 is a structural diagram of another data driver provided by an embodiment of the present invention;

[0036] Figure 4 is a structural diagram of another data driver provided by an embodiment of the present invention;

[0037] Figure 5 is a structural schematic diagram of another display device provided by an embodiment of the present invention;

[0038] Figure 6 is a structural schematic diagram of another display device provided by an embodiment of the present invention;

[0039] Figure 7 is a structural diagram of another data driver provided by an embodiment of the present invention;

[0040] Figure 8 is a structural diagram of another data driver provided by an embodiment of the present invention;

[0041] Fig. 9 is a structural schematic diagram of a reference voltage generating module provided by an embodiment of the present invention;

[0042] Fig.10 It is a comparison diagram showing power consumption provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0045] Figure 1 is a schematic structural diagram of a display device provided by an embodiment of the present invention, Figure 2 is a schematic diagram of the structure of a data driver provided by an embodiment of the present invention, combined with Figure 1 and Figure 2 The display device includes: at least one data driver 10, and the data driver 10 includes a data driving module 11 and a buffer control module 12.

[0046] The data driving module 11 includes multiple output buffers 110, which are used to transmit data voltages to data lines DL corresponding to the data driver 10 when enabled; the buffer control module 12 is connected to the control ends of the multiple output buffers 110, and the buffer control module 12 is used to enable or disable the output buffers 110 according to the control signal CTR.

[0047] Specifically, the display device includes a display panel, and the display panel includes a display area AA and a non-display area NAA, wherein the display area AA is provided with sub-pixels PX for displaying images.

[0048] The display panel may be an organic light emitting diode (OLED) display panel, a liquid crystal display (LCD) display panel, or other types of display panels, which are not limited here.

[0049] The sub-pixel PX may include a plurality of sub-pixels emitting different colors, for example, a red sub-pixel, a green sub-pixel, a blue sub-pixel, and the like.

[0050] The display area of ​​the display panel is provided with a plurality of pixel rows L0, a plurality of pixel columns L1 and a plurality of data lines DL, wherein each data line DL is electrically connected to a corresponding pixel column. The output buffer 110 in the data driving module 11 is correspondingly connected to the data lines DL, and buffers the analog voltage signal transmitted from the D / A converter to provide a data voltage transmitted to the data lines DL. That is, the output buffer 110 is used to amplify the analog voltage signal to enhance its driving capability to obtain the data voltage. In some embodiments, the output buffer 110 may include an operational amplifier.

[0051] The display device further includes a timing controller, which can generate a control signal CTR. The timing controller can generate different control signals CTR in different display scenarios, and different control signals CTR can control different numbers of output buffers 110 to be enabled or disabled.

[0052] The display device of the embodiment of the present invention can control the output buffer to enable different numbers in different display scenarios by setting the buffer control module to enable or disable the output buffer according to the control signal, thereby reducing the power consumption of the display device.

[0053] Optionally, based on the above embodiment, Figure 3 is a schematic diagram of the structure of another data driver provided by an embodiment of the present invention, such as Figure 3 As shown, the buffer control module 12 includes a plurality of logic units 120. The plurality of logic units 120 correspond to the plurality of output buffers 110 one by one, and the logic unit 120 includes an input terminal and an output terminal, and the input terminal includes a first input terminal and a second input terminal. The control signal CTR includes a first control signal ctr1 and a plurality of second control signals ctr2. The first input terminal of the logic unit 120 is connected to the first control signal ctr1, the second input terminal of the logic unit is connected to the corresponding second control signal ctr2, and the output terminal of the logic unit 120 is connected to the control terminal of the corresponding output buffer 110. The logic unit 120 is used to conduct the input terminal with the output terminal according to the first control signal ctr1 and the second control signal ctr2. Further, the logic unit 120 is used to conduct its own input terminal with the output terminal when the first control signal ctr1 and the second control signal ctr2 are both first level signals, so as to enable the corresponding output buffer 110, and not conduct when at least one of the first control signal ctr2 and the second control signal ctr2 is a second level signal, so as to disable the corresponding output buffer.

[0054] The plurality of second control signals ctr2 include a first second control signal SEN1, a second second control signal SEN2, ..., an Xth second control signal SENx, where X is an integer greater than 1. The level values ​​of the first level signal and the second level signal are different. When the first level signal is a high level signal, the second level signal is a low level signal. When the first level signal is a low level signal, the second level signal is a high level signal. This embodiment and the following embodiments are all described by taking the first level signal as a high level signal and the second level signal as a low level signal as an example.

[0055] In some embodiments, the i-th logic unit 120 controls the enablement or disablement of the i-th output buffer according to the first control signal ctr1 and the i-th second control signal SENi. i is an integer greater than or equal to 1 and less than or equal to N. Exemplarily, the first logic unit 120 controls the enablement or disablement of the first output buffer 110 according to the control signal ctr1 and the first second control signal SEN1. When the first control signal ctr1 and the first second control signal SEN1 are both first level signals, the buffer control module 12 controls the first output buffer to be enabled. When at least one of the first control signal ctr1 and the first second control signal SEN1 is a second level signal, the buffer control module 12 controls the first output buffer 110 to be disabled.

[0056] The logic unit 120 may be an integrated module with the above functions, or a circuit of any structure. As an optional implementation provided in this embodiment, Figure 4 is a structural diagram of another data driver provided by an embodiment of the present invention, combined with Figure 3 and Figure 4 The logic unit 120 includes an AND gate A1, a first input end of the AND gate A1 serves as a first input end of the logic unit 120, a second input end of the AND gate A1 serves as a second input end of the logic unit 120, and an output end of the AND gate A1 serves as an output end of the logic unit 120.

[0057] Specifically, the AND gate A1 controls the enabling or disabling of the i-th output buffer 110 according to the first control signal ctr1 and the i-th second control signal SENi. Exemplarily, the buffer control module 12 controls the enabling or disabling of the second output buffer 110 according to the first control signal ctr1 and the second second control signal SEN2. When the first control signal ctr1 and the second second control signal SEN2 are both first level signals, i.e., high level signals, the buffer control module 12 controls the enabling of the second output buffer. When one of the first control signal ctr1 and the second second control signal SEN2 is a second level signal, i.e., a low level signal, the buffer control module 12 controls the disabling of the second output buffer 110.

[0058] Figure 5 FIG. 1 is a schematic diagram of a structure of another display device provided by an embodiment of the present invention. Figure 5 The display device further includes a timing controller 20; the timing controller 20 is connected to the buffer control module 12. The timing controller 20 is used to output a corresponding control signal CTR according to the display mode and refresh frequency of the display device. The control signal CTR corresponding to different display modes and refresh frequencies is different.

[0059] Optionally, based on the above embodiment, continue to refer to Figure 5 At the same refresh rate, the timing controller 20 is used to output a control signal according to a display mode of the display device. The display mode includes a light load display and a heavy load display.

[0060] Specifically, the display device includes m output buffers 110. At the same refresh rate, if the display mode of the display device is light load display, k output buffers 110 among the m output buffers 110 are controlled to be enabled. Wherein, m is an integer greater than or equal to 2, and k is an integer greater than or equal to 1 and less than m. At the same refresh rate, if the display mode of the display device is heavy load display, all the output buffers 110 are controlled to be enabled. This setting can reduce the power consumption of the display device during light load display and improve user experience.

[0061] At the same refresh rate, the light load display of the display device indicates that the color of the display mode is relatively simple or the display content is relatively simple. Exemplarily, when the display device displays a clock screen or a digital screen, the display device is lightly loaded. At this time, the timing controller 20 can output the first second control signal SEN1 and the mth second control signal SENm as first level signals, and the other second control signals ctr2 are second level signals. The buffer control module 12 can control the first output buffer 110 to be enabled according to the first control signal ctrl and the first second control signal SEN1, control the mth output buffer 110 to be enabled according to the first control signal ctrl and the mth second control signal SENm, and control the other output buffers 110 to be disabled. After the timing controller 20 is powered on, the first control signal ctr1 is always a first level signal, and the second control signal ctr2 is a first level signal and a second level signal that are alternately set in timing.

[0062] In other embodiments, the timing controller 20 may output the first second control signal SEN1, the second second control signal SEN2, and the mth second control signal SENm as first level signals, and the buffer control module 12 may control the first output buffer 110 to be enabled according to the first control signal ctrl and the first second control signal SEN1, control the second output buffer 110 to be enabled according to the first control signal ctrl and the second second control signal SEN2, control the mth output buffer 110 to be enabled according to the first control signal ctrl and the mth second control signal SENm, and control other output buffers 110 to be disabled. When the display device is lightly loaded for display, the embodiment of the present invention does not specifically limit the number of enabled output buffers 110 and the specific positions of the enabled output buffers 110, as long as the number of enabled output buffers 110 is less than the total number of output buffers 110.

[0063] The overload display of the display device indicates that the display mode is colorful or the display content is rich. For example, when playing a video, displaying a fruit picture, displaying a smiling face picture, or displaying a colorful landscape picture, the display device is in an overload display state, and it is necessary to control all output buffers 110 to be enabled. That is to say, at this time, the multiple second control signals ctr1 are all first level signals, and since the first control signal ctr2 is always the first level signal after the timing controller 20 is powered on, the output end of the buffer control module 12 outputs a valid level signal. Among them, the valid level signal is a level signal that enables the output buffer 110.

[0064] Optionally, continue to refer to Figure 5The display device includes a display area, in a first period, the refresh frequency of the display area AA is a first refresh frequency, and in a second period, the refresh frequency of the display area AA is a second refresh frequency; the first refresh frequency is less than the second refresh frequency; in the same display mode, the number of output buffers 110 enabled in the first period is less than the number of output buffers 110 enabled in the second period. In the same display mode, adjusting the number of enabled output buffers 110 according to the refresh frequencies in different periods helps to reduce the power consumption of the display device.

[0065] Optionally, when the refresh frequency of the display area is the first refresh frequency, the picture display period of the display device includes at least one hold frame, and the output buffer is closed in the hold frame.

[0066] In the hold frame, the pixel circuit does not need a new data voltage to update the screen. At this time, turning off the output buffer 110 can cut off the data voltage transmission path and avoid the output buffer 110 consuming power unnecessarily, thereby effectively reducing the overall power consumption of the display device.

[0067] Optionally, the picture display cycle further includes at least one refresh frame, the refresh frame includes a blank period and a display period, and the buffer control module 12 controls the output buffer 110 to be closed during the blank period, and controls the output buffer 110 to be opened during the display period.

[0068] Specifically, the blank period can be the time period from the last row of pixel circuit data writing stage of the display panel in the previous refresh frame to the first row of pixel circuit data writing stage of the display panel in the next refresh frame in two adjacent refresh frames when the refresh frequency of the display panel is less than the maximum refresh frequency (at this time, a picture display cycle includes both refresh frames and hold frames).

[0069] During the blank period, the pixels on the display panel will not update and display the image data, and are mainly used to prepare for the display of the next frame; the display period is the time period when the pixels actually update the data and present the image. During this period, the pixels adjust their own luminous state according to the received data voltage and other information, so as to display the corresponding image on the screen. The buffer control module 12 controls the output buffer 110 to be closed during the blank period, which can avoid wasting power when data transmission is not required, thereby reducing the power consumption of the display device. During the display period, the buffer control module 12 controls the output buffer 110 to be opened so as to transmit the data voltage to the pixel circuit. In this way, the pixel circuit can correctly adjust the luminous state of the pixel according to the received data voltage and other information, so as to present a clear and accurate image on the screen.

[0070] Based on the above embodiments, Figure 6 is a schematic diagram of the structure of another display device provided by an embodiment of the present invention. Figure 6 , Optionally, in the same display mode, the timing controller is used to output a control signal according to a refresh frequency.

[0071] Specifically, the display device includes a plurality of display partitions, the plurality of display partitions include a first display partition AA1 and a second display partition AA2, the refresh frequency of the first display partition AA1 is a first refresh frequency, the refresh frequency of the second display partition AA2 is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency. The display partition receives a data voltage transmitted by a corresponding data driver 10.

[0072] In the same display mode, the number of output buffers 110 enabled by the data driver 10 corresponding to the first display partition AA1 is smaller than the number of output buffers 110 enabled by the data driver 10 corresponding to the second display partition AA2.

[0073] Specifically, multiple display partitions may be arranged in the row direction, and multiple display partitions may also be arranged in the column direction. The embodiment of the present invention does not specifically limit the number of display partitions, and the number of display partitions included in the display area AA may be set according to actual conditions. Figure 6 The following description will be made by taking the example that the display area AA includes two display subareas and the display subareas are arranged in the row direction.

[0074] Figure 6 The schematic diagram shows a case where the first display partition AA1 receives the data voltage transmitted by the first data driver 101, and the second display partition receives the data voltage transmitted by the second data driver 102. That is to say, each display partition independently obtains the data voltage from the data output terminal of the corresponding data driver 10. Compared with the case where multiple display partitions receive the data voltage provided by the same data driver, the data voltage does not need to be sequentially transmitted from the sub-pixel PX of the display area closer to the data driver 10 to the sub-pixel PX of the display area farther away, which is beneficial to improving the uniformity of the display of the display panel.

[0075] The number of output buffers 110 included in the first data driver 101 and the second data driver 102 may be the same or different. This embodiment and the following embodiments are described by taking the first data driver 101 and the second data driver 102 including m output buffers 110 as an example. Exemplarily, in the same display mode, the first data driver 101 corresponding to the first display partition AA1 enables p output buffers 110, and the second data driver 101 corresponding to the second display partition AA2 enables q output buffers 110. Wherein, p and q are both integers greater than or equal to 1 and less than or equal to m, and p is less than q. Such a setting can reduce the power consumption of the display device and improve the user experience.

[0076] Figure 7 FIG. 1 is a schematic diagram of the structure of another data driver provided by an embodiment of the present invention. Figure 7 On the basis of the above embodiments, optionally, the data driver 10 further includes a gamma voltage generating module 13 and a filtering module 14 .

[0077] The gamma voltage generating module 13 includes a plurality of output terminals U1, and the gamma voltage generating module 13 is used to generate a plurality of gamma voltages according to a first reference voltage VGMP and a second reference voltage VGSP;

[0078] The input end of the filter module 14 is connected to the gamma voltage generating module 13. The filter module includes multiple output ends U2. The output end U2 of the filter module 14 corresponds to the output end U1 of the gamma voltage generating module 13. Each output end of the filter module 14 is connected to the data driving module 11. The filter module 14 is used to filter each gamma voltage to generate a driving voltage, and output it through the output end U2 corresponding to the filter module 14.

[0079] Specifically, the gamma voltage generating module 13 can generate a gamma voltage according to the first reference voltage VGMP and the second reference voltage VGSP, and divide the voltage between the first reference voltage VGMP and the second reference voltage VGSP to obtain the gamma voltage. Exemplarily, the gamma voltage generating module 13 can generate h gamma voltages, including a first gamma voltage, a second gamma voltage, ..., an hth gamma voltage. The first gamma voltage can be equal to the first reference voltage VGMP, the hth gamma voltage can be equal to the second reference voltage VGSP, and the second gamma voltage to the h-1th gamma voltage can be the voltage obtained by dividing the voltage between the first reference voltage VGMP and the second reference voltage VGSP. h is a positive integer greater than or equal to 2.

[0080] In an optional manner, the output terminal U2 of the filter module 14 can correspond to the output terminal U1 of the gamma voltage generating module 13 one by one, and the gamma voltage outputted by each output terminal U1 of the gamma voltage generating module 13 is filtered by the filter module 14 to generate a driving voltage, and the driving voltage is outputted through the corresponding output terminal of the filter module 14. The filter module 14 can be an RC low-pass filter circuit. Exemplarily, the filter module 14 can include a filter circuit corresponding to the output terminal U1 of the gamma voltage generating module 13 one by one, so that the voltage outputted by each output terminal U1 is outputted after filtering, ensuring the output of a stable driving voltage after filtering, avoiding the influence of other interference signals, and thus ensuring that the subsequent data driving module generates a stable data voltage based on the driving voltage. When the display device displays a grayscale transition picture, a stable data voltage can be written to the corresponding grayscale to avoid the occurrence of bright or dark stripes caused by data voltage fluctuations, thereby improving the problem of horizontal stripes on the display and improving the display effect.

[0081] Figure 8 is a schematic diagram of the structure of another data driver provided by an embodiment of the present invention, referring to Figure 8 Optionally, the multiple output terminals of the gamma voltage generating module 13 include a first reference voltage output terminal U1-1 and a second reference voltage output terminal U1-2; the first reference voltage output terminal U1-1 is used to output a first reference voltage VGMP, and the second reference voltage output terminal U1-2 is used to output a second reference voltage VGSP.

[0082] The gamma voltage generating module 13 also includes: a plurality of voltage-dividing resistors R1 connected in series between the first reference voltage output terminal U1-1 and the second reference voltage output terminal U1-2; wherein the plurality of output terminals of the gamma voltage generating module 13 also include: a plurality of resistor output terminals U1-3, and the resistor output terminal U1-3 is a common terminal between any two adjacent voltage-dividing resistors R1.

[0083] Optionally, the filtering module 14 includes multiple operational amplifier units 141 and multiple filter resistors R2, the input end of each operational amplifier unit 141 is connected to the output end of the gamma voltage generating module 13 in a one-to-one correspondence, and the output end of the operational amplifier unit 141 serves as the output end of the filtering module 14; the filter resistor R2 is connected to the output end of the operational amplifier unit 141.

[0084] The gamma voltage generation module 13 realizes the voltage division of the first reference voltage VGMP and the second reference voltage VGSP through a plurality of voltage-dividing resistors R1 connected in series in sequence to obtain a plurality of gamma voltages. Optionally, the resistance value of each voltage-dividing resistor R1 may be equal. When the gamma voltage generation module 10 includes Y voltage-dividing resistors R1, the gamma voltage generation module 10 correspondingly includes Y-1 resistor output terminals U1-3, where Y is a positive integer greater than or equal to 2. The operational amplifier unit 141 may be set in one-to-one correspondence with the output terminal of the gamma voltage generation module 13, and the operational amplifier unit 141 may be a buffer for impedance transformation, buffer isolation, and enhancing the driving capability of the gamma voltage.

[0085] Optionally, based on the above embodiment, continue to refer to Figure 5 and Figure 8 The timing controller 20 is connected to the control end of the operational amplifier unit 141, and the timing controller 10 is used to output an enable signal AEN according to the grayscale and refresh frequency of the current display frame of the display device; wherein different display frames and refresh frequencies correspond to different enable signals AEN.

[0086] The enable signal AEN includes a first enable signal AEN1 and a second enable signal AEN2. The control ends of the first and last operational amplifier units 141 are connected to the first enable signal AEN1, and the control ends of other operational amplifier units are connected to the corresponding second enable signal AEN2. The first and last operational amplifier units 141 are used to be turned on or off according to the first enable signal AEN1, and the other operational amplifier units 141 are used to be turned on or off according to the corresponding second enable signal AEN2.

[0087] Specifically, the plurality of second enable signals AEN2 include a first second enable signal MEN1, a second second enable signal MEN2, ..., a Y-1th second control signal MENy-1, and a Yth second control signal MENy, wherein Y is an integer greater than or equal to 2. When the first enable signal AEN1 is a first level signal, the first and last op amp units 141 are turned on, and when the first enable signal AEN2 is a second level signal, the first and last op amp units 141 are turned off. Similarly, when the jth second enable signal AEN2 is a first level signal, the jth op amp unit 141 is turned on, and when the jth second enable signal is a second level signal, the jth op amp unit 141 is turned off. Wherein, j is an integer greater than or equal to 2 and less than or equal to Y-1.

[0088] The grayscale of the current display frame can be calculated from the grayscale of each sub-pixel in multiple pixels of the current frame. For example, when the current frame is a pure color picture (such as a black picture and a white picture), the average grayscale of each sub-pixel in multiple pixels of the current frame can be used as the grayscale of the current display frame. Among them, in the image display of the display device, the grayscale is to divide the brightness change between the brightest and the darkest into several parts. The grayscale represents the level of different brightness from the darkest to the brightest. The more intermediate levels, the more delicate the picture effect that can be presented. The color change of each pixel on the screen is actually caused by the grayscale change of the sub-pixels that constitute this point. And the light source behind each sub-pixel can show different brightness levels. When the display device is actually displayed, it is usually necessary to convert the image brightness that the user needs to see and the grayscale value of the sub-pixel of the display device to display the image of the corresponding brightness on the display device.

[0089] At the same refresh frequency, the timing controller 20 is used to output an enable signal AEN according to the grayscale of the current display frame of the display device. Specifically, the grayscale of the current display frame includes three levels: the first grayscale, the second grayscale and the third grayscale, wherein the first grayscale is a high grayscale, the second grayscale is a medium grayscale, and the third grayscale is a low grayscale. At the same refresh frequency, when the grayscale of the current display frame is a low grayscale, the control amplifier units 141 are all turned on; when the grayscale of the current display frame is a medium grayscale or a high grayscale, the first amplifier unit 141 and the last amplifier unit 141 are controlled to be turned on.

[0090] Specifically, at the same refresh frequency, when the grayscale of the current display frame is low grayscale, the first enable signal AEN1 and the second enable signal AEN2 output by the timing controller 20 are both first level signals, so that all operational amplifier units are turned on. When the grayscale of the current display frame is medium grayscale or high grayscale, the first enable signal AEN1 output by the timing controller 20 is a first level signal, and the plurality of second enable signals AEN2 output by the timing controller 20 are all second level signals, so that the first operational amplifier unit 141 and the last operational amplifier unit 141 are turned on, and the other operational amplifier units 141 are all turned off. It should be noted that when the timing controller 20 is powered on, the first enable signal AEN1 is a first level signal, and the second enable signal AEN2 is a first level signal and a second level signal that are alternately set in timing. That is to say, when the timing controller 20 is powered on, the first and last operational amplifier units are turned on to generate the driving voltage of the initial picture.

[0091] Optionally, when the grayscale of the currently displayed frame is less than or equal to the first grayscale threshold, the grayscale of the currently displayed frame is low grayscale. When the grayscale of the currently displayed frame is greater than the first grayscale threshold and less than or equal to the second grayscale threshold, the grayscale of the currently displayed frame is medium grayscale. When the grayscale of the currently displayed frame is greater than the second grayscale threshold, the grayscale of the currently displayed frame is high grayscale.

[0092] Wherein, the first grayscale threshold is greater than the second grayscale threshold. Exemplarily, the numerical range of the first grayscale threshold is 25 to 35, and the numerical range of the second grayscale threshold is 35 to 80. It should be noted that the specific numerical values ​​of the first grayscale threshold and the second grayscale threshold can be selected according to actual conditions, and the embodiment of the present invention is not limited here.

[0093] In practical applications, when the grayscale of the current display frame is low grayscale, the driving voltage output by the filter module 14 and the brightness may be in a nonlinear relationship; when the grayscale of the current display frame is medium grayscale and high grayscale, the driving voltage output by the filter module 14 and the brightness may be in a linear relationship. Since when the grayscale of the current display frame is medium grayscale and high grayscale, the driving voltage output by the filter module 14 and the brightness are in a linear relationship, the driving voltage corresponding to the medium and high grayscale can be obtained according to the first reference voltage VGMP, the second reference voltage VGSP and the voltage therebetween. In this way, by turning off the operational amplifier unit connected to the first resistor output terminal U1-3 and the operational amplifier unit connected to the last first resistor output terminal U1-3 on the basis of ensuring the display effect, the medium and high grayscale binding points can be reduced, that is, the number of operational amplifier units 141 connected to the resistor output terminal U1-3 can be reduced, and the number of operational amplifier units 141 can be reduced, thereby reducing the power consumption of the data driver 10, and then reducing the power consumption of the display device.

[0094] In addition, when the operational amplifier unit 141 corresponding to the resistor output terminal U1-3 is turned off, the output terminal of the operational amplifier unit 141 connected to the resistor output terminal U1-3, that is, the output terminal of the filter module corresponding to the resistor output terminal, will still output the driving voltage. Specifically, there is a voltage difference between the output terminal U2 of the operational amplifier unit 141 connected to the first reference voltage output terminal U1-1 and the output terminal U2 of the operational amplifier unit 141 connected to the second reference voltage output terminal U1-2. Because at least one filter resistor R2 is connected between the output terminals of two adjacent operational amplifier units 141, the filter resistor R2 divides the voltage difference between the output terminal U2 of the operational amplifier unit 141 connected to the first reference voltage output terminal U1-1 and the output terminal U2 of the operational amplifier unit 141 connected to the second reference voltage output terminal U1-2, and outputs it through the output terminal U2 of the operational amplifier unit 141 connected to the resistor output terminal, thereby avoiding affecting the generation of the driving voltage. That is to say, when all the operational amplifier units 141 connected to the resistor output terminals U1-3 are turned off, the driving voltage output by the output terminal of the operational amplifier unit 141 is jointly generated by the operational amplifier unit 141 connected to the first reference voltage output terminal U1-1 and the operational amplifier unit 141 connected to the second reference voltage output terminal U1-2, which will not affect the driving capability of the driving voltage corresponding to the operational amplifier unit 141 connected to the resistor output terminal U1-3.

[0095] In some embodiments, continue to refer to Figure 6 and Figure 8 Optionally, under the same display screen, the timing controller 20 is used to output an enable signal according to the refresh frequency.

[0096] Specifically, the display device includes a plurality of display partitions, the plurality of display partitions include a first display partition AA1 and a second display partition AA2, the refresh frequency of the first display partition AA1 is a first refresh frequency, the refresh frequency of the second display partition AA2 is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency. The display partition receives a data voltage transmitted by a corresponding data driver 10.

[0097] Under the same display screen, the number of operational amplifier units 141 enabled by the data driver 10 corresponding to the first display partition AA1 is less than the number of operational amplifier units 141 enabled by the data driver 10 corresponding to the second display partition AA2. The number of operational amplifier units 141 included in the first data driver 101 and the second data driver 102 may be the same or different. This embodiment and the following embodiments are all described by taking the first data driver 101 and the second data driver 102 including r operational amplifier units 141 as an example. Wherein, r=Y+1, and Y is the number of voltage divider resistors R1. It can be understood that when different display partitions display the same display screen, the grayscale of the current display frame screen of different display partitions is the same. Exemplarily, under the same display screen, the first data driver 101 corresponding to the first display partition AA1 enables p1 operational amplifier units 141, and the second data driver 101 corresponding to the second display partition AA2 enables q1 operational amplifier units 141. Wherein, p1 and q1 are both integers greater than or equal to 1 and less than or equal to r, and p1 is less than q1. This arrangement can reduce the power consumption of the display device and improve user experience.

[0098] Continue to see Figure 5 and Figure 8 On the basis of the above embodiment, optionally, the data driving module 11 is used to generate data voltages based on various driving voltages and image data to transmit to the data lines DL of the corresponding columns.

[0099] The data driving module 11 also includes a register unit 111, a latch unit 112 and a digital-to-analog conversion unit 113; the register unit 111 is connected to the latch unit 112 for generating a latch clock signal; the latch unit 112 is connected to the digital-to-analog conversion unit 113 for latching image data according to the latch clock signal; the digital-to-analog conversion unit 113 is connected to the output buffer 110 for converting the latched image data into a data voltage based on a plurality of driving voltages.

[0100] Specifically, the data driving module 11 includes a plurality of data output terminals U3, and the data output terminals U3 are used to output data voltages. The latch unit 112 includes latches 1121 corresponding to the data output terminals U3 one by one, and the digital-to-analog conversion unit 113 includes digital-to-analog converters 1131 corresponding to the data output terminals U3 one by one.

[0101] The timing controller 20 can generate a data control signal to control the driving timing of the data driving module 11. The register unit 111 generates a latch clock signal in response to the data control signal of the timing controller. The latch unit 112 sequentially samples and stores the image data provided from the timing controller according to the latch clock signal from the register unit 111. At the same time, the latch unit 112 outputs the image data to the digital-to-analog conversion unit 113. The digital-to-analog conversion unit 113 converts the image data into a data voltage of an analog quantity and outputs it through the output buffer 110.

[0102] Continue to refer Figure 8 Optionally, the data driver 10 also includes a reference voltage generating module 15 connected to the driving power supply terminal VDD, the reference voltage generating module 15 is connected to the gamma voltage generating module 13, and the reference voltage generating module 15 is used to generate a first reference voltage VGMP and a second reference voltage VGSP according to the driving power supply voltage AVDD connected to the driving power supply terminal.

[0103] Optionally, the reference voltage generating module 15 includes a first reference voltage generating unit 151 and a second reference voltage generating unit 152. The first reference voltage generating unit 151 is connected to the driving power supply terminal and the first reference voltage terminal, and is used to generate a first reference voltage VGMP according to the driving power supply voltage AVDD and a first reference voltage VGMP' connected to the first reference voltage terminal; the second reference voltage generating unit 151 is connected to the driving power supply terminal and the second reference voltage terminal, and is used to generate a second reference voltage VGSP according to the driving power supply voltage AVDD and a second reference voltage VGSP' connected to the second reference voltage terminal.

[0104] The driving power supply voltage AVDD is greater than the first reference voltage VGMP', and the first reference voltage VGMP' is greater than the second reference voltage VGSP'. By setting the driving power supply voltage AVDD to be greater than the first reference voltage VGMP', and the first reference voltage VGMP' to be greater than the second reference voltage VGSP', the driving power supply voltage AVDD is greater than the first reference voltage VGMP, and the first reference voltage VGMP is greater than the second reference voltage VGSP. In this way, the first reference voltage VGMP can be generated by the first reference voltage generating unit 151, and the second reference voltage VGSP can be generated by the second reference voltage generating unit 152, so as to control the magnitude of the first reference voltage VGMP and the second reference voltage VGSP, respectively, and improve the driving capability of the first reference voltage VGMP and the second reference voltage VGSP.

[0105] Further, the first reference voltage generating unit 151 may include a buffer, and the first reference voltage generating unit 151 is set to amplify the driving capability of the first reference voltage VGMP' under the driving power supply voltage AVDD to obtain the first reference voltage VGMP, and the first reference voltage VGMP' and the first reference voltage VGMP are the same in magnitude, and the second reference voltage generating unit 152 may include a buffer, and under the driving power supply voltage AVDD, the driving capability of the second reference voltage VGSP' is amplified to obtain the second reference voltage VGSP, and the second reference voltage VGSP' and the second reference voltage VGSP are the same in magnitude. The structure of the buffers included in the first reference voltage generating unit 151 and the second reference voltage generating unit 152 may be the same as or different from the structure of the operational amplifier unit 141.

[0106] Fig. 9 is a schematic diagram of the structure of a reference voltage generation module provided by an embodiment of the present invention. Fig. 9 On the basis of the above embodiment, optionally, the first reference voltage generating unit 151 includes a first voltage buffer amplifier OP1, and the second reference voltage generating unit 152 includes a second voltage buffer amplifier OP2.

[0107] A first input terminal of the first voltage buffer amplifier OP1 is connected to a first reference voltage terminal, a second input terminal of the first voltage buffer amplifier OP2 is connected to its own output terminal, a first power supply terminal of the first voltage buffer amplifier OP1 is connected to a driving power supply terminal, a second power supply terminal of the first voltage buffer amplifier OP1 is grounded, and an output terminal of the first voltage buffer amplifier OP1 provides a first reference voltage VGMP.

[0108] The first input terminal of the second voltage buffer amplifier OP2 is connected to the second reference voltage terminal, the second input terminal of the second voltage buffer amplifier OP2 is connected to its own output terminal, the first power terminal of the second voltage buffer amplifier OP2 is connected to the driving power terminal, the second power terminal of the second voltage buffer amplifier OP2 is grounded, and the output terminal of the second voltage buffer amplifier OP2 provides a second reference voltage VGSP. The difference between the driving power voltage AVDD and the first reference voltage VGMP is greater than or equal to the preset bias voltage, and the difference between the driving power voltage AVDD and the second reference voltage VGSP is greater than or equal to the preset bias voltage.

[0109] Specifically, the voltage buffer amplifier is also called a driving capability amplifier or a voltage follower. The voltage gain of the voltage buffer amplifier is 1, realizing the function of a unit gain buffer. The output voltage of the voltage buffer amplifier can follow or track the input voltage, but can provide a larger current gain, thereby providing a power gain, so as to improve the driving capability of the output signal while outputting the input signal with the voltage value unchanged. The first voltage buffer amplifier OP1 can amplify the driving capability of the first reference voltage signal under the drive of the driving power supply voltage AVDD to obtain a first reference voltage signal, and the first reference voltage VGMP' is the same as the first reference voltage VGMP. The second voltage buffer amplifier OP2 can amplify the driving capability of the second reference voltage signal under the drive of the driving power supply voltage AVDD to obtain a second reference voltage signal, and the second reference voltage VGSP' is the same as the second reference voltage VGSP. According to the working principle of the voltage buffer amplifier, in order to drive the first voltage buffer amplifier OP1 and the second voltage buffer amplifier OP2 to work, it is necessary to set the difference between the voltage value of the first power supply terminal of the first voltage buffer amplifier OP1 and the voltage value of the first input terminal (or output terminal) of the second voltage buffer amplifier OP2 to be greater than or equal to a preset bias voltage. The specific value of the preset bias voltage can be determined according to the structure of the first voltage buffer amplifier OP1 and the second voltage buffer amplifier OP2.

[0110] Continue to see Fig. 9 Further, the first reference voltage generating unit 151 further includes a first digital-to-analog conversion unit 1511, the output end of the first digital-to-analog conversion unit 1511 is used as a first reference voltage end, and the first digital-to-analog conversion unit 1511 is used to perform digital-to-analog conversion on the signal inputted from its own input end and output it. The second reference voltage generating unit 152 further includes a second digital-to-analog conversion unit 1521, the output end of the second digital-to-analog conversion unit 1521 is used as a second reference voltage end, and the second digital-to-analog conversion unit 1521 is used to perform digital-to-analog conversion on the signal inputted from its own input end and output it.

[0111] In one embodiment, the first digital-to-analog conversion unit 1511 and the second digital-to-analog conversion unit 1521 may both be digital-to-analog converters. The first digital-to-analog conversion unit 1511 has a first reference voltage signal in the form of a digital signal connected to its input terminal, and the first digital-to-analog conversion unit 1521 may convert the first reference voltage signal into an analog signal and output it. The second digital-to-analog conversion unit 1522 has a second reference voltage signal in the form of a digital signal connected to its input terminal, and the second digital-to-analog conversion unit 1522 may convert the second reference voltage signal into an analog signal and output it.

[0112] It should be noted that the display device provided in the embodiment of the present invention can be a mobile phone, or it can be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiment of the present invention does not make any special limitations on this.

[0113] Fig.10 is a comparison chart showing power consumption provided by an embodiment of the present invention, with reference to Fig.10 , the power consumption of the display device in the related art is 54.07%, and the power consumption of the data driver is 45.93%. The power consumption of the display device provided in the embodiment of the present invention is 32.14%, and the power consumption of the data driver is 13.79%. The power consumption of the display device is reduced by about 20% compared with the power consumption of the display device in the related art. Among them, the data driver 10 provided in the embodiment of the present invention can be a display driver chip (Display Driver IC, DDIC).

[0114] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display device, characterized in that: include: at least one data driver, the data driver comprising a data driving module and a buffer control module; The data driving module includes a plurality of output buffers, and the output buffers are used to transmit data voltages to data lines corresponding to the data driver when enabled; The buffer control module is connected to the control ends of the plurality of output buffers, and the buffer control module is used to enable or disable the output buffers according to a control signal.

2. The display device according to claim 1, characterized in that The buffer control module includes a plurality of logic units, the plurality of logic units correspond to the plurality of output buffers one by one, and the control signal includes a first control signal and a second control signal; The first input end of the logic unit is connected to the first control signal, the second input end of the logic unit is connected to the corresponding second control signal, the output end of the logic unit is connected to the control end of the corresponding output buffer, and the logic unit is used to enable the corresponding output buffer when the first control signal and the second control signal are both first level signals, and disable the corresponding output buffer when at least one of the first control signal and the second control signal is a second level signal; Preferably, the logic unit includes an AND gate, the first input end of the AND gate serves as the first input end of the logic unit, the second input end of the AND gate serves as the second input end of the logic unit, and the output end of the AND gate serves as the output end of the logic unit.

3. The display device according to claim 1, characterized in that Also includes a timing controller; The timing controller is connected to the buffer control module, and the timing controller is used to output the corresponding control signal according to the display mode and refresh frequency of the display device; wherein the control signals corresponding to different display modes and refresh frequencies are different; Preferably, at the same refresh frequency, the timing controller is used to output the control signal according to the display mode of the display device; Preferably, in the same display mode, the timing controller is used to output the control signal according to the refresh frequency; Preferably, the control signal includes a first control signal and a second control signal; after the timing controller is powered on, the first control signal is a first level signal, and the second control signal is a first level signal and a second level signal that are alternately arranged in timing.

4. The display device according to claim 3, characterized in that: The display device includes m output buffers. Under the same refresh frequency, if the display mode of the display device is light-load display, k output buffers among the m output buffers are controlled to be enabled; wherein m is an integer greater than or equal to 2, and k is an integer greater than or equal to 1 and less than m; Preferably, the display device comprises a display area, in a first time period, the refresh frequency of the display area is a first refresh frequency, and in a second time period, the refresh frequency of the display area is a second refresh frequency; the first refresh frequency is less than the second refresh frequency; In the same display mode, the number of the output buffers enabled in the first period is less than the number of the output buffers enabled in the second period; Preferably, when the refresh frequency of the display area is the first refresh frequency, the picture display cycle of the display device includes at least one hold frame, and the output buffer is closed in the hold frame; Preferably, the picture display cycle further includes at least one refresh frame, the refresh frame includes a blank period and a display period, and the buffer control module controls the output buffer to be closed during the blank period, and controls the output buffer to be opened during the display period.

5. The display device according to claim 3, characterized in that: At the same refresh rate, if the display mode of the display device is heavy-load display, the output buffers are controlled to be enabled.

6. The display device according to claim 3, characterized in that: The display device includes a plurality of display partitions, the plurality of display partitions include a first display partition and a second display partition, the refresh frequency of the first display partition is a first refresh frequency, the refresh frequency of the second display partition is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency; The display partition receives a data voltage transmitted by the corresponding data driver; In the same display mode, the number of the output buffers enabled by the data driver corresponding to the first display partition is smaller than the number of the output buffers enabled by the data driver corresponding to the second display partition.

7. The display device according to claim 1, characterized in that: The data driver further includes a gamma voltage generating module and a filtering module; The gamma voltage generating module comprises a plurality of output terminals, and the gamma voltage generating module is used to generate a plurality of gamma voltages according to a first reference voltage and a second reference voltage; The input end of the filtering module is connected to the gamma voltage generating module, the filtering module includes a plurality of output ends, the output end of the filtering module corresponds to the output end of the gamma voltage generating module, each output end of the filtering module is connected to the data driving module, the filtering module is used to filter each of the gamma voltages to generate a driving voltage, and output it through the output end corresponding to the filtering module; Preferably, the multiple output terminals of the gamma voltage generating module include a first reference voltage output terminal and a second reference voltage output terminal; The first reference voltage output terminal is used to output the first reference voltage, and the second reference voltage output terminal is used to output the second reference voltage; The gamma voltage generation module further includes: a plurality of voltage-dividing resistors connected in series between the first reference voltage output terminal and the second reference voltage output terminal; wherein the plurality of output terminals of the gamma voltage generation module further include: a plurality of resistor output terminals, wherein the resistor output terminal is a common terminal between any two adjacent voltage-dividing resistors; Preferably, the filtering module includes multiple operational amplifier units and multiple filtering resistors, the input end of each operational amplifier unit is connected to the output end of the gamma voltage generating module in a one-to-one correspondence, the output end of the operational amplifier unit serves as the output end of the filtering module; the filtering resistor is connected to the output end of the operational amplifier unit.

8. The display device according to claim 7, characterized in that: It also includes a timing controller, which is connected to the control end of the operational amplifier unit, and is used to output an enable signal according to the grayscale and refresh frequency of the current display frame of the display device; wherein different display frames and refresh frequencies correspond to different enable signals; The enable signal includes a first enable signal and a second enable signal, the control ends of the first and last operational amplifier units are connected to the first enable signal, and the control ends of the other operational amplifier units are connected to the corresponding second enable signal, the first and last operational amplifier units are used to be turned on or off according to the first enable signal, and the other operational amplifier units are used to be turned on or off according to the corresponding second enable signal; Preferably, at the same refresh frequency, the timing controller is used to output the enable signal according to the gray scale of the current display frame of the display device; Preferably, the grayscale of the currently displayed frame includes a first grayscale, a second grayscale and a third grayscale, wherein the first grayscale is a high grayscale, the second grayscale is a medium grayscale, and the third grayscale is a low grayscale; At the same refresh frequency, when the grayscale of the currently displayed frame is the low grayscale, all the operational amplifier units are controlled to be turned on; when the grayscale of the currently displayed frame is the medium grayscale or the high grayscale, the first operational amplifier unit and the last operational amplifier unit are controlled to be turned on; Preferably, under the same display screen, the timing controller is used to output the enable signal according to the refresh frequency; Preferably, the display device includes a plurality of display partitions, the plurality of display partitions include a first display partition and a second display partition, the refresh frequency of the first display partition is a first refresh frequency, the refresh frequency of the second display partition is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency. The display partition receives a data voltage transmitted by a corresponding data driver; Under the same display screen, the number of operational amplifier units enabled by the data driver corresponding to the first display partition is less than the number of operational amplifier units enabled by the data driver corresponding to the second display partition; Preferably, the enable signal includes a first enable signal and a second enable signal; after the timing controller is powered on, the first enable signal is a first level signal, and the second enable signal is a first level signal and a second level signal that are alternately set in timing.

9. The display device according to claim 7, characterized in that: The data driver further comprises a reference voltage generating module connected to the driving power supply terminal, the reference voltage generating module is connected to the gamma voltage generating module, and the reference voltage generating module is used to generate the first reference voltage and the second reference voltage according to the driving power supply voltage connected to the driving power supply terminal; Preferably, the reference voltage generating module comprises a first reference voltage generating unit and a second reference voltage generating unit; The first reference voltage generating unit is connected to the driving power supply terminal and the first reference voltage terminal, and is used to generate a first reference voltage according to the driving power supply voltage and a first reference voltage connected to the first reference voltage terminal; The second reference voltage generating unit is connected to the driving power supply terminal and the second reference voltage terminal, and is used to generate a second reference voltage according to the driving power supply voltage and a second reference voltage connected to the second reference voltage terminal; Wherein, the driving power supply voltage is greater than the first reference voltage, and the first reference voltage is greater than the second reference voltage; Preferably, the first reference voltage generating unit includes a first voltage buffer amplifier, and the second reference voltage generating unit includes a second voltage buffer amplifier; The first input terminal of the first voltage buffer amplifier is connected to the first reference voltage terminal, the second input terminal of the first voltage buffer amplifier is connected to its own output terminal, the first power supply terminal of the first voltage buffer amplifier is connected to the driving power supply terminal, the second power supply terminal of the first voltage buffer amplifier is grounded, and the output terminal of the first voltage buffer amplifier provides the first reference voltage; The first input terminal of the second voltage buffer amplifier is connected to the second reference voltage terminal, the second input terminal of the second voltage buffer amplifier is connected to its own output terminal, the first power supply terminal of the second voltage buffer amplifier is connected to the driving power supply terminal, the second power supply terminal of the second voltage buffer amplifier is grounded, and the output terminal of the second voltage buffer amplifier provides the second reference voltage; The difference between the driving power supply voltage and the first reference voltage is greater than or equal to a preset bias voltage, and the difference between the driving power supply voltage and the second reference voltage is greater than or equal to the preset bias voltage.

10. The display device according to claim 1, characterized in that The data driving module also includes a register unit, a latch unit and a digital-to-analog conversion unit; The register unit is connected to the latch unit and is used to generate a latch clock signal; The latch unit is connected to the digital-to-analog conversion unit and is used to latch the image data according to the latch clock signal; The digital-to-analog conversion unit is connected to the output buffer and is configured to convert the latched image data into the data voltage based on a plurality of driving voltages.

Images