Ferroelectric memory circuit capable of improving imprinting effect and imprinting effect improving method

Abstract

The invention discloses a ferroelectric memory circuit capable of improving an imprinting effect and an imprinting effect improving method, the ferroelectric memory circuit comprises a plurality of memory units distributed in rows and columns, each memory unit comprises a ferroelectric capacitor, one polar plate of each ferroelectric capacitor is connected to a plate line PL, the plate line PL is connected with a plate line voltage driving circuit, and the plate line voltage driving circuit is connected with a ferroelectric capacitor. The board line voltage driving circuit is provided with a signal input IN, and comprises a high-low level switching circuit which is used for outputting a high level to a board line PL or outputting a low level to the board line PL according to the high-low level of the signal input IN; and the high-level voltage selection circuit is connected to the at least two high-level voltage outputs and is used for applying the selected high-level voltage to the board line PL when the high level is output to the board line PL according to the signal input IN. The circuit structure of the ferroelectric memory is optimized and improved, the ferroelectric memory is tested before leaving a factory, and voltage compensation adjustment is carried out according to the test, so that memory unit failure possibly caused by an imprinting effect can be prevented, and the read-write frequency of the memory unit is obviously increased.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, and in particular relates to a ferroelectric memory circuit capable of improving imprinting effect and an imprinting effect improving method. Background Art

[0002] There are currently three common reliability issues for ferroelectric memory, one of which is the imprint effect. The imprint effect in ferroelectric memory refers to a phenomenon that under certain conditions, the polarization state of the ferroelectric material may gradually deviate from its initial state after multiple write operations, causing the performance of the memory to gradually decline, affecting the durability and data retention capabilities of the memory.

[0003] like Figure 1 As shown in the figure, the principle of ferroelectric storage is to symmetrically change the polarity of ferroelectric materials by applying positive and negative voltages. The voltage is the horizontal axis E in the figure. The center point of a standard ferroelectric storage unit should be the zero point of E, that is, when the voltage is 0. Ferroelectric storage achieves the effect of distinguishing 0 and 1 by changing the capacitance of the ferroelectric unit by positive and negative voltages. Symmetrical storage units can cause the same polarization change by applying +V and -V voltages respectively, which means that the effective interval for distinguishing 0 and 1 is the same. However, in practical applications, ferroelectrics are not completely symmetrical, that is, the polarization intensity caused by +V and -V to the storage unit is different. In simple terms, the difficulty of a storage unit being identified as 0 or 1 is different under the same positive and negative voltages. When the number of times the storage unit is read and written reaches a certain level, there will be an imprinting effect of moving in the positive direction or the imprinting effect of moving in the negative direction. If it moves in the positive direction, the difficulty of positive polarization will increase, and vice versa. The polarization intensity on the positive and negative sides is asymmetric. Summary of the invention

[0004] The purpose of the present invention is to solve the above-mentioned problems and provide a ferroelectric memory circuit and a method for improving the imprinting effect. By optimizing and improving the circuit structure of the ferroelectric memory and testing it before leaving the factory, voltage compensation adjustment is performed according to the test to prevent the failure of the storage unit that may be caused by the imprinting effect, thereby significantly increasing the number of read and write times of the storage unit.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A ferroelectric memory circuit capable of improving imprinting effect comprises a plurality of memory cells distributed in rows and columns, each memory cell comprises a ferroelectric capacitor, one plate of each ferroelectric capacitor is connected to a plate line PL, the plate line PL is connected to a plate line voltage driving circuit, the plate line voltage driving circuit has a signal input IN, the plate line voltage driving circuit comprises,

[0007] A high-low level switching circuit, used for outputting a high level to the plate line PL or a low level to the plate line PL according to the high or low level of the signal input IN;

[0008] The high-level voltage selection circuit is connected to at least two high-level voltage outputs, and is used to apply the selected high-level voltage to the plate line PL when the high level needs to be output to the plate line PL according to the high or low level of the signal input IN. For example, the two high-level voltage outputs VCC0 and VCC1 are connected, and when the high level needs to be output to the plate line PL according to the high or low level of the signal input IN, the selected VCC0 or VCC1 voltage is applied to the plate line PL.

[0009] In the above-mentioned ferroelectric memory circuit capable of improving the imprinting effect, the plate line voltage driving circuit is connected to a voltage regulator, specifically an LDO (low-dropout linear regulator), the voltage regulator realizes at least two fixed voltage outputs through a voltage divider resistor, and the at least two fixed voltage outputs are used as the high-level voltage outputs, and the at least two fixed voltage outputs are connected to the plate line PL through the high-level voltage selection circuit. The high voltage selection circuit selects one of the high-level voltage outputs as the high voltage of the plate line PL for the memory circuit.

[0010] In the above-mentioned ferroelectric memory circuit capable of improving the imprinting effect, the plate line voltage driving circuit includes a low-level voltage selection circuit connected to at least two low-level voltage outputs, and used to apply the selected low-level voltage to the plate line PL when the low level needs to be output to the plate line PL according to the high or low level of the signal input IN. For example, two low-level voltage outputs VSS and VN are connected, and when the low level needs to be output to the plate line PL according to the high or low level of the signal input IN, the selected VSS or VN voltage is applied to the plate line PL.

[0011] In the above-mentioned ferroelectric memory circuit capable of improving the imprinting effect, the plate line voltage driving circuit is connected to the charge pump and the ground terminal of the ferroelectric memory, and the negative voltage VN output by the charge pump and the ground terminal VSS are respectively used as the low-level voltage outputs, and are connected to the plate line PL through the low-level voltage selection circuit. There are two low-level voltage outputs, one of which uses the negative voltage VN output by the charge pump of the memory itself, and the second one can directly use the ground terminal to simplify the circuit structure, and can also be realized by a voltage divider resistor similar to the high-level voltage output. Of course, there can also be three or more low-level voltage outputs, one of which directly uses the ground terminal, and the rest are realized by a charge pump and a voltage divider resistor.

[0012] In the above-mentioned ferroelectric memory circuit capable of improving the imprinting effect, the high-level voltage selection circuit comprises a plurality of switch tubes N0, N2, P1, P7, P12, P14, etc., and the plurality of switch tubes are connected by the control terminal TM <0> Control opening or closing to select the corresponding high-level voltage output. Multiple switch tubes are controlled by the control terminal TM <0> Direct or indirect control, TM <0> - Includes TM <0> The TM <0> Through inverter I2 <0> The obtained TMB <0> and further by TMB <0> Through inverter I3 <0> The obtained TMR <0> .

[0013] The low-level voltage selection circuit includes multiple switch tubes N4, N6, N8, N10, P16, P17, etc., and the multiple switch tubes are controlled by the control terminal OPTVSS to be turned on or off to select the corresponding low-level voltage output. Similarly, the multiple switch tubes here are also directly or indirectly controlled by the control terminal OPTVSS, and OPTVSS includes itself and OPTVSSN obtained by OPTVSS through inverter I4.

[0014] The high-low level switching circuit includes multiple switch tubes N5, N9, P0, P3, P6, P9, etc., and the multiple switch tubes are controlled by the signal input IN to be turned on or off to switch the high level voltage or the low level voltage; similarly, the multiple switch tubes here are also directly or indirectly controlled by the signal input IN.

[0015] The high-level voltage selection circuit and the multiple switch tubes of the high-low level switching circuit are combined to form a plurality of transmission routes between each high-level voltage output and the plate line PL;

[0016] The low-level voltage selection circuit and the multiple switch tubes of the high-low level switching circuit are combined to form a plurality of transmission routes between each low-level voltage output and the plate line PL;

[0017] The board line voltage driving circuit is based on the control terminal TM <0> The high and low levels of the control terminal OPTVSS and the signal input IN control the transmission path between the corresponding high level voltage output to the plate line PL to be opened, and the other transmission paths to be closed, or control the transmission path between the corresponding low level voltage output to the plate line PL to be opened, and the other transmission paths to be closed.

[0018] In the above-mentioned ferroelectric memory circuit capable of improving the imprinting effect, the plate line voltage driving circuit includes a low-level jump acceleration circuit. When the plate line PL is pulled from a high level to a low level, the high-low level switching circuit and the low-level voltage selection circuit control the corresponding low-level voltage output to open a transmission route between the plate line PL according to the high and low levels of the control terminal OPTVSS and the signal input IN;

[0019] At the same time, the low-level jump acceleration circuit connects the corresponding low-level voltage to the second transmission route of the plate line PL to pull the plate line PL from a high level to a low level more quickly; the low-level jump acceleration circuit includes switch tubes P18, P19, N14, N12, N13, and logic devices I5, I6, etc.

[0020] The plate line voltage driving circuit also includes a high level jump acceleration circuit. When the plate line PL is pulled from a low level to a high level, a high-low level switching circuit and a high level voltage selection circuit control a transmission route between the corresponding high level voltage output to the plate line PL according to the high and low levels of the control terminal OPTVSS and the signal input IN to open;

[0021] The high-level jump acceleration circuit is used to connect the corresponding high-level voltage to the second transmission route of the plate line PL so that the plate line PL is pulled from a low level to a high level more quickly.

[0022] In the above-mentioned ferroelectric memory circuit capable of improving the imprinting effect, the high-level jump acceleration circuit includes a plurality of switch tubes N1, P13, P4, N3, P15, P10, etc., and the plurality of switch tubes are connected by the control terminal TM <1> ~TM <n>Control opening or closing to select a second transmission route for outputting a corresponding high level voltage to the plate line PL;

[0023] N represents the number of high-level voltage outputs. If there are two high-level input voltages, VCC1 and VCC0, then n is 2.

[0024] In the above-mentioned ferroelectric memory circuit capable of improving the imprinting effect, the ferroelectric memory circuit has a plurality of plate lines PL, each plate line PL is connected to a plurality of ferroelectric capacitors, and taking a memory with a capacity of 1M as an example, there may be 16 plate lines, and one plate line is connected to 1024 rows and 64 columns of storage units.

[0025] In the above-mentioned ferroelectric memory circuit capable of improving the imprinting effect, in each ferroelectric memory, all plate lines PL are connected to the plate line voltage driving circuit;

[0026] Alternatively, each plate line PL is connected to one of the plate line voltage driving circuits.

[0027] A method for improving the imprinting effect of a ferroelectric memory, wherein the ferroelectric memory uses the above circuit structure and improves the imprinting effect by the following method:

[0028] Perform sampling tests on memory chips of the same batch to obtain the imprinting effect offset trend of the chips in the batch;

[0029] According to the trend of the imprinting effect offset, any high-level voltage and low-level voltage are selected for the circuit to compensate for the offset caused by the imprinting effect through different electric field strengths. Assuming that the imprinting effect is offset in the forward direction, a higher high-level voltage and / or a lower low-level voltage can be selected to increase the forward electric field strength formed by the plate voltage connected to BL, thereby compensating for the offset of the imprinting effect to the forward electric field. The specific selection is determined by the technician according to the memory characteristics and test results. If the imprinting effect is offset in the reverse direction, a higher high-level voltage and / or a lower low-level voltage can also be selected to increase the forward electric field strength formed by the plate voltage connected to BL, thereby compensating for the offset of the imprinting effect to the forward electric field. The specific selection is determined by the technician according to the memory characteristics and test results.

[0030] The advantages of the present invention are:

[0031] 1. This scheme uses the similar performance of chips in the same batch to perform sampling read and write tests on chips in the same batch to predict the tendency of ferroelectric capacitors to have imprinting effects, and effectively improves the service life of the chips before leaving the factory through voltage compensation adjustment, extending the number of read and write times when imprinting effects occur, thereby improving their service life;

[0032] 2. In conventional designs, when writing "0" or "1" to a ferroelectric capacitor, an electric field of equal magnitude and opposite direction is generally applied to the upper and lower plates. This solution provides a design idea of ​​different electric field strengths for the upper and lower plates when writing "0" and "1", and based on this idea, the effect of improving the reliability of the memory is achieved;

[0033] 3. This solution provides multiple voltage options for the high-level voltage and low-level voltage of the plate line of the ferroelectric capacitor through a specific circuit structure design, and provides a variety of high-level voltage driving capability options, effectively reducing the impact of the imprinting effect of the ferroelectric capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is the hysteresis curve of ferroelectric material;

[0035] Solid line: ideal central symmetric hysteresis loop curve; dotted line: hysteresis loop curve with offset center point

[0036] Figure 2 A ferroelectric memory cell structure of 1T1C structure;

[0037] Figure 3 This is an example of the selection of the plate voltage connected to the ferroelectric capacitor PL according to the present invention;

[0038] Figure 4 The plate line voltage driving circuit provided for this solution. DETAILED DESCRIPTION

[0039] This solution provides a ferroelectric memory circuit that can improve the imprinting effect. The basic unit is similar to the general ferroelectric memory structure and uses a storage unit composed of a transistor and a capacitor. Figure 2 The figure shows a 1T1C structure storage cell, which consists of an NMOS tube MN0 and a ferroelectric capacitor FC. The gate of the NMOS tube MN0 is connected to the word line WL, the source is connected to the bit line BL, and the drain is connected to the upper plate PLE of the ferroelectric capacitor. The upper plate of the ferroelectric capacitor is connected to the plate line PL. When reading data from the storage cell, the voltage of the word line WL is pulled from a low level to a high level, turning on the NMOS tube MN0, and the voltage of the plate line PL is pulled from a low level to a high level. The ferroelectric capacitor is positively polarized by the positive electric field, so that the upper plate PLE of the ferroelectric capacitor generates a voltage and transmits it to the bit line BL through MN0. When writing data into the storage cell, the voltage of the word line WL is also required to be pulled from a low level to a high level to turn on the NMOS tube MN0. If the data written is "0", the voltage of the upper plate PL of the ferroelectric capacitor remains at a high level (in this scheme, it remains VCC0 or VCC1, depending on the setting), and BL transmits the data "0" to the upper plate PLE of the ferroelectric capacitor through MN0. If the written data is "1", the voltage of the upper plate PL of the ferroelectric capacitor is pulled from a high level to a low level (in this scheme, VSS or VN, depending on the setting), and BL transmits the data "1" to the upper plate PLE of the ferroelectric capacitor through MN0. At this time, the ferroelectric capacitor is subjected to the action of the reverse electric field and is reversely polarized.

[0040] This solution designs a plate line voltage driving circuit that can provide different voltages for the memory. The appropriate voltage can be selected from the same batch through sampling tests before leaving the factory to reduce the impact of the imprinting effect of ferroelectric materials in the later stage. In general ferroelectric memories, there are LDO (low-dropout linear regulator) and charge pump. LDO is used to provide a stable voltage source for the ferroelectric memory, and the charge pump is used to provide a negative voltage to prevent the unselected word line voltage from being coupled from 0V to a high voltage by parasitic capacitance, causing the tube that should not be turned on to be turned on. In this solution, the different voltages required by the plate line voltage driving circuit can be realized with the help of the LDO (low-dropout linear regulator) and charge pump of the ferroelectric memory itself. The circuit changes are subtle and the implementation is simple.

[0041] In the traditional ferroelectric memory's plate line voltage driving circuit, the high level is usually achieved by LDO providing a fixed voltage output VCC1, and the low level is achieved by a charge pump providing a negative voltage VN. As mentioned earlier, such fixed high and low level voltages are the same for all memories. When the memories are used, some will shift in the positive direction and eventually show the imprinting effect, while others will shift in the negative direction and eventually show the imprinting effect.

[0042] This solution improves the plate line voltage driving circuit, and uses a voltage divider resistor to divide the output of the LDO into at least two different voltage outputs to provide at least two different high-level voltages for the plate line voltage driving circuit. At the same time, the ground terminal is added to the plate line voltage driving circuit as an option of the low level to provide at least two different low-level voltages for the plate line voltage driving circuit. In this way, the appropriate high-level voltage and low-level voltage can be selected for the same batch of chips through testing, so that the positive offset and reverse offset memories can have a slower imprinting effect, thereby increasing the number of read and write times of the storage unit. Figure 3 As shown, the working voltages of the upper and lower plates of a ferroelectric capacitor are 1.5V and 0V. The upper plate of the ferroelectric capacitor is connected to the plate line PL, and the lower plate is connected to the bit line BL. When writing "0", BL is a low voltage and PL is a high voltage. Assume that the electric field direction of the ferroelectric capacitor is positive at this time. When writing "1", BL is a high voltage, PL is a low voltage, and the electric field direction of the ferroelectric capacitor is negative. When testing the chip, it was found that the imprint effect of reverse movement appeared after reading and writing 100,000 times. When the reverse imprint is offset, a higher reverse electric field strength is required for polarity deflection to occur. At this time, adjusting the low voltage of PL from 0V to -0.5V can produce a higher reverse electric field strength. It was found that the imprint effect of forward movement appeared after reading and writing 100,000 times. When the positive imprint is offset, a higher forward electric field strength is required for polarity deflection to occur. At this time, adjusting the low voltage of PL from 1.5V to 2V can produce a higher forward electric field strength. The influence of the imprinting effect can be prevented by selecting the PL high-level voltage and the low-level voltage, thereby improving the reliability of the memory. Figure 3 P represents the functional relationship between the voltage difference between the upper and lower plates and the electric field strength.

[0043] This embodiment is described in detail by taking an example that an LDO has two fixed voltage outputs VCC0 and VCC1 and two low voltage options.

[0044] Figure 4 The figure shows a plate line voltage driving circuit, in which the output signal PL jumps from a low level to a high level or from a high level to a low level following the input signal IN.

[0045] TM<2:0> represents TM <0> ,TM <1> and TM <2> , TMB<2:0> represents TMB <0> 、TMB <1> and TMB <2> , TMR<2:0> represents TMR <0> 、TRM <1> and TMR <2> I2<2:0> represents I2 <0> 、I2 <1> and I2 <2> , I3<2:0> represents I3 <0> 、I3 <1> and I3 <2> .

[0046] TM <2> ,TM <1> and TM <0> Passing through inverter I2 <2> 、I2 <1> and I2 <0> TMB <2> 、TMB <1> 、TMB <0> .TMB <2> 、TMB <1> 、TMB <0> Through inverter I3 <2> 、I3 <1> and I3 <0> TMR can be obtained separately <2> 、TRM <1> and TMR <0> .

[0047] TM <0> Used to select the high level of output PL to be VCC0 or VCC1 (VCC1>VCC0). If TM <0> If TM is high, select VCC1. <0> If it is low level, select VCC0, which can make TM <0> Connect VCC1 port or VCC0 port to set TM <0> High level makes TM <0> Connect to ground or negative voltage VN to set TM <0> is low level.

[0048] TM <1> , it is used to increase the driving capability of PL when VCC0 is selected.

[0049] TM <2> , it is used to increase the driving capability of PL when VCC1 is selected.

[0050] OPTVSS is used to select the low level of the output PL as VSS or negative voltage VN. If OPTVSS is high, VSS is selected, and if OPTVSS is low, VN is selected. Similarly, OPTVSS can be connected to VCC1 to set OPTVSS to a high level, and connected to negative voltage VN to set OPTVSS to a low level.

[0051] Among them, VSS is provided by the ground, and VN is provided by the charge pump of the memory itself, which is a negative voltage. VCC0 and VCC1 are realized by the existing LDO (low dropout linear regulator). A voltage is introduced through an external power supply. This solution uses the bandgap reference circuit and LDO with a voltage divider resistor to realize the desired different voltages VCC0, VCC1, or more VCC2, VCC3, etc.

[0052] The specific working process is:

[0053] (1)TM<2:0>="000", OPTVSS="0"

[0054] TM <2> ,TM <1> and TM <0> All are "0", the high level of the output PL is selected as VCC0 and the low level is VN.

[0055] When the input signal IN voltage jumps from a low level to a high level (the default low level required by the memory storage unit is the negative voltage VN provided by the charge pump, and the high level is the output voltage VCC1 of the LDO), a buffer circuit composed of inverters I0 and I1 makes the INR signal jump from a low level to a high level, and NMOS tubes N5 and N9 are turned on.

[0056] The negative voltage VN is transmitted to NDRVN and NDRVSS through N5 and N9, so that the voltages of NDRVN and NDRVSS are pulled to the negative voltage VN.

[0057] Since OPTVSS is at a low level, the inverter I4 outputs OPTVSSN at a high level, and the transmission gate composed of the NMOS tube N8 and the PMOS tube P17 is opened, and the transmission gate composed of the NMOS tube N4 and the PMOS tube P16 is closed, and the NMOS tube N10 is also closed.

[0058] Since TM<2:0> are all low level, the outputs TMB<2:0> through the inverter I2<2:0> are all high level, and then the outputs TMR<2:0> through the inverter I3<2:0> are all low level. At this time, the transmission gate composed of N0 and P12 is opened, and the three transmission gates composed of N1 and P13, N2 and P14, and N3 and P15 are closed. At the same time, the P1 tube is closed, and the three PMOS tubes P4, P7 and P10 are opened. VCC0 is transmitted to the gate of P5 through P4 to turn off P5, and VCC1 is transmitted to the gates of P8 and P11 through P7 and P10 respectively, turning off P8 and P11. NDRVN transmits the negative voltage VN to the gate of P2 tube through N8 and P17, and the two open transmission gates of N0 and P12 transmit the negative voltage VN to the gate of P2 tube to turn on P2 tube, and VCC0 is transmitted to PL through P2 tube, so that the PL voltage is pulled to the high level VCC0.

[0059] When the voltage of the input signal IN jumps from high level to low level, INR also jumps from high level to low level. At this time, the four PMOS tubes P0, P3, P6 and P9 are turned on, VCC0 passes through P0 and P3 to turn off P2 and P5, and VCC1 passes through P6 and P9 to turn off P8 and P11. VCC0 is transmitted to the gate of NMOS tube N11 through the transmission gate composed of P0, P12 and N0 and the transmission gate composed of P17 and N8. N11 is turned on, and the negative voltage VN is transmitted to PL through N11, pulling the PL voltage from VCC0 to the negative voltage VN.

[0060] When the PL voltage is low enough to turn on the PMOS tube P18, the high level (VCC1) outputs the PULL signal as a high level through P18 and P19, PULL and OPTVSSN output PULLD as a high level through the AND gate I6, N13 is turned on, and VN is transmitted to PL through N13, prompting the PL voltage to be pulled from VCC0 to VN faster.

[0061] (2)TM<2:0>="010", OPTVSS="0"

[0062] TM <0> ="0",TM <1> = "1", TM <2> = "0", OPTVSS = "0", that is, the high level of the output PL is selected as VCC0, and the low level is VN. When VCC0 is selected, the driving capability of PL is increased.

[0063] On the basis of (1), when TM <1> When it is high, TMB is low, TMR is high, and the transmission gate composed of P13 and N1 is also open, and PMOS tube P4 is closed. When the input signal IN voltage jumps from low level to high level, NDRVN transmits the negative voltage VN to the gates of P2 and P5 through the three open transmission gates N8 and P17, N0 and P12, and N1 and P13, respectively, to open P2 and P5. At this time, VCC0 has two paths to transmit to PL, which makes the PL voltage pull from VN to VCC0 faster, that is, to increase the driving ability of PL.

[0064] In this setting, when the input signal IN voltage jumps from high level to low level, the process is similar to (1).

[0065] (3) TM<2:0> = "000", OPTVSS = "1", which means that the high level of the output PL is selected as VCC0 and the low level is selected as VSS.

[0066] Since OPTVSS is high, the output OPTVSSN of inverter I4 is low. At this time, the transmission gate composed of N4 and P16 is open, the transmission gate composed of N8 and P17 is closed, the NMOS tube N10 is open, and the negative voltage VN is transmitted to the gate NDRVN of N11 through N10 to close N11. When the input signal IN voltage jumps from low level to high level, NDRVSS transmits the negative voltage VN to the gate of P2 tube through N4 and P16, and the two open transmission gates N0 and P12 to open P2 tube, and VCC0 is transmitted to PL through P2 tube, so that the PL voltage is pulled to VCC0.

[0067] When the voltage of the input signal IN jumps from high level to low level, INR also jumps from high level to low level. At this time, the four PMOS tubes P0, P3, P6 and P9 are turned on, VCC0 passes through P0 and P3 to turn off P2 and P5, and VCC1 passes through P6 and P9 to turn off P8 and P11. VCC0 is transmitted to the gate of NMOS tube N7 through the transmission gate composed of P0, P12 and N0 and the transmission gate composed of P16 and N4. N7 is turned on, and the low level VSS is transmitted to PL through N7, pulling the PL voltage from VCC0 to VSS.

[0068] When the PL voltage is low enough to turn on the PMOS tube P18, the high level (VCC1) outputs the PULL signal as a high level through P18 and P19, PULL and OPTVSS output PULLD as a high level through the AND gate I5, N12 is turned on, and VSS is transmitted to PL through N12, prompting the PL voltage to be pulled from VCC0 to VSS faster.

[0069] (4) TM<2:0> = "010", OPTVSS = "1", i.e. TM <0> ="0",TM <1> = "1", TM <2> = "0", OPTVSS = "0", that is, the high level of the output PL is selected as VCC0, and the low level is VSS. When VCC0 is selected, the driving capability of PL is increased.

[0070] Based on (3), when TM <1> When it is high, TMB is low, TMR is high, and the transmission gate composed of P13 and N1 is also open, and PMOS tube P4 is closed. When the input signal IN voltage jumps from low level to high level, NDRVSS transmits the negative voltage VN to the gates of P2 and P5 through the three open transmission gates N4 and P16, N0 and P12, and N1 and P13, respectively, to open P2 and P5. At this time, VCC0 has two paths to transmit to PL, which makes the PL voltage pull to VCC0 faster.

[0071] In this setting, when the input signal IN voltage jumps from a high level to a low level, the process is similar to (3).

[0072] (5)TM<2:0> = "100", OPTVSS = "0", i.e. TM <0> = "1", TM <1> ="0",TM <2> = "0". That is, the high level of output PL is selected as VCC 1 and the low level is selected as VN.

[0073] When the input signal IN voltage jumps from low level to high level, due to TM <0> is high level, passing through inverter I2 <0> Output TMB <0> is low level, and then passes through inverter I3 <0> Output TMR <0> When it is high, the transmission gate composed of N2 and P14 opens, and the three transmission gates composed of N1 and P13, N0 and P12, and N3 and P15 close. At the same time, the P7 tube is closed, and the three PMOS tubes P4, P1 and P10 are opened. VCC0 is transmitted to the gates of P5 and P2 through P1 and P4 to close P5 and P2, and VCC1 is transmitted to the gate of P11 through P10 to close P11. NDRVSS transmits the negative voltage VN to the gate of P8 tube through N4 and P16, and the two open transmission gates of N2 and P14 to open P8 tube. VCC1 is transmitted to PL through P8 tube, so that the PL voltage is pulled to VCC1.

[0074] When the input signal IN jumps from high level to low level, INR also jumps from high level to low level. At this time, the four PMOS tubes P0, P3, P6 and P9 are turned on, VCC0 turns off P2 and P5 through P0 and P3, and VCC1 turns off P8 and P11 through P6 and P9. VCC1 is transmitted to the gate of NMOS tube N11 through the transmission gate composed of PMOS tubes P7, P14 and N2 and the transmission gate composed of P17 and N8. N11 is turned on, and the negative voltage VN is transmitted to PL through N11, pulling the PL voltage from VCC1 to the negative voltage VN.

[0075] When the PL voltage is low enough to turn on the PMOS tube P18, the high level VCC1 outputs the PULL signal as a high level through P18 and P19, PULL and OPTVSSN output PULLD as a high level VCC1 through the AND gate I6, N13 is turned on, and VN is transmitted to PL through N13, prompting the PL voltage to be pulled from VCC1 to VN faster.

[0076] (6) TM<2:0> = "101", OPTVSS = "0", i.e. TM <0> = "1", TM <1> ="0",TM <2> = "1". That is, the high level of the output PL is selected as VCC 1, and the low level is VN. When VCC1 is selected, the driving capability of PL is increased.

[0077] Based on (5), when TM <2> When TMB is high, <2> is low level, TMR <2> is high level, at this time, the transmission gate composed of P15 and N3 is also opened, and the PMOS tube P10 is closed. When the input signal IN voltage jumps from low level to high level, NDRVSS transmits the negative voltage VN to the gates of P8 and P11 through the three open transmission gates N8 and P17, N2 and P14, and N3 and P15, respectively, so that P8 and P11 are turned on. At this time, VCC1 has two paths to transmit to PL, which makes the PL voltage pull to VCC1 faster.

[0078] In this setting, when the input signal IN voltage jumps from a high level to a low level, the process is similar to (5).

[0079] (7) TM<2:0> = "100", OPTVSS = "1", i.e. TM <0> = "1", TM <1> ="0",TM <2> = "0", that is, the high level of output PL is selected as VCC1 and the low level is selected as VSS.

[0080] Since OPTVSS is high, the output OPTVSSN of inverter I4 is low. At this time, the transmission gate composed of N4 and P16 is open, the transmission gate composed of N8 and P17 is closed, the NMOS tube N10 is open, and the negative voltage VN is transmitted to the gate NDRVN of N11 through N10 to close N11. When the input signal IN voltage jumps from low level to high level, NDRVSS transmits the negative voltage VN to the gate of P8 tube through N4 and P16, and the two open transmission gates of N2 and P14 to turn on P8 tube, and VCC1 is transmitted to PL through P8 tube, so that the PL voltage is pulled to VCC1.

[0081] When the voltage of the input signal IN jumps from a high level to a low level, INR also jumps from a high level to a low level. At this time, the four PMOS tubes P0, P3, P6 and P9 are turned on, VCC0 turns off P2 and P5 through P0 and P3, and VCC1 turns off P8 and P11 through P6 and P9. VCC1 is transmitted to the gate of the NMOS tube N7 through the transmission gate composed of the PMOS tubes P7, P14 and N2 and the transmission gate composed of P16 and N4. N7 is turned on, and the low level VSS is transmitted to PL through N7, pulling the PL voltage from VCC1 to VSS. When the PL voltage is low enough to turn on the PMOS tube P18, the high level VCC1 outputs the PULL signal as a high level through P18 and P19, and PULL and OPTVSS output PULLD as a high level through the AND gate I5. N12 is turned on, and VSS is transmitted to PL through N12, prompting the PL voltage to be pulled from VCC1 to VSS faster.

[0082] (8) TM<2:0> = "101", OPTVSS = "1", i.e. TM <0> = "1", TM <1> ="0",TM <2> = "1", that is, the high level of the output PL is selected as VCC1 and the low level is VSS. When VCC1 is selected, the driving capability of PL is increased.

[0083] Based on (7), when TM <2> When TMB is high, <2> is low level, TMR <2> is high level, at this time, the transmission gate composed of P15 and N3 is also opened, and the PMOS tube P10 is closed. When the input signal IN voltage jumps from low level to high level, NDRVSS transmits the negative voltage VN to the gates of P8 and P11 through the three open transmission gates N4 and P16, N2 and P14, and N3 and P15, respectively, so that P8 and P11 are turned on. At this time, VCC1 has two paths to transmit to PL, which makes the PL voltage pull to VCC1 faster.

[0084] In this setting, when the input signal IN voltage jumps from a high level to a low level, the process is similar to (7).

[0085] When put into use, the plate line voltage driving circuit in the original ferroelectric memory is improved as follows Figure 4 The circuit structure shown in the figure is then sampled for read and write tests on the memory chips of the same batch before leaving the factory. After testing, it is found that the batch of chips will have an imprinting effect that shifts in a certain direction as the number of read and write times increases. According to the imprinting effect shift direction, the degree of shift, and the characteristics of the ferroelectric memory, the corresponding high-level voltage and low-level voltage are selected to compensate for the shift caused by the imprinting effect through different electric field strengths. In this way, when the chip is used after leaving the factory, due to the voltage compensation in advance, it can overcome the imprinting effect that will appear in the future, thereby delaying the appearance time of the imprinting effect and extending the service life of the chip.

[0086] The specific embodiments described herein are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

[0087] Although this article uses more terms such as high-low level switching circuit, high-level voltage selection circuit, low-level voltage selection circuit, low-level jump acceleration circuit, high-level jump acceleration circuit, and plate line voltage driving circuit, it does not exclude the possibility of using other terms. These terms are used only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional restrictions is contrary to the spirit of the present invention.

[0088] The plate line voltage driving circuit includes a high-low level switching circuit, a high-level voltage selection circuit, a low-level voltage selection circuit, a low-level jump acceleration circuit, and a high-level jump acceleration circuit. Each switch tube of the plate line voltage driving circuit can belong to one of the high-low level switching circuit, the high-level voltage selection circuit, the low-level voltage selection circuit, the low-level jump acceleration circuit, and the high-level jump acceleration circuit, or can belong to two or more of them at the same time.< / n>

Claims

1. A ferroelectric memory circuit capable of improving imprinting effect, comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising a ferroelectric capacitor, one plate of each ferroelectric capacitor being connected to a plate line PL, the plate line PL being connected to a plate line voltage driving circuit, characterized in that: The plate line voltage driving circuit has a signal input IN, and the plate line voltage driving circuit includes: A high-low level switching circuit, used for outputting a high level to the plate line PL or a low level to the plate line PL according to the high or low level of the signal input IN; The high level voltage selection circuit is connected to at least two high level voltage outputs, and is used to apply the selected high level voltage to the plate line PL when a high level needs to be output to the plate line PL according to the high or low level of the signal input IN.

2. The ferroelectric memory circuit capable of improving imprinting effect according to claim 1, characterized in that: The plate line voltage driving circuit is connected to a voltage regulator, and the voltage regulator has at least two fixed voltage outputs, and the at least two fixed voltage outputs are used as the high level voltage outputs and are connected to the plate line PL through the high level voltage selection circuit.

3. The ferroelectric memory circuit capable of improving imprinting effect according to claim 2, characterized in that: The plate line voltage driving circuit includes a low level voltage selection circuit connected to at least two low level voltage outputs, and is used to apply the selected low level voltage to the plate line PL when a low level needs to be output to the plate line PL according to the high or low level of the signal input IN.

4. The ferroelectric memory circuit capable of improving imprinting effect according to claim 3, characterized in that: The plate line voltage driving circuit is connected to the charge pump and ground of the ferroelectric memory, and the negative voltage output by the charge pump and the ground are respectively used as the low level voltage outputs, and are connected to the plate line PL through the low level voltage selection circuit.

5. The ferroelectric memory circuit capable of improving imprinting effect according to claim 4, characterized in that: The high level voltage selection circuit comprises a plurality of switch tubes, the plurality of switch tubes are connected to the control terminal TM <0> Control opening or closing to select the corresponding high level voltage output; The low-level voltage selection circuit includes a plurality of switch tubes, and the plurality of switch tubes are controlled to be turned on or off by the control terminal OPTVSS to select the corresponding low-level voltage output; The high-low level switching circuit includes a plurality of switch tubes, and the plurality of switch tubes are controlled to be turned on or off by a signal input IN to switch a high level voltage or a low level voltage; The high-level voltage selection circuit and the multiple switch tubes of the high-low level switching circuit are combined to form a plurality of transmission routes between each high-level voltage output and the plate line PL; The low-level voltage selection circuit and the multiple switch tubes of the high-low level switching circuit are combined to form a plurality of transmission routes between each low-level voltage output and the plate line PL; The board line voltage driving circuit is based on the control terminal TM <0> The high and low levels of the control terminal OPTVSS and the signal input IN control the transmission path between the corresponding high level voltage output to the plate line PL to be opened, and the other transmission paths to be closed, or control the transmission path between the corresponding low level voltage output to the plate line PL to be opened, and the other transmission paths to be closed.

6. The ferroelectric memory circuit capable of improving imprinting effect according to claim 5, characterized in that: The plate line voltage driving circuit includes a low-level jump acceleration circuit. When the plate line PL is pulled from a high level to a low level, the high-low level switching circuit and the low-level voltage selection circuit control the corresponding low-level voltage output to open a transmission route between the plate line PL according to the high and low levels of the control terminal OPTVSS and the signal input IN; The low level jump acceleration circuit is used to connect the corresponding low level voltage to the second transmission route of the plate line PL so that the plate line PL is pulled from the high level to the low level faster; The plate line voltage driving circuit also includes a high level jump acceleration circuit. When the plate line PL is pulled from a low level to a high level, the high-low level switching circuit and the high level voltage selection circuit control the high level voltage output of the corresponding high level voltage to open a transmission route between the plate line PL according to the high and low levels of the control terminal OPTVSS and the signal input IN; The high-level jump acceleration circuit is used to connect the corresponding high-level voltage to the second transmission route of the plate line PL so that the plate line PL is pulled from a low level to a high level more quickly.

7. The ferroelectric memory circuit capable of improving imprinting effect according to claim 6, characterized in that: The high-level jump acceleration circuit includes a plurality of switch tubes, and the plurality of switch tubes are connected to the control terminal TM <1> ~TM <n> Control opening or closing to select a second transmission route for outputting a corresponding high level voltage to the plate line PL;< / n> N represents the number of high-level voltage outputs.

8. The ferroelectric memory circuit capable of improving imprinting effect according to claim 1, characterized in that: The ferroelectric memory circuit has a plurality of plate lines PL, and each plate line PL is connected to a plurality of ferroelectric capacitors.

9. The ferroelectric memory circuit capable of improving imprinting effect according to claim 8, characterized in that: In each ferroelectric memory, all plate lines PL are connected to one of the plate line voltage driving circuits; Alternatively, each plate line PL is connected to one of the plate line voltage driving circuits.

10. A method for improving the imprinting effect of a ferroelectric memory, characterized in that: The ferroelectric memory uses the circuit structure described in any one of claims 1 to 9, and improves the imprinting effect by the following method: Perform sampling tests on memory chips of the same batch to obtain the imprinting effect offset trend of the chips in the batch; According to the offset trend of the imprinting effect, any high-level voltage and low-level voltage are selected for the circuit to compensate for the offset caused by the imprinting effect through different electric field strengths.

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