Multi-time programmable memory cell and memory device
By adding a second capacitor to the control end of the programming tube, the source area potential is connected to the ground terminal or the low potential terminal, the existing multiple programmable memory cells have been solved, and the chip cost is reduced and the effect of reducing size.
Patent Information
- Application Number
- CN202410962139.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-17
- Publication Date
- 2025-02-14
AI Technical Summary
The existing multi-programmable memory cells have high costs and large areas, making it difficult to meet the needs of reducing chip costs and reducing chip size.
Add a second capacitance to the control end of the programming tube, so that the source region potential of the programming tube is connected to the ground or low potential end, thereby reducing the overlap between the programming path and the erase path and saving TUB and high voltage well.
The area and layout levels of multiple programmable memory units and storage devices are reduced, reducing chip cost and chip size.
Smart Images
Figure CN119446231A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of storage technology, and in particular to a multi-time programmable storage unit and a storage device. Background Art
[0002] MTP (Multi-time Programmable Cell) is a commonly used technology in integrated circuits. This technology can achieve precision adjustment or customer customization of the chip after it leaves the factory, and can be used as a storage memory module of the chip. Its basic principle is to adjust the device's threshold voltage and other parameters by capturing or releasing the charge in the storage medium, thereby affecting the output current value.
[0003] In the prior art, double-layer polysilicon gate memory cells are the most commonly used technical means. However, since the double-layer polysilicon structure requires an increase in the number of mask layers, the cost of the chip is increased, and the existing multi-time programmable memory cells have a large area layout.
[0004] Therefore, providing a multi-time programmable memory cell and a memory device to reduce chip cost and chip size is a problem to be solved in the art. Summary of the invention
[0005] In view of the above problems, the purpose of the present invention is to provide a multi-time programmable memory cell and a memory device. By adding a second capacitor to the control end of the programming tube, the potential of the source region of the programming tube can be always connected to the ground end or the low potential end, thereby achieving a reduction in the area and layout level of the multi-time programmable memory cell and the memory device, thereby reducing chip cost and reducing chip size.
[0006] According to one aspect of the present invention, there is provided a multi-time programmable memory cell, comprising: a substrate, and:
[0007] A selection tube comprises a first gate region, a first source region, and a first drain region, wherein the first drain region is connected to a bit line, and the first gate region is connected to a word line;
[0008] A programming tube, comprising a second gate region, a second source region, and a second drain region, wherein the second drain region is connected to the first source region, and the second source region is connected to a ground terminal or a low potential terminal;
[0009] a first capacitor, comprising a first end connected to the second gate region, and a second end connected to the control gate line,
[0010] The second capacitor includes a first end connected to the second gate region and a second end connected to the tunneling gate line.
[0011] Preferably, the first well region, the second well region and the third well region are located in the substrate and are spaced apart from each other.
[0012] The first source region and the first drain region of the selection tube are located in the first well region, and the first gate region of the selection tube is located on the first well region;
[0013] The second source region and the second drain region of the programming tube are located in the first well region, and the second gate region of the programming tube is located on the first well region.
[0014] The first source region is a first doped region, the first drain region and the second source region are second doped regions, the second drain region is a third doped region, and the second gate region is a floating gate region.
[0015] Preferably, it further comprises: a fourth doping region, the fourth doping region is located in the first well region, and the third doping region is connected to the fourth doping region and connected to a ground terminal or a low potential terminal.
[0016] Preferably, the first capacitor further comprises:
[0017] a third gate region, located on the second well region and connected to the second gate region;
[0018] The fifth doping region and the sixth doping region are located in the second well region, and the fifth doping region and the sixth doping region are connected to the control gate line.
[0019] The third gate region serves as a first end of the first capacitor, and the second well region serves as a second end of the first capacitor.
[0020] Preferably, the second capacitor further comprises:
[0021] a fourth gate region, located on the third well region and connected to the second gate region;
[0022] A seventh doping region and an eighth doping region are located in the third well region, and the seventh doping region and the eighth doping region are connected and connected to a tunneling gate line;
[0023] The fourth gate region serves as a first end of the second capacitor, and the third well region serves as a second end of the second capacitor.
[0024] Preferably, an area of the third gate region is larger than an area of the second gate region.
[0025] Preferably, the area of the third gate region is greater than or equal to 10 times the area of the second gate region.
[0026] Preferably, the first well region, the fourth doping region, the fifth doping region and the seventh doping region are of the first doping type, and the second well region, the third well region, the first doping region, the second doping region, the third doping region, the sixth doping region and the eighth doping region are of the second doping type,
[0027] The first doping type is one of P type and N type, and the second doping type is the other of P type and N type.
[0028] Preferably, when the multi-time programmable memory cell is programmed, the fifth doping region to the eighth doping region are connected to a positive potential;
[0029] When the multi-time programmable memory cell is erased, the fifth doping region and the sixth doping region are connected to a low potential or grounded, and the seventh doping region and the eighth doping region are connected to a positive potential;
[0030] When the multi-time programmable memory cell is read, the first doping region, the first gate region, and the fifth doping region to the eighth doping region are all connected to a positive potential.
[0031] The present invention also provides a storage device, comprising any of the multi-time programmable storage units described above.
[0032] The multi-time programmable memory cell and the memory device provided by the present invention add a second capacitor at the control end of the programming tube to distinguish the programming path and the erasing path of the programming tube, so that the potential of the source region of the programming tube can always be connected to the ground end or the low potential end, thereby saving the TUB and the high-voltage well in the multi-time programmable memory cell, achieving the reduction of the area and layout level of the multi-time programmable memory cell and the memory device, thereby reducing the chip cost and reducing the chip size.
[0033] Furthermore, the multi-time programmable memory cell and memory device of the present application use the tunneling principle to enable the floating gate to capture and release electrons for programming and erasing, that is, the multi-time programmable memory cell is designed using the tunneling principle, which reduces the size of the multi-time programmable memory cell and thus reduces the cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0035] Figure 1 A circuit diagram of a multi-time programmable memory cell according to an embodiment of the present invention is shown;
[0036] Figure 2 A schematic structural diagram of a multi-time programmable memory cell according to an embodiment of the present invention is shown. DETAILED DESCRIPTION
[0037] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.
[0038] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.
[0039] Figure 1 A circuit diagram of a multi-time programmable memory cell according to an embodiment of the present invention is shown; Figure 2 A schematic structural diagram of a multi-time programmable memory cell according to an embodiment of the present invention is shown.
[0040] refer to Figure 1 The multi-time programmable memory cell 100 of the present application includes a selection tube 10, a programming tube 20, a first capacitor (CG capacitor or control gate capacitor) 30 and a second capacitor (TG capacitor or tunneling gate capacitor) 40. Specifically, the selection tube 10 is connected in series with the programming tube 20, the first end of the selection tube 10 is connected to the bit line BL (Bit Line), the second end is connected to the first end of the programming tube 20, and the control end is connected to the word line WL; the second end of the programming tube 20 is connected to the ground end or the low potential end VSS; the first end of the first capacitor 30 is connected to the control end of the programming tube 20, and the second end is connected to the control gate line (Control Gate, CG); the first end of the second capacitor 40 is connected to the first end of the first capacitor 30, and the second end is connected to the tunneling gate line (Tunnel Gate, TG). Among them, the first end of the selection tube 10 and the programming tube 20 is, for example, a drain end, and the second end is, for example, a source end.
[0041] Further, refer to Figure 2 The semiconductor structure of the multi-time programmable memory cell 100 includes a substrate 147, and a selection tube 10, a programming tube 20, a first capacitor 30 and a second capacitor 40 located on the substrate 147. The selection tube 10 includes a first gate region 134, a first source region and a first drain region, the first drain region is connected to the bit line BL, and the first gate region 134 is connected to the word line WL; the programming tube 20 includes a second gate region, a second source region and a second drain region, the second drain region is connected to the first source region, and the second source region is connected to the ground terminal or the low potential terminal; the first capacitor 30 includes a first end connected to the second gate region 135, and a second end connected to the control gate line CG; the second capacitor 40 includes a first end connected to the second gate region 135, and a second end connected to the tunneling gate line TG.
[0042] Specifically, the substrate 147 includes: a first well region 144, a second well region 145, and a third well region 146 that are spaced apart, a first doping region 131, a second doping region 132, a third doping region 133, and a fourth doping region 138 located in the first well region 144, and a first gate region 134 and a second gate region 135 located on the first well region 134. Among them, the first doping region 131 is the first source region of the selection tube 10, the second doping region 132 is the first drain region of the selection tube 10 and the second source region of the programming tube 20, and the third doping region 133 is the second drain region of the programming tube 20. The fourth doping region 138 is coupled to the third doping region 133 and coupled to the ground terminal or the low potential terminal, and the second gate region 135 is a floating gate region.
[0043] The first capacitor 30 specifically includes: a fifth doping region 139 and a sixth doping region 140 located in the second well region 145, and a third gate region 136 located on the second well region 145. The third gate region 136 is connected to the second gate region 135 of the programming tube 20, and the fifth doping region 139 and the sixth doping region 140 are connected and connected to the control gate line CG (Control Gate).
[0044] The second capacitor 40 specifically includes: a seventh doping region 141 and an eighth doping region 142 located in the third well region 146, and a fourth gate region 137 located on the third well region 146. The fourth gate region 137 is connected to the second gate region 135 of the programming tube 20, and the seventh doping region 141 and the eighth doping region 142 are connected and connected to the tunnel gate line TG (Tunnel Gate).
[0045] The first well region 144 is of the first doping type, the second well region 145 and the third well region 146 are of the second doping type, the first doping region 131, the second doping region 132 and the third doping region 133 are of the second doping type, the fourth doping region 138 is of the first doping type, the fifth doping region 139 is of the first doping type, the sixth doping region 140 is of the second doping type, the seventh doping region is of the first doping type, and the eighth doping region is of the second doping type.
[0046] In this embodiment, the first doping type and the second doping type are opposite doping types, the first doping type is, for example, one of N-type and P-type, and the second doping type is the other of N-type and P-type. In the present application, the first doping type is, for example, P-type, and the second doping type is, for example, N-type.
[0047] Furthermore, combining Figure 1 and Figure 2 , the following description is made by taking the programming tube 20 and the selection tube 10 of the multi-time programmable memory cell 100 as NMOS tubes as an example.
[0048] The substrate 147 is, for example, a P-type substrate. The first well region 144 is a P-type well region (Pwell), the second well region 145 is an N-type well region (Nwell), the third well region 146 is an N-type well region (Nwell), the first doping region 131, the second doping region 132, the third doping region 133, the sixth doping region 140 and the eighth doping region 142 are N-type heavily doped (N+), and the fourth doping region 138, the fifth doping region 139 and the seventh doping region 141 are P-type heavily doped (P+).
[0049] Specifically, the substrate 147, the first well region 144, the first doping region 131, the second doping region 132 and the first gate region 134 constitute, for example, the selection tube 10 of the multi-time programmable memory cell 100. The first doping region 131 is connected to the bit line BL (BitLine), and the first gate region 134 is connected to the word line WL (Word Line).
[0050] The substrate 147, the first well region 144, the second doping region 132, the third doping region 133 and the second gate region 135, for example, constitute the programming tube 20 of the multi-time programmable memory cell 100, and the second gate region 135, for example, is a floating gate region. The third doping region 133 is connected to the fourth doping region 138, and is connected to the ground terminal or the low potential terminal VSS.
[0051] In addition, the third gate region 136 is equivalent to one electrode of the first capacitor 30, and the second well region 145 is equivalent to the other electrode of the first capacitor 30, that is, the third gate region 136 and the second well region 145 form the first capacitor 30, and the fifth doping region 139 and the sixth doping region 140 serve as the lead-out region of the other electrode of the first capacitor 30. In the first capacitor 30, the third gate region 136 is connected to the second gate region 135 of the programming tube 20, and the fifth doping region 139 is connected to the sixth doping region 140 and connected to the control gate line CG (Control Gate). In this embodiment, due to the existence of the first capacitor 30, the second gate region 135 of the programming tube 20 is floating, so that the programming tube 20 is a floating gate transistor.
[0052] The fourth gate region 137 is equivalent to one electrode of the second capacitor 40, and the third well region 146 is equivalent to the other electrode of the second capacitor 40, that is, the fourth gate region 137 and the third well region 146 form the second capacitor 40, and the seventh doping region 141 and the eighth doping region 142 serve as the lead-out region of the other electrode of the second capacitor 40. In the second capacitor 40, the fourth gate region 137 is connected to the second gate region 135 of the programming tube 20, and the seventh doping region 141 and the eighth doping region 142 are connected and connected to the tunnel gate line TG (Tunnel Gate).
[0053] In this embodiment, the area of the third gate region 136 is greater than the area of the second gate region 135. For example, the area of the third gate region 136 may be greater than or equal to 10 times the area of the second gate region 135, so that when a positive potential is applied to both ends of the tunneling gate line TG and the control gate line CG at the same time, most of the voltage drop will drop on the second gate region 135, that is, on the gate of the programming tube 20; when a positive potential is applied to the tunneling gate line TG and the control gate line CG is connected to the low potential VSS or grounded, most of the voltage drop will drop on the second capacitor 40.
[0054] In addition, the multi-time programmable memory cell 100 of the present application further includes a gate oxide layer (not shown in the figure), which is located between the first gate region 134, the second gate region 135, the third gate region 136 and the fourth gate region 137 and the surface of the substrate 147, and is used to isolate the gate region from the substrate 147. Figure 2 The gap between each gate region and the substrate 147 is used to represent gate oxide. A plurality of shallow trench isolation structures 143 may also be included. The shallow trench isolation structures 143 are located between adjacent well regions and are used to isolate adjacent well regions.
[0055] Further, refer to Figure 1 and Figure 2 , the working principle of the multi-time programmable storage unit 100 of the present application is explained.
[0056] When the multi-time programmable memory cell 100 needs to be programmed, the tunneling gate line TG and the control gate line CG are both connected to a positive potential, and the word line WL and the bit line BL are floating. That is, in the case of programming, the fifth doping region 139, the seventh doping region 141 and the eighth doping region 142 are connected to a positive potential. At this time, most of the voltage difference between the tunneling gate line TG and the control gate line CG falls on the gate of the programming tube 20, that is, most of the voltage difference falls on the second gate region (floating gate) 135. At this time, according to the tunneling principle, the second gate region 135 can capture electrons, thereby increasing the threshold voltage of the programming tube 20.
[0057] When the multi-time programmable memory cell 100 needs to be erased, the tunneling gate line TG is connected to a positive potential, the control gate line CG is connected to a negative potential, and the word line WL and the bit line BL are floating. That is to say, in the case of erasing, the seventh doping region 141 and the eighth doping region 142 are connected to a positive potential, and the fifth doping region 139 is connected to a negative potential. At this time, most of the voltage difference between the tunneling gate line TG and the control gate line CG falls on the second capacitor 40. At this time, according to the tunneling principle, the second gate region 135 can release electrons, thereby reducing the threshold voltage of the programming tube 20.
[0058] In this embodiment, it should be particularly pointed out that when erasing, under such bias, the third gate region 136 of the first capacitor 30 will deplete the second well region 145 and invert it, so the potential of the silicon under the gate oxide (not shown) of the first capacitor 30 cannot be directly drawn out through the sixth doping region 140. This is because the third gate region 136 and the second well region 145 form an electric field with an electric field direction from bottom to top, and the electrons in the second well region 145 move downward, so that the sixth doping region 140 and the electrons moved to the bottom layer of the second well region 145 form a reverse diode, which in turn causes the sixth doping region 140 to be unable to draw out the potential of the silicon under the gate oxide (not shown) of the first capacitor 30. By changing the doping region of the second doping type (N+) on one side of the first capacitor 30 to the fifth doping region 139 of the first doping type (P+), the potential of the silicon under the gate oxide (not shown) of the first capacitor 30 can be drawn out.
[0059] When the multi-time programmable memory cell 100 is read, the tunneling gate line TG, the control gate line CG, the word line WL and the bit line BL are all connected to a high potential. In this case, the programming tube 20 and the selection tube 10 are both turned on. If the programming tube 20 is programmed, the measured current value will become smaller; if the programming tube 20 is not programmed or has been erased, the measured current value will be normal. In addition, the multi-time programmable memory cell 100 can be erased and programmed multiple times.
[0060] In the above-mentioned embodiments, the transistor of the multi-time programmable memory unit 100 is described by taking an NMOS tube as an example, that is, the conductivity type is N-type. In other embodiments, the multi-time programmable memory unit 100 may also be a PMOS tube, that is, the conductivity type is P-type. For those skilled in the art, it is easy to switch the NMOS tube to the PMOS tube. For the sake of brevity, it will not be described here.
[0061] Furthermore, the present application also provides a storage device, which includes the above-mentioned multi-time programmable storage unit 100.
[0062] The multi-time programmable memory cell and the memory device provided by the present invention add a second capacitor at the control end of the programming tube to distinguish the programming path and the erasing path of the programming tube, so that the potential of the source region of the programming tube can always be connected to the ground end or the low potential end, thereby saving the TUB and the high-voltage well in the multi-time programmable memory cell, achieving the reduction of the area and layout level of the multi-time programmable memory cell and the memory device, thereby reducing the chip cost and reducing the chip size.
[0063] Furthermore, the multi-time programmable memory cell and memory device of the present application use the tunneling principle to enable the floating gate to capture and release electrons for programming and erasing, that is, the multi-time programmable memory cell is designed using the tunneling principle, which reduces the size of the multi-time programmable memory cell and thus reduces the cost.
[0064] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A multi-time programmable memory cell, comprising: A substrate, and disposed on the substrate: A selection tube comprises a first gate region, a first source region, and a first drain region, wherein the first drain region is connected to a bit line, and the first gate region is connected to a word line; A programming tube, comprising a second gate region, a second source region, and a second drain region, wherein the second drain region is connected to the first source region, and the second source region is connected to a ground terminal or a low potential terminal; a first capacitor, comprising a first end connected to the second gate region, and a second end connected to the control gate line, The second capacitor includes a first end connected to the second gate region and a second end connected to the tunneling gate line.
2. The multi-time programmable memory cell according to claim 1, wherein: Also includes: a first well region, a second well region and a third well region located in the substrate and spaced apart from each other, The first source region and the first drain region of the selection tube are located in the first well region, and the first gate region of the selection tube is located on the first well region; The second source region and the second drain region of the programming tube are located in the first well region, and the second gate region of the programming tube is located on the first well region. The first source region is a first doped region, the first drain region and the second source region are second doped regions, the second drain region is a third doped region, and the second gate region is a floating gate region.
3. The multi-time programmable memory cell according to claim 2, wherein: It also includes: a fourth doping region, the fourth doping region is located in the first well region, and the third doping region is connected to the fourth doping region and connected to a ground terminal or a low potential terminal.
4. The multi-time programmable memory cell according to claim 3, wherein: The first capacitor further comprises: a third gate region, located on the second well region and connected to the second gate region; The fifth doping region and the sixth doping region are located in the second well region, and the fifth doping region and the sixth doping region are connected to the control gate line. The third gate region serves as a first end of the first capacitor, and the second well region serves as a second end of the first capacitor.
5. The multi-time programmable memory cell according to claim 4, wherein: The second capacitor further comprises: a fourth gate region, located on the third well region and connected to the second gate region; A seventh doping region and an eighth doping region are located in the third well region, and the seventh doping region and the eighth doping region are connected and connected to a tunneling gate line; The fourth gate region serves as a first end of the second capacitor, and the third well region serves as a second end of the second capacitor.
6. The multi-time programmable memory cell according to claim 4, wherein: An area of the third gate region is greater than an area of the second gate region.
7. The multi-time programmable memory cell according to claim 6, wherein: An area of the third gate region is greater than or equal to 10 times an area of the second gate region.
8. The multi-time programmable memory cell according to claim 5, wherein: The first well region, the fourth doping region, the fifth doping region and the seventh doping region are of the first doping type, and the second well region, the third well region, the first doping region, the second doping region, the third doping region, the sixth doping region and the eighth doping region are of the second doping type, The first doping type is one of P type and N type, and the second doping type is the other of P type and N type.
9. The multi-time programmable memory cell according to claim 5, wherein: When the multi-time programmable memory cell is programmed, the fifth doping region to the eighth doping region are connected to a positive potential; When the multi-time programmable memory cell is erased, the fifth doping region and the sixth doping region are connected to a low potential or grounded, and the seventh doping region and the eighth doping region are connected to a positive potential; When the multi-time programmable memory cell is read, the first doping region, the first gate region, and the fifth doping region to the eighth doping region are all connected to a positive potential.
10. A storage device, wherein: The invention comprises a multi-time programmable memory cell as claimed in any one of claims 1 to 9.