Preparation method of integrated packaging structure for wafer back power supply

Abstract

The invention provides a preparation method of an integrated packaging structure for wafer back power supply, which comprises the following steps: directly forming an epitaxial silicon layer and an active region on the front surface of a first semiconductor substrate, forming an STI (shallow trench isolation) groove and a buried power rail in the active region, grinding the first semiconductor substrate with the grinding thickness being 80%-95% of the initial thickness, and then carrying out a CMP (chemical mechanical polishing) process to obtain the integrated packaging structure for wafer back power supply. And planarizing and thinning the ground first semiconductor substrate, enabling the end point of planarizing and thinning to stop on the epitaxial silicon layer, and forming a nano silicon through hole electrically connected with the buried power rail. Compared with a preparation technology of an existing integrated packaging structure, the back face of the first semiconductor substrate is smoother, so that a process window is increased, a germanium-silicon layer does not need to be grown, control is easier in the actual production process, the germanium-silicon layer does not need to be removed in the later period, a wafer cannot be damaged, the production yield is greatly improved, and the production cost is reduced. And the requirement of epitaxial silicon on equipment is relatively low, so that the production cost can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a method for preparing an integrated packaging structure for powering the back side of a wafer. Background Art

[0002] In existing integrated circuits, the power transmission network is generally set on the front side of the wafer, so as to provide a steady supply of power and reference voltage (i.e., VDD and VSS) to the active devices on the chip through the power transmission network. However, there is also a signal network in the front area of ​​the wafer. As the size of integrated circuits gradually decreases, it is becoming increasingly difficult to arrange the power transmission network and the signal network to coexist on the front side of the chip.

[0003] The existing solution is to solve the above problem by supplying power from the back side of the wafer. The principle of back side power supply is to separate the power transmission network from the signal network by transferring the entire power transmission network to the back side of the wafer. In this process, the wafer is only used as a carrier, and the electrons do not need to pass through a complex stack. Power can be directly delivered to a standard battery, which is expected to reduce IR voltage drop, improve power transmission performance, and reduce wiring congestion in the back-end process.

[0004] At present, the commonly used preparation process of the back power supply device is as follows: first, a layer of germanium silicon layer is epitaxially grown on the surface of the wafer, and then silicon is epitaxially grown on the surface of the germanium silicon layer, and active areas, STI grooves, and buried power rails and other devices are prepared on the epitaxial silicon layer, and the wafer prepared with the device is bonded to another wafer on the front side, and the germanium silicon layer can be used as a stop layer when the wafer is polished and thinned, and the back of the wafer prepared with the device is thinned to the germanium silicon layer and the germanium silicon layer is removed by a wet etching process, and finally a nano silicon via connected to the buried power rail is prepared on the back of the wafer. However, due to the relatively high technical requirements of the epitaxial germanium silicon layer, it is not easy to control it in the actual production process, resulting in a low yield rate of the product. In addition, the epitaxial germanium silicon layer also has relatively high requirements for equipment, thereby increasing the production cost in disguise. When using a wet etching solution to remove the germanium silicon layer, it is easy to cause the surface of the wafer to be uneven, thereby damaging the wafer, which further reduces the production yield rate. Summary of the invention

[0005] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a method for preparing an integrated packaging structure for back-side power supply of a wafer, so as to solve the problems in the existing preparation technology of the integrated packaging structure for back-side power supply that in the production process of the device, it is necessary to use an epitaxial germanium silicon layer technology that is difficult to control, resulting in low production yield and high production cost and easy damage to the wafer.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing an integrated packaging structure for wafer backside power supply, the preparation method comprising:

[0007] Providing a first semiconductor substrate, wherein the first semiconductor substrate comprises a front surface and a back surface that are oppositely disposed;

[0008] forming an epitaxial silicon layer on the front surface of the first semiconductor substrate;

[0009] forming an active area and a plurality of STI trenches in the active area on the epitaxial silicon layer;

[0010] forming a buried power rail between the plurality of STI trenches and inverting the first semiconductor substrate;

[0011] Providing a second semiconductor substrate and forming a second silicon oxide layer on the front surface of the second semiconductor substrate;

[0012] Bonding the second silicon oxide layer to the active area and grinding the back side of the first semiconductor substrate to remove a certain thickness of the first semiconductor substrate;

[0013] Using sensors of a CMP machine to detect, collect and analyze data such as the flatness of the first semiconductor substrate, and adjusting the pressure of different areas of the CMP machine head to flatten and thin the first semiconductor substrate after grinding, and making the end point of the flattening and thinning of the first semiconductor substrate stop at the epitaxial silicon layer;

[0014] The epitaxial silicon layer is etched to form a nano-through silicon via and the nano-through silicon via is filled to form a conductive filling portion electrically connected to the buried power rail.

[0015] Optionally, after forming the buried power rail, the method further includes performing sputtering deposition on the active area to seal the buried power rail.

[0016] Optionally, the step of forming the conductive filling portion includes: first forming a dielectric protection layer in the nano-silicon via, the dielectric protection layer covering the two side walls of the nano-silicon via and the epitaxial silicon layer, forming a seed layer in the nano-silicon via, the seed layer covering the dielectric protection layer and the bottom wall of the nano-silicon via, and starting to grow the conductive filling portion on the bottom wall of the nano-silicon via.

[0017] Optionally, a top of the conductive filling portion is flush with a top of the dielectric protection layer.

[0018] Optionally, the conductive filling part has a thermal stability of at least 650°C.

[0019] Optionally, the conductive filling portion and the buried power rail are made of the same material.

[0020] Optionally, both the conductive filling portion and the buried power rail include refractory metals such as tungsten or ruthenium.

[0021] Optionally, the initial thickness of the first semiconductor substrate is 200 μm to 800 μm and the thickness of the epitaxial silicon layer is 5 μm to 80 μm.

[0022] Optionally, the thickness of the first semiconductor substrate removed during grinding accounts for 80% to 95% of the initial thickness of the first semiconductor substrate.

[0023] Optionally, the spacing between the nano-through silicon vias is 40 μm to 110 μm.

[0024] As described above, a preparation method of an integrated packaging structure for wafer backside power supply of the present invention has the following beneficial effects: an epitaxial silicon layer is directly formed on the front side of the first semiconductor substrate, an active area is prepared on the epitaxial silicon layer, and an STI groove and a buried power rail are formed in the active area, the first semiconductor substrate is ground, and the grinding thickness is 80% to 95% of the initial thickness of the first semiconductor substrate, and then the remaining first semiconductor substrate is flattened and thinned by adjusting the CMP machine, and the end point of this flattening and thinning stops at the epitaxial silicon layer, so that the back side of the first semiconductor substrate is smoother, and a nano-silicon through-hole electrically connected to the buried power rail is formed on the back side of the first semiconductor substrate, thereby increasing the process window, and compared with the existing preparation technology of the integrated packaging structure with backside power supply, there is no need to grow an epitaxial germanium silicon layer, so that the actual production process is easier to control, and there is no need to use a wet etching solution to remove the germanium silicon layer, and no damage to the wafer is caused, thereby greatly improving the production yield, and further, the requirements of epitaxial silicon on equipment are relatively low, so that the production cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a flow chart showing the steps of the method for preparing the integrated packaging structure for wafer back side power supply of the present invention.

[0026] Figure 2 It is a cross-sectional schematic diagram of a first semiconductor substrate in the method for preparing an integrated packaging structure for wafer backside power supply of the present invention.

[0027] Figure 3 It is a cross-sectional schematic diagram showing the formation of an epitaxial silicon layer in the method for preparing an integrated packaging structure for wafer backside power supply of the present invention.

[0028] Figure 4It is a cross-sectional schematic diagram showing the formation of STI grooves in the method for preparing an integrated packaging structure for wafer backside power supply of the present invention.

[0029] Figure 5 It is a cross-sectional schematic diagram showing the formation of an initial power rail groove in the method for preparing an integrated packaging structure for wafer backside power supply of the present invention.

[0030] Figure 6 It is a cross-sectional schematic diagram showing the formation of a buried power rail in the method for preparing an integrated packaging structure for wafer backside power supply of the present invention.

[0031] Figure 7 It is a cross-sectional schematic diagram showing the inversion of the first semiconductor substrate in the method for preparing an integrated packaging structure for wafer back side power supply of the present invention.

[0032] Figure 8 It is a cross-sectional schematic diagram showing the bonding of the first semiconductor substrate and the second semiconductor substrate in the method for preparing the integrated packaging structure for wafer back side power supply of the present invention.

[0033] Fig. 9 It is a schematic cross-sectional view of the first semiconductor substrate after grinding in the method for preparing an integrated packaging structure for wafer back side power supply of the present invention.

[0034] Fig.10 It is a cross-sectional schematic diagram showing the first semiconductor substrate being planarized and thinned by a CMP machine in the method for preparing an integrated packaging structure for wafer backside power supply of the present invention.

[0035] Fig.11 It is a cross-sectional schematic diagram of forming a through silicon via in the method for preparing an integrated packaging structure for power supply on the back side of a wafer according to the present invention.

[0036] Fig.12 Shown is a schematic cross-sectional view of an integrated packaging structure for wafer back side power supply prepared by the method for preparing an integrated packaging structure for wafer back side power supply of the present invention.

[0037] Component number description

[0038] 101, first semiconductor substrate; 1011, front side; 1012, back side; 102, epitaxial silicon layer; 103, active area; 104, STI groove; 105, initial power rail groove; 106, buried power rail; 107, second semiconductor substrate; 108, second silicon oxide layer; 109, nano-silicon via; 110, dielectric protection layer; 111, conductive filling part; S1~S8, steps. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0041] It should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the above components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0042] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limitations of the present invention. As used herein, unless the context otherwise clearly indicates, the singular form "a (kind / person)" is also intended to include the plural form. It will also be understood that when the terms "comprise" and its variations, "include" and its variations are used in this specification, the stated features, wholes, steps, operations, elements and / or components are indicated, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations are not excluded.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0044] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0045] See also Figures 1 to 12 The present invention provides a method for preparing an integrated packaging structure for power supply on the back side of a wafer, such as Figure 1 As shown, it is shown as a step flow chart of the preparation method, comprising the following steps:

[0046] S1: providing a first semiconductor substrate 101, wherein the first semiconductor substrate 101 comprises a front surface 1011 and a back surface 1012 which are arranged opposite to each other;

[0047] S2: forming an epitaxial silicon layer 102 on the front surface 1011 of the first semiconductor substrate 101;

[0048] S3: forming an active area 103 and a plurality of STI trenches 104 located in the active area 103 on the epitaxial silicon layer 102;

[0049] S4: forming a buried power rail 106 between the plurality of STI trenches 104 and inverting the first semiconductor substrate 101;

[0050] S5: providing a second semiconductor substrate 107 and forming a second silicon oxide layer 108 on the front surface of the second semiconductor substrate 107;

[0051] S6: bonding the second silicon oxide layer 108 to the active region 103 and grinding the back surface 1012 of the first semiconductor substrate 101 to remove a certain thickness of the first semiconductor substrate 101;

[0052] S7: using sensors of a CMP machine to detect, collect and analyze data such as the flatness of the first semiconductor substrate 101, and adjusting the pressure of different areas of the CMP machine head to flatten and thin the polished first semiconductor substrate 101, and making the end point of the flattening and thinning of the first semiconductor substrate 101 stop at the epitaxial silicon layer 102;

[0053] S8: etching the epitaxial silicon layer 102 to form a nano-through silicon via 109 , and filling the nano-through silicon via 109 to form a conductive filling portion 111 electrically connected to the buried power rail 106 .

[0054] The following is a further introduction to the preparation method of the integrated packaging structure for wafer backside power supply in conjunction with the accompanying drawings, as follows:

[0055] In step S1, see Figure 1 and Figure 2 , providing a first semiconductor substrate 101, wherein the first semiconductor substrate 101 includes a front side 1011 and a back side 1012 that are oppositely arranged.

[0056] Optionally, the material of the first semiconductor substrate 101 includes but is not limited to one of a bare silicon (Si) wafer, gallium nitride, silicon carbide or glass, and the initial thickness of the first semiconductor substrate 101 is 200 μm to 800 μm, for example, 200 μm, 500 μm or 800 μm, and its shape can be circular, square or any other desired shape.

[0057] Specifically, in this embodiment, the first semiconductor substrate 101 is a bare silicon (Si) wafer, and the thickness of the first semiconductor substrate 101 is 500 μm.

[0058] In step S2, see Figure 1 and Figure 3 , an epitaxial silicon layer 102 is formed on the front side 1011 of the first semiconductor substrate 101 .

[0059] Specifically, Figure 3 As shown, an epitaxial formation process is performed on the first semiconductor substrate 101 to form an epitaxial silicon layer 102 on the front surface 1011 of the first semiconductor substrate 101. In some embodiments, the formation process of the epitaxial silicon layer 102 includes an epitaxial growth process, and the epitaxial silicon layer 102 formed can be a single-layer crystalline silicon epitaxial layer or a multi-layer crystalline silicon epitaxial layer. The thickness of the epitaxial silicon layer 102 is 5 μm to 80 μm, which can be set as needed and is not limited.

[0060] In step S3, see Figure 1 and Figure 4 , an active area 103 and a plurality of STI trenches 104 located in the active area 103 are formed on the epitaxial silicon layer 102 .

[0061] Specifically, ion implantation is first performed on the top of the epitaxial silicon layer 102 to form an active area 103, and then a trench isolation process is performed in the active area 103 to form a plurality of STI trenches 104. In this process, the shape of the STI trench 104 finally formed can be controlled by controlling etching parameters. For example, an anisotropic etching process can be used to obtain an STI trench 104 with a square cross-sectional shape. The etching process does not add additional operations to the etching process and can reduce the risk of lateral etching. The plurality of STI trenches 104 obtained by the above process are independent structures. In addition, oxide is filled in the STI trench 104 to achieve an isolation effect on the active area 103. The type of oxide can be silicon dioxide or other types, and the oxide can also cover the top of the active area 103. Then, the STI trench 104 filled with oxide is subjected to an annealing process.

[0062] In step S4, see Figure 1 , Figure 5 and Figure 6 , forming a buried power rail 106 between the plurality of STI trenches 104 , and inverting the first semiconductor substrate 101 .

[0063] Specifically, in this embodiment, the steps of forming the buried power rail 106 between the plurality of STI grooves 104 are as follows: first, when forming the plurality of STI grooves 104, an initial power rail groove 105 is reserved on the active area 103, such as Figure 5 As shown, the initial power rail trench 105 is located between the STI trenches 104 and exposes the epitaxial silicon layer 102, and then the exposed epitaxial silicon layer 102 is etched using a patterned mask process to form a power rail trench located in the epitaxial silicon layer 102, and a conductive material is filled in each power rail trench to form a buried power rail 106, as shown in FIG. Figure 6 Optionally, after forming the buried power rail 106 , the active area 103 is sputtered to close the buried power rail 106 . Specifically, the initial power rail groove 105 is sputtered to close the initial power rail groove 105 , so that the buried power rail 106 is completely surrounded or encapsulated by the active area 103 .

[0064] like Figure 7 As shown, after the buried power rail 106 is formed, the first semiconductor substrate 101 is turned upside down so that the front side 1011 of the first semiconductor substrate 101 can be bonded to other unpatterned semiconductor substrates.

[0065] In step S5, refer to Figure 1 and Figure 8 , providing a second semiconductor substrate 107 and forming a second silicon oxide layer 108 on the front surface of the second semiconductor substrate 107 .

[0066] Optionally, the material of the second semiconductor substrate 107 includes, but is not limited to, one of a bare silicon (Si) wafer, gallium nitride, silicon carbide or glass, and its shape may be circular, square or any other desired shape.

[0067] Preferably, the second semiconductor substrate 107 is a bare silicon (Si) wafer, so that the material of the second semiconductor substrate 107 is consistent with the material of the first semiconductor substrate 101, so as to achieve a better bonding effect, and a second silicon oxide layer 108 is formed on the front side of the second semiconductor substrate 107 by a thermal oxidation process, so that the second silicon oxide layer 108 can be bonded to the active area 103, wherein the formed second silicon oxide layer 108 can act as an insulating layer on the one hand, and on the other hand, it can also improve the bonding strength between the first semiconductor substrate 101 and the second semiconductor substrate 107.

[0068] In step S6, refer to Figure 1 and Fig. 9 , the second silicon oxide layer 108 is bonded to the active area 103 and the back side 1012 of the first semiconductor substrate 101 is ground, so as to remove a certain thickness of the first semiconductor substrate 101 .

[0069] Specifically, Fig. 9 As shown, the second semiconductor substrate 107 is bonded to the first semiconductor substrate 101, and the back side 1012 of the first semiconductor substrate 101 is ground. Since the epitaxial silicon layer 102 may be damaged during grinding, only a certain thickness of the first semiconductor substrate 101 is removed during grinding. In this embodiment, the thickness of the first semiconductor substrate 101 removed during grinding accounts for 80% to 95% of the initial thickness of the first semiconductor substrate 101, and then the CMP process with better flattening and thinning process is used to prevent damage to the epitaxial silicon layer 102, thereby improving the reliability and stability of the device.

[0070] In step S7, refer to Figure 1 and Fig.10 , using the sensors of the CMP machine to detect, collect and analyze the flatness and other data of the first semiconductor substrate 101, and by adjusting the pressure of different areas of the CMP machine head, the first semiconductor substrate 101 after grinding is flattened and thinned, and the end point of the flattening and thinning of the first semiconductor substrate 101 is stopped at the epitaxial silicon layer 102.

[0071] When the first semiconductor substrate 101 is initially thinned by a grinding process, damage to the first semiconductor substrate 101 will inevitably be introduced during the grinding process and there will still be slight depressions on the first semiconductor substrate 101 after grinding. Therefore, the first semiconductor substrate 101 after grinding is thinned again by a CMP process. Specifically, in this embodiment, the flatness and other data of the first semiconductor substrate 101 after grinding and thinning are first detected, collected and analyzed by a sensor of a CMP machine. According to the result of the data analysis, the pressure of different areas of the CMP machine head is adjusted to achieve flattening and thinning of the first semiconductor substrate 101 after grinding again, and the end point of the flattening and thinning of the first semiconductor substrate 101 is stopped on the epitaxial silicon layer 102, thereby achieving precise thinning of the first semiconductor substrate 101 and preventing damage to the epitaxial silicon layer 102.

[0072] In step S8, refer to Figure 1 and Fig.11, the epitaxial silicon layer 102 is etched to form a nano-through silicon via 109 and the nano-through silicon via 109 is filled to form a conductive filling portion 111 electrically connected to the buried power rail 106 .

[0073] Specifically, Fig.11 As shown, the epitaxial silicon layer 102 is patterned and etched to form nano-silicon vias 109, the bottom of the nano-silicon vias 109 is arranged in contact with the buried power rail 106, and the spacing between the nano-silicon vias 109 is 40μm to 110μm, for example, 40μm, 70μm or 110μm. Further, the nano-silicon vias 109 are arranged opposite to the buried power rail 106 and have the same size.

[0074] In this embodiment, the step of forming the conductive filling portion 111 includes: first forming a dielectric protection layer 110 in the nano-silicon via 109, the dielectric protection layer 110 covers the two side walls of the nano-silicon via 109 and the epitaxial silicon layer 102, forming a seed layer in the nano-silicon via 109, the seed layer covers the dielectric protection layer 110 and the bottom wall of the nano-silicon via 109, and starting to grow the conductive filling portion 111 on the bottom wall of the nano-silicon via 109.

[0075] Specifically, Fig.12 As shown, a dielectric protection layer 110 is first formed in the nano-silicon via 109, which includes depositing a dielectric material on the epitaxial silicon layer 102, the dielectric protection layer 110 covers the two side walls of the nano-silicon via 109 and the non-nano-silicon via 109 area on the epitaxial silicon layer 102, then, a seed layer is formed on the dielectric protection layer 110, the seed layer completely covers the dielectric protection layer 110 on the two side walls of the nano-silicon via 109 and the bottom wall of the nano-silicon via 109, finally, a conductive filling portion 111 is grown from the seed layer on the bottom wall of the nano-silicon via 109, and a planarization process is performed on the protruding conductive filling portion 111, so that the top of the conductive filling portion 111 is flush with the top of the dielectric protection layer 110. In this embodiment or other embodiments, in order to improve the conductivity between the conductive filling portion 111 and the buried power rail 106, the conductive filling portion 111 and the buried power rail 106 are set to the same material. For example, the conductive filling portion and the buried power rail 106 may include refractory metals such as tungsten or ruthenium or any other suitable metal.

[0076] When the conductive filling portion 111 is formed, a high-temperature annealing process is performed on it. In this embodiment or other further embodiments, the conductive filling portion 111 has a thermal stability of at least 650°C, so that when the conductive filling portion 111 is subsequently annealed at a temperature of about 650°C or greater (such as greater than about 700°C or greater than about 800°C), the internal structure of the conductive filling portion 111 will not change too much, so as not to affect the reliability and stability of the device.

[0077] In summary, the present invention provides a method for preparing an integrated packaging structure for back-side power supply of a wafer, by directly forming an epitaxial silicon layer on the front side of a first semiconductor substrate, preparing an active area on the epitaxial silicon layer, forming an STI groove and a buried power rail in the active area, and forming a nano-silicon through hole electrically connected to the buried power rail on the back side of the first semiconductor substrate, grinding the first semiconductor substrate, the grinding thickness is 80% to 95% of the initial thickness of the first semiconductor substrate, and then by adjusting the CMP machine, the first semiconductor substrate after grinding is flattened and thinned, and the end point of the flattening and thinning is finally stopped at the epitaxial silicon layer, so that the back side of the first semiconductor substrate is smoother, thereby increasing the process window, compared with the existing preparation technology of the back-side power supply integrated packaging structure, there is no need to grow an epitaxial germanium silicon layer, therefore, it is easier to control in the actual production process, and there is no need to remove the germanium silicon layer, so that the wafer will not be damaged, thereby greatly improving the production yield, and further, the requirements of epitaxial silicon on equipment are relatively low, thereby reducing the production cost. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0078] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing an integrated packaging structure for wafer backside power supply, characterized in that: The preparation method comprises: Providing a first semiconductor substrate, wherein the first semiconductor substrate comprises a front surface and a back surface that are oppositely disposed; forming an epitaxial silicon layer on the front surface of the first semiconductor substrate; forming an active area and a plurality of STI trenches in the active area on the epitaxial silicon layer; forming a buried power rail between the plurality of STI trenches and inverting the first semiconductor substrate; Providing a second semiconductor substrate and forming a second silicon oxide layer on the front surface of the second semiconductor substrate; Bonding the second silicon oxide layer to the active area and grinding the back side of the first semiconductor substrate to remove a certain thickness of the first semiconductor substrate; Using sensors of a CMP machine to detect, collect and analyze data such as the flatness of the first semiconductor substrate, and adjusting the pressure of different areas of the CMP machine head to flatten and thin the first semiconductor substrate after grinding, and making the end point of the flattening and thinning of the first semiconductor substrate stop at the epitaxial silicon layer; The epitaxial silicon layer is etched to form a nano-through silicon via, and the nano-through silicon via is filled to form a conductive filling portion electrically connected to the buried power rail.

2. The preparation method according to claim 1, characterized in that: After forming the buried power rail, the method further includes performing sputtering deposition on the active area to seal the buried power rail.

3. The preparation method according to claim 1, characterized in that: The step of forming the conductive filling portion includes: first forming a dielectric protection layer in the nano-silicon via, the dielectric protection layer covers the two side walls of the nano-silicon via and the epitaxial silicon layer, forming a seed layer in the nano-silicon via, the seed layer covers the dielectric protection layer and the bottom wall of the nano-silicon via, and starting to grow the conductive filling portion on the bottom wall of the nano-silicon via.

4. The preparation method according to claim 3, characterized in that: The top of the conductive filling part is flush with the top of the dielectric protection layer.

5. The preparation method according to claim 1, characterized in that: The conductive filling part has a thermal stability of at least 650°C.

6. The preparation method according to claim 1, characterized in that: The conductive filling portion is composed of the same material as the buried power rail.

7. The preparation method according to claim 1, characterized in that: The conductive filling portion and the buried power rail both include refractory metals such as tungsten or ruthenium.

8. The preparation method according to claim 1, characterized in that: The initial thickness of the first semiconductor substrate is 200 μm to 800 μm and the thickness of the epitaxial silicon layer is 5 μm to 80 μm.

9. The preparation method according to claim 1, characterized in that: The thickness of the first semiconductor substrate removed during grinding accounts for 80% to 95% of the initial thickness of the first semiconductor substrate.

10. The preparation method according to claim 1, characterized in that: The spacing between the nano-silicon through holes is 40 μm to 110 μm.

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