Wafer flaw detection system

Abstract

The invention mainly discloses a wafer flaw detection system. The wafer flaw detection system comprises a line light source, a camera and a processor, according to the design of the invention, the processor is coupled with the camera and the line light source so as to control the line light source to provide detection light to be incident on a wafer, and an included angle between the detection light and the surface of the wafer is between 45 degrees and 90 degrees. After the detection light enters the wafer, the detection light travels inside the wafer according to the principle of total reflection, and under the condition that the detection light encounters a crack, part of the detection light is emitted from the surface of the wafer through the crack. Moreover, the processor controls the camera to obtain a wafer image containing at least one defect feature, and after the wafer image is processed into a detection wafer image, the wafer image is compared with a reference wafer image, so that the at least one defect feature is determined.

Description

Technical Field

[0001] The present invention relates to the technical field of automatic optical inspection (AOI), and in particular to a wafer defect detection system. Background Art

[0002] Engineers familiar with semiconductor integrated circuit (IC) manufacturing must know that dedicated IC foundry has four main manufacturing processes, namely etching, photo, diffusion, and thin film. In other words, in the process of manufacturing multiple IC chips on a wafer, these four manufacturing processes will be used repeatedly until an electronic circuit containing multiple active components (i.e., transistors) and multiple passive components is implemented in each IC chip.

[0003] It is worth noting that after any process of etching, yellow light, diffusion, or thin film is completed, the wafer must undergo defect inspection by an automatic optical inspection (AOI) device before being transferred to the next process. For example, Taiwan Patent No. I713130 ​​discloses a system for online inspection of semiconductor chips, which includes: a conveyor, a camera, and a processor, wherein the conveyor is used to transport a wafer from a processing station to an inspection station so that the camera faces the wafer to capture at least one wafer image. The processor is used to process the wafer image to determine whether the wafer has surface defects. The defects are, for example: line widths that do not meet standards and / or particles that can be used as killer defects.

[0004] Unfortunately, the conventional AOI still shows some deficiencies in detecting wafer scratches. In view of this, the inventor of the present case made great efforts to research and create, and finally developed a lead-free metal halide memristor for wafer defect detection system of the present invention. Summary of the invention

[0005] The first object of the present invention is to provide a wafer defect detection system for realizing scratch detection on a wafer by utilizing the total reflection principle.

[0006] In order to achieve the first objective of the present invention, a first embodiment of the wafer defect detection system is provided, which includes:

[0007] A line of light source is disposed above the wafer;

[0008] a camera, disposed above the wafer and facing the wafer; and

[0009] an electronic device coupled to the camera and the line light source;

[0010] The electronic device is configured to perform the following functions:

[0011] The line light source is controlled to provide a detection light to be incident on a surface of an edge of a wafer, wherein an angle between the detection light and the surface of the wafer is in a range of 45° to 90°, so that the detection light travels inside the wafer according to the total reflection principle after being incident on the wafer; wherein, in the case of encountering a crack, a portion of the detection light passes through the crack and is emitted from the surface of the wafer;

[0012] Controlling the camera to photograph the wafer, thereby obtaining a wafer image including at least one defect feature; wherein the detection light is emitted from a defect position on the surface of the wafer, and the defect feature corresponds to the defect position in the wafer image; and

[0013] The wafer image is compared with a reference wafer image to identify the at least one defect feature.

[0014] According to an embodiment of the present invention, the defect feature is a wafer scratch.

[0015] The second object of the present invention is to provide a wafer defect detection system for detecting foreign particles and / or etching residues on the surface of a wafer by utilizing the total reflection principle.

[0016] In order to achieve the second objective of the present invention, a second embodiment of the wafer defect detection system is provided, which includes:

[0017] A line of light source is disposed above the wafer;

[0018] a camera, disposed above the wafer and facing the wafer; and

[0019] an electronic device coupled to the camera and the line light source;

[0020] The electronic device is configured to perform the following functions:

[0021] The line light source is controlled to provide a detection light to be incident on the surface of an edge of a wafer, wherein an angle between the detection light and the surface of the wafer is in a range of 45° to 90°, so that after the detection light is incident on the wafer, it travels inside the wafer according to the principle of total reflection, and a portion of the detection light is emitted from the surface of the wafer; wherein, in the case where there are foreign particles and / or etching residues on the surface of the wafer, the detection light emitted from the surface of the wafer will be blocked by the foreign particles and / or the etching residues;

[0022] Controlling the camera to photograph the wafer, thereby obtaining a wafer image including at least one defect feature; wherein the detection light is blocked from a defect position on the wafer surface, and the defect feature corresponds to the defect position in the wafer image; and

[0023] The wafer image is compared with a reference wafer image to identify the at least one defect feature.

[0024] In a feasible embodiment, the wafer defect inspection system of the present invention further includes a rod lens, which is disposed between the line light source and the wafer and is located on an optical path of the inspection light.

[0025] In a feasible embodiment, the wafer defect detection system of the present invention further comprises:

[0026] A first adjustment mechanism connected to the camera and coupled to the electronic device;

[0027] A second adjustment mechanism, pivotally connected to the line light source and coupled to the electronic device;

[0028] In a feasible embodiment, the wafer defect detection system of the present invention further comprises:

[0029] an optical device, disposed between the line light source and the wafer and located on the optical path of the detection light, for guiding the detection light so that the detection light has the angle with the surface of the wafer;

[0030] The optical device is any one selected from the group consisting of a reflector and a polarizer.

[0031] In another feasible embodiment, the wafer defect detection system of the present invention further comprises:

[0032] an optical device, disposed between the line light source and the cylindrical lens and located on the optical path of the detection light, for guiding the detection light so that the detection light is vertically incident on the cylindrical lens;

[0033] The optical device is any one selected from the group consisting of a reflector and a polarizer.

[0034] In a feasible embodiment, the wafer is any one selected from the group consisting of a silicon wafer, a germanium wafer, a gallium arsenide wafer, and a gallium nitride wafer. Moreover, the wafer has any wafer size selected from the group consisting of 3 inches, 4 inches, 6 inches, 8 inches, 12 inches, and 18 inches.

[0035] In a feasible embodiment, the electronic device includes a processor and a memory storing an application program, so that the processor executes the application program by accessing the memory, thereby enabling the plurality of functions.

[0036] In a possible embodiment, the application includes:

[0037] an image processing program, wherein the processor executes the image processing program and is configured to perform an image processing on the wafer image;

[0038] a defect recognition program, wherein the processor executes the defect recognition program and is configured to compare the wafer image with the reference wafer image to identify the at least one defect feature; and

[0039] A control program, wherein the processor executes the control program to control the first adjustment mechanism to adjust a horizontal position and a vertical position of the camera, and controls the second adjustment mechanism to pivot the line light source to adjust the angle. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1A A first stereoscopic diagram of a wafer defect detection system according to the present invention;

[0041] Figure 1B A second stereoscopic diagram of a wafer defect detection system according to the present invention;

[0042] Figure 1C A third stereoscopic diagram of a wafer defect detection system according to the present invention;

[0043] Figure 2 for Figure 1A A block diagram of an electronic device therein;

[0044] Figure 3 for Figure 1A a first side cross-sectional view of a wafer therein;

[0045] Figure 4 for Figure 1A a second side cross-sectional view of the wafer;

[0046] Figure 5 for Figure 1A a third side cross-sectional view of the wafer;

[0047] Figure 6 for Figure 1A a fourth side cross-sectional view of the wafer; and

[0048] Figure 7 for Figure 1A A fifth side cross-sectional view of the wafer.

[0049] Description of reference numerals:

[0050] 1: Wafer defect detection system

[0051] 10: Wafer transfer device

[0052] 11: Linear light source

[0053] 12: Camera

[0054] 13: Electronic devices

[0055] 13P: Processor

[0056] 13M: Memory

[0057] 13M1: Image processing program

[0058] 13M2: Defect Recognition Program

[0059] 13M3: Control Program

[0060] 14: cylindrical lens

[0061] 15: The first adjustment mechanism

[0062] 16: Second adjustment mechanism

[0063] 17: Optical Devices

[0064] 2: Wafer

[0065] 3a: Wafer output device of the first process station

[0066] 3b: Wafer input equipment at the second process station DETAILED DESCRIPTION

[0067] In order to more clearly describe the wafer defect detection system proposed by the present invention, the preferred embodiments of the present invention will be described in detail below with reference to the drawings.

[0068] First embodiment

[0069] Figure 1A , Figure 1B and Figure 1C The first, second and third stereograms of a wafer defect detection system proposed by the present invention are shown. Figure 1A , Figure 1B and Figure 1CAs shown, a wafer transfer device 10 transfers a wafer 2 from a first process site to a second process site, and the wafer defect detection system 1 of the present invention is arranged on a wafer transferring path between the first process site and the second process site, so as to realize scratch detection of a wafer 2 by utilizing the total reflection principle. In practical applications, the wafer 2 can be a silicon wafer, a germanium wafer, a gallium arsenide wafer, or a gallium nitride wafer. Moreover, the size of the wafer 2 can be 3 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 18 inches. In other words, the wafer defect detection system of the present invention can be applied to scratch detection of any type of wafer. It should be understood that component symbol 3a refers to the wafer output device of the first process site, and component symbol 3b refers to the wafer input device of the second process site. To explain in more detail, the wafer defect detection system 1 of the present invention mainly includes: a line light source 11, a camera 12, an electronic device 13 coupled to the camera 12 and the line light source 11, a first adjustment mechanism 15, and a second adjustment mechanism 16, wherein the camera 12 is a line scan camera, and the line light source 11 is disposed above the wafer 2. In addition, the camera 12 is also disposed above the wafer 2 and faces the wafer 2.

[0070] Continue to read Figure 1A , Figure 1B and Figure 1C , and please also refer to Figure 2 , which is Figure 1A. According to the design of the present invention, the electronic device 13 includes a processor 13P and a memory 13M, wherein the memory 13M stores an application program, and the processor 13P executes the application program by accessing the memory 13M. When the application program is executed, the processor 13P is configured to execute multiple functions, wherein the first function is to control the line light source 11 to provide a detection light incident on the surface of the edge of a wafer 2. The second function is to control the first adjustment mechanism 15 to adjust a horizontal position and a vertical position of the camera 12, and control the second adjustment mechanism 16 to pivot the line light source 11 so that the detection light and the surface of the wafer 2 have an angle θ ranging from 45° to 90°. In this configuration, the detection light travels inside the wafer 2 according to the principle of total reflection after being incident on the wafer 2. Furthermore, when encountering a crack, part of the detection light passes through the crack and is emitted from the surface of the wafer 2. To explain in more detail, if the wafer 2 has a wafer scratch, then when the detection light traveling inside the wafer 2 according to the total reflection principle encounters a crack formed by the wafer scratch, part of the detection light passes through the crack and is emitted from the surface of the wafer 2.

[0071] Figure 3 for Figure 1A A first side cross-sectional view of a wafer is shown in FIG. Figure 2 and Figure 3 As shown, the third of the plurality of functions is: controlling the camera 12 to photograph the wafer 2, thereby obtaining a wafer image including at least one defect feature; wherein the detection light is emitted from a defect position on the surface of the wafer 2, and the defect feature corresponds to the defect position in the wafer image. Figure 1A As shown, the first adjustment mechanism 15 is connected to the camera 12 and coupled to the processor 13, so that the camera 12 controls the first adjustment mechanism 15 to adjust a horizontal position and a vertical position of the camera 12, so as to obtain a wafer image of the wafer containing at least one defect feature at an optimal imaging position. In other words, the processor 13 can perform a light intensity distribution analysis on the wafer image to confirm whether the wafer image contains at least one defect feature. The fourth of the multiple functions is: comparing the wafer image with a reference wafer image to identify the at least one defect feature. After completing the light intensity distribution analysis of the wafer image, a detection wafer image with the defect feature position marked can be generated. It should be understood that by comparing the detection wafer image with a reference wafer image, it is possible to identify and determine whether the wafer 2 has a wafer scratch.

[0072] like Figure 2 As shown, in one embodiment, the application includes: an image processing program 13M1, a defect recognition program 13M2 and a control program 13M3, wherein the processor 13P executes the image processing program 13M1, thereby being configured to perform an image processing on the wafer image to obtain the detection wafer image. In addition, the processor 13P executes the defect recognition program 13M2, thereby being configured to compare the detection wafer image with the reference wafer image, thereby identifying the at least one defect feature (i.e., wafer scratch). On the other hand, the processor 13P executes the control program 13M3, thereby controlling the first adjustment mechanism 15, the second adjustment mechanism 16 and / or the camera 12.

[0073] Figure 4 show Figure 1A A second side cross-sectional view of wafer 2 is shown in FIG. Figure 1A and Figure 4 As shown, when the wafer defect detection system 1 of the present invention is actually applied, a rod lens 14 can be further arranged between the line light source 11 and the wafer 2, and located on an optical path of the detection light. According to this arrangement, if the illumination of the detection light emitted by the line light source 11 on the surface of the wafer 2 is 40 lux, after being focused by the rod lens 14, the illumination of the detection light on the surface of the wafer 2 can be increased to 400 lux.

[0074] Figure 5 show Figure 1A The third side cross-sectional view of the wafer 2 is shown in FIG. Figure 1A and Figure 4 As shown, when the wafer defect detection system 1 of the present invention is actually applied, an optical device 17 can be further arranged between the line light source 11 and the wafer 2, and located on an optical path of the detection light. According to this arrangement, the detection light can be guided by the optical device 17 to ensure that the detection light has the angle θ (i.e., 45° to 90°) with the surface of the wafer 2. In a feasible embodiment, the optical device 17 can be a reflector or a polarizer.

[0075] Figure 6 show Figure 1A FIG. 4 is a fourth side cross-sectional view of the wafer 2. Figure 1A and Figure 6As shown, when the wafer defect detection system 1 of the present invention is actually applied, an optical device 17 can be further arranged between the line light source 11 and the wafer 2, and a cylindrical lens 14 can be arranged between the optical device 17 and the wafer 2, and the cylindrical lens 14 and the optical device 17 are both located on an optical path of the detection light. According to this arrangement, the optical device 17 can be used to guide the detection light to ensure that the detection light has the angle θ (i.e., 45° to 90°) with the surface of the wafer 2. At the same time, the cylindrical lens 14 can also be used to focus the detection light onto the surface of the edge of the wafer 2.

[0076] Second embodiment

[0077] Please refer to Figure 1A , Figure 1B , Figure 1C ,as well as Figure 2 , and please also refer to Figure 7 , which shows Figure 1A 5 is a side cross-sectional view of the wafer 2 in the wafer 2. In the second embodiment, the wafer defect detection system 1 of the present invention is disposed on a wafer transferring path between a first process site and a second process site, and is used to detect foreign particles and / or etching residues on the surface of a wafer 2 by using the total reflection principle. Therefore, the second embodiment of the wafer defect detection system 1 of the present invention also includes: a line light source 11, a camera 12, a processor 13 coupled to the camera 12 and the line light source 11, a first adjustment mechanism 15, and a second adjustment mechanism 16.

[0078] like Figure 1A and Figure 7 As shown, the processor 13 controls the line light source 11 to provide a detection light to be incident on the surface of the edge of a wafer 2, so that the detection light and the surface of the wafer 2 have an angle θ ranging from 45° to 90°. After being incident on the wafer 2, the detection light travels inside the wafer 2 according to the principle of total reflection, and part of the detection light will be emitted from the surface of the wafer 2 during the travel. It is worth noting that if there are foreign particles and / or etching residues on the surface of the wafer 2, the light emitted from the surface of the wafer 2 will inevitably be blocked by these substances. In other words, the camera 12 and the processor 13 can determine whether there are foreign particles and / or etching residues on the surface of the wafer 2 by analyzing the intensity distribution of the emitted light. Therefore, if Figure 1A and Figure 7As shown, the processor 13 controls the camera 12 to obtain a wafer image including at least one defect feature, and after processing the wafer image into a detection wafer image, compares the wafer image with a reference wafer image to determine the at least one defect feature (i.e., foreign particles and / or etching residues).

[0079] Thus, the above has completely and clearly described a wafer defect detection system of the present invention. It must be emphasized that the above detailed description is a specific description of a feasible embodiment of the present invention, but the embodiment is not used to limit the patent scope of the present invention. Any equivalent implementation or change that does not deviate from the technical spirit of the present invention should be included in the patent scope of this case.

Claims

1. A wafer defect detection system, characterized in that: It includes: A line of light source is disposed above the wafer; a camera, disposed above the wafer and facing the wafer; as well as an electronic device coupled to the camera and the line light source; The electronic device is configured to perform the following functions: The line light source is controlled to provide a detection light to be incident on a surface of an edge of a wafer, wherein an angle between the detection light and the surface of the wafer is in a range of 45° to 90°, so that the detection light travels inside the wafer according to the total reflection principle after being incident on the wafer; wherein, in the case of encountering a crack, a portion of the detection light passes through the crack and is emitted from the surface of the wafer; Controlling the camera to photograph the wafer, thereby obtaining a wafer image including at least one defect feature; wherein the detection light is emitted from a defect position on the surface of the wafer, and the defect feature corresponds to the defect position in the wafer image; and The wafer image is compared with a reference wafer image to identify the at least one defect feature.

2. The wafer defect detection system according to claim 1, characterized in that: The defect feature is wafer scratch.

3. The wafer defect detection system according to claim 1, characterized in that: The invention further comprises a rod lens, which is arranged between the line light source and the wafer and is located on an optical path of the detection light.

4. The wafer defect detection system according to claim 1, characterized in that: The camera is a line scan camera.

5. The wafer defect detection system according to claim 1, characterized in that: Also includes: a first adjustment mechanism connected to the camera and coupled to the electronic device; and A second adjustment mechanism is pivotally connected to the line light source and coupled to the electronic device.

6. The wafer defect detection system according to claim 1, characterized in that: Also includes: an optical device, disposed between the line light source and the wafer and located on the optical path of the detection light, for guiding the detection light so that the detection light has the angle θ with the surface of the wafer; The optical device is any one selected from the group consisting of a reflector and a polarizer.

7. The wafer defect detection system according to claim 3, characterized in that: Also includes: an optical device, disposed between the line light source and the cylindrical lens and located on the optical path of the detection light, for guiding the detection light so that the detection light is vertically incident on the cylindrical lens; The optical device is any one selected from the group consisting of a reflector and a polarizer.

8. The wafer defect detection system according to claim 1, characterized in that: The wafer is any one selected from the group consisting of silicon wafers, germanium wafers, gallium arsenide wafers, and gallium nitride wafers, and the wafer has any wafer size selected from the group consisting of 3 inches, 4 inches, 6 inches, 8 inches, 12 inches, and 18 inches.

9. The wafer defect detection system according to claim 5, characterized in that: The electronic device includes a processor and a memory storing an application program, so that the processor executes the application program by accessing the memory, thereby enabling the plurality of functions.

10. The wafer defect detection system according to claim 9, characterized in that: The app includes: an image processing program, wherein the processor executes the image processing program and is configured to perform an image processing on the wafer image; a defect recognition program, wherein the processor executes the defect recognition program and is configured to compare the wafer image with the reference wafer image to identify the at least one defect feature; and A control program, wherein the processor executes the control program to control the first adjustment mechanism to adjust a horizontal position and a vertical position of the camera, and controls the second adjustment mechanism to pivot the line light source to adjust the angle.

11. A wafer defect detection system, characterized in that: It includes: A line of light source is disposed above the wafer; a camera, disposed above the wafer and facing the wafer; as well as an electronic device coupled to the camera and the line light source; The electronic device 13 is configured to perform the following functions: The line light source is controlled to provide a detection light to be incident on the surface of an edge of a wafer 2, wherein an angle θ between the detection light and the surface of the wafer is in a range of 45° to 90°, so that after the detection light is incident on the wafer, it travels inside the wafer according to the principle of total reflection, and part of the detection light is emitted from the surface of the wafer; wherein, in the case where there are foreign particles and / or etching residues on the surface of the wafer, the detection light emitted from the surface of the wafer will be blocked by the foreign particles and / or the etching residues; Controlling the camera to photograph the wafer, thereby obtaining a wafer image including at least one defect feature; wherein the detection light is blocked from a defect position on the wafer surface, and the defect feature corresponds to the defect position in the wafer image; and The wafer image is compared with a reference wafer image to identify the at least one defect feature.

12. The wafer defect detection system according to claim 11, characterized in that: The invention further comprises a rod lens, which is arranged between the line light source and the wafer and is located on an optical path of the detection light.

13. The wafer defect detection system according to claim 11, characterized in that: The camera is a line scan camera.

14. The wafer defect detection system according to claim 11, characterized in that: Also includes: a first adjustment mechanism connected to the camera and coupled to the processor; and A second adjustment mechanism is pivotally connected to the line light source and coupled to the processor.

15. The wafer defect detection system according to claim 12, characterized in that: Also includes: an optical device, disposed between the line light source and the wafer and located on the optical path of the detection light, for guiding the detection light so that the detection light has the angle θ with the surface of the wafer; The optical device is any one selected from the group consisting of a reflector and a polarizer.

16. The wafer defect detection system according to claim 12, characterized in that: Also includes: an optical device, disposed between the line light source and the cylindrical lens and located on the optical path of the detection light, for guiding the detection light so that the detection light is vertically incident on the cylindrical lens; The optical device is any one selected from the group consisting of a reflector and a polarizer.

17. The wafer defect detection system according to claim 11, characterized in that: The wafer is any one selected from the group consisting of silicon wafers, germanium wafers, gallium arsenide wafers, and gallium nitride wafers, and the wafer has any wafer size selected from the group consisting of 3 inches, 4 inches, 6 inches, 8 inches, 12 inches, and 18 inches.

18. The wafer defect detection system according to claim 14, characterized in that: The electronic device includes a processor and a memory storing an application program, so that the processor executes the application program by accessing the memory, thereby enabling the plurality of functions.

19. The wafer defect detection system according to claim 18, characterized in that: The app includes: an image processing program, wherein the processor executes the image processing program and is configured to perform an image processing on the wafer image; a defect recognition program, wherein the processor executes the defect recognition program and is configured to compare the wafer image with the reference wafer image to identify the at least one defect feature; and A control program, wherein the processor executes the control program to control the first adjustment mechanism to adjust a horizontal position and a vertical position of the camera, and controls the second adjustment mechanism to pivot the line light source to adjust the angle.

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