Wafer annealing device and wafer annealing process method

Abstract

The invention discloses a wafer annealing device and a wafer annealing process method, relates to the technical field of microelectronics, and can simplify the process flow and improve the distortion improvement precision. According to the first aspect of the embodiment of the invention, the wafer annealing device is provided, and the wafer annealing device comprises a carrying table assembly which comprises a carrying table and a positioning part, the carrying table is used for carrying a wafer, the wafer is provided with a plurality of components, and the carrying table is in contact with the side, away from the components, of the wafer; the pressure applying assembly is used for applying pressure to the wafer carried on the carrying table assembly; the pressure applying assembly comprises a main body structure and a plurality of convex blocks, the convex blocks are connected with the main body structure, the convex blocks are of structures protruding relative to the surface of the main body structure, and the end faces, deviating from the main body structure, of the convex blocks are used for making contact with the surface of the side, deviating from the carrying table, of the wafer; the contact area of the bump and the wafer is not overlapped with the area where the component is located.

Description

Technical Field

[0001] The present application relates to the field of microelectronics technology, and in particular to a wafer annealing device and a wafer annealing process method. Background Art

[0002] At present, in the wafer processing process, when processing larger MEMS (micro-electromechanical) wafers, the internal stress during processing will cause the wafer to deform, resulting in a higher tape-out rate, especially the part near the center of the wafer where the distortion is the most serious. Therefore, process technology improvements for the problem of wafer distortion are urgently needed. However, the existing process methods for improving the distortion problem in the wafer processing process usually have the problems of complex processes and poor precision. Summary of the invention

[0003] The embodiments of the present application provide a wafer annealing device and a wafer annealing process method, which can simplify the process flow and improve the distortion improvement accuracy.

[0004] According to a first aspect of an embodiment of the present application, a wafer annealing device is provided, comprising:

[0005] A carrier assembly, comprising a carrier and a positioning member, wherein the carrier is used to carry a wafer, wherein the wafer is provided with a plurality of components, and the carrier contacts a side of the wafer away from the components;

[0006] A pressure-applying assembly, used for applying pressure to the wafer carried on the stage assembly;

[0007] The pressure-applying assembly includes a main structure and a plurality of bumps, wherein the bumps are connected to the main structure, are structures protruding relative to the surface of the main structure, and the end surfaces of the bumps facing away from the main structure are used to contact the surface of the wafer facing away from the stage;

[0008] The contact area between the bump and the wafer does not overlap with the area where the components are located.

[0009] In some embodiments, the wafer includes a cutting line, and at least a portion of the contact area between the bump and the wafer covers at least a portion of the area where the cutting line is located.

[0010] In some embodiments, the plurality of bumps include a first bump and a second bump, and an orthographic projection of the first bump on the main structure at least partially surrounds an orthographic projection of the second bump on the main structure.

[0011] In some embodiments, the plurality of bumps include a third bump and a second bump, the second bump is at a distance from an edge of the main structure, and a portion of an edge of the third bump is flush with the edge of the main structure.

[0012] In some embodiments, the plurality of bumps include a first sub-bump, a second sub-bump, and a third sub-bump, the orthographic projection area of ​​the first sub-bump on the main structure is a first area, the orthographic projection area of ​​the second sub-bump on the main structure is a second area, and the orthographic projection area of ​​the third sub-bump on the main structure is a third area;

[0013] The first area is larger than the second area, and the third area is larger than the second area;

[0014] The first sub-bump is farther away from the edge of the main structure than the second sub-bump, and the third sub-bump is closer to the edge of the main structure than the second sub-bump.

[0015] In some embodiments, the carrier includes a groove, the wafer is used to be at least partially embedded in the groove, and the groove is used to limit the position of the wafer; and / or,

[0016] The main structure is provided with a positioning hole, and the positioning hole passes through the main structure.

[0017] In some embodiments, the stage assembly and the pressure assembly are arranged in a one-to-many manner; or,

[0018] The applying components and the carrier components are arranged in a one-to-many manner.

[0019] In some embodiments, a plurality of the bumps are arranged in an array; and / or,

[0020] The orthographic projection shape of the protrusion on the main structure includes a rectangle, a circle or an ellipse; and / or,

[0021] The surface of the carrier is a plane, and the contact surface between the bump and the wafer is a plane; and / or,

[0022] The materials of the carrier, the main structure and the bump include at least one of metal and ceramic; and / or,

[0023] A silicon carbide film is provided on the surface of at least one of the bump, the stage and the positioning member; and / or,

[0024] The ratio of the weight of the main structure to the weight of the carrier is greater than 100.

[0025] A second aspect of the embodiment of the present application provides a wafer annealing process method, which is applied to the wafer annealing device as described in the first aspect, and the method includes:

[0026] Placing the wafer on a stage assembly of a wafer annealing device, wherein a side of the wafer facing away from the components contacts the stage, and the positioning member limits the position of the wafer;

[0027] Controlling the pressure-applying assembly to apply pressure to the wafer so that the wafer is deformed under the pressure, wherein an end of the protrusion of the pressure-applying assembly away from the main structure contacts a surface of the wafer on a side away from the carrier;

[0028] The wafer is heated and annealed by the wafer annealing device, or,

[0029] The wafer annealing device holding the wafer is placed in an annealing furnace.

[0030] In some embodiments, before the pressure-applying component is controlled to apply pressure to the wafer, the process includes:

[0031] Preheating the wafer by the stage, wherein the preheating temperature is lower than the heating annealing temperature;

[0032] and / or,

[0033] In the case where the main structure is provided with a positioning hole, before the control pressure-applying assembly applies pressure to the wafer, the control pressure-applying assembly comprises:

[0034] The main structure, the stage and the wafer are optically positioned by using the positioning holes.

[0035] The wafer annealing device and method provided in the embodiment of the present application, by setting a stage assembly to carry the wafer, using the bump of the pressure assembly to contact the wafer for pressure transmission, so that the pressure assembly applies pressure to the wafer, and can squeeze and deform the wafer that has been distorted by other process steps to correct the shape of the distorted wafer. The setting of the bump can avoid damage to the components of the wafer. In addition, the shape correction of the distorted wafer and the annealing process are integrated together to simplify the process flow. In addition, by using the pressure assembly and the stage assembly together, the shape correction of the distorted wafer can be more accurate by mechanical means, and the wafer annealing device of the present application can also be reused without causing waste of resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic structural diagram of a wafer annealing device provided in an embodiment of the present application;

[0037] Figure 2 A schematic diagram of the working principle of a wafer annealing device provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram of the working principle of another wafer annealing device provided in an embodiment of the present application;

[0039] Figure 4 A schematic structural diagram of a pressure-applying assembly provided in an embodiment of the present application;

[0040] Figure 5 A schematic structural diagram of another pressure-applying assembly provided in an embodiment of the present application;

[0041] Figure 6 A schematic structural diagram of another pressure-applying assembly provided in an embodiment of the present application;

[0042] Figure 7 A schematic structural diagram of another pressure-applying assembly provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of the working principle of a wafer annealing device provided in an embodiment of the present application;

[0044] Fig. 9 A schematic structural diagram of another wafer annealing device provided in an embodiment of the present application;

[0045] Fig.10 A schematic structural diagram of a carrier assembly provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification are described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0047] In this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. The term "more than two" includes two or more than two situations.

[0048] Usually, when processing smaller MEMS wafers, such as wafers below 8 inches, since the wafers are relatively small, the internal stress distortion during processing is relatively small, so in most cases no special method for dealing with internal stress is required. When the wafer becomes larger (more than eight inches), the internal stress during processing will cause the wafer to deform, resulting in a higher tape-out rate, especially the part near the center of the wafer where the distortion is most serious. Therefore, in order to solve the problem of wafer distortion, a layer of metal can be plated on the back of the wafer to form a bimetallic layer, so that the internal stress of the metal on the surface when heated offsets the internal stress of the wafer during processing, and a micro-architecture that can control the shape of the wafer is formed on the back of the wafer. These micro-architectures are used to solve the internal stress problem. When the distortion is serious, multiple heat treatments are required after the processing to ensure that the internal force of the wafer is released once after every few steps during processing. However, this method is complicated and requires additional resources for processes such as electroplating that will not directly enter the product. It also requires parameter calibration according to the process and different products, which is time-consuming and labor-intensive. In addition, the distortion can be improved by using microstructures, but the microstructures need to be measured and calibrated for individual chips. After calibration, the microstructure patterns need to be used separately and cannot be reused, which still requires a lot of additional resources.

[0049] Figure 1 The schematic structure diagram of a wafer annealing device provided in an embodiment of the present application. Figure 1 As shown, in the first aspect of the embodiment of the present application, a wafer annealing device is provided, comprising: a stage assembly 100 and a pressure assembly 200; illustratively, the stage assembly 100 may be fixed or movable; the pressure assembly 200 is movable relative to the stage assembly 100. illustratively, the pressure assembly 200 may be moved under the drive of a driving member, and the driving member driving the pressure assembly 200 may include a spring, a pneumatic pipeline or a hydraulic pipeline to control its movement or apply pressure.

[0050] Exemplary, reference Figure 1 The stage assembly 100 includes a stage 110 and a positioning member 120. The stage 110 is used to carry a wafer 101. The wafer 101 is provided with a plurality of components. The stage contacts the side of the wafer 101 away from the components. The positioning member 120 can be used to position and limit the wafer 101. The positioning member 120 can include a limiting column 121 and a fixing member 122. The limiting column 121 can be fixed, and the fixing member 122 can be moved to clamp the wafer after the wafer 101 is placed to fix the wafer 101. The components on the wafer 101 can be semiconductor devices and capacitors integrated on the wafer 101.

[0051] Exemplary, reference Figure 1The pressure-applying assembly 200 is used to apply pressure to the wafer 101 carried on the stage assembly 100; the pressure-applying assembly 200 includes a main structure 210 and a plurality of bumps 220, the bumps 220 are connected to the main structure 210, the bumps 220 are structures protruding relative to the surface of the main structure 210, and the end surface of the bumps 220 away from the main structure 210 is used to contact the side surface of the wafer 101 away from the stage 110. The contact area between the bumps 220 and the wafer 101 does not overlap with the area where the components are located, so as to avoid the contact between the bumps 220 and the wafer 101 to damage the components.

[0052] For example, when the pressure-applying assembly 200 applies pressure to the wafer 101 , the bumps 220 support the wafer 101 , so that the shape of the distorted wafer 101 can be corrected, thereby improving the wafer distortion problem.

[0053] Exemplarily, the pressure applying method of the pressure applying assembly 200 may be to use an external force to act on the main structure 210 , and then apply the bump 220 on the wafer 101 .

[0054] For example, the weight of the main structure 210 and the bumps 220 may be used to apply pressure to the wafer 101 .

[0055] For example, the weight of the main structure 210 may be several hundred or several thousand times the weight of the carrier 110 of the carrier assembly. For example, the ratio of the weight of the main structure 210 to the weight of the carrier 110 is greater than 100, and may be 200, 300, 150, 550, or 600, etc.

[0056] Figure 2 A schematic diagram of the working principle of a wafer annealing device provided in an embodiment of the present application. For example, refer to Figure 2 The chip 101 is a chip with a downward arc distortion. After the pressure component 200 applies pressure, the main structure 210 is pressed toward the lens 101, the bump 220 contacts the chip 101, and the chip contacts the carrier 110, so that the chip 101 can be flattened and the arc distortion can be reduced.

[0057] Figure 3 Another schematic diagram of the working principle of a wafer annealing device provided in an embodiment of the present application. Figure 3 The chip 101 is an upper arc-shaped twisted chip. After the pressure of the pressure component 200, the main structure 210 is pressed toward the lens 101, the bump 220 contacts the chip 101, and the chip contacts the carrier 110, which can flatten the chip 101 and reduce the arc-shaped twist.

[0058] For example, the lens 101 can be heated and annealed during the pressing process by utilizing the heat conduction of the stage assembly 100 and the pressure assembly 200. That is, by performing thermal annealing during the deformation correction process, the deformation correction and thermal annealing processes can be combined into one process, thus simplifying the process flow. Thermal annealing during the deformation correction process can enhance the effect and efficiency of the deformation correction.

[0059] Exemplarily, a wafer annealing device may be placed in a thermal annealing furnace to perform thermal annealing on the wafer. Thermal annealing during the deformation correction process may enhance the effect and efficiency of the deformation correction and may also simplify the process flow.

[0060] The wafer annealing device provided in the embodiment of the present application, by setting a stage assembly 200 to carry the wafer 101, using the bump of the pressure assembly 200 to contact the wafer 101 for pressure conduction, so that the pressure assembly 200 applies pressure to the wafer 101, and can squeeze and deform the wafer that has been distorted by other process steps to correct the shape of the distorted wafer. The setting of the bump 220 can avoid damage to the components of the wafer. In addition, the shape correction of the distorted wafer and the annealing process are integrated together, which can simplify the process flow. In addition, by using the pressure assembly 200 and the stage assembly 100 in combination, the shape correction of the distorted wafer can be more accurate by mechanical means, and the wafer annealing device of the present application can also be reused without causing waste of resources.

[0061] In some embodiments, a plurality of bumps are arranged in an array, and the array arrangement is more uniform, which can uniformly improve wafer warpage.

[0062] In some embodiments, the orthographic projection shape of the bump on the main structure includes a rectangle, a circle, or an ellipse. The shape of the bump can be selected according to the processing technology, and the bump can be an integrally formed structure with the main structure.

[0063] In some embodiments, the surface of the stage is a plane, and the contact surface between the bump and the wafer is a plane. The plane can be obtained by grinding after turning, or can be obtained directly by grinding. The plane can better protect the wafer, and the surface contact can exert greater pressure on the wafer.

[0064] In some embodiments, the material of the carrier, the main structure and the bump may include at least one of metal and ceramic. Metal and ceramic can conduct heat better, have higher hardness and are not easily deformed. The thermal expansion coefficient of ceramic and metal is close to that of single crystal silicon, which can be consistent with the thermal expansion degree of the wafer, and can ensure better flatness of the base position of the bump.

[0065] In some embodiments, the surface of the bump is provided with a silicon carbide thin film coating, and the surface of the carrier is provided with a silicon carbide thin film. The thermal expansion coefficient of silicon carbide is close to that of single crystal silicon, and a good flatness can be maintained. The positioning piece can be made of single crystal silicon, and the surface of the single crystal silicon can be attached with silicon carbide, so that the thermal expansion coefficient of the positioning piece and the wafer can be relatively consistent, and the wafer positioning can be kept without deviation during thermal annealing.

[0066] In some embodiments, the wafer includes a cutting line, and at least a portion of the contact area between the bump and the wafer covers at least a portion of the area where the cutting line is located. The cutting line is used to cut a large wafer into chip units. The cutting line can be a virtual boundary or a physical line. The bump corresponds to the position of the cutting line, and the cutting line space can be used to contact the bump for shape correction, which does not affect the normal use of the lens, and there is no need to set a separate blank area to avoid the bump.

[0067] In some embodiments, the plurality of bumps include a first bump and a second bump, and an orthographic projection of the first bump on the main structure at least partially surrounds an orthographic projection of the second bump on the main structure.

[0068] Exemplarily, the first bump may be an annular bump, which may apply pressure to the edge of the corresponding wafer. The first bump may also be a semi-annular or arc-shaped bump. More pressure contacts may be provided for the edge of the wafer, which may further improve the effect of distortion correction.

[0069] Figure 4 A schematic structural diagram of a pressure-applying assembly provided in an embodiment of the present application. Figure 4 The first bump 221 surrounds the second bump 222 , the first bump 221 is close to the edge of the main structure, and the second bump 222 is arranged in the middle area of ​​the main structure 210 .

[0070] Figure 5 A schematic structural diagram of another pressure-applying assembly provided in an embodiment of the present application. Figure 5 There are two first bumps 221, and there is a gap between the two first bumps 221. The setting of the gap can avoid pressure concentration on the edge of the wafer and provide a space for partial pressure release. The semi-annular first bump 221 can provide pressure for the edge of the wafer.

[0071] Figure 6 A schematic structural diagram of another pressure-applying assembly provided in an embodiment of the present application. Figure 6 The number of the first bumps 221 is 4. The first bumps 221 are arc-shaped and distributed at the edge of the main structure 210, which can make the pressure on the wafer more uniform.

[0072] In some embodiments, the plurality of bumps include a third bump and a second bump, the second bump is spaced apart from an edge of the main structure, and a portion of an edge of the third bump is flush with the edge of the main structure, which can provide better contact pressure for the edge of the wafer.

[0073] In some embodiments, the plurality of bumps include a first sub-bump, a second sub-bump, and a third sub-bump, the orthographic projection area of ​​the first sub-bump on the main structure is a first area, the orthographic projection area of ​​the second sub-bump on the main structure is a second area, and the orthographic projection area of ​​the third sub-bump on the main structure is a third area; the first area is greater than the second area, and the third area is greater than the second area; the first sub-bump is away from the edge of the main structure relative to the second sub-bump, and the third sub-bump is close to the edge of the main structure relative to the second sub-bump.

[0074] Figure 7 A schematic structural diagram of another pressure-applying assembly provided in an embodiment of the present application. Figure 7 , the first sub-bump 223 is located in the middle area of ​​the main structure, the second sub-bump 224 is located between the center and the edge area of ​​the main structure, the third sub-bump 225 is located at the edge of the main structure, the area of ​​the third sub-bump 225 used to contact the wafer is larger than the area of ​​the second sub-bump 224 used to contact the wafer, and the area of ​​the first sub-bump 223 used to contact the wafer is larger than the area of ​​the second sub-bump 224 used to contact the wafer. The third sub-bump 225 can be used as a third bump, and part of the edge of the third sub-bump 225 overlaps with the edge of the main structure. The middle contact area and the edge contact area are larger, which can provide better pressure uniformity.

[0075] For example, it is necessary to ensure that there are enough contact points on the corners and center of the wafer to ensure that both the upper arc and the lower concave state can have good contact points with the silicon wafer. The corners of the contacts should be broken to ensure that the wafer will not be broken by excessive single-point contact pressure when contacting the wafer at the beginning. If the wafer is still too distorted or still easy to break, the wafer should be preheated and tried again, or more contacts should be used.

[0076] Exemplarily, the annealing process varies according to the specific process. The annealing temperature is maintained between 500-1150° C. until the distortion is reduced to an acceptable range and then cooled to complete the process.

[0077] In some embodiments, the carrier includes a groove, and the chip is used to be at least partially embedded in the groove, and the groove is used to limit the position of the chip.

[0078] Figure 8 A schematic diagram of the working principle of a wafer annealing device provided in an embodiment of the present application. For example, Figure 8As shown, the linear guide 300 can be used to directly place the wafer 101 in the groove 130, and the stage assembly also includes a matching protrusion 230, which matches the shape of the groove 130 to ensure that the bump 220 can contact the wafer 101. In order to ensure the positioning relative to the wafer 101, the stage should be made of single crystal silicon with silicon carbide attached to the surface to achieve a similar thermal expansion coefficient so that there will be no positional deviation during annealing. The weight of the pressure assembly should be 100 to 1,000 times the weight of all the wafers being processed to ensure that the wafer can be flattened relatively quickly during the annealing process, but the wafer is not crushed during the initial positioning.

[0079] In some embodiments, the main structure is provided with a positioning hole, and the positioning hole passes through the main structure.

[0080] Fig. 9 A schematic structural diagram of another wafer annealing device provided in an embodiment of the present application. Fig. 9 As shown, the main structure 210 is provided with a positioning hole 240, which can be set at the center of the main structure 210 and penetrate the main structure 210. The wafer and the main structure 210 can be optically positioned through the positioning hole 240, and optical positioning can be performed along the central axis 201 of the main structure 210 through the positioning hole 240, which can further position the wafer and improve the accuracy of wafer deformation correction.

[0081] In some embodiments, the stage assembly and the pressure assembly are arranged one-to-many, and multiple wafers can be placed on the stage assembly at one time, and pressure deformation correction can be performed using one pressure assembly. The stage can be used to limit and position the wafers through grooves or other forms. The annealing process of multiple wafers can be performed at one time, saving production capacity.

[0082] In some embodiments, the pressure applying component and the stage component are arranged one-to-many. Multiple wafers can be placed on multiple stage components, and a pressure applying component can be used to simultaneously apply pressure to multiple wafers. The annealing process of multiple wafers can be performed at one time, saving production capacity.

[0083] Fig.10 A schematic structural diagram of a stage assembly provided in an embodiment of the present application. For example, refer to Fig.10 The wafer is a 12-inch silicon wafer, but after the magnetron sputtering process, the silicon wafer will be distorted and deviate from the plane by about 300um. The next photolithography process requires that it should not deviate from the plane by more than 5um. Due to the large throughput of the production environment, multiple silicon wafers need to be processed at one time. Fig.10 For the stage assembly, since the silicon wafer is large, even if the arc is distorted, the reduction in the external geometry of the silicon wafer will only reduce the width by less than one millimeter, which is completely within the range of mechanical control and does not require optical calibration.

[0084] Exemplarily, in order to ensure the flatness of the bottom, the device should be composed of two parts, the lower half is a large piece of completely flat material, and the upper half is a positioning system with positioning shapes.

[0085] A second aspect of the embodiment of the present application provides a wafer annealing process method, which is applied to the wafer annealing device as described in the first aspect, and the method includes:

[0086] Step 1: placing the wafer on a carrier assembly of a wafer annealing device, wherein a side of the wafer facing away from the components contacts the carrier, and a positioning member limits the position of the wafer.

[0087] Exemplarily, step one may be positioning and fixing the wafer.

[0088] Step 2: Control the pressure-applying component to apply pressure to the wafer so that the wafer is deformed under the pressure, wherein one end of the protrusion of the pressure-applying component away from the main structure contacts the surface of the wafer on the side away from the carrier.

[0089] For example, when the pressure-applying assembly 200 applies pressure to the wafer 101 , the bumps 220 support the wafer 101 , so that the shape of the distorted wafer 101 can be corrected, thereby improving the wafer distortion problem.

[0090] Exemplarily, the pressure applying method of the pressure applying assembly 200 may be to use an external force to act on the main structure 210 , and then apply the bump 220 on the wafer 101 .

[0091] Step 3: Heat and anneal the wafer through the wafer annealing device. For example, the lens 101 can be heated and annealed during the pressure application process by utilizing the heat conduction of the stage assembly 100 and the pressure application assembly 200. That is, thermal annealing is performed during the deformation correction process, and the deformation correction and thermal annealing processes can be combined into one process to simplify the process flow. Thermal annealing during the deformation correction process can enhance the effect and efficiency of the deformation correction.

[0092] or,

[0093] Step 4: Place the wafer annealing device holding the wafer in an annealing furnace. For example, the wafer annealing device can be placed in a thermal annealing furnace to perform thermal annealing on the wafer. Thermal annealing during the deformation correction process can enhance the effect and efficiency of the deformation correction and simplify the process flow.

[0094] The wafer annealing method provided in the embodiment of the present application, by setting a stage assembly 200 to carry the wafer 101, using the bump of the pressure assembly 200 to contact the wafer 101 for pressure conduction, so that the pressure assembly 200 applies pressure to the wafer 101, and can squeeze and deform the wafer that has been distorted by other process steps to correct the shape of the distorted wafer. The setting of the bump 220 can avoid damage to the components of the wafer. In addition, the shape correction of the distorted wafer and the annealing process are integrated together, which can simplify the process flow. In addition, by using the pressure assembly 200 and the stage assembly 100 in combination, the shape correction of the distorted wafer can be more accurate by mechanical means, and the wafer annealing device of the present application can also be reused without causing waste of resources.

[0095] In some embodiments, before step 2, the following may be included:

[0096] The wafer is preheated by the stage, and the preheating temperature is lower than the heating annealing temperature.

[0097] In some embodiments, when the main structure is provided with a positioning hole, before controlling the pressure-applying assembly to apply pressure to the wafer, the steps include:

[0098] The main structure, the carrier and the wafer are optically positioned by using the positioning holes.

[0099] The wafer annealing method provided in the embodiment of the present application, the peripheral device is generally divided into two parts, the plane of the bottom stage assembly has a standard flatness, and the pressure component is used to apply pressure perpendicular to the plane direction when contacting the warped wafer. There is a device for fixing the wafer on the surface of the bottom stage. The pressure component is a removable weight, and there is a protrusion at the bottom of the main structure corresponding to the existing dividing line on the wafer. If a more controllable use is required, the weight can be controlled by a spring or a pneumatic tube. Both the upper and lower surfaces are made of metal or ceramic or other materials that can withstand high temperatures (above 1100°C), and their thermal expansion coefficient is as close to that of single crystal silicon as possible. The contacts at the bottom of the weight should also have extremely high coplanarity with each other, and can be polished after turning, or a flat surface can be polished first, and then the non-contact point part can be turned. The initial positioning of the wafer with a small amount of removal is achieved by a mechanical device, and there can be many specific applications. After the initial positioning, the weight can be accurately calibrated when it is placed above the wafer. A small hole is drilled in the center of the weight, which can be used for calibration of the optical and calibration indications on the wafer. The specific calibration device may vary depending on the situation. After calibration, a weight is placed on the wafer for annealing.

[0100] In addition, after the wafer is placed, the weight should have only a small contact point with the wafer, and the contact point should be located within the dividing line so as not to damage the device on the wafer due to contact. During the annealing process, the wafer is pressed by the weight and sticks to the bottom plane at high temperature, and then returns to a flat state after bonding. At the same time, since the internal stress is released due to high temperature, the wafer should not be distorted after annealing. The cooling time should be appropriate according to the process and the degree of distortion. When the degree of distortion of the wafer reaches an acceptable range, the wafer can be cooled and the process ends. If the degree of distortion is too large and cannot be solved by annealing, you can consider increasing the number of contact points to reduce their spacing.

[0101] The present invention provides a method for mechanically controlling the deformation of wafers larger than 8 inches during heating and annealing. The bending of the wafer when heated is limited by mechanically supporting the front and back sides of the wafer, and the internal stress caused by the force on the side of the wafer is also avoided. In this process, the processed wafer is clamped between two high-temperature (500-1150°C) non-deformable metal or ceramic devices; the contact point of the clamping device can contact the wafer at, but not limited to, the wafer dividing line; it can be used in dry or wet etching process processing; the wafer can be initially positioned by a mechanical device; the wafer can be optically calibrated using the existing calibration mark on the wafer.

[0102] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0103] Although the preferred embodiments of this specification have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this specification.

[0104] Obviously, those skilled in the art can make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalents, this specification is also intended to include these modifications and variations.

Claims

1. A wafer annealing device, characterized in that: include: A carrier assembly, comprising a carrier and a positioning member, wherein the carrier is used to carry a wafer, wherein the wafer is provided with a plurality of components, and the carrier contacts a side of the wafer away from the components; A pressure-applying assembly, used for applying pressure to the wafer carried on the stage assembly; The pressure-applying assembly includes a main structure and a plurality of bumps, wherein the bumps are connected to the main structure, are structures protruding relative to the surface of the main structure, and the end surfaces of the bumps facing away from the main structure are used to contact the surface of the wafer facing away from the stage; The contact area between the bump and the wafer does not overlap with the area where the components are located.

2. The wafer annealing device according to claim 1, characterized in that: The wafer comprises a cutting line, and at least a portion of the contact area between the bump and the wafer covers at least a portion of the area where the cutting line is located.

3. The wafer annealing device according to claim 1, characterized in that: The plurality of bumps include a first bump and a second bump, wherein an orthographic projection of the first bump on the main structure at least partially surrounds an orthographic projection of the second bump on the main structure.

4. The wafer annealing device according to claim 1, characterized in that: The plurality of bumps include a third bump and a second bump, the second bump is spaced apart from an edge of the main structure, and a portion of an edge of the third bump is flush with the edge of the main structure.

5. The wafer annealing device according to claim 1, characterized in that: The plurality of bumps include a first sub-bump, a second sub-bump and a third sub-bump, the orthographic projection area of ​​the first sub-bump on the main structure is a first area, the orthographic projection area of ​​the second sub-bump on the main structure is a second area, and the orthographic projection area of ​​the third sub-bump on the main structure is a third area; The first area is larger than the second area, and the third area is larger than the second area; The first sub-bump is farther away from the edge of the main structure than the second sub-bump, and the third sub-bump is closer to the edge of the main structure than the second sub-bump.

6. The wafer annealing device according to any one of claims 1 to 5, characterized in that: The carrier comprises a groove, the wafer is used to be at least partially embedded in the groove, and the groove is used to limit the position of the wafer; and / or, The main structure is provided with a positioning hole, and the positioning hole passes through the main structure.

7. The wafer annealing device according to any one of claims 1 to 5, characterized in that: The platform assembly and the pressure assembly are arranged in a one-to-many manner; or, The applying components and the carrier components are arranged in a one-to-many manner.

8. The wafer annealing device according to claim 1, characterized in that: A plurality of said bumps are arranged in an array; and / or, The orthographic projection shape of the protrusion on the main structure includes a rectangle, a circle or an ellipse; and / or, The surface of the carrier is a plane, and the contact surface between the bump and the wafer is a plane; and / or, The materials of the carrier, the main structure and the bump include at least one of metal and ceramic; and / or, A silicon carbide film is provided on the surface of at least one of the bump, the stage and the positioning member; and / or, The ratio of the weight of the main structure to the weight of the carrier is greater than 100.

9. A wafer annealing process method, characterized in that: Applied to the wafer annealing device according to any one of claims 1 to 8, the method comprising: Placing the wafer on a stage assembly of a wafer annealing device, wherein a side of the wafer facing away from the components contacts the stage, and the positioning member limits the position of the wafer; Controlling the pressure-applying assembly to apply pressure to the wafer so that the wafer is deformed under the pressure, wherein an end of the protrusion of the pressure-applying assembly away from the main structure contacts a surface of the wafer on a side away from the carrier; The wafer is heated and annealed by the wafer annealing device, or, The wafer annealing device holding the wafer is placed in an annealing furnace.

10. The wafer annealing process according to claim 9, characterized in that: Before the pressure-applying component is controlled to apply pressure to the wafer, the method includes: Preheating the wafer by the stage, wherein the preheating temperature is lower than the heating annealing temperature; and / or, In the case where the main structure is provided with a positioning hole, before the control pressure-applying assembly applies pressure to the wafer, the control pressure-applying assembly comprises: The main structure, the stage and the wafer are optically positioned by using the positioning holes.

Images