STI structure based on ONO type three-layer Liner and manufacturing method thereof

Abstract

The invention provides an STI (Shallow Trench Isolation) structure based on an ONO type three-layer Liner and a manufacturing method thereof, the STI structure comprises a silicon substrate arranged at the bottom and a U-shaped STI groove arranged in the silicon substrate, and an ISSG SiO2 bottom layer, a SiNx middle layer and an ISSG SiO2 top layer are sequentially arranged in the STI groove in a covering manner and are filled through an HDP SiO2 layer. According to the STI structure based on the ONO type three-layer Liner and the manufacturing method of the STI structure, the SiO2 bottom layer grows through ISSG, so that the uniformity of the top corner and the bottom corner of the STI groove is improved, undercutting of SiNx during oxidation is avoided, and etching damage of the STI groove is better repaired; the SiNx middle layer deposited by the LPCVD process has stronger insulation capability, and can reduce or even completely counteract accumulation of subsequent thicker HDP SiO2 pressure stress; siNx is re-oxidized by adopting ISSG, so that the SiO2 top layer has fewer defects and a better isolation effect, and the etching damage of the STI trench can be further repaired through ISSG annealing.

Description

Technical Field

[0001] The invention belongs to the technical field of silicon microelectronics, and in particular relates to an STI structure based on an ONO-type three-layer Liner and a manufacturing method thereof. Background Art

[0002] The development trend of integrated circuit technology is that the device feature size continues to shrink along Moore's Law. The isolation between active areas (AA) of CMOS processes with feature sizes above 0.35μm uses the local oxidation of silicon (LOCOS) isolation process. Due to the bird beak effect of field oxygen erosion and the lateral diffusion of field injection, the LOCOS process is greatly limited. In CMOS processes with feature sizes of 0.25μm and below, the LOCOS process is replaced by shallow trench isolation (STI) with smaller size and better isolation effect. When etching the STI trench, a large number of etching defects will be generated on the sidewalls of the STI trench, and the sharp top and bottom angles of the STI trench will also cause parasitic leakage and reduce the isolation characteristics of the STI. As an improvement measure, a linear oxide layer (liner oxide) is grown by thermal oxidation before filling the STI trench with high density plasma oxide (HDP SiO2). First, liner oxide rounds the sharp top and bottom corners of the STI trench, increasing the contact surface; second, liner oxide avoids the thinning effect of SiO2 at the top and bottom corners; third, liner oxide repairs the etching damage of the STI trench; and finally, liner oxide also serves as a buffer layer during HDP SiO2 deposition. As the device feature size decreases, higher and higher requirements are placed on the isolation characteristics and stress distribution of STI.

[0003] In-Situ Steam Generation (ISSG) is a new type of low-pressure rapid oxidation technology. A small amount of H2 is introduced into the O2 atmosphere as a catalyst. A chemical reaction similar to combustion occurs on the surface of the silicon wafer at high temperature, generating a large number of gas-phase active free radicals mainly composed of atomic oxygen. Due to the strong oxidizing effect of atomic oxygen, the resulting SiO2 layer has fewer defects and interface state density than ordinary thermal oxide layers (Thermal oxide), a smooth silicon-oxygen interface, and a relatively high film quality. In addition, ISSG can x The layer is then oxidized to a SiO2 layer, forming an upper SiO2 layer / lower SiN x composite membrane.

[0004] Therefore, it is necessary to provide an STI structure based on an ONO-type three-layer liner to improve the isolation characteristics of the STI and reduce the stress accumulation of the STI filler. Summary of the invention

[0005] The present invention provides an STI structure based on an ONO-type three-layer Liner and a manufacturing method thereof, thereby improving the isolation characteristics and reliability of the STI structure.

[0006] The present invention provides an STI structure based on an ONO-type three-layer liner, comprising a silicon substrate arranged at the bottom, a U-shaped STI groove arranged in the silicon substrate, the ISSG SiO2 bottom layer, the SiN x The middle layer and the ISSG SiO2 top layer are sequentially covered in the STI trench and filled with the HDP SiO2 layer.

[0007] Preferably, the thickness of the ISSG SiO2 bottom layer is S N x The thickness of the middle layer is The thickness of the top layer of ISSGSiO2 is

[0008] Preferably, for the STI process of CMOS with a feature size of less than 90nm, the HDP SiO2 layer includes a first HDP SiO2 layer, a second HDP SiO2 layer and a third HDP SiO2 layer formed in sequence; for the STI process of CMOS with a feature size of more than 90nm, the HDP SiO2 layer is a single layer.

[0009] The present invention also provides a method for manufacturing an STI structure based on an ONO-type three-layer Liner, comprising the following steps:

[0010] Step 1, growth of SiO2 pad oxygen and Si3N4 barrier layer: oxidation growth of SiO2 pad oxygen on the original silicon wafer, and low pressure chemical vapor deposition (LPCVD) deposition growth of Si3N4 barrier layer;

[0011] Step 2, STI trench etching: The active area is defined by photolithography, the Si3N4 barrier layer is dry-etched, and then the STI trench is etched on the silicon surface, and the resist is removed after etching;

[0012] Step 3, growing SiO2 bottom layer by ISSG process: rounding the sharp top and bottom angles of STI trenches, and repairing STI trench etching damage by ISSG annealing;

[0013] Step 4: LPCVD process to deposit SiN x Middle layer: SiN x The middle layer has strong insulation ability and can reduce or even completely offset the accumulation of subsequent HDP SiO2 compressive stress;

[0014] Step 5, ISSG to SiN x Re-oxidation realizes the SiO2 top layer: forming an ONO three-layer liner with better isolation effect, and ISSG annealing further repairs the STI trench etching damage;

[0015] Step 6, STI trench filling: deposit the first HDP SiO2 layer by HDP process, and then rinse with BHF (40 40% NH4F: 1 49% HF) for planarization; deposit the second HDP SiO2 layer by HDP process, and then rinse with BHF for planarization; deposit the third HDP SiO2 layer by HDP process to complete the filling of STI trenches;

[0016] Step 7, annealing the HDP SiO2 layer: annealing the HDP SiO2 layer at high temperature to improve the compactness of the HDP SiO2 and eliminate plasma damage to the HDP SiO2;

[0017] Step 8, Chemical Mechanical Polishing (CMP) of the HDP SiO2 layer and the ONO three-layer Liner: Use CMP to polish away the HDP SiO2, ONO three-layer Liner and part of the Si3N4 barrier layer on the Si3N4 barrier layer, and the CMP finally stops on the remaining Si3N4 barrier layer;

[0018] Step 9, complete stripping of Si3N4 barrier layer: First rinse off the SiO x N y , and then the remaining Si3N4 barrier layer is completely stripped to form an STI structure.

[0019] Preferably, in step 3, the SiO2 bottom layer is grown by ISSG process.

[0020] The SiO2 bottom layer is grown by ISSG oxidation with a volume ratio of H2:O2 of 1:(3-30) at a reaction temperature of 1000℃-1200℃ and a time of 20s-600s.

[0021] Preferably, in step 4, SiN is deposited by LPCVD process. x Middle level.

[0022] LPCVD Deposition of SiN xIn the middle layer, the volume ratio of the reaction gas SiH2Cl2 to NH3 is 1:(0.3-10), the reaction temperature is 700℃-900℃, the pressure is 0.1Torr-5.0Torr, the time is 5min-30min, and the thickness is

[0023] Preferably, in step 5, the SiN x Reoxidation achieves the SiO2 top layer.

[0024] S N x The reoxidation is carried out according to the ISSG oxidation method with a volume ratio of H2:O2 of 1:(3-30) as the reaction gas, a reaction temperature of 900℃-1200℃ and a reaction time of 20s-400s. SiN x The middle layer is reoxidized to The SiO2 top layer eventually forms

[0025] Preferably, in step 6, a HDP SiO2 layer is used to fill the STI trench.

[0026] When depositing the HDP SiO2 layer, the volume ratio of the reaction gas SiH4 to O2 is 1:(1~3), the volume ratio of the reaction gas SiH4 to the bombardment gas Ar is 1:(1~3), the reaction temperature is 300℃~450℃, and the chamber pressure is 1mTorr~10mTorr.

[0027] A 40:1 BHF rinse was used for planarization between the two HDP SiO2 layer depositions.

[0028] Preferably, in step 6, for a CMOS STI process with a feature size of less than 90 nm, three HDP depositions are used.

[0029] The deposition time of the first HDP SiO2 layer is 0.5min~2min, and the thickness is Rinse after deposition of the first HDP SiO2 layer SiO2 is used for planarization.

[0030] The deposition time of the second HDP SiO2 layer is 0.5min to 2min, and the thickness is Rinse after deposition of the second HDPSiO2 layer SiO2 is used for planarization.

[0031] The deposition time of the third HDP SiO2 layer is 0.5min~3min, and the thickness is

[0032] Preferably, in step 6, for a CMOS STI process with a feature size of more than 90 nm, a single HDP deposition is used, the time is 1 min to 6 min, and the thickness is

[0033] Compared with the related art, the STI structure based on the ONO type three-layer Liner and the manufacturing method thereof provided by the present invention have the following beneficial effects:

[0034] Use ISSG SiO2 top layer / SiN x The ONO three-layer liner in the middle layer / ISSG SiO2 bottom layer replaces the liner oxide, which improves the breakdown voltage of STI, reduces the isolation leakage, and can reduce the stress accumulation of STI filling HDP SiO2.

[0035] The SiO2 bottom layer is grown using the ISSG process. The ISSG process can round the sharp top and bottom corners of the STI groove, reducing stress concentration and electric field concentration; improve the uniformity of SiO2 at the top and bottom corners, avoiding the thinning effect of the SiO2 bottom layer; repair the etching damage of the STI groove, and avoid the generation of silicon defects at the edge of the STI groove. Compared with the ordinary dry or wet thermal oxidation growth of Liner oxide, ISSG has the following advantages: (1) higher uniformity of SiO2 at the top and bottom corners, (2) avoids the undercutting of the Si3N4 barrier layer during oxidation, and (3) ISSG high temperature annealing can better repair the etching damage of the STI groove.

[0036] SiN deposited by LPCVD process x Middle layer. SiN x The dielectric constant of SiN is about twice that of SiO2, and it has stronger insulation capability than SiO2. x The stress is 10 8 MPa~10 9 MPa, can be achieved through SiN x The Si content in the SiN is adjusted. The higher the Si content, the smaller the stress. x The tensile stress can reduce or even completely offset the accumulation of compressive stress in the subsequent thicker HDP SiO2.

[0037] Using ISSG to SiN x Reoxidation of SiO2 top layer. ISSG to SiN x The SiO2 achieved by reoxidation has fewer defects and better isolation effect than SiO2 deposited by CVD, and ISSG annealing can further repair the STI trench etching damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic diagram of the STI structure based on the ONO-type three-layer Liner proposed in the present invention;

[0039] Figure 2 This is a flow chart of the STI manufacturing method based on the ONO type three-layer Liner proposed by the present invention;

[0040] Figure 3 Schematic diagram of silicon substrate for growing SiO2 pad oxygen and Si3N4 barrier layer;

[0041] Figure 4 Schematic diagram of silicon substrate after STI trench etching is completed;

[0042] Figure 5 Schematic diagram of the ISSG process for growing SiO2 bottom layer proposed by the present invention;

[0043] Figure 6 SiN deposition by LPCVD process proposed in the present invention x Middle level schematic diagram;

[0044] Figure 7 The ISSG of the present invention is to SiN x Re-oxidation realizes the SiO2 top layer to form an ONO-type three-layer Liner with better isolation effect;

[0045] Figure 8 Schematic diagram of depositing the first HDP SiO2 layer by the HDP process proposed by the present invention;

[0046] Fig. 9 Schematic diagram of depositing the second HDP SiO2 layer by the HDP process proposed by the present invention;

[0047] Fig.10 Schematic diagram of depositing the third HDP SiO2 layer by the HDP process proposed by the present invention;

[0048] Fig.11 Schematic diagram of HDP SiO2 layer after annealing;

[0049] Fig.12 Schematic diagram of the HDP SiO2 layer and ONO three-layer Liner after CMP.

[0050] Among them: 1. Silicon substrate; 2. SiO2 pad oxygen; 3. Si3N4 barrier layer; 4. ISSG SiO2 bottom layer; 5. SiN x middle layer; 6. ISSG SiO2 top layer; 7. HDP SiO2 layer (including: 7a. first HDP SiO2 layer; 7b. second HDP SiO2 layer; 7c. third HDPSiO2 layer); 10. STI groove. DETAILED DESCRIPTION

[0051] The present invention will be further described below in conjunction with the accompanying drawings and implementation modes.

[0052] The invention provides an STI structure based on an ONO-type three-layer liner and a manufacturing method thereof, aiming to improve the isolation characteristics and reliability of the STI structure. x The ONO three-layer liner of the middle layer / ISSG SiO2 bottom layer replaces the liner oxide, which improves the isolation characteristics of STI and can reduce or even completely offset the stress accumulation of HDP SiO2 filled in STI. Among them, the SiO2 bottom layer grown by the ISSG process can round the sharp top and bottom angles of the STI groove, improve the uniformity of SiO2 at the top and bottom angles, and repair annealing of the STI groove etching damage; the SiN deposited by the LPCVD process x The middle layer has stronger insulation ability than SiO2, and can reduce or even completely offset the accumulation of subsequent HDP SiO2 compressive stress; ISSG is used to treat SiN x Re-oxidation to achieve the SiO2 top layer can further improve the isolation characteristics of STI, repair STI trench etching damage and x Perform annealing.

[0053] Example 1

[0054] See also Figures 1 to 12 The present invention provides an STI structure based on an ONO-type three-layer Liner, such as Figure 1 As shown, the present invention comprises a silicon substrate 1 disposed at the bottom, a U-shaped STI trench 10 disposed in the silicon substrate 1, the ISSG SiO2 bottom layer 4, the SiN x The middle layer 5 and the ISSG SiO2 top layer 6 are sequentially covered in the STI trench 10 and are filled by the HDP SiO2 layer 7 .

[0055] The HDP SiO2 layer 7 includes a first HDP SiO2 layer 7a, a second HDP SiO2 layer 7b and a third HDP SiO2 layer 7c which are formed in sequence.

[0056] In the 0.25 μm CMOS STI based on the ONO type three-layer liner in this embodiment, the thickness of the ISSG SiO2 bottom layer is The SiN x The thickness of the middle layer is The thickness of the ISSG SiO2 top layer is

[0057] The present invention provides a method for manufacturing an STI structure based on an ONO-type three-layer liner, such as Figure 2 As shown, the following steps are included:

[0058] Step 1, growth of SiO2 pad oxide and Si3N4 barrier layer: SiO2 pad oxide is grown by oxidation on the original silicon wafer, and Si3N4 barrier layer is grown by LPCVD deposition.

[0059] like Figure 3 As shown, SiO2 pad oxide 2 is grown by oxidation on the original silicon wafer, and Si3N4 barrier layer 3 is grown by LPCVD deposition, which serves as a stop layer for the subsequent HDP SiO2 layer 7CMP.

[0060] The SiO2 pad oxide 2 is grown by dry oxidation with O2, the reaction temperature is 800℃~1000℃, the time is 1min~30min, and the thickness is

[0061] The Si3N4 barrier layer 3 is deposited by LPCVD, the volume ratio of the reaction gas SiH2Cl2 to NH3 is 1:(4-10), the reaction temperature is 700℃-900℃, the pressure is 0.1Torr-5.0Torr, the time is 20min-120min, and the thickness is

[0062] Step 2, STI trench etching: The active area is defined by photolithography, the Si3N4 barrier layer is dry-etched, and then the STI trench is etched on the silicon surface, and the resist is removed after etching.

[0063] Perform photolithography of the active area (including coating, exposure, and development), cover the active area with photoresist, and etch the STI trench 10, using dry etching to achieve a higher selectivity. In the first step, the Si3N4 barrier layer 3 in the STI trench 10 area is etched, the main etching gas is CF4, CH3F and O2, the etching selectivity of Si3N4 to SiO2 is 10:1, and the etching endpoint is selected to stay on the SiO2 pad oxide 2; in the second step, the STI trench 10 is etched, the main etching gas is HBr, Cl2 and O2, the side wall angle of the formed STI trench 10 is 75° to 88°, and the depth-to-width ratio of the STI trench 10 is 1:1 to 4:1.

[0064] After etching, the debonding is performed by dry and wet processes. The dry debonding process is O2 plasma debonding, and the wet debonding process is SPM (H2SO4:H2O2 volume ratio is 5:1) debonding. The morphology of the STI trench 10 after etching and debonding is as follows: Figure 4 shown.

[0065] Step 3, grow SiO2 bottom layer by ISSG process: round the sharp top and bottom angles of STI trench, and repair STI trench etching damage by ISSG annealing.

[0066] like Figure 5 As shown, the ISSG process grows the SiO2 bottom layer 4. The SiO2 bottom layer 4 is grown in an ISSG oxidation manner with a volume ratio of H2:O2 of 1:(3-30) as the reaction gas, a reaction temperature of 1000°C-1200°C, a time of 20s-600s, and a thickness of

[0067] While the ISSG process is growing the SiO2 bottom layer 4, the sharp top and bottom angles of the STI trench 10 are also rounded, reducing stress concentration and electric field concentration, and avoiding the thinning effect of the SiO2 bottom layer 4. The ISSG process also repairs the STI trench etching damage, avoiding the generation of silicon defects at the edge of the STI trench 10.

[0068] Step 4: LPCVD process to deposit SiN x Middle layer: SiN x The middle layer has strong insulation capability and can reduce or even completely offset the subsequent accumulation of HDP SiO2 compressive stress.

[0069] like Figure 6 As shown, the LPCVD process deposits SiN x Middle layer 5. SiN x When the middle layer 5 is deposited, the volume ratio of the reaction gas SiH2Cl2 to NH3 is 1:(0.3-10), the reaction temperature is 700℃-900℃, the pressure is 0.1Torr-5.0Torr, the time is 5min-30min, and the thickness is The volume ratio of SiH2Cl2 to NH3 can be adjusted to change the SiN x The Si content of the middle layer 5, the greater the volume ratio of SiH2Cl2 to NH3, the higher the Si content.

[0070] S N x The dielectric constant of SiN is about twice that of SiO2. x The film has a higher breakdown voltage, i.e., dielectric strength, than SiO2 film of the same thickness.

[0071] LPCVD SiN x The stress is tensile stress. x The increase of Si content in SiN x The stress of Si3N4 is from ~10 9 MPa is reduced to Si-rich SiN x ~10 8MPa. The stress of HDP SiO2 is compressive stress. 8 MPa. Therefore, SiN x Medium Si content adjustment SiN x stress, thereby reducing or even completely offsetting the subsequent accumulation of HDPSiO2 compressive stress.

[0072] Step 5, ISSG to SiN x Re-oxidation realizes the SiO2 top layer: an ONO three-layer Liner with better isolation effect is formed, and ISSG annealing further repairs the STI trench etching damage.

[0073] like Figure 7 As shown, the ISSG x Reoxidation to achieve SiO2 top layer 6. SiN x The reoxidation is carried out according to the ISSG oxidation method with a volume ratio of H2:O2 of 1:(3-30) as the reaction gas, a reaction temperature of 900℃-1200℃ and a reaction time of 20s-400s. SiN x The middle layer 5 is then oxidized to The SiO2 top layer 6 finally forms a better isolation effect ISSG SiO2 Top Layer S N x Middle level The ISSG SiO2 bottom layer 4 has an ONO three-layer liner, and the ISSG annealing further repairs the etching damage of the STI trench 10.

[0074] Step 6, STI trench filling: deposit the first SiO2 layer by HDP process, and rinse it for planarization after deposition; deposit the second SiO2 layer by HDP process, and rinse it for planarization after deposition; deposit the third SiO2 layer by HDP process to complete the filling of the STI trench.

[0075] During HDP deposition, the volume ratio of the reaction gas SiH4 to O2 is 1:(1~3), the volume ratio of the reaction gas SiH4 to the bombardment gas Ar is 1:(1~3), the reaction temperature is 300℃~450℃, and the chamber pressure is 1mTorr~10mTorr.

[0076] For the STI process of CMOS with feature size below 90nm, three HDP depositions are used. A 40:1 BHF rinse is used between two HDP SiO2 layer depositions for planarization, making it easier to fill in the subsequent HDP deposition.

[0077] like Figure 8As shown, the first HDP SiO2 7a layer is deposited and planarized to preliminarily fill the STI trench 10. The deposition time is 0.5min to 2min, and the thickness is BHF rinse after deposition SiO2 is used for planarization.

[0078] like Fig. 9 As shown, a thick second HDP SiO2 layer 7b is deposited and planarized, and the STI trench 10 is continuously filled. The deposition time is 0.5min to 2min, and the thickness is BHF rinse after deposition SiO2 is used for planarization.

[0079] like Fig.10 As shown, a third HDP SiO2 layer 7c is deposited to complete the filling of the STI trench 10. The deposition time is 0.5min to 3min, and the thickness is

[0080] For the STI process of CMOS with a feature size of more than 90nm, a single HDP deposition is used, the time is 1min to 6min, and the thickness is That is, not Figure 8 and Fig. 9 Deposition and rinsing of Fig.10 of deposition.

[0081] Step 7, annealing the HDP SiO2 layer: annealing the HDP SiO2 layer at a high temperature to improve the compactness of the HDP SiO2 and eliminate plasma damage to the HDP SiO2.

[0082] like Fig.11 As shown, the HDP SiO2 layer 7 is annealed in N2. The annealing can be rapid annealing or long-term furnace annealing, with a temperature of 900°C to 1000°C and a time of 0.3min to 30min. The purpose of annealing is to densify the HDP SiO2 layer 7 and eliminate plasma damage to the HDP SiO2 layer 7.

[0083] Step 8, HDP SiO2 layer and ONO three-layer Liner CMP: Use CMP to grind off the HDP SiO2, ONO three-layer Liner and part of the Si3N4 barrier layer on the Si3N4 barrier layer, and the CMP finally stops on the remaining Si3N4 barrier layer.

[0084] The HDP SiO2 layer 7, ONO three-layer liner and part of the Si3N4 barrier layer 3 on the Si3N4 barrier layer 3 are ground by CMP. A certain amount of over-grinding is set during CMP, and the HDP SiO2 layer 7 on the Si3N4 barrier layer 3 and the ISSG SiO2 top layer 6 / SiN x The ONO three-layer liner of the middle layer 5 / ISSG SiO2 bottom layer 4 will be ground off, and part of the Si3N4 barrier layer 3 will also be ground off. The remaining Si3N4 barrier layer 3 thickness is CMP finally stops on the remaining Si3N4 barrier layer 3. At the same time, since the Si3N4 barrier layer 3 has a higher hardness than the HDP SiO2 layer 7, the HDP SiO2 layer 7 will be lower than the Si3N4 barrier layer 3 after grinding, forming a certain dipping. The morphology after CMP is as follows: Fig.12 shown.

[0085] Step 9, complete stripping of Si3N4 barrier layer: First rinse off the SiO x N y , and then the remaining Si3N4 barrier layer is completely stripped to form an STI structure.

[0086] SiO will form on the surface of Si3N4 barrier layer 3 x N y The natural oxide is removed by rinsing with 100:1 HF (100H2O:1 49% HF) at a temperature of 22°C for 60s to 1200s. HF also thins the HDP SiO2 layer 7, thereby accurately controlling the height of the HDP SiO2 layer 7 above the silicon substrate 1 (STI height).

[0087] The Si3N4 barrier layer 3 is completely stripped using H3PO4 etching solution at a temperature of 155°C to 170°C for 30min to 120min, and finally forms a Figure 1 The STI structure shown.

[0088] Furthermore, in this embodiment, the 0.25 μm CMOS STI process based on the ONO type three-layer Liner is as follows:

[0089] Oxide growth on pristine silicon wafer SiO2 pad oxygen, LPCVD deposition growth Si3N4 barrier layer;

[0090] Active area photolithography, dry etching depth is STI trench, stripping after etching;

[0091] ISSG oxidation growth SiO2 bottom layer;

[0092] LPCVD deposition process S N x Middle level;

[0093] ISSG vs SiN x Reoxidation to achieve the SiO2 top layer, SiN x The middle layer is reoxidized to The SiO2 top layer finally achieves ISSG SiO2 S N x ISSG SiO2 bottom ONO three-layer liner;

[0094] HDP SiO2 filling;

[0095] The HDP SiO2 layer was rapidly annealed in N2 at 1000°C for 20 seconds;

[0096] HDP SiO2 layer and ONO three-layer Liner CMP, use CMP to grind off the HDP SiO2 and ONO three-layer Liner on the Si3N4 barrier layer, and grind off part of the Si3N4 barrier layer, and CMP finally stops at the remaining On Si3N4 barrier layer;

[0097] 100:1 HF rinse to remove SiO on the surface of Si3N4 barrier layer x N y , time is 850s, because rinsing HDP SiO2 also loses

[0098] H3PO4 corrosion liquid completely peels off the remaining The Si3N4 barrier layer is formed for 60 minutes and the height above the silicon substrate is STI.

[0099] Example 2

[0100] Based on the STI structure based on the ONO type three-layer liner and its manufacturing method provided in the first embodiment of the present application, the second embodiment of the present application proposes another STI structure based on the ONO type three-layer liner and its manufacturing method. The second embodiment is only a preferred mode of the first embodiment, and the implementation of the second embodiment will not affect the independent implementation of the first embodiment.

[0101] The 45nm CMOS STI process based on ONO-type three-layer Liner is as follows:

[0102] Oxide growth on pristine silicon wafer SiO2 pad oxygen, CVD deposition growth Si3N4 barrier layer;

[0103] Active area photolithography, dry etching depth is STI trench, stripping after etching;

[0104] ISSG oxidation growth SiO2 bottom layer;

[0105] LPCVD deposition process S N x Middle level;

[0106] ISSG vs SiN x Reoxidation to achieve the SiO2 top layer, SiN x The middle layer is reoxidized to The SiO2 top layer finally achieves ISSG SiO2 S N x ISSG SiO2 bottom ONO three-layer liner;

[0107] HDP SiO2 filling;

[0108] 40:1BHF rinse SiO2 for planarization;

[0109] HDP SiO2 filling;

[0110] 40:1BHF rinse SiO2 for planarization;

[0111] HDP SiO2 layer filling;

[0112] HDP SiO2 layer and ONO three-layer Liner CMP, use CMP to grind off the HDP SiO2 and ONO three-layer Liner on the Si3N4 barrier layer, and grind off part of the Si3N4 barrier layer, and CMP finally stops at the remaining On Si3N4 barrier layer;

[0113] 100:1 HF rinse to remove SiO on the surface of Si3N4 barrier layer x N y, time is 400s, because rinsing HDP SiO2 also loses

[0114] H3PO4 corrosion liquid completely peels off the remaining The Si3N4 barrier layer is formed for 40 minutes and the height above the silicon substrate is STI.

[0115] The STI structure based on the ONO-type three-layer Liner and the manufacturing method thereof proposed in the present invention have the following advantages:

[0116] 1) The SiO2 bottom layer grown by ISSG improves the uniformity of the top and bottom corners of the STI trench and avoids the oxidation of SiN x The drilling and etching can better repair the STI trench etching damage;

[0117] 2) SiN deposited by LPCVD process x The middle layer has stronger insulation ability than SiO2, SiN x The tensile stress of the middle layer can reduce or even completely offset the accumulation of compressive stress of the subsequent thicker HDP SiO2;

[0118] 3) Using ISSG for SiN x The SiO2 top layer achieved by reoxidation has fewer defects and better isolation effect than SiO2 deposited by CVD, and ISSG annealing can further repair STI trench etching damage.

[0119] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An STI structure based on an ONO-type three-layer Liner, characterized in that: The invention comprises a silicon substrate arranged at the bottom, a U-shaped STI groove arranged in the silicon substrate, the ISSG SiO2 bottom layer, the SiN x The middle layer and the ISSG SiO2 top layer are sequentially covered in the STI trench and filled with the HDP SiO2 layer.

2. The STI structure based on the ONO type three-layer Liner according to claim 1, characterized in that: ISSG SiO2 bottom layer thickness is S N x The thickness of the middle layer is ISSG SiO2 top layer thickness is 3. The STI structure based on ONO type three-layer Liner according to claim 1, characterized in that: For the STI process of CMOS with a feature size of less than 90nm, the HDP SiO2 layer includes a first HDP SiO2 layer, a second HDPSiO2 layer and a third HDP SiO2 layer formed in sequence; for the STI process of CMOS with a feature size of more than 90nm, the HDP SiO2 layer is a single layer.

4. A method for manufacturing an STI structure based on an ONO-type three-layer liner, characterized in that: The steps include: Step 1, growth of SiO2 pad oxygen and Si3N4 barrier layer: oxidation growth of SiO2 pad oxygen on the original silicon wafer, and LPCVD deposition growth of Si3N4 barrier layer; Step 2, STI trench etching: The active area is defined by photolithography, the Si3N4 barrier layer is dry-etched, and then the STI trench is etched on the silicon surface, and the resist is removed after etching; Step 3, growing SiO2 bottom layer by ISSG process: rounding the sharp top and bottom angles of STI trenches, and repairing STI trench etching damage by ISSG annealing; Step 4: LPCVD process to deposit SiN x Middle layer: SiN x The middle layer has strong insulation ability and can reduce or even completely offset the accumulation of subsequent HDP SiO2 compressive stress; Step 5, ISSG to SiN x Re-oxidation realizes the SiO2 top layer: forming an ONO three-layer liner with better isolation effect, and ISSG annealing further repairs the STI trench etching damage; Step 6, STI trench filling: deposit the first HDP SiO2 layer by HDP process, and planarize it by BHF rinsing after deposition; deposit the second HDP SiO2 layer by HDP process, and planarize it by BHF rinsing after deposition; deposit the third HDP SiO2 layer by HDP process to complete the filling of STI trench; Step 7, annealing the HDP SiO2 layer: annealing the HDP SiO2 layer at high temperature to improve the compactness of the HDP SiO2 and eliminate plasma damage to the HDPSiO2; Step 8, HDP SiO2 layer and ONO three-layer Liner CMP: Use CMP to grind away the HDP SiO2, ONO three-layer Liner and part of the Si3N4 barrier layer on the Si3N4 barrier layer, and the CMP finally stops on the remaining Si3N4 barrier layer; Step 9: Complete stripping of Si3N4 barrier layer: First, rinse off the SiO x N y , and then the remaining Si3N4 barrier layer is completely stripped to form an STI structure.

5. The method for manufacturing an STI structure based on an ONO-type three-layer Liner according to claim 4, characterized in that: In step 3, a SiO2 bottom layer is grown by an ISSG process; The SiO2 bottom layer is grown by ISSG oxidation with a volume ratio of H2:O2 of 1:(3-30) at a reaction temperature of 1000℃-1200℃ and a time of 20s-600s.

6. The method for manufacturing an STI structure based on an ONO-type three-layer Liner according to claim 4, characterized in that: In step 4, SiN is deposited by LPCVD process. x Middle level; LPCVD Deposition of SiN x In the middle layer, the volume ratio of the reaction gas SiH2Cl2 to NH3 is 1:(0.3-10), the reaction temperature is 700℃-900℃, the pressure is 0.1Torr-5.0Torr, the time is 5min-30min, and the thickness is 7. The method for manufacturing an STI structure based on an ONO-type three-layer Liner according to claim 4, characterized in that: In step 5, the SiN x Reoxidation to achieve the SiO2 top layer; S N x The reoxidation is carried out according to the ISSG oxidation method with a volume ratio of H2:O2 of 1:(3-30), a reaction temperature of 900℃-1200℃ and a time of 20s-400s. SiN x The middle layer is reoxidized to The SiO2 top layer eventually forms ISSG SiO2 top layer / S N x Middle level / ISSG ONO three-layer liner with SiO2 bottom layer.

8. The method for manufacturing an STI structure based on an ONO-type three-layer Liner according to claim 4, characterized in that: In step 6, the STI trench is filled with a HDP SiO2 layer; When depositing the HDP SiO2 layer, the volume ratio of the reaction gas SiH4 to O2 is 1:(1-3), the volume ratio of the reaction gas SiH4 to the bombardment gas Ar is 1:(1-3), the reaction temperature is 300℃~450℃, and the chamber pressure is 1mTorr~10mTorr; A 40:1 BHF rinse was used for planarization between the two HDP SiO2 layer depositions.

9. The method for manufacturing an STI structure based on an ONO-type three-layer Liner according to claim 4, characterized in that: In step 6, for the STI process of CMOS with a feature size below 90 nm, three HDP depositions are used; The deposition time of the first HDP SiO2 layer is 0.5min~2min, and the thickness is Rinse after deposition of the first HDP SiO2 layer SiO2 for planarization; The deposition time of the second HDP SiO2 layer is 0.5min to 2min, and the thickness is Rinse after deposition of the second HDP SiO2 layer SiO2 for planarization; The deposition time of the third HDP SiO2 layer is 0.5min~3min, and the thickness is 10. The method for manufacturing an STI structure based on an ONO-type three-layer Liner according to claim 4, characterized in that: In step 6, for the STI process of CMOS with a feature size of more than 90nm, a single HDP deposition is used, the time is 1min to 6min, and the thickness is

Images