Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, and the method comprises the steps: forming a bottom interconnection structure layer on a bearing surface, and the bottom interconnection structure layer comprises a connection region; providing an interconnection chip, wherein the interconnection chip comprises a bonding surface and a back surface which are opposite; an interconnection chip is bonded on the bottom interconnection structure layer of the connection area, the bonding surface and the bottom interconnection structure layer are oppositely arranged, and the interconnection chip and the bottom interconnection structure layer are electrically connected; carrying out thinning processing on the back surface of the interconnection chip; after the back face of the interconnection chip is thinned, a top interconnection structure layer is formed on the bottom interconnection structure layer, and the top interconnection structure layer is electrically connected with the bottom interconnection structure layer; providing a first chip and a chip set; bonding a first chip and a chip group on the top interconnection structure layer, wherein the first chip and the chip group are electrically connected with the top interconnection structure layer respectively; the chipset and the first chip are electrically connected through the top interconnection structure layer, the bottom interconnection structure layer and the interconnection chip. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor packaging, and in particular to a packaging structure and a packaging method. Background Art

[0002] Conventional chip manufacturing technologies are being pushed to their limits in terms of the size of a single chip. However, applications are eager to use the latest technology to achieve the capabilities of large-scale integrated circuits, and achieving high-speed and small-volume interconnections between chips is a major challenge.

[0003] One current solution is to use a smaller integrated circuit of a silicon bridge (Si Bridge) chip embedded in a silicon substrate to interconnect chips through the silicon bridge chip, thereby providing a heterogeneous chip package.

[0004] However, the performance of the current packaging structure still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method to improve the performance of the packaging structure.

[0006] To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a bottom interconnection structure layer, including a connection area; an interconnection chip, bonded to the bottom interconnection structure layer in the connection area, and electrically connected to the bottom interconnection structure layer; the interconnection chip includes a bonding surface and a back surface opposite to each other, the bonding surface is arranged opposite to the bottom interconnection structure layer, and the back surface is thinned; a top interconnection structure layer, located on the bottom interconnection structure layer and electrically connected to the bottom interconnection structure layer; a first chip, bonded to the top interconnection structure layer, and electrically connected to the top interconnection structure layer; a chipset, located on the top interconnection structure layer bonded to the side of the first chip, and electrically connected to the top interconnection structure layer; the chipset is electrically connected to the first chip through the top interconnection structure layer, the bottom interconnection structure layer and the interconnection chip.

[0007] Correspondingly, an embodiment of the present invention also provides a packaging method, comprising: providing a carrier substrate, comprising a carrier surface; forming a bottom interconnection structure layer on the carrier surface, the bottom interconnection structure layer comprising a connection area; providing an interconnection chip, comprising a bonding surface and a back surface opposite to each other; bonding the interconnection chip on the bottom interconnection structure layer in the connection area, the bonding surface and the bottom interconnection structure layer are arranged opposite to each other, and the interconnection chip and the bottom interconnection structure layer are electrically connected; thinning the back side of the interconnection chip; after thinning the back side of the interconnection chip, forming a top interconnection structure layer on the bottom interconnection structure layer, the top interconnection structure layer and the bottom interconnection structure layer are electrically connected; providing a first chip and a chipset; bonding the first chip and the chipset on the top interconnection structure layer, the first chip and the chipset are electrically connected to the top interconnection structure layer respectively; the chipset and the first chip are electrically connected through the top interconnection structure layer, the bottom interconnection structure layer and the interconnection chip.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the packaging structure provided by the embodiment of the present invention, the interconnection chip is bonded to the bottom interconnection structure layer of the connection area, and the interconnection chip is electrically connected to the bottom interconnection structure layer; the top interconnection structure layer is located on the bottom interconnection structure layer and is electrically connected to the bottom interconnection structure layer; the first chip is bonded to the top interconnection structure layer and is electrically connected to the top interconnection structure layer; the chipset is located on the top interconnection structure layer bonded to the side of the first chip and is electrically connected to the top interconnection structure layer, so that the electrical connection between the first chip and the chipset can be achieved through the top interconnection structure layer, the bottom interconnection structure layer and the interconnection chip; and the back side of the interconnection chip is thinned to reduce the thickness of the interconnection chip, which is beneficial to reducing the thickness of the top interconnection structure layer and the packaging structure, thereby simplifying the packaging structure and facilitating the thinning of the device, and the packaging structure generally also includes a packaging substrate bonded to the side of the bottom interconnection structure layer opposite to the interconnection chip. Since the interconnection chip is thinner, it is beneficial to shorten the distance between the first chip and the chipset and the packaging substrate, thereby facilitating the heat dissipation of the packaging structure and improving the performance of the packaging structure.

[0010] In the packaging method provided by the embodiment of the present invention, an interconnection chip is bonded on the bottom interconnection structure layer of the connection area, and the interconnection chip is electrically connected to the bottom interconnection structure layer; a top interconnection structure layer is formed on the bottom interconnection structure layer, and the top interconnection structure layer is electrically connected to the bottom interconnection structure layer; a first chip and a chipset are bonded on the top interconnection structure layer, and the first chip and the chipset are electrically connected to the top interconnection structure layer respectively, so that the electrical connection between the first chip and the chipset can be achieved through the top interconnection structure layer, the bottom interconnection structure layer and the interconnection chip; and after bonding the interconnection chip and before forming the top interconnection structure layer, the back side of the interconnection chip is thinned to reduce The thickness of the small interconnected chip is conducive to reducing the thickness of the top interconnected structure layer and the packaging structure, thereby simplifying the packaging structure and facilitating the thinning of the device. Moreover, after the packaging structure is subsequently bonded to the packaging substrate, since the interconnected chip is thinner, it is conducive to shortening the distance between the first chip and the chipset and the packaging substrate, thereby facilitating the heat dissipation of the packaging structure and improving the performance of the packaging structure. In addition, after the top interconnected structure layer is formed and before the first chip and the chipset are bonded on the top interconnected structure layer, the electrical connection performance of the top interconnected structure layer, the bottom interconnected structure layer and the interconnected chip can also be tested, thereby facilitating improving the packaging yield after the first chip and the chipset are bonded. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention;

[0012] Figures 2 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention. DETAILED DESCRIPTION

[0013] As can be seen from the background technology, the performance of the current packaging structure needs to be improved.

[0014] In order to solve the technical problem, an embodiment of the present invention provides a packaging structure, wherein an interconnection chip is bonded to a bottom interconnection structure layer of a connection area, and the interconnection chip is electrically connected to the bottom interconnection structure layer; a top interconnection structure layer is located on the bottom interconnection structure layer and is electrically connected to the bottom interconnection structure layer; a first chip is bonded to the top interconnection structure layer and is electrically connected to the top interconnection structure layer; a chipset is located on the top interconnection structure layer bonded to the side of the first chip and is electrically connected to the top interconnection structure layer, so that the electrical connection between the first chip and the chipset can be achieved through the top interconnection structure layer, the bottom interconnection structure layer and the interconnection chip; and the back side of the interconnection chip is thinned to reduce the thickness of the interconnection chip, which is beneficial to reducing the thickness of the top interconnection structure layer and the packaging structure, thereby simplifying the packaging structure and facilitating the thinning of the device, and the packaging structure generally also includes a packaging substrate bonded to the side of the bottom interconnection structure layer opposite to the interconnection chip. Since the interconnection chip is thinner, it is beneficial to shorten the distance between the first chip and the chipset and the packaging substrate, thereby facilitating the heat dissipation of the packaging structure and improving the performance of the packaging structure.

[0015] In order to solve the technical problem, an embodiment of the present invention also provides a packaging method, wherein an interconnection chip is bonded on the bottom interconnection structure layer of the connection area, and the interconnection chip is electrically connected to the bottom interconnection structure layer; a top interconnection structure layer is formed on the bottom interconnection structure layer, and the top interconnection structure layer is electrically connected to the bottom interconnection structure layer; a first chip and a chipset are bonded on the top interconnection structure layer, and the first chip and the chipset are electrically connected to the top interconnection structure layer respectively, so that the electrical connection between the first chip and the chipset can be achieved through the top interconnection structure layer, the bottom interconnection structure layer and the interconnection chip; and after bonding the interconnection chip and before forming the top interconnection structure layer, the back side of the interconnection chip is thinned. The thickness of the interconnected chip is reduced, which is beneficial to reducing the thickness of the top interconnected structure layer and the packaging structure, thereby simplifying the packaging structure and facilitating the thinning of the device. In addition, after the packaging structure is subsequently bonded to the packaging substrate, since the interconnected chip is thinner, it is beneficial to shorten the distance between the first chip and the chipset and the packaging substrate, which is beneficial to the heat dissipation of the packaging structure and improves the performance of the packaging structure. In addition, after the top interconnected structure layer is formed and before the first chip and the chipset are bonded on the top interconnected structure layer, the electrical connection performance of the top interconnected structure layer, the bottom interconnected structure layer and the interconnected chip can also be tested, which is beneficial to improving the packaging yield after the first chip and the chipset are bonded.

[0016] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0017] refer to Figure 1, showing a schematic structural diagram of an embodiment of a packaging structure of the present invention.

[0018] like Figure 1 As shown, in this embodiment, the package structure includes: a bottom interconnect structure layer 310, including a connection area 310a (combined with reference Figure 3 ); an interconnection chip 30, bonded to the bottom interconnection structure layer 310 of the connection area 310a, and electrically connected to the bottom interconnection structure layer 310; the interconnection chip 30 includes a bonding surface 301 and a back surface 302 opposite to each other, the bonding surface 301 is arranged opposite to the bottom interconnection structure layer 310, and the back surface 302 is thinned; a top interconnection structure layer 320, located on the bottom interconnection structure layer 310 and electrically connected to the bottom interconnection structure layer 310; a first chip 10, bonded to the top interconnection structure layer 320, and electrically connected to the top interconnection structure layer 320; a chipset 200, located on the top interconnection structure layer 320 bonded to the side of the first chip 10, and electrically connected to the top interconnection structure layer 320; the chipset 200 and the first chip 10 are electrically connected through the top interconnection structure layer 320, the bottom interconnection structure layer 310 and the interconnection chip 30.

[0019] The bottom interconnect structure layer 310 is used to provide a process operation platform for bonding the interconnect chip 30 and for forming the top interconnect structure layer 320. The bottom interconnect structure layer 310 is also used to electrically connect the interconnect chip 30 and the top interconnect structure layer 320 so as to realize the interconnection between the top interconnect structure layer 320 and the interconnect chip 30 through the bottom interconnect structure layer 310.

[0020] In this embodiment, the bottom interconnect structure layer 310 includes a connection region 310 a , and the connection region 310 a is used to achieve bonding with the interconnect chip 30 .

[0021] In this embodiment, the bottom interconnection structure layer 310 is the first rewiring structure layer. The first rewiring structure layer is conducive to redistributing the connection ends of the interconnection chip 30, thereby facilitating the interconnection between the top interconnection structure layer 320 and the interconnection chip 30 through the first rewiring structure layer; moreover, the packaging structure generally also includes a fourth conductive bump disposed on the opposite side of the bottom interconnection structure layer 310 and the top interconnection structure layer 320, and the first rewiring structure layer is also conducive to providing a process basis for forming the fourth conductive bump, so as to reduce the pitch of the fourth conductive bump and increase the density of the fourth conductive bump, thereby improving the interconnection performance between the bottom interconnection structure layer 310 and the packaging substrate.

[0022] Specifically, the first redistribution structure layer may include one or more first redistribution layers. Specifically, the material of the first redistribution layer is a conductive material. As an example, the material of the first redistribution structure layer is a metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0023] It should also be noted that, in each first redistribution layer, a dielectric material is formed between the side portions of the first redistribution layers to achieve isolation between the first redistribution layers.

[0024] The interconnection chip 30 is used as a chip bridge to realize the interconnection between the first chip and the chipset. Specifically, the electrical connection between the top interconnection structure layer 320 and the interconnection chip 30 is realized through the bottom interconnection structure layer 310, thereby realizing the interconnection between the first chip 10 and the chipset 200.

[0025] The bonding surface 301 is used for bonding to the bottom interconnection structure layer 310 to achieve electrical connection with the bottom interconnection structure layer 310. The back surface 302 is used for thinning processing to reduce the thickness of the interconnection chip 30.

[0026] In this embodiment, the interconnection chip 30 includes a base layer (not shown) and a conductive structure layer (not shown) located on the base layer. The side of the base layer opposite to the conductive structure layer is used as the back side 302, and the side of the conductive structure layer opposite to the base layer is used as the bonding surface 301.

[0027] In this embodiment, the base layer is used to provide support for forming the conductive structure layer, and the side of the base layer opposite to the conductive structure layer is used for thinning, thereby reducing the thickness of the interconnection chip 30 while ensuring that the interconnection chip 30 is used to achieve the interconnection performance between the first chip 10 and the chipset 200.

[0028] That is, during the formation of the packaging structure, when the back side 302 of the interconnection chip 30 is thinned, only a portion of the base layer is removed to reduce the probability of damaging the conductive structure layer, thereby reducing process risks.

[0029] In this embodiment, the material of the base layer is silicon.

[0030] The conductive structure layer is used to electrically connect to the bottom interconnection structure layer 310 and the top interconnection structure layer 320 , thereby realizing the interconnection between the first chip 10 and the chipset 200 .

[0031] As an example, the conductive structure layer is a third rewiring structure layer. The third rewiring structure layer can redistribute the connection ends of the interconnection chip 30, so as to form a first conductive bump on the bonding surface 301 whose density and position meet the process requirements, thereby facilitating the electrical connection between the interconnection chip 30 and the bottom interconnection structure layer 310 through the first conductive bump, and also facilitating the first conductive bump to have a smaller pitch and higher density, thereby facilitating the interconnection performance between the interconnection chip 30 and the bottom interconnection structure layer 310, thereby improving the interconnection performance between the first chip 10 and the chipset 200.

[0032] Correspondingly, the conductive structure layer is also used to provide a process platform for forming the first conductive bump.

[0033] Specifically, the third redistribution structure layer may include one or more third redistribution layers. Specifically, the material of the third redistribution layer is a conductive material. As an example, the material of the third redistribution structure is a metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0034] It should be noted that, in each third redistribution layer, a dielectric material is further formed on the side of the third redistribution layer to achieve electrical isolation between the third redistribution layers.

[0035] In other embodiments, the base layer can also be completely thinned and removed to further reduce the thickness of the interconnection chip, so that the interconnection chip only retains the conductive structure layer, thereby ensuring the interconnection function of the interconnection chip. Accordingly, the interconnection chip only includes the conductive structure layer, and the side of the conductive structure layer opposite to the bottom interconnection structure layer is used as the bonding surface, and the side of the conductive structure layer opposite to the bottom interconnection structure layer is used as the back surface.

[0036] It should be noted that the thickness of the interconnection chip 30 should not be too small or too large. If the thickness of the remaining interconnection chip 30 is too small, the thickness of the thinning process on the back side 302 of the interconnection chip 30 is too large, which easily increases the risk of damaging the conductive structure layer; if the thickness of the remaining interconnection chip 30 is too large, the thickness of the thinning process on the back side of the interconnection chip 30 is too small, which easily leads to an insignificant effect of reducing the thickness of the interconnection chip 30. For this reason, in this embodiment, the thickness of the interconnection chip 30 is 2μm to 15μm.

[0037] In this embodiment, the package structure further includes: a first conductive bump 11, located between the bottom interconnect structure layer 310 and the interconnect chip 30. The first conductive bump 11 is used to achieve bonding between the interconnect chip 30 and the bottom interconnect structure layer 310, thereby achieving electrical connection between the interconnect chip 30 and the bottom interconnect structure layer 310.

[0038] In this embodiment, the material of the first conductive bump 11 includes

[0039] One or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the first conductive bump 11 is tin.

[0040] In this embodiment, the packaging structure further includes: a first sealing layer 305 , which is located between the interconnection chip 30 and the bottom interconnection structure layer 310 and seals the first conductive bump 11 .

[0041] The first sealing layer 305 fills the gap between the interconnection chip 30 and the bottom interconnection structure layer 310 to seal the first conductive bump 11. As an example, the material of the first sealing layer 305 is epoxy resin.

[0042] The top interconnection structure layer 320 is electrically connected to the bottom interconnection structure layer 310, so that the top interconnection structure layer 320 and the interconnection chip 30 can be electrically connected through the bottom interconnection structure layer 310, and then the first chip 10 and the chipset 200 are electrically connected through the top interconnection structure layer 320, the bottom interconnection structure layer 310 and the interconnection chip 30. The top interconnection structure layer 320 is also used to provide a process operation platform for bonding between the chipset 200 and the first chip 10.

[0043] In this embodiment, the top interconnect structure layer 320 is located on the back side 302 of the interconnect chip 30 and on the bottom interconnect structure layer 310 exposed from the interconnect chip 30 .

[0044] Among them, the top interconnection structure layer 320 located on the bottom interconnection structure layer 310 exposed by the interconnection chip 30 is used to contact the bottom interconnection structure layer 310 to achieve electrical connection with the bottom interconnection structure layer 310; the top interconnection structure layer 320 is also located on the back side 302 of the interconnection chip 30, so as to provide a bonding surface with good consistency for bonding the first chip 10 and the chipset 200, and also to facilitate the first chip 10, the chipset 200, and the interconnection chip 30 to have overlapping areas along the projection plane parallel to the bottom interconnection structure layer 310, so that the interconnection chip 30 can play the role of a chip interconnection bridge.

[0045] It should be noted that, in this embodiment, the top interconnection structure layer 320 located on the top of the interconnection chip 30 is not directly electrically connected to the interconnection chip 30 , but is electrically connected to the interconnection chip 30 through the bottom interconnection structure layer 310 .

[0046] That is to say, in this embodiment, the first chip 10 and the chipset 200 are electrically connected through the top interconnection structure layer 320, the bottom interconnection structure layer 310 and the interconnection chip 30. Compared with the solution of realizing the electrical connection between the first chip and the chipset only through any one or both of the top interconnection structure layer and the bottom interconnection structure layer, in this embodiment, the interconnection chip 30 is used to increase the number of connection lines per unit width, thereby improving the interconnection density and communication speed between the first chip 10 and the chipset 200, and improving the performance of the packaging structure.

[0047] In this embodiment, since the back side 302 of the interconnection chip 30 has been thinned, the thickness of the interconnection chip 30 is reduced, which is helpful to reduce the thickness of the top interconnection structure layer 320, and further helps to make the packaging structure thinner and smaller.

[0048] In this embodiment, the top interconnection structure layer 320 is a second rewiring structure layer. The second rewiring structure layer is conducive to redistributing the connection ends of the first chip 10 and the chipset 200, thereby facilitating the interconnection between the top interconnection structure layer 320 and the first chip 10, and between the top interconnection structure layer 320 and the chipset 200 through the second conductive bumps, and is conducive to reducing the pitch of the second conductive bumps and increasing the density of the second conductive bumps, thereby improving the interconnection performance between the top interconnection structure layer 320 and the first chip 10, and between the top interconnection structure layer 320 and the chipset 200.

[0049] Specifically, the second redistribution structure layer may include one or more second redistribution layers. Specifically, the material of the second redistribution layer is a conductive material. As an example, the material of the second redistribution structure is a metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0050] It should also be noted that, in each second redistribution layer, a dielectric material is formed between the side portions of the second redistribution layers to achieve isolation between the second redistribution layers.

[0051] The first chip 10 is used to be bonded to the top interconnection structure layer 320 , and is electrically connected to the chipset 200 through the top interconnection structure layer 320 , the bottom interconnection structure layer 310 and the interconnection chip 30 .

[0052] In this embodiment, the first chip 10 is a first logic chip, which is used to perform logic control on the chipset 200. Specifically, the first logic chip can be a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip or a SoC (System on Chip) chip.

[0053] Specifically, the first chip 10 includes a first surface (not labeled) and a second surface (not labeled) opposite to each other, wherein the first surface is used for bonding to the top interconnection structure layer 320 .

[0054] In this embodiment, the first surface is the chip front side of the first chip 10, and the second surface is the chip back side of the first chip 10. The chip front side of the first chip 10 refers to the side of the first chip 10 facing the device, and the chip back side of the first chip 10 refers to the side of the first chip 10 facing away from the device.

[0055] In this embodiment, one or more metal layers (not shown) are formed on the front side of the first chip 10 so as to bond the first chip 10 on the top interconnection structure layer 320, and the front side of the first chip 10 is arranged opposite to the top interconnection structure layer 320, thereby achieving electrical connection with the top interconnection structure layer 320 through the metal layer on the front side of the first chip 10.

[0056] The chipset 200 is used to bond to the top interconnect structure layer 320 and be electrically connected to the top interconnect structure layer 320, and then the electrical connection between the chipset 200 and the first chip 10 is achieved through the top interconnect structure layer 320, the bottom interconnect structure layer 310 and the interconnect chip 30, thereby forming a corresponding packaging structure to achieve corresponding functions.

[0057] That is, the chipset 200 is electrically connected to the first chip 10 through the top interconnection structure layer 320, the bottom interconnection structure layer 310 and the interconnection chip 30.

[0058] In this embodiment, the chipset 200 includes a third surface 203 and a fourth surface 204 that are opposite to each other.

[0059] Specifically, in this embodiment, the third surface 203 is bonded to the top interconnection structure layer 320 , thereby achieving electrical connection between the chipset 200 and the top interconnection structure layer 320 .

[0060] In this embodiment, the chipset 200 includes a plurality of second chips 20 stacked in a direction perpendicular to the bottom interconnect structure layer 310 , and the second chips 20 adjacent to each other in a direction perpendicular to the bottom interconnect structure layer 310 are electrically connected.

[0061] In this embodiment, in the chipset 200, a plurality of second chips 20 stacked in the longitudinal direction (i.e., perpendicular to the third surface 203 and the fourth surface 204) constitute a high bandwidth memory (HBM) structure. By adopting the HBM structure, it is helpful to meet the requirements for higher information transmission speed.

[0062] In this embodiment, adjacent second chips 20 are electrically connected along a direction perpendicular to the third surface 203 and the fourth surface 204 , thereby achieving electrical integration between the second chips 20 .

[0063] Specifically, in this embodiment, third conductive bumps 13 are formed between adjacent second chips 20 in a direction perpendicular to the third surface 203 and the fourth surface 204 , and electrical connection between adjacent second chips 20 is achieved through the third conductive bumps 13 .

[0064] In this embodiment, the material of the third conductive bump 13 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the third conductive bump 13 is tin.

[0065] In this embodiment, in the chipset 200 , along a direction perpendicular to the third surface 203 and the fourth surface 204 , a second chip 20 closest to the third surface 203 is used as the bottom chip 21 , and the remaining second chips 20 are used as the top chips 22 .

[0066] In this embodiment, the bottom chip 21 is a second logic chip, which is used to control the top chip 22 .

[0067] In this embodiment, the top chip 22 is a memory chip, such as a DRAM chip. In this embodiment, the number of the top chips 22 can be one or more. In this embodiment, the number of the top chips 22 is four as an example for description. In other embodiments, the number of the top chips can also be other numbers.

[0068] Specifically, in this embodiment, the bottom chip 21 is used as a logic control chip in the chipset 200 to control the memory chip.

[0069] In this embodiment, the top interconnection structure layer 320 is also located on the back side 302 of the interconnection chip 30 ; along the projection plane parallel to the bottom interconnection structure layer 310 , the first chip 10 and the chipset 200 have overlapping areas with the interconnection chip 30 .

[0070] That is to say, at least part of the first chip 10 is located on the top interconnection structure layer 320 on the top of the interconnection chip 30, and at least part of the chipset 200 is located on the top interconnection structure layer 320 on the top of the interconnection chip 30, that is, the first chip 10 and the chipset 200 are adjacent, and in the direction parallel to the bottom interconnection structure layer 310, the distances between the first chip 10 and the chipset 200, between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30 are relatively close, which is beneficial to saving the area of ​​the packaging structure and improving the integration per unit area.

[0071] Accordingly, in this embodiment, the first chip 10 is electrically connected to the top interconnection structure layer 320 located on the top of the interconnection chip 30 , and the chipset 200 is electrically connected to the top interconnection structure layer 320 located on the top of the interconnection chip 30 .

[0072] In this embodiment, the packaging structure further includes: a second conductive bump 12 located between the first chip 10 and the top interconnect structure layer 320 , and between the chipset 200 and the top interconnect structure layer 320 .

[0073] Accordingly, in this embodiment, bonding between the first chip 10 and the top interconnection structure layer 320 , and bonding between the chipset 200 and the top interconnection structure layer 320 are achieved through the second conductive bumps 12 .

[0074] Specifically, in this embodiment, the second conductive bumps 12 are located between the first chip 10 and the top interconnect structure layer 320 , and between the third surface 203 of the chipset 200 and the top interconnect structure layer 320 .

[0075] In this embodiment, the second conductive bump 12 is formed between the bottom chip 21 and the top interconnection structure layer 320 of the chipset 200 to achieve electrical connection between the bottom chip 21 and the top interconnection structure layer 320 .

[0076] In this embodiment, the material of the second conductive bump 12 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 12 is tin.

[0077] In this embodiment, the packaging structure further includes: a second sealing layer 306 , which is located between the first chip 10 and the top interconnection structure layer 320 , and between the chipset 200 and the top interconnection structure layer 320 , and seals the second conductive bumps 12 .

[0078] The second sealing layer 306 fills the gaps between the first chip 10 and the top interconnect structure layer 320 , and between the chip set 200 and the top interconnect structure layer 320 , so as to seal the second conductive bumps 12 .

[0079] As an example, the material of the second sealing layer 306 is epoxy resin.

[0080] In this embodiment, the packaging structure further includes: a packaging layer 110 , which is located on the top interconnection structure layer 320 and covers the first chip 10 and the chipset 200 .

[0081] The packaging layer 110 is used to realize the packaging integration between the first chip 10 and the chipset 200 and the top interconnection structure layer 320. The packaging layer 110 can also play the role of insulation, sealing and moisture-proof, which is beneficial to improve the reliability of the packaging structure.

[0082] The packaging layer 110 also covers the top of the first chip 10 and the chipset 200 , thereby improving the protection of the first chip 10 and the chipset 200 and further improving the reliability of the packaging structure.

[0083] As an embodiment, the material of the encapsulation layer 110 is a molding material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. In other embodiments, the encapsulation layer can also use other suitable encapsulation materials.

[0084] In this embodiment, the packaging structure further includes a packaging substrate 300 bonded to the opposite side of the bottom interconnection structure layer 310 and the top interconnection structure layer 320. The packaging substrate 300 is used to realize packaging integration and electrical integration between the chipset 200, the first chip 10 and the interconnection chip 30.

[0085] In this embodiment, the packaging substrate 300 is a PCB (Printed Circuit Board).

[0086] In this embodiment, the packaging structure further includes: a fourth conductive bump 14 , which is located on a side of the bottom interconnection structure layer 310 opposite to the top interconnection structure layer 320 and is electrically connected to the bottom interconnection structure layer 310 .

[0087] The fourth conductive bump 14 is used to realize the electrical connection between the bottom interconnect structure layer 310 and the package substrate 300. In this embodiment, the fourth conductive bump 14 is a solder ball. As an embodiment, the material of the solder ball includes tin.

[0088] Specifically, the solder ball is C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties, and has a larger number of I / Os under the same solder ball spacing. In addition, C4 is suitable for mass production and is conducive to significantly reducing size and weight. In other embodiments, the material of the fourth conductive bump includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0089] In this embodiment, the packaging structure further includes: a third sealing layer 205 , which is located between the bottom interconnect structure layer 310 and the packaging substrate 300 and seals the fourth conductive bump 14 .

[0090] The third sealing layer 205 fills the gap between the bottom interconnect structure layer 310 and the package substrate 300 to seal the fourth conductive bump 14. As an example, the material of the third sealing layer 205 is epoxy resin.

[0091] In this embodiment, the packaging structure further includes: a fifth conductive bump 15 located on a surface of the packaging substrate 300 opposite to the first chip 10 and the chipset 200 , and the fifth conductive bump 15 is used to achieve electrical connection between the packaging substrate 300 and an external circuit.

[0092] In this embodiment, the fifth conductive bump 15 is a solder ball. As an example, the material of the fifth conductive bump 15 is tin.

[0093] The packaging structure may be formed by the packaging method provided by the embodiment of the present invention, or may be formed by other methods.

[0094] Correspondingly, the present invention also provides a packaging method. Figures 2 to 12 The following is a structural schematic diagram of each step corresponding to an embodiment of a packaging method of the present invention. The packaging method of this embodiment is described in detail in conjunction with the accompanying drawings.

[0095] refer to Figure 2 , providing a carrying substrate 100 including a carrying surface 100a.

[0096] The carrier substrate 100 is used to subsequently form a bottom interconnection structure layer, bond an interconnection chip on the bottom interconnection structure layer in the connection area, thin the back of the interconnection chip, form a top interconnection structure layer on the bottom interconnection structure layer, and bond the first chip and the chipset on the top interconnection structure layer to provide a process operation platform. Specifically, the carrier surface 100a is used to provide a process operation platform for subsequent processes.

[0097] In this embodiment, the carrier substrate 100 is a carrier wafer. In other embodiments, the carrier substrate may also be other types of substrates. In this embodiment, the material of the carrier substrate 100 may include one or more of silicon, glass, silicon oxide, and aluminum oxide.

[0098] In this embodiment, subsequent steps further include: forming a bottom interconnection structure layer on the carrying surface 100 a.

[0099] refer to Figure 2 Before forming the bottom interconnect structure layer on the carrier surface 100a, the packaging method further includes: forming a temporary bonding layer 109 on the carrier surface 100a. The temporary bonding layer 109 is formed on the carrier surface 100a so that in the subsequent step of forming the bottom interconnect structure layer, the bottom interconnect structure layer can be formed on the temporary bonding layer 109, thereby facilitating the subsequent removal of the carrier substrate to achieve separation between the carrier substrate and the bottom interconnect structure layer.

[0100] As an example, the temporary bonding layer 109 is an adhesive layer. More specifically, the material of the temporary bonding layer 109 may include a thermally decomposable bonding film, a photodecomposable bonding film, an electrically decomposable bonding film, or a chemically decomposable bonding film to reduce the difficulty of removing the carrier substrate 100 by debonding.

[0101] refer to Figure 3 , a bottom interconnect structure layer 310 is formed on the carrying surface 100 a , and the bottom interconnect structure layer 310 includes a connection area 310 a .

[0102] The bottom interconnect structure layer 310 is used to provide a process operation platform for the subsequent bonding of the interconnect chip and for forming the top interconnect structure layer. The bottom interconnect structure layer 310 is also used to electrically connect with the interconnect chip and the subsequent top interconnect structure layer so as to realize the interconnection between the top interconnect structure layer and the interconnect chip through the bottom interconnect structure layer 310.

[0103] In this embodiment, the bottom interconnect structure layer 310 includes a connection region 310 a , and the connection region 310 a is used to achieve bonding with the interconnect chip.

[0104] In this embodiment, the bottom interconnect structure layer 310 is formed on the temporary bonding layer 109 .

[0105] In this embodiment, the bottom interconnection structure layer 310 is the first rewiring structure layer. The first rewiring structure layer is conducive to redistributing the connection ends of the subsequent interconnection chips, thereby facilitating the subsequent interconnection between the top interconnection structure layer and the interconnection chip through the first rewiring structure layer; and, after the carrier substrate is removed, a fourth conductive bump is formed on the side opposite to the top interconnection structure layer of the bottom interconnection structure layer 310. The first rewiring structure layer is also conducive to providing a process basis for forming the fourth conductive bump, so as to reduce the pitch of the fourth conductive bump and increase the density of the fourth conductive bump, thereby improving the interconnection performance between the bottom interconnection structure layer 310 and the packaging substrate.

[0106] Specifically, the first redistribution structure layer may include one or more first redistribution layers. Specifically, the material of the first redistribution layer is a conductive material. As an example, the material of the first redistribution structure layer is a metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0107] It should also be noted that, in each first redistribution layer, a dielectric material is formed between the side portions of the first redistribution layers to achieve isolation between the first redistribution layers.

[0108] refer to Figure 4 , providing an interconnection chip 30, including a bonding surface 301 and a back surface 302 facing each other.

[0109] An interconnection chip 30 is provided so that the interconnection chip can be subsequently bonded on the bottom interconnection structure layer of the connection area and a top interconnection structure layer can be formed on the bottom interconnection structure layer, thereby realizing the interconnection between the first chip and the chipset through the top interconnection structure layer, the bottom interconnection structure layer and the interconnection chip 30.

[0110] Specifically, the interconnection chip 30 is used as a chip bridge (Bridge Die) to achieve the interconnection between the subsequent first chip and the chipset.

[0111] The bonding surface 301 is used for subsequent bonding to the bottom interconnection structure layer 310 to achieve electrical connection with the bottom interconnection structure layer 310. The back surface 302 is used for subsequent thinning treatment to reduce the thickness of the interconnection chip 30.

[0112] In this embodiment, the interconnection chip 30 includes a base layer (not shown) and a conductive structure layer (not shown) located on the base layer. The side of the base layer opposite to the conductive structure layer is used as the back side 302, and the side of the conductive structure layer opposite to the base layer is used as the bonding surface 301.

[0113] In this embodiment, the base layer is used to provide support for forming the conductive structure layer, and in the subsequent step of thinning the back surface 302 of the interconnection chip 30 , the base layer is thinned.

[0114] By thinning the base layer, the thickness of the interconnection chip 30 is reduced while ensuring the interconnection performance of the interconnection chip 30 for realizing the interconnection between the first chip 10 and the chipset 200 .

[0115] In this embodiment, the material of the base layer is silicon.

[0116] The conductive structure layer is used to electrically connect with the bottom interconnection structure layer and the subsequent top interconnection structure layer, thereby realizing the interconnection between the first chip and the chipset.

[0117] As an example, the conductive structure layer is a third rewiring structure layer. The third rewiring structure layer can redistribute the connection ends of the interconnection chip 30, so as to form a first conductive bump on the bonding surface 301 whose density and position meet the process requirements, thereby facilitating the subsequent electrical connection between the interconnection chip 30 and the bottom interconnection structure layer 310 through the first conductive bump, and also facilitating the first conductive bump to have a smaller pitch and higher density, thereby facilitating the interconnection performance between the interconnection chip 30 and the bottom interconnection structure layer 310, thereby improving the subsequent first chip and chipset.

[0118] Correspondingly, the conductive structure layer is also used to provide a process platform for forming the first conductive bump.

[0119] Specifically, the third redistribution structure layer may include one or more third redistribution layers. Specifically, the material of the third redistribution layer is a conductive material. As an example, the material of the third redistribution structure is a metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0120] It should be noted that, in each third redistribution layer, a dielectric material is further formed on the side of the third redistribution layer to achieve electrical isolation between the third redistribution layers.

[0121] refer to Figure 5 , in the connection area 310a (such as Figure 3 The interconnect chip 30 is bonded to the bottom interconnect structure layer 310 of FIG. 1 , the bonding surface 301 is arranged opposite to the bottom interconnect structure layer 310 , and the interconnect chip 30 and the bottom interconnect structure layer 310 are electrically connected.

[0122] The interconnection chip 30 is electrically connected to the bottom interconnection structure layer 310, so that after a top interconnection structure layer is subsequently formed on the bottom interconnection structure layer 310, the electrical connection between the top interconnection structure layer and the interconnection chip can be achieved through the bottom interconnection structure layer, thereby facilitating the interconnection chip to serve as a chip bridge to achieve electrical connection between the subsequent chipset and the first chip.

[0123] In this embodiment, the step of bonding the interconnection chip 30 on the bottom interconnection structure layer 310 includes: forming a first conductive bump 11 between the bottom interconnection structure layer 310 and the interconnection chip 30; and achieving bonding between the interconnection chip 30 and the bottom interconnection structure layer 310 through the first conductive bump 11.

[0124] In this embodiment, the material of the first conductive bump 11 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the first conductive bump 11 is tin.

[0125] In a specific implementation, the first conductive bump 11 may be formed on the bonding surface 301 of the interconnection chip 30, or the first conductive bump 11 may be formed on the bottom interconnection structure layer 310; then, the bonding between the bottom interconnection structure layer 310 and the interconnection chip 30 is achieved through the first conductive bump 11; or, a first sub-conductive bump (not shown) may be formed on the bonding surface 301, and a second sub-conductive bump may be formed on the bottom interconnection structure layer 310; bonding between the first sub-conductive bump and the second sub-conductive bump may be achieved.

[0126] In this embodiment, the packaging method further includes: after bonding between the interconnection chip 30 and the bottom interconnection structure layer 310 is achieved through the first conductive bump 11 , a first sealing layer 305 is formed between the interconnection chip 30 and the bottom interconnection structure layer 310 to seal the first conductive bump 11 .

[0127] The first sealing layer 305 fills the gap between the interconnection chip 30 and the bottom interconnection structure layer 310 to achieve sealing of the first conductive bump 11. As an example, an underfill process is used to form the first sealing layer 305. As an example, the material of the first sealing layer 305 is epoxy resin.

[0128] refer to Figure 6 , the back side 302 of the interconnection chip 30 is thinned.

[0129] The back side 302 of the interconnection chip 30 is thinned to reduce the thickness of the interconnection chip 30, which is beneficial to reducing the thickness of the subsequent top interconnection structure layer and the packaging structure, thereby simplifying the packaging structure and facilitating the thinning of the device; in addition, after the packaging structure is subsequently bonded to the packaging substrate, since the interconnection chip 30 is thinner, it is beneficial to shorten the distance between the first chip and the chipset and the packaging substrate, thereby facilitating the heat dissipation of the packaging structure and improving the performance of the packaging structure.

[0130] In the present embodiment, since the back side 302 of the interconnection chip 30 is thinned after the interconnection chip 30 is bonded on the bottom interconnection structure layer 310, the interconnection chip 30 is fixed on the bottom interconnection structure layer 310, which is conducive to thinning the interconnection chip 30 to the thickness required by the process and is conducive to reducing the process difficulty of thinning the back side 302 of the interconnection chip 30, thereby facilitating the thinning of the interconnection chip 30 and the packaging structure.

[0131] In this embodiment, in the step of thinning the back surface 302 of the interconnection chip 30, the base layer is thinned. In a specific implementation, in the step of thinning the base layer, the base layer can be removed to further reduce the thickness of the interconnection chip 30, and the interconnection chip 30 only retains the conductive structure layer, thereby ensuring the interconnection function of the interconnection chip 30; or, a part of the base layer is removed to reduce the probability of damaging the conductive structure layer, thereby reducing the process risk.

[0132] In this embodiment, after the back side 302 of the interconnection chip 30 is thinned, the thickness of the remaining interconnection chip 30 should not be too small or too large. If the thickness of the remaining interconnection chip 30 is too small, the thickness of the back side 302 of the interconnection chip 30 is too large, which is easy to increase the risk of damage to the conductive structure layer and the process risk; if the thickness of the remaining interconnection chip 30 is too large, the thickness of the back side 302 of the interconnection chip 30 is too small, which is easy to cause the thickness reduction effect of the interconnection chip 30 to be not obvious. For this reason, in this embodiment, after the back side 302 of the interconnection chip 30 is thinned, the thickness of the remaining interconnection chip 30 is 2μm to 15μm.

[0133] In this embodiment, an etching process is used to thin the back side 302 of the interconnection chip 30. The etching process has high process precision, which is conducive to improving the control precision of the thickness of the thinning process and reducing the probability of causing damage to the interconnection structure layer or other film layer structures.

[0134] As an example, the etching process may include an anisotropic dry etching process. The anisotropic dry etching process has high etching precision and low etching rate. In other embodiments, the etching process may also be a wet etching process, or a process combining the dry etching process and the wet etching process.

[0135] refer to Figure 7 After the back side 302 of the interconnect chip 30 is thinned, a top interconnect structure layer 320 is formed on the bottom interconnect structure layer 310 , and the top interconnect structure layer 320 is electrically connected to the bottom interconnect structure layer 310 .

[0136] The top interconnection structure layer 320 is electrically connected to the bottom interconnection structure layer 310, so that the top interconnection structure layer 320 and the interconnection chip 30 can be electrically connected through the bottom interconnection structure layer 310. The top interconnection structure layer 320 is also used to provide a process operation platform for the subsequent bonding between the chipset and the first chip.

[0137] In this embodiment, in the step of forming the top interconnect structure layer 320 , the top interconnect structure layer 320 is formed on the interconnect chip 30 and on the bottom interconnect structure layer 310 exposed from the interconnect chip 30 .

[0138] Among them, the top interconnection structure layer 320 located on the bottom interconnection structure layer 310 exposed by the interconnection chip 30 is used to contact the bottom interconnection structure layer 310 to achieve electrical connection with the bottom interconnection structure layer 310; the top interconnection structure layer 320 is also formed on the back side 302 of the interconnection chip 30, so as to provide a bonding surface with good consistency for the subsequent bonding of the first chip and the chipset, and also to facilitate the first chip, the chipset, and the interconnection chip 30 to have overlapping areas along the projection plane parallel to the carrier substrate 100, so that the interconnection chip 30 can play the role of a chip interconnection bridge.

[0139] It should be noted that, in this embodiment, the top interconnection structure layer 320 is also formed on the interconnection chip 30 . The top interconnection structure layer 320 located on the top of the interconnection chip 30 is not directly electrically connected to the interconnection chip 30 , but is electrically connected to the interconnection chip 30 through the bottom interconnection structure layer 310 .

[0140] In this embodiment, the back side 302 of the interconnection chip 30 is thinned to reduce the thickness of the interconnection chip 30 , which is beneficial to reduce the thickness of the top interconnection structure layer 320 , thereby facilitating the thinning and miniaturization of the packaging structure.

[0141] In this embodiment, the top interconnection structure layer 320 is a second rewiring structure layer. The second rewiring structure layer is conducive to redistributing the connection ends of the subsequent first chip and the chipset, thereby facilitating the subsequent interconnection between the top interconnection structure layer 320 and the first chip, and between the top interconnection structure layer 320 and the chipset through the second conductive bumps, and is conducive to reducing the pitch of the second conductive bumps and increasing the density of the second conductive bumps, thereby improving the interconnection performance between the top interconnection structure layer 320 and the first chip, and between the top interconnection structure layer 320 and the chipset.

[0142] Specifically, the second redistribution structure layer may include one or more second redistribution layers. Specifically, the material of the second redistribution layer is a conductive material. As an example, the material of the second redistribution structure is a metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0143] It should also be noted that, in each second redistribution layer, a dielectric material is formed between the side portions of the second redistribution layers to achieve isolation between the second redistribution layers.

[0144] refer to Figure 8 , a first chip 10 and a chipset 200 are provided.

[0145] The first chip 10 is used to be subsequently bonded to the top interconnection structure layer 320 , and is electrically connected to the chipset 200 through the top interconnection structure layer 320 , the bottom interconnection structure layer 310 and the interconnection chip 30 .

[0146] In this embodiment, the first chip 10 is a first logic chip, which is used to perform logic control on the chipset. Specifically, the first logic chip can be a CPU chip, a GPU chip or a SoC chip.

[0147] Specifically, the first chip 10 includes a first surface (not labeled) and a second surface (not labeled) opposite to each other, wherein the first surface is used for subsequent bonding to the top interconnect structure layer 320 .

[0148] In this embodiment, the first surface is the chip front side of the first chip 10, and the second surface is the chip back side of the first chip 10. The chip front side of the first chip 10 refers to the side of the first chip 10 facing the device, and the chip back side of the first chip 10 refers to the side of the first chip 10 facing away from the device.

[0149] In this embodiment, one or more metal layers (not shown) are formed on the front side of the first chip 10 so as to bond the first chip 10 on the top interconnection structure layer 320, and the front side of the first chip 10 is arranged opposite to the top interconnection structure layer 320, thereby achieving electrical connection with the top interconnection structure layer 320 through the metal layer on the front side of the first chip 10.

[0150] The chipset 200 is used to be subsequently bonded to the top interconnect structure layer 320 and electrically connected to the top interconnect structure layer 320, and then the electrical connection between the chipset 200 and the first chip 10 is achieved through the top interconnect structure layer 320, the bottom interconnect structure layer 310 and the interconnect chip 30, thereby forming a corresponding packaging structure to achieve corresponding functions.

[0151] In this embodiment, the chipset 200 includes a third surface 203 and a fourth surface 204 that are opposite to each other.

[0152] Specifically, in this embodiment, the third surface 203 is used for subsequent bonding to the top interconnection structure layer 320 , thereby achieving electrical connection between the chipset 200 and the top interconnection structure layer 320 .

[0153] In this embodiment, the chipset 200 includes a plurality of second chips 20 stacked in a direction perpendicular to the third surface 203 and the fourth surface 204 , and the adjacent second chips 20 in the direction perpendicular to the third surface 203 and the fourth surface 204 are electrically connected.

[0154] In this embodiment, in the chipset 200, a plurality of second chips 20 stacked in the longitudinal direction (ie, perpendicular to the third surface 203 and the fourth surface 204) form a high-bandwidth memory storage structure. By adopting the HBM structure, it is helpful to meet the requirements for higher information transmission speed.

[0155] In this embodiment, the adjacent second chips 20 are electrically connected along the direction perpendicular to the third surface 203 and the fourth surface 204, thereby realizing electrical integration between the second chips 20. Specifically, in this embodiment, the third conductive bumps 13 are formed between the adjacent second chips 20 along the direction perpendicular to the third surface 203 and the fourth surface 204, and the electrical connection between the adjacent second chips 20 is realized through the third conductive bumps 13.

[0156] In this embodiment, the material of the third conductive bump 13 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the third conductive bump 13 is tin.

[0157] In this embodiment, along a direction perpendicular to the third surface 203 and the fourth surface 204 , a second chip 20 closest to the third surface 203 is used as the bottom chip 21 , and the remaining second chips 20 are used as the top chips 22 .

[0158] In this embodiment, the bottom chip 21 is a second logic chip, which is used to control the top chip 22 .

[0159] In this embodiment, the top chip 22 is a memory chip, such as a DRAM chip. In this embodiment, the number of the top chips 22 can be one or more. In this embodiment, four top chips 22 are used as an example for description. In other embodiments, the number of top chips can also be other numbers.

[0160] Specifically, in this embodiment, the bottom chip 21 is used as a logic control chip in the chipset 200 to control the memory chip.

[0161] refer to Fig. 9 The first chip 10 and the chipset 200 are bonded on the top interconnect structure layer 320, and the first chip 10 and the chipset 200 are electrically connected to the top interconnect structure layer 320 respectively; the chipset 200 and the first chip 10 are electrically connected through the top interconnect structure layer 320, the bottom interconnect structure layer 310 and the interconnect chip 30.

[0162] The first chip 10 and the chipset 200 are bonded on the top interconnect structure layer 320 , and the first chip 10 and the chipset 200 are electrically connected to the top interconnect structure layer 320 , respectively, so that the electrical connection between the first chip 10 and the chipset 200 can be achieved through the top interconnect structure layer 320 , the bottom interconnect structure layer 310 and the interconnect chip 30 .

[0163] Furthermore, in this embodiment, after bonding the interconnection chip 30 and before forming the top interconnection structure layer 320, the back side 302 of the interconnection chip 30 is thinned, thereby reducing the thickness of the interconnection chip 30, which is beneficial to reducing the thickness of the top interconnection structure layer 320 and the packaging structure, thereby simplifying the packaging structure and facilitating the thinning of the device.

[0164] Moreover, in this embodiment, after the packaging structure is subsequently bonded to the packaging substrate, since the interconnection chip 30 is thinner, it is beneficial to shorten the distance between the first chip 10 and the chipset 200 and the packaging substrate, which is beneficial to the heat dissipation of the packaging structure and improves the performance of the packaging structure.

[0165] In addition, after forming the top interconnect structure layer 320 and before bonding the first chip 10 and the chipset 200 on the top interconnect structure layer 320, the electrical connection performance of the top interconnect structure layer 320, the bottom interconnect structure layer 310 and the interconnect chip 30 can be tested, which is beneficial to improving the packaging yield after bonding the first chip 10 and the chipset 200.

[0166] In this embodiment, the first chip 10 and the chipset 200 are electrically connected through the top interconnection structure layer 320, the bottom interconnection structure layer 310 and the interconnection chip 30. Compared with the solution of realizing the electrical connection between the first chip and the chipset only through any one or both of the top interconnection structure layer and the bottom interconnection structure layer, in this embodiment, the interconnection chip 30 is used to increase the number of connection lines per unit width, thereby improving the interconnection density and communication speed between the first chip 10 and the chipset 200, and improving the performance of the packaging structure.

[0167] Specifically, in this embodiment, the third surface 203 of the chipset 200 is bonded to the top interconnect structure layer 320 .

[0168] More specifically, in this embodiment, the bottom chip 21 in the chipset 200 is bonded to the top interconnection structure layer 320 , so that the bottom chip 21 and the top interconnection structure layer 320 are electrically connected.

[0169] In this embodiment, the top interconnection structure layer 320 is also formed on the back side 302 of the interconnection chip 30; in the step of bonding the first chip 10 and the chipset 200 on the top interconnection structure layer 320, the first chip 10 and the chipset 200 have overlapping areas with the interconnection chip 30 along a projection plane parallel to the carrier substrate 100.

[0170] That is to say, at least part of the first chip 10 is located on the top interconnection structure layer 320 on the top of the interconnection chip 30, and at least part of the chipset 200 is located on the top interconnection structure layer 320 on the top of the interconnection chip 30, that is, the first chip 10 and the chipset 200 are adjacent, and in the direction parallel to the carrier substrate 100, the distances between the first chip 10 and the chipset 200, between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30 are relatively close, which is beneficial to saving the area of ​​the packaging structure and improving the integration per unit area.

[0171] Accordingly, in this embodiment, the first chip 10 is electrically connected to the top interconnection structure layer 320 located on the top of the interconnection chip 30 , and the chipset 200 is electrically connected to the top interconnection structure layer 320 located on the top of the interconnection chip 30 .

[0172] In this embodiment, the step of bonding the first chip 10 and the chipset 200 on the top interconnect structure layer 320 includes: forming a second conductive bump 12 between the top interconnect structure layer 320 and the first chip 10, and between the top interconnect structure layer 320 and the chipset 200; and bonding between the first chip 10 and the top interconnect structure layer 320, and between the chipset 200 and the top interconnect structure layer 320 is achieved through the second conductive bump 12.

[0173] Specifically, in this embodiment, the second conductive bumps 12 are formed between the top interconnect structure layer 320 and the first chip 10 , and between the top interconnect structure layer 320 and the third surface 203 of the chipset 200 .

[0174] In this embodiment, the second conductive bump 12 is formed between the bottom chip 21 and the top interconnection structure layer 320 of the chipset 200 to achieve electrical connection between the bottom chip 21 and the top interconnection structure layer 320 .

[0175] In this embodiment, the material of the second conductive bump 12 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 12 is tin.

[0176] In a specific implementation, a second conductive bump 12 may be formed on the top interconnect structure layer 320, or a second conductive bump 12 may be formed on the first chip 10 and the chipset 200; thereafter, bonding between the first chip 10 and the top interconnect structure layer 320, and between the chipset 200 and the top interconnect structure layer 320 may be achieved through the second conductive bump 12; alternatively, a third sub-conductive bump (not shown) may be formed on the top interconnect structure layer 320, and a fourth sub-conductive bump (not shown) may be formed on the first chip 10 and the chipset 200; bonding between the third sub-conductive bump and the fourth sub-conductive bump may be achieved.

[0177] In this embodiment, the packaging method also includes: after bonding between the first chip 10 and the top interconnect structure layer 320, and between the chipset 200 and the top interconnect structure layer 320 is achieved through the second conductive bump 12, a second sealing layer 306 for sealing the second conductive bump 12 is formed between the first chip 10 and the top interconnect structure layer 320, and between the chipset 200 and the top interconnect structure layer 320.

[0178] The second sealing layer 306 fills the gaps between the first chip 10 and the top interconnect structure layer 320 , and between the chip set 200 and the top interconnect structure layer 320 , so as to seal the second conductive bumps 12 .

[0179] As an example, an underfill process is used to form the second sealing layer 306. As an example, the material of the second sealing layer 306 is epoxy resin.

[0180] refer to Fig.10 In this embodiment, the packaging method further includes: after bonding the first chip 10 and the chipset 200 on the top interconnect structure layer 320 , forming a packaging layer 110 covering the first chip 10 and the chipset 200 on the top interconnect structure layer 320 .

[0181] The packaging layer 110 is used to realize the packaging integration between the first chip 10 and the chipset 200 and the top interconnection structure layer 320. The packaging layer 110 can also play the role of insulation, sealing and moisture-proof, which is beneficial to improve the reliability of the packaging structure.

[0182] The packaging layer 110 also covers the top of the first chip 10 and the chipset 200 , thereby improving the protection of the first chip 10 and the chipset 200 and further improving the reliability of the packaging structure.

[0183] As an embodiment, the material of the encapsulation layer 110 is a molding material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. In other embodiments, the encapsulation layer can also use other suitable encapsulation materials.

[0184] As an example, the step of forming the packaging layer 110 includes: forming a packaging material layer (not shown) on the top interconnect structure layer 320 to cover the top of the first chip 10 and the chipset 200; planarizing the packaging material layer, and the remaining packaging material layer is used as the packaging layer 110.

[0185] As an example, a plastic encapsulation process is used to form the encapsulation material layer. In other embodiments, based on actual process requirements, other suitable processes may also be used to form the encapsulation material layer.

[0186] As an example, a grinding process is used to planarize the packaging material layer, thereby improving the flatness of the top surface of the packaging layer 110 and facilitating subsequent processes.

[0187] refer to Fig.11 In this embodiment, the packaging method further includes: after bonding the first chip 10 and the chipset 200 on the top interconnect structure layer 320, removing the carrier substrate 100, thereby exposing the side of the bottom interconnect structure layer 310 opposite to the top interconnect structure layer 320, so as to subsequently realize the electrical connection between the bottom interconnect structure layer 310 and the external circuit, and then realize the electrical connection between the packaging structure and the external circuit through the bottom interconnect structure layer 310.

[0188] Specifically, in this embodiment, after the encapsulation layer 110 is formed, the carrier substrate 100 is removed so that the carrier substrate 100 can provide a process operation platform for forming the encapsulation layer 110 .

[0189] In this embodiment, the step of removing the carrier substrate 100 includes: removing the temporary bonding layer 109 .

[0190] More specifically, in this embodiment, a debonding process is performed to remove the carrier substrate 100 and the temporary bonding layer 109 , thereby reducing the difficulty of removing the carrier substrate 100 .

[0191] refer to Fig.12 In this embodiment, the packaging method further includes: after removing the carrier substrate 100 , forming a fourth conductive bump 14 on the opposite side of the bottom interconnect structure layer 310 and the top interconnect structure layer 320 , and the fourth conductive bump 14 is electrically connected to the bottom interconnect structure layer 310 .

[0192] Subsequent steps also include: providing a packaging substrate; bonding the bottom interconnect structure layer 310 and the top interconnect structure layer 320 on the packaging substrate, and the fourth conductive bump 14 is used to achieve electrical connection between the bottom interconnect structure layer 310 and the packaging substrate.

[0193] In this embodiment, the fourth conductive bump 14 is a solder ball. As an embodiment, the material of the solder ball includes tin.

[0194] Specifically, the solder ball is C4, which has excellent electrical and thermal properties. Moreover, under the condition of the same solder ball pitch, C4 has a larger number of I / Os. In addition, C4 is also suitable for mass production and is conducive to significantly reducing size and weight. In other embodiments, the material of the fourth conductive bump includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0195] Continue to refer Fig.12 In this embodiment, the packaging method further includes: providing a packaging substrate 300; after removing the carrier substrate 100, bonding the bottom interconnection structure layer 310 and the top interconnection structure layer 320 on the opposite side to the packaging substrate 300.

[0196] The packaging substrate 300 is used to realize packaging integration and electrical integration between the chipset 200, the first chip 10 and the interconnection chip 30. In this embodiment, the packaging substrate 300 is a PCB (Printed Circuit Board).

[0197] Specifically, in this embodiment, the bonding between the bottom interconnect structure layer 310 and the packaging substrate 300 is achieved through the fourth conductive bumps 14 .

[0198] In this embodiment, the packaging method further includes: after bonding between the bottom interconnect structure layer 310 and the packaging substrate 300 is achieved, forming a third sealing layer 205 between the bottom interconnect structure layer 310 and the packaging substrate 300 to seal the fourth conductive bump 14 .

[0199] The third sealing layer 205 fills the gap between the bottom interconnect structure layer 310 and the package substrate 300 to seal the fourth conductive bump 14. As an example, the third sealing layer 205 is formed by a bottom filling process. As an example, the material of the third sealing layer 205 is epoxy resin.

[0200] In this embodiment, the packaging method further includes: forming a fifth conductive bump 15 on a surface of the packaging substrate 300 opposite to the first chip 10 and the chipset 200 , wherein the fifth conductive bump 15 is used to achieve electrical connection between the packaging substrate 300 and an external circuit.

[0201] In this embodiment, the fifth conductive bump 15 is a solder ball. As an example, the material of the fifth conductive bump 15 is tin.

[0202] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: a bottom interconnect structure layer including a connection region; An interconnection chip is bonded to the bottom interconnection structure layer of the connection area, and the interconnection chip is electrically connected to the bottom interconnection structure layer; the interconnection chip comprises a bonding surface and a back surface opposite to each other, the bonding surface is arranged opposite to the bottom interconnection structure layer, and the back surface is thinned; A top interconnect structure layer, located on the bottom interconnect structure layer and electrically connected to the bottom interconnect structure layer; A first chip is bonded to the top interconnect structure layer and electrically connected to the top interconnect structure layer; A chipset, located on the top interconnect structure layer bonded to the side of the first chip and electrically connected to the top interconnect structure layer; The chipset is electrically connected to the first chip via the top interconnection structure layer, the bottom interconnection structure layer and the interconnection chip.

2. The packaging structure according to claim 1, characterized in that: The top interconnect structure layer is located on the interconnect chip and on the bottom interconnect structure layer exposed by the interconnect chip; On a projection plane parallel to the bottom interconnect structure layer, the first chip and the chipset have overlapping areas with the interconnect chip; the first chip is electrically connected to the top interconnect structure layer located on the top of the interconnect chip, and the chipset is electrically connected to the top interconnect structure layer located on the top of the interconnect chip.

3. The packaging structure according to claim 1, characterized in that: The bottom interconnect structure layer is a first redistribution structure layer; the top interconnect structure layer is a second redistribution structure layer.

4. The packaging structure according to claim 1, characterized in that: The interconnect chip comprises a base layer and a conductive structure layer on the base layer, the side of the base layer opposite to the conductive structure layer is used as the back side, and the side of the conductive structure layer opposite to the base layer is used as the bonding surface; or, The interconnection chip only includes a conductive structure layer, a side of the conductive structure layer opposite to the bottom interconnection structure layer is used as the bonding surface, and a side of the conductive structure layer opposite to the bottom interconnection structure layer is used as the back surface.

5. The packaging structure according to claim 4, characterized in that: The conductive structure layer is a third redistribution structure layer.

6. The packaging structure according to claim 1, 4 or 5, characterized in that: The interconnection chip has a thickness of 2 μm to 15 μm.

7. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a first conductive bump located between the bottom interconnect structure layer and the interconnect chip; and a second conductive bump located between the first chip and the top interconnect structure layer, and between the chipset and the top interconnect structure layer.

8. The packaging structure according to claim 1 or 2, characterized in that: The packaging structure further includes: a packaging layer located on the top interconnect structure layer and covering the first chip and the chipset.

9. The packaging structure according to claim 1, characterized in that: The chipset includes a plurality of second chips stacked in a vertical direction, and the second chips adjacent to each other in the vertical direction are electrically connected; the first chip is a logic chip, and the chipset is a high-bandwidth memory chipset.

10. A packaging method, characterized in that: include: Providing a carrier substrate, including a carrier surface; forming a bottom interconnect structure layer on the bearing surface, wherein the bottom interconnect structure layer includes a connection area; Providing an interconnect chip, including a bonding surface and a back surface facing each other; Bonding an interconnection chip on the bottom interconnection structure layer of the connection area, wherein the bonding surface is arranged opposite to the bottom interconnection structure layer, and the interconnection chip is electrically connected to the bottom interconnection structure layer; Performing a thinning process on the back side of the interconnect chip; After thinning the back side of the interconnection chip, a top interconnection structure layer is formed on the bottom interconnection structure layer, and the top interconnection structure layer is electrically connected to the bottom interconnection structure layer; Providing a first chip and a chipset; A first chip and a chipset are bonded on the top interconnect structure layer, and the first chip and the chipset are electrically connected to the top interconnect structure layer respectively; the chipset and the first chip are electrically connected via the top interconnect structure layer, the bottom interconnect structure layer and the interconnect chip.

11. The packaging method according to claim 10, characterized in that: In the step of forming a top interconnect structure layer, the top interconnect structure layer is formed on the interconnect chip and on the bottom interconnect structure layer exposed by the interconnect chip; In the step of bonding the first chip and the chipset on the top interconnection structure layer, the first chip and the chipset have overlapping areas with the interconnection chip along a projection plane parallel to the carrier substrate; the first chip is electrically connected to the top interconnection structure layer located on the top of the interconnection chip, and the chipset is electrically connected to the top interconnection structure layer located on the top of the interconnection chip.

12. The packaging method according to claim 10, characterized in that: In the step of providing an interconnection chip, the interconnection chip comprises a base layer and a conductive structure layer located on the base layer, a side of the base layer opposite to the conductive structure layer is used as the back side, and a side of the conductive structure layer opposite to the base layer is used as the bonding surface; In the step of thinning the back side of the interconnection chip, the base layer is thinned.

13. The packaging method according to claim 12, characterized in that: In the step of thinning the base layer, the base layer is removed, or a portion of the thickness of the base layer is removed.

14. The packaging method according to claim 10, characterized in that: The back side of the interconnection chip is thinned by using an etching process.

15. The packaging method according to claim 10, characterized in that: After the back side of the interconnection chip is thinned, the remaining thickness of the interconnection chip is 2 μm to 15 μm.

16. The packaging method according to claim 10, characterized in that: The packaging method further comprises: after bonding the first chip and the chipset on the top interconnect structure layer, removing the carrier substrate.

17. The packaging method according to claim 10, characterized in that: The bottom interconnect structure layer is a first redistribution structure layer; the top interconnect structure layer is a second redistribution structure layer.

18. The packaging method according to claim 10, characterized in that: The step of bonding the interconnect chip on the bottom interconnect structure layer comprises: forming a first conductive bump between the bottom interconnect structure layer and the interconnect chip; and achieving bonding between the interconnect chip and the bottom interconnect structure layer through the first conductive bump; The step of bonding the first chip and the chipset on the top interconnect structure layer includes: forming a second conductive bump between the top interconnect structure layer and the first chip, and between the top interconnect structure layer and the chipset; and achieving bonding between the first chip and the top interconnect structure layer, and between the chipset and the top interconnect structure layer through the second conductive bump.

19. The packaging method according to claim 10 or 11, characterized in that: The packaging method further comprises: after bonding the first chip and the chipset on the top interconnect structure layer, forming a packaging layer covering the first chip and the chipset on the top interconnect structure layer.

20. The packaging method according to claim 10, characterized in that: The chipset includes a plurality of second chips stacked in a direction perpendicular to the carrier substrate, and the adjacent second chips in the direction perpendicular to the carrier substrate are electrically connected; the first chip is a logic chip, and the chipset is a high-bandwidth memory chipset.

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