Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, and the packaging method comprises the steps: providing a bearing substrate which comprises a bearing surface; providing a first chip, wherein the first chip comprises a first surface and a second surface which are opposite; a chip set is provided, the chip set comprises a third face and a fourth face which are opposite to each other, the chip set comprises a plurality of second chips stacked in the direction perpendicular to the bearing substrate, and the adjacent second chips in the direction perpendicular to the bearing substrate are electrically connected; attaching the first chip to the bearing substrate, wherein the first surface is opposite to the bearing surface; the chip set is attached to the bearing substrate, and the third face and the bearing face are oppositely arranged; providing an interconnection chip, wherein the interconnection chip comprises a bonding surface and a back surface which are opposite to each other; an interconnection chip is bonded on the first chip and the chip set, the bonding surface is arranged opposite to the second surface and the fourth surface, and the interconnection chip is electrically connected with the chip set and the first chip; and after an interconnection chip is bonded on the first chip and the chip set, thinning processing is carried out on the back surface of the interconnection chip. According to the embodiment of the invention, the performance of the packaging structure is optimized.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor packaging, and in particular to a packaging structure and a packaging method. Background Art

[0002] Conventional chip manufacturing technologies are being pushed to their limits in terms of the size of a single chip. However, applications are eager to use the latest technology to achieve the capabilities of large-scale integrated circuits, and achieving high-speed and small-volume interconnections between chips is a major challenge.

[0003] One current solution is to use a smaller integrated circuit of a silicon bridge (Si Bridge) chip embedded in a silicon substrate to interconnect chips through the silicon bridge chip, thereby providing a heterogeneous chip package.

[0004] However, the performance of the current packaging structure still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method to optimize the performance of the packaging structure.

[0006] To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a first chip, including a first surface and a second surface relative to each other; a chipset, located on the side of the first chip, the chipset including a plurality of second chips stacked in a vertical direction, and the second chips adjacent to each other in the vertical direction are electrically connected; the chipset including a third surface and a fourth surface relative to each other, and the first surface and the third surface face the same direction; an interconnection chip, the interconnection chip including a bonding surface and a back surface opposite to each other, the interconnection chip is located on the first chip and the chipset, the bonding surface is arranged opposite to the second surface and the fourth surface, and the interconnection chip electrically connects the chipset and the first chip; the back surface of the interconnection chip is thinned.

[0007] Optionally, the packaging structure further includes: a packaging layer located on the side of the first chip and the chipset, and the packaging layer covers the side walls of the first chip and the chipset.

[0008] Optionally, the interconnection chip includes a base layer and an interconnection structure layer located on the base layer, the side of the base layer opposite to the interconnection structure layer is used as the back side, and the side of the interconnection structure layer opposite to the base layer is used as the bonding side; or, the interconnection chip only includes the interconnection structure layer, the side of the interconnection structure layer opposite to the first chip and the chipset is used as the bonding side, and the side of the interconnection structure layer opposite to the first chip and the chipset is used as the back side.

[0009] Optionally, the interconnect structure layer is a redistribution structure layer.

[0010] Optionally, the interconnection chip has a thickness of 2 μm to 15 μm.

[0011] Optionally, the packaging structure further includes: a first conductive bump located between the first chip and the interconnection chip, and between the chipset and the interconnection chip.

[0012] Optionally, the packaging structure also includes: a second conductive bump located on the second and fourth surfaces exposed by the interconnected chip, the second conductive bump being electrically connected to the first chip and the chipset respectively, and the height of the second conductive bump being flush with or higher than the height of the back side of the interconnected chip.

[0013] Optionally, the first chip is a logic chip, and the chipset is a high-bandwidth memory chipset.

[0014] Correspondingly, an embodiment of the present invention also provides a packaging method, comprising: providing a carrier substrate, the carrier substrate comprising a carrier surface; providing a first chip, comprising a first surface and a second surface relative to each other; providing a chipset, the chipset comprising a third surface and a fourth surface relative to each other, the chipset comprising a plurality of second chips stacked in a direction perpendicular to the carrier substrate, and the adjacent second chips in a direction perpendicular to the carrier substrate are electrically connected; attaching the first chip to the carrier substrate, the first surface being arranged opposite to the carrier surface; attaching the chipset to the carrier substrate, the third surface being arranged opposite to the carrier surface; providing an interconnection chip, the interconnection chip comprising a bonding surface and a back surface opposite to each other; bonding the interconnection chip to the first chip and the chipset, the bonding surface being arranged opposite to the second surface and the fourth surface, and the interconnection chip electrically connecting the chipset and the first chip; after bonding the interconnection chip to the first chip and the chipset, thinning the back surface of the interconnection chip.

[0015] Optionally, in the step of providing an interconnect chip, the interconnect chip includes a base layer and an interconnect structure layer located on the base layer, the side of the base layer opposite to the interconnect structure layer is used as the back side, and the side of the interconnect structure layer opposite to the base layer is used as the bonding side; in the step of thinning the back side of the interconnect chip, the base layer is thinned.

[0016] Optionally, in the step of thinning the base layer, the base layer is removed, or a portion of the thickness of the base layer is removed.

[0017] Optionally, the interconnect structure layer is a redistribution structure layer.

[0018] Optionally, the packaging method also includes: after laminating the first chip to the carrier substrate and laminating the chipset to the carrier substrate, and before bonding the interconnection chip to the first chip and chipset, forming a packaging layer on the carrier surface of the side of the first chip and the chipset, the packaging layer covering the side walls of the first chip and chipset and exposing the second surface and the fourth surface; in the step of bonding the interconnection chip to the first chip and chipset, bonding the interconnection chip to the first chip and chipset and the packaging layer.

[0019] Optionally, the step of bonding the interconnection chip on the first chip and the chipset includes: forming a first conductive bump between the first chip and the interconnection chip, and between the chipset and the interconnection chip, and achieving bonding between the first chip and the interconnection chip, and between the chipset and the interconnection chip through the first conductive bump.

[0020] Optionally, an etching process is used to thin the back side of the interconnection chip.

[0021] Optionally, after the back side of the interconnection chip is thinned, the remaining thickness of the interconnection chip is 2 μm to 15 μm.

[0022] Optionally, the packaging method further includes: removing the carrier substrate after the thinning process.

[0023] Optionally, the packaging method also includes: after the thinning process and before removing the carrier substrate, forming second conductive bumps on the second and fourth surfaces exposed by the interconnected chip, the second conductive bumps being electrically connected to the first chip and the chipset, respectively, and the height of the second conductive bumps being flush with or higher than the height of the back side of the interconnected chip.

[0024] Optionally, the packaging method further includes: providing a packaging substrate; after removing the carrier substrate, bonding the second surface of the first chip and the fourth surface of the chipset to the packaging substrate.

[0025] Optionally, the first chip is a logic chip, and the chipset is a high-bandwidth memory chipset.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] The packaging structure provided by the embodiment of the present invention further comprises an interconnection chip, wherein the interconnection chip comprises a bonding surface and a back surface facing each other, the interconnection chip is located on the first chip and the chipset, the bonding surface is arranged opposite to the second surface and the fourth surface, and the interconnection chip electrically connects the chipset and the first chip, thereby realizing electrical connection between the chipset and the first chip through the interconnection chip; and the back surface of the interconnection chip is thinned, thereby reducing the thickness of the interconnection chip, which is beneficial to simplifying the packaging structure and facilitating the thinning of the device, and after the packaging structure is bonded to the packaging substrate, since the interconnection chip is thinner, it is beneficial to shorten the distance between the first chip and the chipset and the packaging substrate, which is beneficial to the heat dissipation of the packaging structure and improves the performance of the packaging structure.

[0028] The packaging method provided by the embodiment of the present invention bonds an interconnection chip to the first chip and the chipset, the bonding surface is arranged opposite to the second surface and the fourth surface, and the interconnection chip electrically connects the chipset and the first chip, thereby realizing electrical connection between the chipset and the first chip through the interconnection chip; and after the interconnection chip is bonded to the second surface and the fourth surface, the back surface of the interconnection chip is thinned to reduce the thickness of the interconnection chip, which is beneficial to simplifying the packaging structure and facilitating the thinning of the device. Moreover, after the packaging structure is subsequently bonded to the packaging substrate, since the interconnection chip is thinner, it is beneficial to shorten the distance between the first chip and the chipset and the packaging substrate, which is beneficial to the heat dissipation of the packaging structure and improves the performance of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention;

[0030] Figures 2 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention. DETAILED DESCRIPTION

[0031] As can be seen from the background technology, the performance of the current packaging structure needs to be improved.

[0032] In order to solve the technical problem, an embodiment of the present invention provides a packaging structure, wherein an interconnection chip is also provided, wherein the interconnection chip includes a bonding surface and a back surface facing each other, the interconnection chip is located on the first chip and the chipset, the bonding surface is arranged opposite to the second surface and the fourth surface, and the interconnection chip is electrically connected to the chipset and the first chip, so that the electrical connection between the chipset and the first chip is achieved through the interconnection chip; and the back surface of the interconnection chip is thinned to reduce the thickness of the interconnection chip, which is conducive to simplifying the packaging structure and facilitating the thinning of the device, and after the packaging structure is bonded to the packaging substrate, since the interconnection chip is thinner, it is conducive to shortening the distance between the first chip and the chipset and the packaging substrate, which is conducive to the heat dissipation of the packaging structure and improves the performance of the packaging structure.

[0033] In order to solve the technical problem, an embodiment of the present invention further provides a packaging method, wherein an interconnection chip is bonded to the first chip and the chipset, the bonding surface is arranged opposite to the second surface and the fourth surface, and the interconnection chip is electrically connected to the chipset and the first chip, thereby realizing electrical connection between the chipset and the first chip through the interconnection chip; and after the interconnection chip is bonded to the second surface and the fourth surface, the back side of the interconnection chip is thinned to reduce the thickness of the interconnection chip, which is beneficial to simplifying the packaging structure and facilitating the thinning of the device. Moreover, after the packaging structure is subsequently bonded to the packaging substrate, since the interconnection chip is thinner, it is beneficial to shorten the distance between the first chip and the chipset and the packaging substrate, which is beneficial to the heat dissipation of the packaging structure and improves the performance of the packaging structure.

[0034] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] refer to Figure 1 , showing a schematic structural diagram of an embodiment of a packaging structure of the present invention.

[0036] like Figure 1As shown, in this embodiment, the packaging structure includes: a first chip 10, including a first surface 101 and a second surface 102 opposite to each other; a chipset 200, located on the side of the first chip 10, the chipset 200 includes a plurality of second chips 20 stacked in a vertical direction, and the second chips 20 adjacent to each other in the vertical direction are electrically connected; the chipset 200 includes a third surface 203 and a fourth surface 204 opposite to each other, and the first surface 101 and the third surface 203 face the same direction; an interconnection chip 30, the interconnection chip 30 includes a bonding surface 301 and a back surface 302 opposite to each other, the interconnection chip 30 is located on the first chip 10 and the chipset 200, the bonding surface 301 is arranged opposite to the second surface 102 and the fourth surface 204, and the interconnection chip 30 is electrically connected to the chipset 200 and the first chip 10; the back surface 302 of the interconnection chip 30 is thinned.

[0037] The first chip 10 is used to realize electrical connection with the chipset 200 through the interconnection chip 30 , so as to realize package integration with the chipset 200 .

[0038] In this embodiment, the first chip 10 is a first logic chip, which is used to perform logic control on the chipset 200. Specifically, the first logic chip can be a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip or a SoC (System on Chip) chip.

[0039] In this embodiment, the first surface 101 is the back surface of the first chip 10, and the second surface 102 is the front surface of the first chip 10. The front surface of the first chip 10 refers to the side of the first chip 10 facing the device, and the back surface of the first chip 10 refers to the side of the first chip 10 facing away from the device.

[0040] In this embodiment, one or more metal layers (not shown) are formed on the front side of the first chip 10 so as to bond the interconnection chip 30 on the first chip 10 and the chipset 200. The bonding surface 301 of the interconnection chip 30 is arranged opposite to the second surface 102. The interconnection chip 30 can be electrically connected to the first chip 10 through the metal layer on the second surface 102 of the first chip 10.

[0041] The chipset 200 is used to achieve bonding with the interconnection chip 30 , and then the chipset 200 is electrically connected to the first chip 10 through the interconnection chip 30 , thereby forming a corresponding packaging structure to achieve corresponding functions.

[0042] Specifically, in this embodiment, the fourth surface 204 is used to achieve bonding with the interconnection chip 30, thereby achieving electrical connection between the chipset 204 and the interconnection chip.

[0043] In this embodiment, the first surface 101 and the third surface 203 face the same direction, and thus the second surface 102 and the fourth surface 204 face the same direction, so that the interconnection chip 30 can be bonded to the second surface 102 and the fourth surface 204 .

[0044] In this embodiment, in the chipset 200, a plurality of second chips 20 stacked in the longitudinal direction form a high bandwidth memory (HBM) structure. By adopting the HBM structure, it is helpful to meet the requirement for higher information transmission speed.

[0045] In this embodiment, adjacent second chips 20 in the vertical direction are electrically connected to achieve electrical integration between the second chips 20. In this embodiment, the vertical direction refers to a direction perpendicular to the second chip 20 and the third surface 203 and the fourth surface 204.

[0046] Specifically, in this embodiment, third conductive bumps 13 are formed between adjacent second chips 20 along the vertical direction, and electrical connection between adjacent second chips 20 is achieved through the third conductive bumps 13 .

[0047] In this embodiment, the material of the third conductive bump 13 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the third conductive bump 13 is tin.

[0048] In this embodiment, in the chipset 200 , the second chips 20 closest to the fourth surface 204 are used as bottom chips 20 a , and the remaining second chips 20 are used as top chips 20 b .

[0049] Accordingly, in the present embodiment, in the chipset 200, the bottom chip 20a is bonded to the interconnection chip 30, so that the bottom chip 20a is electrically connected to the interconnection chip 30. Moreover, the adjacent second chips 20 are electrically connected, so that the top chip 20b can be electrically connected to the interconnection chip 30 through the bottom chip 20a.

[0050] In this embodiment, the bottom chip 20a is a second logic chip for controlling the top chip 20b.

[0051] In this embodiment, the top chip 20b is a memory chip, such as a DRAM chip. In this embodiment, the number of the top chips 20b can be one or more. In this embodiment, the number of the top chips 20b is four as an example for description. In other embodiments, the number of the top chips can also be other numbers.

[0052] Specifically, in this embodiment, the bottom chip 20a is used as a logic control chip in the chipset 200 to control the memory chip.

[0053] In this embodiment, the packaging structure further includes: a packaging layer 110 located on the side of the first chip 10 and the chipset 200 , and the packaging layer 110 covers the side walls of the first chip 10 and the chipset 200 .

[0054] The packaging layer 110 is used to realize the packaging integration between the first chip 10 and the chipset 200 . The packaging layer 110 can also play the role of insulation, sealing and moisture-proof, which is beneficial to improve the reliability of the packaging structure. The packaging layer 110 is also used to provide a process platform for bonding and interconnecting the chips 30 .

[0055] The packaging layer 110 exposes the second surface 102 and the fourth surface 204 so that the interconnection chip 30 can be bonded on the second surface 102 of the first chip 10 and the fourth surface 204 of the chipset 200, so that the interconnection chip 30 is electrically connected to the first chip 10, and the interconnection chip 30 is electrically connected to the chipset 200, thereby realizing electrical connection between the first chip 10 and the chipset 200 through the interconnection chip 30.

[0056] As an embodiment, the material of the encapsulation layer 110 is a molding material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. In other embodiments, the encapsulation layer can also use other suitable encapsulation materials.

[0057] The interconnection chip 30 is used as a chip bridge to realize the interconnection between the first chip 10 and the chipset 200 .

[0058] In this embodiment, the interconnection chip 30 is bonded to the top surfaces of the first chip 10 and the chipset 200 that are adjacent to each other, that is, the interconnection chip 30 also exposes a portion of the surface of the second surface 102 and a portion of the surface of the fourth surface 204, so as to achieve bonding between the second surface 102 and the fourth surface 204 exposed by the interconnection chip 30 and the packaging substrate, thereby achieving electrical connection between the first chip 10 and the chipset 200 and the packaging substrate.

[0059] More specifically, the exposed second surface 102 and fourth surface 204 of the interconnection chip 30 are used to provide the second conductive bumps 12 so as to bond the second conductive bumps 12 to the package substrate.

[0060] The bonding surface 301 is used to achieve bonding with the first chip 10 and the chipset 200 , and further achieve electrical connection between the first chip 10 and the chipset 200 through the interconnection chip 30 .

[0061] The back surface 302 is thinned to reduce the thickness of the interconnection chip 30 .

[0062] In this embodiment, the interconnection chip 30 includes a base layer (not shown) and an interconnection structure layer (not shown) located on the base layer, and the side of the base layer opposite to the interconnection structure layer is used as the back side 302, and the side of the interconnection structure layer opposite to the base layer is used as the bonding surface 301.

[0063] In this embodiment, the base layer is used to provide support for forming an interconnection structure layer, and the side of the base layer opposite to the interconnection structure layer is used for thinning, thereby reducing the thickness of the interconnection chip 30 while ensuring that the interconnection chip 30 is used to achieve the interconnection performance between the first chip 10 and the chipset 200.

[0064] That is, during the formation of the packaging structure, when the back side 302 of the interconnection chip 30 is thinned, only a portion of the base layer is removed to reduce the probability of damaging the interconnection structure layer, thereby reducing process risks.

[0065] In this embodiment, the material of the base layer is silicon.

[0066] The interconnection structure layer is used to electrically connect the first chip 10 and the chipset 200 .

[0067] As an example, the interconnection structure layer is a rewiring structure layer. The rewiring structure layer can redistribute the connection ends of the interconnection chips so as to form first conductive bumps whose density and position meet the process requirements, thereby facilitating the electrical connection between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30 through the first conductive bumps. The first conductive bumps have a small pitch and a high density, which is also conducive to improving the interconnection performance between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30, thereby improving the interconnection performance between the first chip 10 and the chipset 200.

[0068] Correspondingly, in this embodiment, the interconnection structure layer is also used to provide a process platform for forming the first conductive bump.

[0069] Specifically, the redistribution structure layer may include one or more redistribution layers. Specifically, the material of the redistribution layer is a conductive material. As an example, the material of the redistribution structure is a metal, including any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0070] In other embodiments, the base layer can also be completely thinned and removed to further reduce the thickness of the interconnection chip, so that the interconnection chip only retains the interconnection structure layer, thereby ensuring the interconnection function of the interconnection chip. Accordingly, the interconnection chip only includes the interconnection structure layer, and the surface of the interconnection structure layer opposite to the first chip and the chipset is used as the bonding surface, and the surface of the interconnection structure layer opposite to the first chip and the chipset is used as the back surface.

[0071] It should be noted that the thickness of the interconnection chip 30 should not be too small or too large. If the thickness of the remaining interconnection chip 30 is too small, the thickness of the thinning process on the back side 302 of the interconnection chip 30 is too large, which easily increases the risk of damaging the interconnection structure layer; if the thickness of the remaining interconnection chip 30 is too large, the thickness of the thinning process on the back side of the interconnection chip 30 is too small, which easily leads to an insignificant effect of reducing the thickness of the interconnection chip 30. For this reason, in this embodiment, the thickness of the interconnection chip 30 is 2μm to 15μm.

[0072] In this embodiment, the packaging structure further includes: a first conductive bump 11 located between the first chip 10 and the interconnection chip 30 , and between the chipset 200 and the interconnection chip 30 .

[0073] The first conductive bump 11 is used to realize bonding between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30. Specifically, in this embodiment, the first conductive bump 11 is located between the bottom chip 20a of the chipset 200 and the interconnection chip 30 to realize electrical connection between the bottom chip 20a and the interconnection chip 30.

[0074] In this embodiment, the material of the first conductive bump 11 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the first conductive bump 11 is tin.

[0075] In this embodiment, the packaging structure further includes: a first sealing layer 305 , which is located between the first chip 10 and the interconnection chip 30 and between the chipset 200 and the interconnection chip 30 , and seals the first conductive bump 11 .

[0076] The first sealing layer 305 fills the gap between the first chip 10 and the interconnection chip 30 and between the chipset 200 and the interconnection chip 30 to seal the first conductive bumps 11 .

[0077] As an example, the material of the first sealing layer 305 is epoxy resin.

[0078] In this embodiment, the packaging structure also includes: a second conductive bump 12, located on the second surface 102 and the fourth surface 204 exposed by the interconnection chip 30, the second conductive bump 12 is electrically connected to the first chip 10 and the chipset 200 respectively, and the height of the second conductive bump 12 is flush with or higher than the height of the back side of the interconnection chip 30.

[0079] The second conductive bumps 12 are used to realize electrical connection between the first chip 10 and the packaging substrate, and between the chipset 200 and the packaging substrate.

[0080] More specifically, in this embodiment, the second conductive bump 12 is located on the bottom chip 20 a exposed by the interconnection chip 30 and is electrically connected to the bottom chip 20 a , thereby achieving electrical connection between the bottom chip 20 a and the package substrate through the second conductive bump 12 .

[0081] The height of the second conductive bump 12 is flush with or higher than the height of the back side 302 of the interconnection chip 30, thereby preventing the interconnection chip 30 from affecting the bonding between the first chip 10 and the packaging substrate, and between the chipset 200 and the packaging substrate, and the height of the interconnection chip 30 is flush with or lower than the height of the second conductive bump 12. The back side 302 of the interconnection chip 30 is thinned, and the height of the interconnection chip 30 is relatively low, which is also beneficial to reducing the height of the second conductive bump 12, thereby reducing the distance between the first chip 10 and the packaging substrate, and between the chipset 200 and the packaging substrate, and improving the interconnection performance between the first chip 10 and the packaging substrate, and between the chipset 200 and the packaging substrate.

[0082] In this embodiment, the second conductive bump 12 is a solder ball. As an embodiment, the material of the solder ball includes tin.

[0083] Specifically, the solder ball is C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of the same solder ball pitch, the I / O number of C4 can be very high. In addition, it is suitable for mass production and can significantly reduce size and weight.

[0084] In other embodiments, the material of the second conductive bump includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0085] In this embodiment, the packaging structure further includes: a packaging substrate 300 bonded to the second surface 102 and the fourth surface 204 exposed by the interconnection chip.

[0086] The packaging substrate 300 is used to realize packaging integration and electrical integration between the chipset 200 and the first chip 10 .

[0087] In this embodiment, the packaging substrate 300 is a PCB (Printed Circuit Board).

[0088] Specifically, in this embodiment, the bonding between the first chip 10 and the packaging substrate 300 and the bonding between the chipset 200 and the packaging substrate 300 are achieved through the second conductive bumps 12 .

[0089] In this embodiment, the packaging structure further includes: a second sealing layer 205 located between the second surface 102 of the first chip 10 and the packaging substrate 300 , and between the fourth surface 204 of the chipset 200 and the packaging substrate 300 , and the second sealing layer 205 seals the second conductive bump 12 .

[0090] The second sealing layer 205 fills the gap between the second surface 102 of the first chip 10 and the packaging substrate 300 , and the gap between the fourth surface 204 of the chipset 200 and the packaging substrate 300 , so as to seal the second conductive bumps 12 .

[0091] As an example, the material of the second sealing layer 205 is epoxy resin.

[0092] In this embodiment, the packaging structure also includes: a fourth conductive bump 340, located on the surface of the packaging substrate 300 opposite to the first chip 10 and the chipset 200, for realizing electrical connection between the packaging substrate 300 and the external circuit, and further realizing electrical connection between the packaging structure and the external circuit.

[0093] In this embodiment, the fourth conductive bump 340 is a solder ball. As an example, the material of the fourth conductive bump 340 is tin.

[0094] The packaging structure may be formed by the packaging method provided by the embodiment of the present invention, or may be formed by other methods.

[0095] Correspondingly, the present invention also provides a packaging method. Figures 2 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention.

[0096] The packaging method of this embodiment is described in detail below with reference to the accompanying drawings.

[0097] refer to Figure 2, providing a carrier substrate 100, wherein the carrier substrate 100 includes a carrier surface 100a.

[0098] The carrier substrate 100 is used to provide a process operation platform for the subsequent bonding of the chipset and the first chip.

[0099] Specifically, the carrying surface 100a is used to carry the chipset and the first chip subsequently.

[0100] In this embodiment, the carrier substrate 100 is a carrier wafer. In other embodiments, the carrier substrate may also be other types of substrates. In this embodiment, the material of the carrier substrate 100 may include one or more of silicon, glass, silicon oxide, and aluminum oxide.

[0101] refer to Figure 3 , a first chip 10 is provided, comprising a first surface 101 and a second surface 102 opposite to each other.

[0102] The first chip 10 is used to be subsequently attached to the carrier substrate 100 and to realize electrical connection with the chipset through the interconnection chip.

[0103] In this embodiment, the first chip 10 is a first logic chip for performing logic control on the chipset. Specifically, the first logic chip may be a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip or a SoC (System on Chip) chip.

[0104] In this embodiment, the first surface 101 is the back surface of the first chip 10, and the second surface 102 is the front surface of the first chip 10. The front surface of the first chip 10 refers to the side of the first chip 10 facing the device, and the back surface of the first chip 10 refers to the side of the first chip 10 facing away from the device.

[0105] In this embodiment, one or more metal layers (not shown) are formed on the front side of the first chip 10 so that an interconnection chip can be bonded to the front side of the first chip 10 later, and the bonding surface of the interconnection chip is arranged opposite to the second surface 102. The interconnection chip can be electrically connected to the first chip 10 through the metal layer on the second surface 102 of the first chip 10.

[0106] refer to Figure 4, providing a chipset 200, the chipset 200 comprising a third surface 203 and a fourth surface 204 opposite to each other, the chipset 200 comprising a plurality of second chips 20 stacked along a direction perpendicular to a carrier substrate 100, and the adjacent second chips 20 along a direction perpendicular to the carrier substrate 100 are electrically connected.

[0107] The chipset 200 is used to be subsequently attached to the carrier surface 100a and bonded with the subsequent interconnection chip, and then the chipset 200 is electrically connected to the first chip through the interconnection chip, thereby forming a corresponding packaging structure to achieve corresponding functions.

[0108] Specifically, in this embodiment, the third surface 203 is used to be subsequently attached to the carrier surface 100 a , and the fourth surface 204 is used to achieve bonding with the interconnection chip, thereby achieving electrical connection between the chipset 204 and the interconnection chip.

[0109] In this embodiment, in the chipset 200, a plurality of second chips 20 stacked in the longitudinal direction (ie, perpendicular to the direction of the carrier substrate 100) form a high bandwidth memory (HBM) structure. By adopting the HBM structure, it is helpful to meet the requirements for higher information transmission speed.

[0110] In this embodiment, adjacent second chips 20 are electrically connected along a direction perpendicular to the carrier substrate 100 , thereby achieving electrical integration between the second chips 20 .

[0111] Specifically, in this embodiment, third conductive bumps 13 are formed between adjacent second chips 20 along a direction perpendicular to the carrier substrate 100 , and electrical connection between adjacent second chips 20 is achieved through the third conductive bumps 13 .

[0112] In this embodiment, the material of the third conductive bump 13 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the third conductive bump 13 is tin.

[0113] In this embodiment, in the chipset 200 , the second chips 20 closest to the fourth surface 204 are used as bottom chips 20 a , and the remaining second chips 20 are used as top chips 20 b .

[0114] In this embodiment, the bottom chip 20a is a second logic chip used to control the top chip 20b.

[0115] In this embodiment, the top chip 20b is a memory chip, such as a DRAM chip. In this embodiment, the number of the top chips 20b can be one or more. In this embodiment, the number of the top chips 20b is four as an example for description. In other embodiments, the number of the top chips can also be other numbers.

[0116] Specifically, in this embodiment, the bottom chip 20a is used as a logic control chip in the chipset 200 to control the memory chip.

[0117] refer to Figure 5 , the first chip 10 is attached to the carrier substrate 100 , and the first surface 101 is arranged opposite to the carrier surface 100 a .

[0118] The first chip 10 is attached to the carrier substrate 100 , so that after the chipset 200 is attached to the carrier substrate 100 , packaging integration between the first chip 10 and the chipset 200 can be achieved.

[0119] The first surface 101 is arranged opposite to the carrying surface 100a, that is, the second surface 102 of the first chip 10 is arranged opposite to the carrying surface 100a, and the second surface 102 is exposed to the carrying substrate 100, so that the interconnection chip can be bonded on the second surface 102 later, thereby realizing the electrical connection between the interconnection chip and the first chip 10.

[0120] In a specific embodiment, the first chip 10 may be attached to the carrier substrate 100 by temporary bonding, so as to reduce the difficulty of removing the carrier substrate 100 later.

[0121] refer to Figure 5 , the chipset 200 is attached to the carrier substrate 100 , and the third surface 203 is arranged opposite to the carrier surface 100 a .

[0122] The chipset 200 is attached to the carrier substrate 100 , so that after the first chip 10 is attached to the carrier substrate 100 , packaging integration between the first chip 10 and the chipset 200 can be achieved.

[0123] In this embodiment, the third surface 203 is arranged relative to the carrying surface 100a, that is, the fourth surface 204 of the chipset 200 is arranged opposite to the carrying surface 100a, and the fourth surface 204 is exposed to the carrying substrate 100, so as to subsequently bond the interconnection chip on the fourth surface 204, thereby realizing the electrical connection between the interconnection chip and the chipset 200, and realizing the electrical connection between the chipset 200 and the first chip 10 through the interconnection chip.

[0124] In a specific embodiment, the chipset 200 may be attached to the carrier substrate 100 by temporary bonding, so as to reduce the difficulty of removing the carrier substrate 100 later.

[0125] refer to Figure 6 In this embodiment, the packaging method further includes: after laminating the first chip 10 on the carrier substrate 100 and laminating the chipset 200 on the carrier substrate 100, and before bonding the interconnection chip on the first chip 10 and the chipset 200, forming a packaging layer 110 on the carrier surface 100a on the side of the first chip 10 and the chipset 200, the packaging layer 110 covers the side walls of the first chip 10 and the chipset 200, and exposes the second surface 102 and the fourth surface 204.

[0126] The packaging layer 110 is used to realize the packaging integration between the first chip 10 and the chipset 200. The packaging layer 110 can also play the role of insulation, sealing and moisture-proof, which is beneficial to improve the reliability of the packaging structure. The packaging layer 110 is also used to provide a process platform for subsequent bonding and interconnecting chips.

[0127] The packaging layer 110 exposes the second surface 102 and the fourth surface 204 so that an interconnection chip can be bonded on the second surface 102 of the first chip 10 and the fourth surface 204 of the chipset 200 later, so as to electrically connect the interconnection chip to the first chip and to electrically connect the interconnection chip to the chipset 200, thereby realizing electrical connection between the first chip 10 and the chipset 200 through the interconnection chip.

[0128] As an embodiment, the material of the encapsulation layer 110 is a molding material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. In other embodiments, the encapsulation layer can also use other suitable encapsulation materials.

[0129] As an example, the step of forming the packaging layer 110 includes: forming a packaging material layer (not shown) on the carrier substrate 100, covering the first chip 10 and the chipset 200; removing the packaging material layer above the second surface 102 of the first chip 10 and the fourth surface 204 of the chipset 200, and the remaining packaging material layer covering the side walls of the first chip 10 and the chipset 200 is used as the packaging layer 110.

[0130] As an example, a plastic encapsulation process is used to form the encapsulation material layer. In other embodiments, based on actual process requirements, other suitable processes may also be used to form the encapsulation material layer.

[0131] As an example, a grinding process is used to remove the packaging material layer above the second side 102 of the first chip 10 and the fourth side 204 of the chipset 200, thereby improving the flatness of the top surface of the packaging layer 110, which is beneficial to subsequent processes and provides a flat surface for subsequent bonding and interconnection chips.

[0132] refer to Figure 7 , providing an interconnection chip 30, wherein the interconnection chip 30 includes a bonding surface 301 and a back surface 302 facing each other.

[0133] An interconnection chip 30 is provided so that the interconnection chip 30 can be subsequently bonded to the first chip 10 and the chipset 200 , thereby realizing interconnection between the first chip 10 and the chipset 200 .

[0134] Specifically, the interconnection chip 30 is used as a chip bridge to realize the interconnection between the first chip 10 and the chipset 200 .

[0135] The bonding surface 301 is used to subsequently realize bonding with the first chip 10 and the chipset 200 , and further realize electrical connection between the first chip 10 and the chipset 200 through the interconnection chip 30 .

[0136] The back surface 302 is used for subsequent thinning processing to reduce the thickness of the interconnection chip 30 .

[0137] In this embodiment, the interconnection chip 30 includes a base layer (not shown) and an interconnection structure layer (not shown) located on the base layer, and the side of the base layer opposite to the interconnection structure layer is used as the back side 302, and the side of the interconnection structure layer opposite to the base layer is used as the bonding surface 301.

[0138] In this embodiment, the base layer is used to provide support for forming an interconnection structure layer, and in the subsequent step of thinning the back side 302 of the interconnection chip 30 , the base layer is thinned.

[0139] By thinning the base layer, the thickness of the interconnection chip 30 is reduced while ensuring the interconnection performance of the interconnection chip 30 for realizing the interconnection between the first chip 10 and the chipset 200 .

[0140] In this embodiment, the material of the base layer is silicon.

[0141] The interconnection structure layer is used to subsequently electrically connect the first chip 10 and the chipset 200 .

[0142] As an example, the interconnection structure layer is a rewiring structure layer. The rewiring structure layer can redistribute the connection ends of the interconnection chips so as to form first conductive bumps whose density and position meet the process requirements, thereby facilitating the subsequent electrical connection between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30 through the first conductive bumps. The first conductive bumps have a small pitch and a high density, which is also conducive to improving the interconnection performance between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30, thereby improving the interconnection performance between the first chip 10 and the chipset 200.

[0143] Correspondingly, in this embodiment, the interconnection structure layer is also used to provide a process platform for forming the first conductive bump.

[0144] Specifically, the redistribution structure layer may include one or more redistribution layers. Specifically, the material of the redistribution layer is a conductive material. As an example, the material of the redistribution structure is a metal, including any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0145] refer to Figure 8 An interconnection chip 30 is bonded to the first chip 10 and the chipset 200, the bonding surface 301 is arranged opposite to the second surface 102 and the fourth surface 204, and the interconnection chip 30 electrically connects the chipset 200 and the first chip 10, so that the interconnection chip 30 is used as a chip bridge to realize the electrical connection between the chipset 200 and the first chip 10.

[0146] Specifically, in this embodiment, in the step of bonding the interconnection chip 30 on the first chip 10 and the chipset 200 , the interconnection chip 30 is bonded on the first chip 10 , the chipset 200 and the packaging layer 110 .

[0147] More specifically, in the present embodiment, in the chipset 200, the bottom chip 20a is bonded to the interconnection chip 30, so that the bottom chip 20a is electrically connected to the interconnection chip 30. Moreover, the adjacent second chips 20 are electrically connected, so that the top chip 20b can be electrically connected to the interconnection chip 30 through the bottom chip 20a.

[0148] In this embodiment, the step of bonding the interconnection chip 30 on the first chip 10 and the chipset 200 includes: forming a first conductive bump 11 between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30, and achieving bonding between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30 through the first conductive bump 11.

[0149] Specifically, in this embodiment, the first conductive bump 11 is located between the bottom chip 20 a and the interconnection chip 30 of the chipset 200 to achieve electrical connection between the bottom chip 20 a and the interconnection chip 30 .

[0150] In this embodiment, the material of the first conductive bump 11 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the first conductive bump 11 is tin.

[0151] In a specific implementation, the first conductive bump 11 may be formed on the bonding surface 301 of the interconnection chip 30; or, the first conductive bump may be formed on the second surface 102 of the first chip 10 and the fourth surface 204 of the chipset 200; and then, the first chip 10 is bonded to the interconnection chip 30 and the chipset 200 is bonded to the interconnection chip 30 through the first conductive bump 11.

[0152] It should be noted that, in the present embodiment, the interconnection chip 30 is bonded to the top surfaces of the first chip 10 and the chipset 200 that are adjacent to each other, that is, the interconnection chip 30 also exposes a portion of the surface of the second surface 102 and a portion of the surface of the fourth surface 204, so as to achieve bonding between the second surface 102 and the fourth surface 204 exposed by the interconnection chip 30 and the packaging substrate, thereby achieving electrical connection between the first chip 10 and the chipset 200 and the packaging substrate.

[0153] More specifically, the exposed second surface 102 and fourth surface 204 of the interconnection chip 30 are used to set the second conductive bumps so as to bond the second conductive bumps to the package substrate.

[0154] In this embodiment, the packaging method also includes: after the first chip 10 is bonded to the interconnection chip 30 and the chipset 200 is bonded to the interconnection chip 30 through the first conductive bump 11, a first sealing layer 305 is formed between the first chip 10 and the interconnection chip 30 and between the chipset 200 and the interconnection chip 30 to seal the first conductive bump 11.

[0155] The first sealing layer 305 fills the gap between the first chip 10 and the interconnection chip 30 , and between the chipset 200 and the interconnection chip 30 , so as to seal the first conductive bumps 11 .

[0156] As an example, the first sealing layer 305 is formed by adopting an underfill process.

[0157] As an example, the material of the first sealing layer 305 is epoxy resin.

[0158] refer to Fig. 9 After the interconnection chip 30 is bonded to the first chip 10 and the chipset 200 , a back side 302 of the interconnection chip 30 is thinned.

[0159] The back side 302 of the interconnection chip 30 is thinned to reduce the thickness of the interconnection chip 30, which is beneficial to simplifying the packaging structure and thinning the device. Moreover, after the packaging structure is subsequently bonded to the packaging substrate, since the interconnection chip 30 is thinner, it is beneficial to shorten the distance between the first chip 10 and the chipset 200 and the packaging substrate, which is beneficial to the heat dissipation of the packaging structure and improves the performance of the packaging structure.

[0160] In the present embodiment, since the back side 302 of the interconnection chip 30 is thinned after the interconnection chip 30 is bonded to the first chip 10 and the chipset 200, the interconnection chip 30 is fixed on the first chip 10 and the chipset 200, which is beneficial to thinning the interconnection chip 30 to the thickness required by the process, thereby facilitating the thinning of the interconnection chip 30 and the packaging structure.

[0161] In this embodiment, in the step of thinning the back surface 302 of the interconnection chip 30 , the base layer is thinned.

[0162] In a specific implementation, in the step of thinning the base layer, the base layer can be removed to further reduce the thickness of the interconnection chip 30, so that the interconnection chip 30 only retains the interconnection structure layer, thereby ensuring the interconnection function of the interconnection chip 30; or, a part of the thickness of the base layer can be removed to reduce the probability of damaging the interconnection structure layer, thereby reducing the process risk.

[0163] In this embodiment, after the back side 302 of the interconnection chip 30 is thinned, the thickness of the remaining interconnection chip 30 should not be too small or too large. If the thickness of the remaining interconnection chip 30 is too small, the thickness of the back side 302 of the interconnection chip 30 that is thinned is too large, which easily increases the risk of damaging the interconnection structure layer; if the thickness of the remaining interconnection chip 30 is too large, the thickness of the back side 302 of the interconnection chip 30 that is thinned is too small, which easily leads to an insignificant effect of reducing the thickness of the interconnection chip 30. For this reason, in this embodiment, after the back side 302 of the interconnection chip 30 is thinned, the thickness of the remaining interconnection chip 30 is 2μm to 15μm.

[0164] In this embodiment, an etching process is used to thin the back side 302 of the interconnection chip 30. The etching process has high process precision, which is conducive to improving the control precision of the thickness of the thinning process and reducing the probability of causing damage to the interconnection structure layer or other film layer structures.

[0165] As an example, the etching process may include an anisotropic dry etching process. The anisotropic dry etching process has high etching accuracy and low etching rate.

[0166] In other embodiments, the etching process may also be a wet etching process, or a process combining a dry etching process and a wet etching process.

[0167] refer to Fig.10 In this embodiment, after the thinning process and before removing the carrier substrate 100, a second conductive bump 12 is formed on the second surface 102 and the fourth surface 204 exposed by the interconnection chip 30, and the second conductive bump 12 is electrically connected to the first chip 10 and the chipset 200 respectively, and the height of the second conductive bump 12 is flush with or higher than the height of the back side 302 of the interconnection chip 30.

[0168] Subsequent steps also include: providing a packaging substrate; bonding the second side 102 of the first chip 10 and the fourth side 204 of the chipset 200 to the packaging substrate, wherein the second conductive bumps 12 are used to achieve electrical connection between the first chip 10 and the packaging substrate, and between the chipset 200 and the packaging substrate.

[0169] More specifically, in this embodiment, the second conductive bump 12 is located on the bottom chip 20 a exposed by the interconnection chip 30 and is electrically connected to the bottom chip 20 a , thereby achieving electrical connection between the bottom chip 20 a and the package substrate through the second conductive bump 12 .

[0170] The height of the second conductive bump 12 is flush with or higher than the height of the back side 302 of the interconnection chip 30, so as to avoid the influence of the interconnection chip 30 on the bonding process in the subsequent step of bonding the second side 102 of the first chip 10 and the fourth side 204 of the chipset 200 to the packaging substrate. In addition, the height of the interconnection chip 30 is flush with or lower than the height of the second conductive bump 12. The back side 302 of the interconnection chip 30 is thinned, and the height of the interconnection chip 30 is relatively low, which is also conducive to reducing the height of the second conductive bump 12, thereby reducing the distance between the first chip 10 and the packaging substrate, and between the chipset 200 and the packaging substrate, and improving the interconnection performance between the first chip 10 and the packaging substrate, and between the chipset 200 and the packaging substrate.

[0171] In this embodiment, the second conductive bump 12 is a solder ball. As an embodiment, the material of the solder ball includes tin.

[0172] Specifically, the solder ball is C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of the same solder ball pitch, the I / O number of C4 can be very high. In addition, it is suitable for mass production and can significantly reduce size and weight.

[0173] In other embodiments, the material of the second conductive bump includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0174] refer to Fig.11 and Fig.12 In this embodiment, the packaging method further includes: after the thinning process, removing the carrier substrate 100 so as to subsequently bond the second surface 102 of the first chip 10 and the fourth surface 204 of the chipset 200 to the packaging substrate.

[0175] More specifically, in this embodiment, after the second conductive bumps 12 are formed, the carrier substrate 100 is removed.

[0176] As an example, the carrier substrate 100 may be removed through a debonding process, thereby reducing the difficulty of removing the carrier substrate 100 .

[0177] refer to Fig.13 The packaging method further includes: providing a packaging substrate 300 ; after removing the carrier substrate 100 , bonding the second surface 102 of the first chip 10 and the fourth surface 204 of the chipset 200 to the packaging substrate 400 .

[0178] The packaging substrate 300 is used to realize packaging integration and electrical integration between the chipset 200 and the first chip 10 .

[0179] In this embodiment, the packaging substrate 300 is a PCB (Printed Circuit Board).

[0180] Specifically, in this embodiment, the first chip 10 and the chipset 200 are bonded to the packaging substrate 300 through the second conductive bumps 12 .

[0181] In this embodiment, the packaging method also includes: after the bonding between the first chip 10 and the chipset 200 is achieved through the second conductive bump 12, a second sealing layer 205 for sealing the second conductive bump 12 is formed between the second side 102 of the first chip 10 and the packaging substrate 300, and between the fourth side 204 of the chipset 200 and the packaging substrate 300.

[0182] The second sealing layer 205 fills the gap between the second surface 102 of the first chip 10 and the packaging substrate 300 , and the gap between the fourth surface 204 of the chipset 200 and the packaging substrate 300 , so as to seal the second conductive bumps 12 .

[0183] As an example, an underfill process is adopted to form the second sealing layer 205 .

[0184] As an example, the material of the second sealing layer 205 is epoxy resin.

[0185] In this embodiment, the packaging method further includes: forming a fourth conductive bump 340 on a surface of the packaging substrate 300 opposite to the first chip 10 and the chipset 200 to achieve electrical connection between the packaging substrate 300 and an external circuit.

[0186] In this embodiment, the fourth conductive bump 340 is a solder ball. As an example, the material of the fourth conductive bump 340 is tin.

[0187] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: A first chip including a first side and a second side opposite to each other; a chipset located at a side of the first chip, the chipset comprising a plurality of second chips stacked in a vertical direction, wherein the second chips adjacent to each other in the vertical direction are electrically connected; the chipset comprising a third surface and a fourth surface opposite to each other, wherein the first surface and the third surface face the same direction; An interconnection chip, wherein the interconnection chip comprises a bonding surface and a back surface facing each other, the interconnection chip is located on the first chip and the chipset, the bonding surface is arranged opposite to the second surface and the fourth surface, and the interconnection chip is electrically connected to the chipset and the first chip; the back surface of the interconnection chip is thinned.

2. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a packaging layer located at the side of the first chip and the chipset, and the packaging layer covers the side walls of the first chip and the chipset.

3. The packaging structure according to claim 1, characterized in that: The interconnection chip comprises a base layer and an interconnection structure layer located on the base layer, the side of the base layer opposite to the interconnection structure layer is used as the back side, and the side of the interconnection structure layer opposite to the base layer is used as the bonding surface; or, The interconnection chip only includes an interconnection structure layer, a side of the interconnection structure layer opposite to the first chip and the chipset is used as the bonding surface, and a side of the interconnection structure layer opposite to the first chip and the chipset is used as the back surface.

4. The packaging structure according to claim 3, characterized in that: The interconnection structure layer is a redistribution structure layer.

5. The packaging structure according to claim 1, 3 or 4, characterized in that: The interconnection chip has a thickness of 2 μm to 15 μm.

6. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a first conductive bump located between the first chip and the interconnection chip, and between the chipset and the interconnection chip.

7. The packaging structure according to claim 1, characterized in that: The packaging structure also includes: second conductive bumps located on the second and fourth surfaces exposed by the interconnection chip, the second conductive bumps are electrically connected to the first chip and the chipset respectively, and the height of the second conductive bumps is flush with or higher than the height of the back side of the interconnection chip.

8. The packaging structure according to claim 1, characterized in that: The first chip is a logic chip, and the chipset is a high bandwidth memory chipset.

9. A packaging method, characterized in that: include: Providing a carrier substrate, the carrier substrate comprising a carrier surface; Providing a first chip including a first side and a second side opposite to each other; Providing a chipset, the chipset comprising a third surface and a fourth surface opposite to each other, the chipset comprising a plurality of second chips stacked in a direction perpendicular to a carrier substrate, and the second chips adjacent to each other in a direction perpendicular to the carrier substrate being electrically connected; Laminating the first chip on the carrier substrate, with the first surface being arranged opposite to the carrier surface; Laminating the chipset on the carrier substrate, wherein the third surface is arranged opposite to the carrier surface; Providing an interconnect chip, the interconnect chip comprising a bonding surface and a back surface facing each other; Bonding an interconnection chip onto the first chip and the chipset, wherein the bonding surface is arranged opposite to the second surface and the fourth surface, and the interconnection chip electrically connects the chipset and the first chip; After bonding the interconnection chip to the first chip and the chipset, the backside of the interconnection chip is thinned.

10. The packaging method according to claim 9, characterized in that: In the step of providing an interconnection chip, the interconnection chip comprises a base layer and an interconnection structure layer located on the base layer, a side of the base layer opposite to the interconnection structure layer is used as the back side, and a side of the interconnection structure layer opposite to the base layer is used as the bonding surface; In the step of thinning the back side of the interconnection chip, the base layer is thinned.

11. The packaging method according to claim 10, characterized in that: In the step of thinning the base layer, the base layer is removed, or a portion of the thickness of the base layer is removed.

12. The packaging method according to claim 10, characterized in that: The interconnection structure layer is a redistribution structure layer.

13. The packaging method according to claim 9, characterized in that: The packaging method further includes: after attaching the first chip to the carrier substrate and attaching the chipset to the carrier substrate, and before bonding the interconnection chip to the first chip and the chipset, forming a packaging layer on the carrier surface of the first chip and the chipset, wherein the packaging layer covers the side walls of the first chip and the chipset and exposes the second surface and the fourth surface; In the step of bonding the interconnection chip on the first chip and chipset, the interconnection chip is bonded on the first chip and chipset and the packaging layer.

14. The packaging method according to claim 9, characterized in that: The step of bonding the interconnection chip on the first chip and the chipset includes: forming first conductive bumps between the first chip and the interconnection chip, and between the chipset and the interconnection chip, and achieving bonding between the first chip and the interconnection chip, and between the chipset and the interconnection chip through the first conductive bumps.

15. The packaging method according to claim 9, characterized in that: The back side of the interconnection chip is thinned by using an etching process.

16. The packaging method according to claim 9, characterized in that: After the back side of the interconnection chip is thinned, the remaining thickness of the interconnection chip is 2 μm to 15 μm.

17. The packaging method according to claim 9, characterized in that: The packaging method further includes: removing the carrier substrate after the thinning process.

18. The packaging method according to claim 17, characterized in that: The packaging method also includes: after the thinning process and before removing the carrier substrate, forming second conductive bumps on the second and fourth surfaces exposed by the interconnected chip, the second conductive bumps being electrically connected to the first chip and the chipset respectively, and the height of the second conductive bumps being flush with or higher than the height of the back side of the interconnected chip.

19. The packaging method according to claim 17 or 18, characterized in that: The packaging method further includes: providing a packaging substrate; and after removing the carrier substrate, bonding the second surface of the first chip and the fourth surface of the chipset to the packaging substrate.

20. The packaging method according to claim 9, characterized in that: The first chip is a logic chip, and the chipset is a high bandwidth memory chipset.

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