Test structure of memory and forming method thereof

Abstract

The invention discloses a memory test structure and a forming method thereof, and the method comprises the steps: forming an initial memory gate structure on a memory region, which comprises a floating gate structure located on the surface of a first region, a control gate structure located on the surface of the floating gate structure, and a word line gate structure located on the surface of a second region, the floating gate structure comprises a first oxide layer located on the surface of the first region and a floating gate located on the first oxide layer, and the word line gate structure comprises a second oxide layer located on the surface of the second region and a word line gate located on the second oxide layer; forming a first opening in the initial memory gate structure by adopting a first etching process, wherein the first opening exposes the surface of the word line gate structure; removing the word line grid by adopting a second etching process, wherein the difference value of the removal rate of the second etching process to the word line grid material and the removal rate of the second etching process to the second oxide layer material is greater than a first threshold value; and after the word line gate is removed, the second oxide layer is removed to form a memory gate structure on the surface of the first oxide layer, so that the possibility of damage to an active region of the test structure of the memory is reduced.

Description

Technical Field

[0001] The invention relates to a semiconductor manufacturing process, and in particular to a memory test structure and a forming method thereof. Background Art

[0002] Embedded Flash (eFlash) is a non-volatile memory commonly used in embedded systems. The 28nm embedded Flash (28-eflash) platform is based on the 28nm high-k metal gate (28High-K, 28HK) platform and embeds the third-generation embedded super flash (ESF3) architecture. The 28nm logic device itself is a relatively advanced process. At the same time, the third-generation embedded super flash architecture itself has the advantages of high reliability, fast speed, and large capacity. The two are integrated and developed in embedded special processes, and the future market prospects are huge. In the process of building the embedded flash platform process, the word line and the common source need to be etched cleanly to expose the active area, and then the metal silicide layer is grown and the conductive plug is connected.

[0003] However, the current embedded flash memory platform process construction needs to be further improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a test structure of a memory and a method for forming the same, so that the tunneling oxide layer is completely retained, the doped region is protected from being exposed, and the electrical stability of the test structure of the memory is improved.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a test structure of a memory and a method for forming the same, wherein the forming method comprises: providing a substrate, wherein the substrate comprises a plurality of storage areas, each storage area comprises two first areas and a second area located between the two first areas, wherein the first area has a doped area; forming an initial storage gate structure on the storage area, wherein the initial storage gate structure comprises: a floating gate structure located on the surface of the first area, a control gate structure located on the surface of the floating gate structure, and a word line gate structure located on the surface of the second area, wherein the floating gate structure comprises a first oxide layer located on the surface of the first area and a floating gate located on the first oxide layer, wherein the word line gate structure comprises a second oxide layer located on the surface of the second area and a word line gate located on the second oxide layer; and using the first oxide layer to form a floating gate structure. An etching process is used to form a first opening in the initial storage gate structure, and the first opening exposes the surface of the word line gate structure; a second etching process is used to remove the word line gate, and the difference between the removal rate of the word line gate material and the removal rate of the second oxide layer material by the second etching process is greater than a first threshold; after removing the word line gate, the second oxide layer is removed to form a storage gate structure located on the surface of the first oxide layer, the storage gate structure includes a floating gate structure and a control gate structure located on the surface of the floating gate structure, the storage gate structure includes a first side wall adjacent to the second region, the floating gate structure surface of the first side wall protrudes from the control gate structure surface of the first side wall, and a second opening exposing the surface of the second region is provided between adjacent storage gate structures.

[0006] Optionally, the control gate structure includes a control gate dielectric layer and a control gate located on a surface of the control gate dielectric layer; the initial storage gate structure also includes an initial first spacer located on a sidewall surface of the control gate structure.

[0007] Optionally, the control gate includes a first part and a second part located on the first part; the first etching process also etches a portion of the control gate adjacent to the word line gate and an initial first sidewall, so that the first opening extends into the second part and exposes a portion of the top surface of the first part, and a first sidewall is provided on the sidewall surface of the first part.

[0008] Optionally, the first opening exposes a portion of a top surface of the control gate adjacent to the word line gate and a top surface of an initial first spacer.

[0009] Optionally, the first etching process further etches a portion of the control gate adjacent to the word line gate and an initial first sidewall spacer until the control gate dielectric layer is exposed, so that the first opening extends into the control gate and exposes the control gate dielectric layer.

[0010] Optionally, the floating gate structure further includes: a third oxide layer located on the surface of the floating gate sidewall; the distance from the top of the third oxide layer to the top of the floating gate is: The thickness range of the third oxide layer is:

[0011] Optionally, after forming the initial storage gate structure and before forming the first opening, the method further includes: forming a dielectric structure located on the initial storage gate structure; the dielectric structure includes a stack of one or more layers of silicon oxide, polysilicon or silicon nitride.

[0012] Optionally, the method for forming the first opening includes: forming a first mask layer on the surface of the dielectric structure, the first mask layer having a first projection on the substrate surface and the word line gate structure having a second projection on the substrate surface, the second projection being within the range of the first projection; using the first mask layer as a mask, etching the dielectric structure and the initial storage gate structure by a first etching process to form a first opening exposing the surface of the word line gate structure; the distance range from the bottom of the first opening to the top of the third oxide layer is: The difference between the removal rate of the initial storage gate structure material and the removal rate of the dielectric structure material by the first etching process is less than a second threshold; the second threshold is 2A / S.

[0013] Optionally, the first etching process includes anisotropic dry etching and isotropic wet etching; the parameters of the first etching process include etching time; the etching time is negatively correlated with the distance from the bottom of the first opening to the top of the third oxide layer.

[0014] Optionally, after forming the second opening, the method further includes: forming a conductive layer on the surface of the second region; and after forming the conductive layer, the method further includes: forming a conductive plug on the surface of the conductive layer.

[0015] Optionally, when the first etching process is anisotropic dry etching, the parameters of the first etching process include: etching gas includes: carbon tetrafluoride, trifluoromethane, helium, argon, sulfur dioxide or hydrogen bromide; etching time range is: 20s~60s; plasma applied electric field strength range is: 50V~400V.

[0016] Optionally, when the first etching process is isotropic wet etching, the parameters of the first etching process include: etching liquid includes: sulfuric acid, phosphoric acid, hydrofluoric acid or distilled water; etching liquid concentration ratio includes: 1:500, 1:1000, 1:2000 or 1:10000; etching time range is: 25s to 200s.

[0017] Optionally, the second etching process includes: anisotropic dry etching; when the second etching process is anisotropic dry etching, the parameters of the second etching process include: etching gas includes: carbon tetrafluoride, trifluoromethane, helium, argon, sulfur dioxide or hydrogen bromide; etching time range is: 40s~150s; plasma applied electric field strength range is: 50V~350V; the size of the first threshold is: 30A / s.

[0018] Optionally, the thickness range of the first oxide layer is: The thickness range of the second oxide layer is:

[0019] Optionally, the method for removing the second oxide layer includes: a third etching process; the third etching process includes: anisotropic dry etching; the difference between the removal rate of the second oxide layer material and the removal rate of the floating gate material by the third etching process is greater than a third threshold; the etching parameters include: etching gas includes: carbon tetrafluoride, trifluoromethane, helium, argon, sulfur dioxide or hydrogen bromide; etching time range is: 30s~80s; plasma applied electric field strength range is: 50V~300V; the size of the third threshold is: 40A / s.

[0020] Optionally, before forming the initial storage gate structure, the method further includes: performing a modification treatment on the second region; the modification treatment method includes: forming a second mask layer on the surface of the substrate, the second mask layer exposing the surface of the second region; performing a modification treatment on the substrate exposed by the second mask layer; the modification treatment process is ion implantation; the parameters of the ion implantation process include: the energy range of the ion implantation is: 5KeV~50KeV; the dose range of the ion implantation is: 6E13ions / cm 2 ~6E15 ions / cm 2 .

[0021] Correspondingly, the technical solution of the present invention also provides a test structure of a memory, comprising: a substrate, the substrate comprising a plurality of storage areas, each storage area comprising two first areas and a second area located between the two first areas, the first area having a doped area; a first oxide layer located on the surface of the first area; a storage gate structure located on the surface of the first oxide layer, the storage gate structure comprising a floating gate and a control gate structure located on the surface of the floating gate, the storage gate structure comprising a first side wall adjacent to the second area, the floating gate surface of the first side wall protruding from the control gate structure surface of the first side wall, and a second opening exposing the surface of the second area is provided between adjacent storage gate structures.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] In the method for forming a test structure of a memory provided by the technical solution of the present invention, first, a second etching process is used to remove the word line gate, and the difference between the removal rate of the word line gate material and the removal rate of the second oxide layer material by the second etching process is greater than a first threshold value, so that the word line gate is removed without damaging the second oxide layer, thereby improving the etching accuracy in the process of removing the word line gate; secondly, the second oxide layer is removed after removing the word line gate, and by adopting a high selectivity etching method, only one material of the second oxide layer is removed in the process of removing the second oxide layer without damaging the floating gate, so that the doped area is not exposed, thereby reducing the possibility of leakage of the test structure of the memory, and improving the electrical performance of the test structure of the memory.

[0024] Furthermore, the floating gate structure further includes: a third oxide layer located on the side wall surface of the floating gate. The third oxide layer is located on the side wall surface of the floating gate, and in the process of removing the word line gate in the second etching process and removing the second oxide layer, the integrity of the floating gate is protected, and the exposure of the doped region caused by the loss of the floating gate is avoided, the possibility of leakage of the test structure of the memory is reduced, and the electrical performance of the test structure of the memory is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 3 The present invention is a schematic cross-sectional structure diagram of a formation process of a test structure of a memory.

[0026] Figures 4 to 13 It is a schematic cross-sectional structure diagram of a formation process of a test structure of a memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] As described in the background art, the current embedded flash memory platform process construction needs to be further improved.

[0028] Figures 1 to 3 The present invention is a schematic cross-sectional structure diagram of a formation process of a test structure of a memory.

[0029] Please refer to Figure 1The test structure of the memory comprises: a substrate 100, wherein the substrate 100 comprises a plurality of storage areas, each storage area comprises two first areas I and a second area II located between two adjacent first areas I, wherein the first area I has a doped area (not marked); an initial storage gate structure 103 is formed on the storage area, wherein the initial storage gate structure 103 comprises: a floating gate structure 104 located on the surface of the first area, a control gate structure 105 located on the surface of the floating gate structure 104, and a word line gate structure 107 located on the surface of the second area, wherein the floating gate structure 104 comprises a first oxide layer 101 located on the surface of the first area and a floating gate 106 located on the first oxide layer 101, wherein the word line gate structure 107 comprises a second oxide layer 102 located on the surface of the second area and a word line gate 108 located on the second oxide layer 102; and a dielectric structure 109 is formed on the surface of the initial storage gate structure 103.

[0030] The memory test structure further includes: a third oxide layer 110 located on the sidewall surface of the floating gate 106 .

[0031] Please refer to Figure 2 A first opening 111 is formed in the dielectric structure 109 and the initial storage gate structure 103, wherein the first opening 111 exposes the sidewall surface of the control gate structure 105, the sidewall surface of the floating gate 106, a portion of the surface of the second oxide layer 102, the surface of the first oxide layer 101, and a portion of the surface of the third oxide layer 110.

[0032] Please refer to Figure 3 After the first opening 111 is formed, the first oxide layer 101 , the second oxide layer 102 , and the third oxide layer 110 located on the surface of the first opening 111 are removed.

[0033] In the process of etching to form the first opening 111, since the materials of the dielectric structure 109 and the initial storage gate structure 103 are different from the materials of the first oxide layer 101, the second oxide layer 102, and the third oxide layer 110, the material of the initial storage gate structure 103 is relatively loose, while the materials of the first oxide layer 101, the second oxide layer 102, and the third oxide layer 110 are relatively dense, resulting in a large difference in etching rates between the dielectric structure 109, the initial storage gate structure 103 and the first oxide layer 101, the second oxide layer 102, and the third oxide layer 110, so that when the first opening 111 is formed, the third oxide layer 110 remains, and the bottom of the first opening is different in height. When the first oxide layer 101, the second oxide layer 102, and the third oxide layer 110 located on the surface of the first opening 111 are subsequently removed, the first oxide layer 101 with a smaller thickness is prone to over-etching, resulting in surface loss of the first region I, exposing the doped region, increasing the possibility of leakage of the test structure of the memory, and reducing the electrical performance of the test structure of the memory.

[0034] In order to solve the above technical problems, the technical solution of the present invention provides a test structure of a memory and a method for forming the same. First, a second etching process is used to remove the word line gate. The difference between the removal rate of the word line gate material and the removal rate of the second oxide layer material by the second etching process is greater than a first threshold. The word line gate is removed without damaging the second oxide layer, thereby improving the etching accuracy in the process of removing the word line gate. Secondly, the second oxide layer is removed after removing the word line gate. By adopting a high selectivity etching method, only one material of the second oxide layer is removed in the process of removing the second oxide layer without damaging the floating gate, so that the doped area is not exposed, thereby reducing the possibility of damage to the active area of ​​the test structure of the memory, and improving the electrical performance of the test structure of the memory.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 4 to 13 It is a schematic cross-sectional structure diagram of a formation process of a test structure of a memory according to an embodiment of the present invention.

[0037] Please refer to Figure 4 , providing a substrate 200, the substrate 200 includes a plurality of storage areas, each storage area includes two first areas I and a second area II located between the two first areas I, the first area I has a doped area (not shown).

[0038] The material of the substrate 200 includes: silicon, silicon germanium, silicon carbide, silicon on insulator (SOI), germanium on insulator (GOI), etc.

[0039] The storage region provides a structural basis for the subsequent formation of an initial storage gate structure 201 .

[0040] The first region I provides a structural basis for the floating gate structure 202 and the control gate structure 203 formed subsequently.

[0041] The second region II provides a structural foundation for a word line gate structure 204 formed subsequently.

[0042] Please refer to Figure 5 , the second zone II is modified.

[0043] The modification method includes: forming a second mask layer (not shown) on the surface of the substrate 200, wherein the second mask layer (not shown) exposes the surface of the second region II; and performing modification on the substrate 200 exposed by the second mask layer (not shown).

[0044] Specifically, in this embodiment, the modification process is ion implantation; the parameters of the ion implantation process include: the energy range of ion implantation is: 5KeV~50KeV; the dose range of ion implantation is: 6E13 ions / cm 2 ~6E15 ions / cm 2 .

[0045] Specifically, in this embodiment, after the modification treatment, the material of the second region II is amorphous.

[0046] The modification process breaks the valence bonds between silicon atoms in the substrate 200 , so that the oxidation rate of the second region II is faster than that of the first region I, thereby providing a structural basis for the subsequent formation of a thicker second oxide layer 207 .

[0047] Please refer to Figure 6 , an initial storage gate structure 201 is formed on the storage area, the initial storage gate structure 201 includes: a floating gate structure 202 located on the surface of the first area I, a control gate structure 203 located on the surface of the floating gate structure 202, and a word line gate structure 204 located on the surface of the second area II, the floating gate structure 202 includes a first oxide layer 205 located on the surface of the first area I and a floating gate 206 located on the first oxide layer 205, the word line gate structure 204 includes a second oxide layer 207 located on the surface of the second area II and a word line gate 208 located on the second oxide layer 207.

[0048] The method for forming the initial storage gate structure 201 includes: forming an initial oxide layer (not shown) on the surface of the substrate 200; forming a floating gate material layer (not shown) on the surface of the initial oxide layer (not shown); forming a control gate dielectric material layer (not shown) on the floating gate material layer (not shown); forming a control gate material layer (not shown) on the control gate dielectric material layer (not shown); etching the control gate material layer (not shown) and the control gate dielectric material layer (not shown) until the surface of the floating gate material layer (not shown) is exposed, and forming two separate control gate structures 203 on the surface of the floating gate material layer (not shown), each of the control gate structures 203 including a control gate dielectric layer 210 and a control gate 211 located on the surface of the control gate dielectric layer 210, forming the control gate 211 with the control gate material layer (not shown), and forming the control gate dielectric layer 210 with the control gate dielectric material layer (not shown); etching the control gate material layer (not shown) and the control gate structure 203 on the surface of the floating gate material layer (not shown). An initial first sidewall material layer (not shown) is formed on the surface; the initial first sidewall material layer (not shown) is etched back until the floating gate material layer (not shown) is exposed to form an initial first sidewall 212; the floating gate material layer (not shown) is etched to form a floating gate 206, a first oxide layer 205 is formed with the initial oxide layer (not shown), a floating gate structure 202 is formed with the first oxide layer 205 and the floating gate 206, and a first storage gate structure (not shown) is formed with the floating gate structure 202 and a control gate structure 203 located on the surface of the floating gate structure 202; there is an opening (not shown) between adjacent first storage gate structures, and each floating gate 206 has a third oxide layer 209 exposed by the opening (not shown); a second oxide layer 207 is formed with the initial oxide layer (not shown), and a word line gate structure 204 is formed in the opening (not shown), wherein the word line gate structure 204 includes a second oxide layer 207 located on the surface of the second region II and a word line gate 208 located on the second oxide layer 207.

[0049] The initial memory gate structure 201 has the function of providing a structural basis for subsequently forming a memory test structure and performing electrical detection on the memory gate structure.

[0050] Specifically, in this embodiment, the thickness range of the first oxide layer 205 is: The thickness range of the second oxide layer 207 is:

[0051] The floating gate 206 is made of polysilicon.

[0052] The word line gate 208 is made of polysilicon.

[0053] The floating gate structure 202 further includes a third oxide layer 209 located on the sidewall surface of the floating gate 206 .

[0054] Specifically, in this embodiment, the distance from the top of the third oxide layer 209 to the top of the floating gate 206 is: The thickness range of the third oxide layer 209 is:

[0055] The third oxide layer 209 is located on the side wall surface of the floating gate 206. During the subsequent first etching process to remove the word line gate 208 and the process to remove the second oxide layer 207, the integrity of the floating gate 206 is protected, and the exposure of the doped region due to the loss of the floating gate 206 is avoided, thereby reducing the possibility of damage to the active area of ​​the test structure of the memory and improving the electrical performance of the test structure of the memory.

[0056] The control gate structure 203 includes a control gate dielectric layer 210 and a control gate 211 located on the surface of the control gate dielectric layer 210 .

[0057] The material of the control gate 211 includes polysilicon.

[0058] The material of the control gate dielectric layer 210 includes: a stack of one or more layers of silicon nitride or silicon oxide.

[0059] Specifically, in this embodiment, the initial storage gate structure 201 further includes an initial first spacer 212 located on the sidewall surface of the control gate structure 203 .

[0060] The material of the initial first spacer 212 includes: a stack of one or more layers of silicon nitride or silicon oxide.

[0061] Please refer to Figure 7 After the initial storage gate structure 201 is formed, a dielectric structure 213 is formed on the initial storage gate structure 201 .

[0062] The method for forming the dielectric structure 213 includes: chemical vapor deposition.

[0063] The dielectric structure 213 includes a stack of one or more layers of silicon oxide, polysilicon or silicon nitride. Specifically, in this embodiment, the dielectric structure 213 is silicon oxide.

[0064] Please refer to Figure 8 After forming the dielectric structure 213 , a first etching process is used to form a first opening 214 in the initial storage gate structure 201 , wherein the first opening 214 exposes the surface of the word line gate structure 204 .

[0065] The method for forming the first opening 214 includes: forming the first opening 214 in the dielectric structure 213 (such as Figure 7 A first mask layer (not shown) is formed on the surface of the substrate 200, the first mask layer (not shown) has a first projection on the surface of the substrate 200, and the word line gate structure 204 has a second projection on the surface of the substrate 200, and the second projection is within the range of the first projection; the first mask layer (not shown) is used as a mask, and the dielectric structure 213 (as shown) is etched by a first etching process. Figure 7 ) and the initial storage gate structure 201, forming a first opening 214 exposing the surface of the word line gate structure 204.

[0066] The first etching process includes anisotropic dry etching and isotropic wet etching. Specifically, in this embodiment, the first etching process is isotropic dry etching; in other embodiments, the first etching process may also be isotropic wet etching.

[0067] Specifically, in the present embodiment, the advantage of the first etching process is that the first etching process is anisotropic dry etching. Compared with isotropic wet etching, the first etching process has a higher etching precision and better edge morphology control.

[0068] Specifically, in this embodiment, the difference between the first etching process and the subsequent second etching process for removing the word line gate 208 is that: the first etching process is a non-selective etching process, and the difference in removal rate between the material of the initial storage gate structure 201 and the material of the dielectric structure 213 is small. By controlling the etching time of the first etching process, the distance from the bottom of the first opening 214 formed by etching to the top of the third oxide layer 209 is kept within a certain range, thereby avoiding the third oxide layer 209 from being consumed; and the subsequent second etching process for removing the word line gate 208 is a selective etching process. Compared with the first etching process, the etching gas composition, electric field strength and chamber pressure of the etching process are different. The removal rate of the word line gate 208 material is significantly different from the removal rate of the second oxide layer 207 material. In the process of etching and removing the word line gate 208, the second oxide layer 207 is not damaged, thereby improving the etching accuracy in the process of removing the word line gate 208, protecting the integrity of the floating gate 206, avoiding the exposure of the doped area due to the damage of the floating gate 206, reducing the possibility of damage to the active area of ​​the test structure of the memory, and improving the electrical performance of the test structure of the memory.

[0069] The parameters of the first etching process include etching time; there is a negative correlation between the etching time and the distance from the bottom of the first opening 214 to the top of the third oxide layer 209 .

[0070] Specifically, in this embodiment, the distance from the bottom of the first opening 214 to the top of the third oxide layer 209 is in the range of:

[0071] Specifically, in this embodiment, the difference between the removal rate of the initial storage gate structure 201 material and the removal rate of the dielectric structure 213 material by the first etching process is less than a second threshold; the second threshold is 2A / S.

[0072] The difference between the removal rate of the initial storage gate structure 201 material and the removal rate of the dielectric structure 213 material by the first etching process is less than a second threshold value. The first etching process includes selective etching and non-selective etching, providing more options for the process.

[0073] Specifically, in this embodiment, please refer to Figure 8 , when the distance from the bottom of the first opening 214 to the top of the third oxide layer 209 is When the first opening 214 is formed, the top surface of the portion of the control gate 211 adjacent to the word line gate 208 and the top surface of the initial first spacer 212 are exposed.

[0074] The first etching process etches the materials of the initial storage gate structure 201 and the dielectric structure 213 but does not etch the materials of the third oxide layer 209 and the second oxide layer 207. This will prevent the initial storage gate structure 201, the dielectric structure 213 from having loose materials and the second oxide layer 207 and the third oxide layer 209 from having dense materials. This will avoid different depths of the first opening 214 at different locations, thereby improving the etching accuracy.

[0075] In another embodiment, please refer to Fig. 9 The first etching process also etches a portion of the control gate 211 and the initial first spacer 212 (such as Figure 7 As shown in FIG. 1 , the first opening 214 extends into the second portion and exposes a portion of the top surface of the first portion, and a first sidewall 215 is provided on the sidewall surface of the first portion.

[0076] The first etching process etches the materials of the initial storage gate structure 201 and the dielectric structure 213 but does not etch the materials of the third oxide layer 209 and the second oxide layer 207. This will prevent the initial storage gate structure 201, the dielectric structure 213 from having loose materials and the second oxide layer 207 and the third oxide layer 209 from having dense materials. This will avoid different depths of the first opening 214 at different locations, thereby improving the etching accuracy.

[0077] In another embodiment, please refer to Fig.10 When the distance from the bottom of the first opening 214 to the top of the third oxide layer 209 is 0, the first etching process also etches a portion of the control gate 211 adjacent to the word line gate 208 and the initial first spacer 212 (such as Figure 7 As shown), until the control gate dielectric layer 210 is exposed, the first opening 214 extends into the control gate 211 and exposes the control gate dielectric layer 210.

[0078] The first etching process etches the materials of the initial storage gate structure 201 and the dielectric structure 213 but does not etch the materials of the third oxide layer 209 and the second oxide layer 207. This will prevent the initial storage gate structure 201, the dielectric structure 213 from having loose materials and the second oxide layer 207 and the third oxide layer 209 from having dense materials. This will avoid different depths of the first opening 214 at different locations, thereby improving the etching accuracy.

[0079] When the first etching process is anisotropic dry etching, the parameters of the first etching process include: etching gas includes: carbon tetrafluoride, trifluoromethane, helium, argon, sulfur dioxide or hydrogen bromide; etching time range is: 20s~60s; plasma applied electric field strength range is: 50V~400V.

[0080] When the first etching process is isotropic wet etching, the parameters of the first etching process include: etching liquid includes: sulfuric acid, phosphoric acid, hydrofluoric acid or distilled water; etching liquid concentration ratio includes: 1:500, 1:1000, 1:2000 or 1:10000; etching time range is: 25s~200s.

[0081] Please Figure 8 Based on reference Fig.11 , a second etching process is used to remove the word line gate 208 (such as Figure 8 As shown), the second etching process is performed on the word line gate 208 (as shown Figure 8 The difference between the removal rate of the material of the second oxide layer 207 and the removal rate of the material of the second oxide layer 207 is greater than a first threshold.

[0082] Specifically, in this embodiment, the second etching process includes: anisotropic dry etching; when the second etching process is anisotropic dry etching, the parameters of the second etching process include: etching gas includes: carbon tetrafluoride, trifluoromethane, helium, argon, sulfur dioxide or hydrogen bromide; etching time range is: 40s to 150s; plasma applied electric field strength range is: 50V to 350V; the first threshold value is: 30A / s. The second etching process is different from the first etching process mainly in gas composition, electric field strength, and chamber pressure.

[0083] Specifically, in the present embodiment, the second etching process has the advantage that the second etching process is anisotropic dry etching, and the second oxide layer 207 is not damaged during the process of removing the word line gate 208 .

[0084] Specifically, in the present embodiment, the difference between the second etching process and the first etching process is that: the first etching process is a non-selective etching process, and the difference in removal rate between the material of the initial storage gate structure 201 and the material of the dielectric structure 213 is small. The etching time of the first etching process can be controlled so that the distance from the bottom of the first opening 214 formed by etching to the top of the third oxide layer 209 is maintained within a certain range, thereby avoiding the third oxide layer 209 from being consumed; while the second etching process is a selective etching process, and the difference in removal rate between the material of the word line gate 208 and the material of the second oxide layer 207 is large. In the process of etching and removing the word line gate 208, the second oxide layer 207 is not consumed, thereby improving the etching accuracy in the process of removing the word line gate 208, protecting the integrity of the floating gate 206, avoiding the exposure of the doped region caused by the loss of the floating gate 206, reducing the possibility of damage to the active area of ​​the test structure of the memory, and improving the electrical performance of the test structure of the memory.

[0085] The second etching process is performed on the word line gate 208 (such as Figure 8 The difference between the removal rate of the material of the second oxide layer 207 and the removal rate of the material of the second oxide layer 207 is greater than a first threshold, and the second etching process is selective etching.

[0086] The word line gate 208 is made of polysilicon.

[0087] Specifically, in this embodiment, the first threshold is 30 A / s.

[0088] The word line gate 208 is removed by a second etching process, the difference between the removal rate of the word line gate 208 material and the removal rate of the second oxide layer 207 material by the second etching process is greater than a first threshold, the word line gate 208 is removed without damaging the second oxide layer 207, and the etching accuracy is improved during the removal of the word line gate 208. The possibility of damage to the active area of ​​the test structure of the memory is reduced, and the electrical performance of the test structure of the memory is improved.

[0089] Please refer to Fig.12 , after removing the word line gate 208 (such as Figure 8 After that, the second oxide layer 207 (as shown in Fig.11 As shown), a storage gate structure 216 is formed on the surface of the first oxide layer 205, the storage gate structure 216 includes a floating gate structure 202 and a control gate structure 203 located on the surface of the floating gate structure 202, the storage gate structure 216 includes a first side wall adjacent to the second region II, the surface of the floating gate structure 202 of the first side wall protrudes from the surface of the control gate structure 203 of the first side wall, and a second opening 217 exposing the surface of the second region II is provided between adjacent storage gate structures 216.

[0090] Specifically, in this embodiment, the first sidewall includes: a third oxide layer 209 and an initial first sidewall 212 .

[0091] The second opening 217 provides a structural foundation for the subsequent formation of a conductive layer 218 and a conductive plug 219 .

[0092] The method for removing the second oxide layer 207 includes: a third etching process; the third etching process includes: anisotropic dry etching; the difference between the removal rate of the second oxide layer 207 material and the removal rate of the floating gate 206 material by the third etching process is greater than a third threshold.

[0093] The etching parameters of the third etching process include: etching gas includes: carbon tetrafluoride, trifluoromethane, helium, argon, sulfur dioxide or hydrogen bromide; etching time range is: 30s to 80s; plasma applied electric field strength range is: 50V to 300V.

[0094] The third threshold value is 40A / s.

[0095] The difference between the removal rate of the second oxide layer 207 material and the removal rate of the floating gate 206 material by the third etching process is greater than a third threshold value. By adopting a high selectivity etching method, only the second oxide layer 207 material is removed during the removal of the second oxide layer 207 without consuming the floating gate 206, so that the doped area is not exposed, thereby reducing the possibility of leakage of the test structure of the memory and improving the electrical performance of the test structure of the memory.

[0096] Please refer to Fig.13 , when forming the second opening 217 (such as Fig.12 As shown in the figure, a conductive layer 218 is formed on the surface of the second region II; after the conductive layer 218 is formed, a conductive plug 219 is formed on the surface of the conductive layer 218.

[0097] The conductive layer 218 has the function of reducing contact resistance and increasing electrical conductivity.

[0098] The material of the conductive layer 218 includes metal silicide.

[0099] The conductive plug 219 is used to electrically connect to the conductive layer 218 for testing the electrical properties of the storage gate structure.

[0100] The method for forming the conductive plug 219 includes: forming a dielectric layer (not shown) on the conductive layer 218 to fill the second opening 217; forming a third opening (not shown) in the dielectric layer, wherein the third opening (not shown) exposes a portion of the surface of the conductive layer 218; and forming the conductive plug 219 in the third opening (not shown).

[0101] Accordingly, the embodiment of the present invention also provides a memory test structure, please continue to refer to Fig.13 , comprising: a substrate 200, wherein the substrate 200 comprises a plurality of storage areas, each storage area comprises two first areas I and a second area II located between the two first areas I, wherein the first area I has a doped area; a first oxide layer 205 located on the surface of the first area I; a storage gate structure 216 located on the surface of the first oxide layer 205, wherein the storage gate structure 216 comprises a floating gate 206 and a control gate structure 203 located on the surface of the floating gate 206, wherein the storage gate structure 216 comprises a first side wall adjacent to the second area II, wherein the surface of the floating gate 206 of the first side wall protrudes from the surface of the control gate structure 203 of the first side wall, and a second opening 217 exposing the surface of the second area II is provided between adjacent storage gate structures 216.

[0102] Specifically, in this embodiment, the first sidewall includes: a third oxide layer 209 and an initial first sidewall 212 .

[0103] The memory test structure further includes: a conductive layer 218 located on a surface of the second opening 217 ; and a conductive plug 219 located on a surface of the conductive layer 218 .

[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A memory test structure, characterized in that: include: A substrate, the substrate comprising a plurality of storage areas, each storage area comprising two first areas and a second area located between the two first areas, the first areas having a doped area; a first oxide layer located on a surface of the first region; A storage gate structure is located on the surface of the first oxide layer, the storage gate structure includes a floating gate and a control gate structure located on the surface of the floating gate, the storage gate structure includes a first side wall adjacent to the second region, the floating gate surface of the first side wall protrudes from the control gate structure surface of the first side wall, and a second opening exposing the surface of the second region is provided between adjacent storage gate structures.

2. A method for forming a test structure of a memory, characterized in that: include: Providing a substrate, the substrate comprising a plurality of storage areas, each storage area comprising two first areas and a second area located between the two first areas, the first area having a doped area; An initial storage gate structure is formed on the storage area, the initial storage gate structure comprising: a floating gate structure located on the surface of the first area, a control gate structure located on the surface of the floating gate structure, and a word line gate structure located on the surface of the second area, the floating gate structure comprising a first oxide layer located on the surface of the first area and a floating gate located on the first oxide layer, and the word line gate structure comprising a second oxide layer located on the surface of the second area and a word line gate located on the second oxide layer; Using a first etching process to form a first opening in the initial storage gate structure, wherein the first opening exposes a surface of the word line gate structure; A second etching process is used to remove the word line gate, and the difference between the removal rate of the word line gate material and the removal rate of the second oxide layer material by the second etching process is greater than a first threshold; after removing the word line gate, the second oxide layer is removed to form a storage gate structure located on the surface of the first oxide layer, the storage gate structure includes a floating gate structure and a control gate structure located on the surface of the floating gate structure, the storage gate structure includes a first side wall adjacent to the second region, the floating gate structure surface of the first side wall protrudes from the control gate structure surface of the first side wall, and a second opening exposing the surface of the second region is provided between adjacent storage gate structures.

3. The method for forming a memory test structure according to claim 2, wherein: The control gate structure includes a control gate dielectric layer and a control gate located on the surface of the control gate dielectric layer; the initial storage gate structure also includes an initial first spacer located on the sidewall surface of the control gate structure.

4. The method for forming a memory test structure according to claim 3, wherein: The control gate includes a first part and a second part located on the first part; the first etching process also etches a portion of the control gate adjacent to the word line gate and an initial first sidewall, so that the first opening extends into the second part and exposes a portion of the top surface of the first part, and a first sidewall is provided on the sidewall surface of the first part.

5. The method for forming a memory test structure according to claim 3, wherein: The first opening exposes a portion of a top surface of the control gate adjacent to the word line gate and a top surface of an initial first spacer.

6. The method for forming a memory test structure according to claim 3, wherein: The first etching process also etches a portion of the control gate adjacent to the word line gate and an initial first spacer until the control gate dielectric layer is exposed, so that the first opening extends into the control gate and exposes the control gate dielectric layer.

7. The method for forming a memory test structure according to claim 2, wherein: The floating gate structure further includes: a third oxide layer located on the sidewall surface of the floating gate; the distance from the top of the third oxide layer to the top of the floating gate is: The thickness range of the third oxide layer is:

8. The method for forming a test structure of a memory as claimed in claim 7, characterized in that: After forming the initial storage gate structure and before forming the first opening, the method further includes: forming a dielectric structure located on the initial storage gate structure; the dielectric structure includes a stack of one or more layers of silicon oxide, polysilicon or silicon nitride.

9. The method for forming a memory test structure according to claim 8, wherein: The method for forming the first opening includes: forming a first mask layer on the surface of the dielectric structure, the first mask layer having a first projection on the substrate surface and the word line gate structure having a second projection on the substrate surface, the second projection being within the range of the first projection; using the first mask layer as a mask, etching the dielectric structure and the initial storage gate structure by a first etching process to form a first opening exposing the surface of the word line gate structure; the distance range from the bottom of the first opening to the top of the third oxide layer is: The difference between the removal rate of the initial storage gate structure material and the removal rate of the dielectric structure material by the first etching process is less than a second threshold; the second threshold is 2A / S.

10. The method for forming a memory test structure according to claim 9, wherein: The first etching process includes anisotropic dry etching and isotropic wet etching; the parameters of the first etching process include etching time; there is a negative correlation between the etching time and the distance from the bottom of the first opening to the top of the third oxide layer.

11. The method for forming a memory test structure according to claim 2, wherein: After forming the second opening, the method further includes: forming a conductive layer on the surface of the second region; and after forming the conductive layer, the method further includes: forming a conductive plug on the surface of the conductive layer.

12. The method for forming a memory test structure according to claim 10, wherein: When the first etching process is anisotropic dry etching, the parameters of the first etching process include: etching gas includes: carbon tetrafluoride, trifluoromethane, helium, argon, sulfur dioxide or hydrogen bromide; etching time range is: 20s~60s; plasma applied electric field strength range is: 50V~400V.

13. The method for forming a memory test structure according to claim 10, wherein: When the first etching process is isotropic wet etching, the parameters of the first etching process include: etching liquid includes: sulfuric acid, phosphoric acid, hydrofluoric acid or distilled water; etching liquid concentration ratio includes: 1:500, 1:1000, 1:2000 or 1:10000; etching time range is: 25s~200s.

14. The method for forming a memory test structure according to claim 2, wherein: The second etching process includes: anisotropic dry etching; when the second etching process is anisotropic dry etching, the parameters of the second etching process include: etching gas includes: carbon tetrafluoride, trifluoromethane, helium, argon, sulfur dioxide or hydrogen bromide; etching time range is: 40s~150s; plasma applied electric field strength range is: 50V~350V; the size of the first threshold is: 30A / s.

15. The method for forming a memory test structure according to claim 2, wherein: The thickness range of the first oxide layer is: The thickness range of the second oxide layer is:

16. The method for forming a memory test structure according to claim 2, wherein: The method for removing the second oxide layer includes: a third etching process; the third etching process includes: anisotropic dry etching; the difference between the removal rate of the second oxide layer material and the removal rate of the floating gate material by the third etching process is greater than a third threshold; the etching parameters include: etching gas includes: carbon tetrafluoride, trifluoromethane, helium, argon, sulfur dioxide or hydrogen bromide; the etching time range is: 30s to 80s; the plasma applied electric field strength range is: 50V to 300V; the size of the third threshold is: 40A / s.

17. The method for forming a memory test structure according to claim 2, wherein: Before forming the initial storage gate structure, the method further includes: performing a modification treatment on the second region; the modification treatment method includes: forming a second mask layer on the surface of the substrate, wherein the second mask layer exposes the surface of the second region; performing a modification treatment on the substrate exposed by the second mask layer; the modification treatment process is ion implantation; the parameters of the ion implantation process include: the energy range of the ion implantation is: 5KeV to 50KeV; the dose range of the ion implantation is: 6E13 ions / cm 2 ~6E15ions / cm 2 .

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