Power device PCM monitoring structure and monitoring method

Abstract

The invention discloses a power device PCM monitoring structure and a monitoring method, and relates to the field of power devices.The power device PCM monitoring structure is characterized in that a plurality of stacked resistor strips are designed and arranged on a scribing channel of a wafer, the resistor strips are connected with two adjacent p columns in an SJ MOS, the number of the resistor strips is the same as the number of times of p-type ion implantation of the p columns, and the number of the p columns is smaller than the number of times of p-type ion implantation of the p columns; by testing the resistance value of a resistor strip in a scribing channel, detection of any one layer or any multiple layers of pilar resistors of p columns of SJ MOS in wafers of different Lot is achieved, and by comparing the difference of the resistance value of any one layer or any multiple layers of pilar resistors of p columns of SJ MOS in wafers of different Lot, the corresponding relation between pilar doping and BVDSS stability is confirmed. Factors of BVDSS fluctuation can be accurately and rapidly found through a comparison result, and stability of a mass production process is better achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power devices, and in particular relates to a power device PCM (Process Control Monitor) monitoring structure and a monitoring method. Background Art

[0002] In order to form a matching p-type structure, the SJ MOS (super junction MOSFET) with multiple epitaxial implantation process must undergo multiple epitaxial layer growth and p-type ion implantation. The number of growths is directly proportional to the cost. Although the multiple epitaxial implantation process is more expensive, different parameters such as implantation energy and implantation dose can be controlled after each epitaxy to form different p-type region distributions at different depths as required.

[0003] The mass production of SJ MOS requires precise control of the charge balance between n-type and p-type. How to precisely control the charge balance is of great significance to the mass production of SJ MOS, and it significantly affects the level of BVDSS (drain-source breakdown voltage).

[0004] In the current mass production of SJ MOS multi-layer epitaxy, it is necessary to monitor the stability of one or more pillar doping layers to simultaneously monitor the stability of the BVDSS of the SJ MOS. In current mass production, the stability of doping is mainly ensured by monitoring the stability of ion implantation RS (square resistance). In the existing monitoring method, the RS overlaps for every 0.1e13 difference in boron ion implantation, resulting in low monitoring accuracy. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a power device PCM monitoring structure and monitoring method. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a power device PCM monitoring structure, comprising: a plurality of stacked resistor bars located in a wafer scribe line, the resistor bars are connected to two adjacent p columns in SJ MOS, and the number of the resistor bars is the same as the number of p-type ion implantations of the p columns.

[0007] In one embodiment of the present invention, the resistor bar is a rectangular parallelepiped structure formed by epitaxial layer growth and p-type ion implantation.

[0008] In one embodiment of the present invention, the width-to-length ratio of the resistor strip is 10 / 1000.

[0009] In one embodiment of the present invention, the p-pillar includes a plurality of pillars stacked from bottom to top, and the pillars are formed by epitaxial layer growth and p-type ion implantation.

[0010] In one embodiment of the present invention, the p-type ion implantation dosage of the resistor strip is the same as the p-type ion implantation dosage of the corresponding pillar in the p-column.

[0011] In one embodiment of the present invention, two contact holes are further provided in the ILD layer, and the two contact holes correspond to positions of two adjacent p-columns in a one-to-one manner.

[0012] In one embodiment of the present invention, a metal lead is disposed in the contact hole, one end of the metal lead is connected to the p-column, and the other end of the metal lead is connected to the pad.

[0013] The present invention provides a monitoring method of a power device PCM monitoring structure as described in any one of the above embodiments, comprising:

[0014] Expose the resistor strip corresponding to the pillar to be monitored in the SJ MOS;

[0015] Loading voltage on the pad to test the resistance value of the exposed resistor strip, and obtaining the resistance detection value of the pillar to be monitored;

[0016] The resistance detection values ​​of the pillar to be monitored of the SJ MOS in wafers of different lots are compared, and whether the BVDSS of the SJ MOS is stable is determined according to the comparison result.

[0017] In one embodiment of the present invention, when the difference in resistance detection values ​​of the pillar to be monitored of the SJ MOS in wafers of different lots is greater than a preset threshold, the BVDSS of the SJ MOS is unstable.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The power device PCM monitoring structure of the present invention designs and arranges multiple stacked resistor bars in the wafer dicing lane, the resistor bars are connected to two adjacent p-pillars in the SJ MOS, the number of resistor bars is the same as the number of p-type ion implantations of the p-pillars, and the resistance value of the resistor bars in the dicing lane is tested to detect any one or more layers of pillar resistance of the p-pillars of the SJ MOS in wafers of different lots, and the corresponding relationship between pillar doping and BVDSS stability is confirmed by comparing the difference in the pillar resistance value of any one or more layers of the p-pillars of the SJ MOS in wafers of different lots. By comparing the results, the factors of BVDSS fluctuation can be accurately and quickly found, the stability of mass production process can be better achieved, BVDSS fluctuation can be reduced, and thus the economic losses caused by BVDSS fluctuation can be reduced.

[0020] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following specifically cites a preferred embodiment and describes it in detail with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of a PCM monitoring structure of a power device provided by an embodiment of the present invention;

[0022] Figure 2 It is a schematic diagram of monitoring the resistance value of the first layer of pillar in a p-pillar through a power device PCM monitoring structure provided by an embodiment of the present invention;

[0023] Figure 3 It is a schematic diagram of monitoring the resistance value of the first layer pillar + the second layer pillar in a p-pillar through a power device PCM monitoring structure provided by an embodiment of the present invention;

[0024] Figure 4 It is a schematic diagram of monitoring the resistance value of the first layer of pillar + the second layer of pillar + the third layer of pillar in a p-pillar through a power device PCM monitoring structure provided by an embodiment of the present invention;

[0025] Figure 5 It is a schematic diagram of monitoring the resistance value of the first layer of pillar + the second layer of pillar + the third layer of pillar + the fourth layer of pillar in a p-pillar through a power device PCM monitoring structure provided by an embodiment of the present invention;

[0026] Figure 6 It is a schematic diagram of monitoring the resistance values ​​of the first layer of pillar + the second layer of pillar + the third layer of pillar + the fourth layer of pillar + the fifth layer of pillar in a p-pillar through a power device PCM monitoring structure provided by an embodiment of the present invention;

[0027] Figure 7 It is a schematic diagram of monitoring the resistance value of the second layer of pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention;

[0028] Figure 8 It is a schematic diagram of monitoring the resistance value of the second layer pillar + the third layer pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention;

[0029] Fig. 9 It is a schematic diagram of monitoring the resistance value of the second layer pillar+the third layer pillar+the fourth layer pillar in a p-pillar through a power device PCM monitoring structure provided by an embodiment of the present invention;

[0030] Fig.10 It is a schematic diagram of monitoring the resistance value of the third pillar layer in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention;

[0031] Fig.11 It is a schematic diagram of monitoring the resistance value of the third pillar layer + the fourth pillar layer in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention.

[0032] Icons: 10-resistance strip; 20-p pillar; 21-first layer pillar; 22-second layer pillar; 23-third layer pillar; 24-fourth layer pillar; 25-fifth layer pillar; 26-sixth layer pillar; 30-ILD layer; 31-contact hole; 32-metal lead; 40-pad. DETAILED DESCRIPTION

[0033] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, a power device PCM monitoring structure and monitoring method proposed in accordance with the present invention are described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0034] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0035] In the first aspect, the embodiment of the present invention provides a power device PCM monitoring structure, see Figure 1 , Figure 1 Schematic diagram of a power device PCM monitoring structure provided by an embodiment of the present invention. Figure 1 As shown, the power device PCM monitoring structure of this embodiment includes: a plurality of stacked resistor bars 10 located in the dicing lanes of the wafer, the resistor bars 10 are connected to two adjacent p-pillars 20 in the SJ MOS, and the number of the resistor bars 10 is the same as the number of p-type ion implantations of the p-pillars 20.

[0036] In the process of preparing SJ MOS, the p-pillar is formed by multiple epitaxial layer growth and p-type ion implantation, and the p-pillar can be regarded as composed of multiple pillars stacked from bottom to top. In this embodiment, when preparing the p-pillar, epitaxial layer growth and p-type ion implantation are performed simultaneously in the wafer dicing lane to form a rectangular parallelepiped structure, which serves as the resistor bar 10, and the p-type ion implantation dose of the resistor bar 10 is the same as the p-type ion implantation dose of the corresponding pillar in the p-pillar 20.

[0037] For example, Figure 1 As shown, the p-pillar in the SJ MOS includes six pillars stacked from bottom to top, namely, the first layer pillar 21, the second layer pillar 22, the third layer pillar 23, the fourth layer pillar 24, the fifth layer pillar 25 and the sixth layer pillar 26. Therefore, six resistor bars 10 are correspondingly arranged in the power device PCM monitoring structure of this embodiment.

[0038] Optionally, the ratio of width to length of the resistor strip 10 is 10 / 1000.

[0039] Please continue to see Figure 1 The power device PCM monitoring structure of this embodiment also includes two contact holes 31 arranged in the ILD (InterLayer Dielectric) layer 30, and a metal lead 32 is arranged in the contact hole 31. One end of the metal lead 32 is connected to the p column 20, and the other end is connected to the pad 40.

[0040] In this embodiment, the resistance value of the resistor bar 10 can be tested by applying a voltage across the pad 40 .

[0041] In the power device PCM monitoring structure of this embodiment, since the p-type ion implantation dosage of the resistor bar 10 is the same as the p-type ion implantation dosage of the corresponding pillar in the p-pillar 20, the resistance value of the corresponding pillar in the p-pillar 20 can be monitored by measuring the resistance value of the resistor bar 10, thereby determining the stability of doping. For example, the resistance value of the first layer of pillar 21 can be monitored by testing the resistance value of the resistor bar 10 corresponding to the first layer of pillar 21, that is, the resistance value of the bottom layer of resistor bar 10, thereby determining the stability of the first doping of the p-pillar 20; the resistance values ​​of the first layer of pillar 21 and the second layer of pillar 22 can be monitored by testing the resistance values ​​of the resistor bars 10 corresponding to the first layer of pillar 21 and the second layer of pillar 22, that is, the resistance values ​​of the two resistor bars 10 at the bottom layer, thereby determining the stability of the first and second doping superposition of the p-pillar 20.

[0042] The power device PCM monitoring structure of this embodiment can monitor the resistance value of one or more pillar layers of the p-pillar 20 , solving the problem that the doping of one or more pillar layers of the p-pillar 20 cannot be arbitrarily monitored.

[0043] The PCM monitoring structure of the power device of the embodiment of the present invention designs and arranges multiple stacked resistor bars in the wafer dicing lane, the resistor bars are connected to two adjacent p-pillars in the SJ MOS, the number of resistor bars is the same as the number of p-type ion implantations of the p-pillars, and the resistance value of the resistor bars in the dicing lane is tested to detect any one or more layers of pillar resistance of the p-pillars of the SJ MOS in wafers of different lots, and the corresponding relationship between pillar doping and BVDSS stability is confirmed by comparing the difference in the pillar resistance value of any one or more layers of the p-pillars of the SJ MOS in wafers of different lots. By comparing the results, the factors of BVDSS fluctuation can be accurately and quickly found, the stability of mass production process can be better achieved, BVDSS fluctuation can be reduced, and thus the economic losses caused by BVDSS fluctuation can be reduced.

[0044] In a second aspect, an embodiment of the present invention provides a monitoring method for a PCM monitoring structure of a power device, comprising:

[0045] Step 1: Expose the resistor strip corresponding to the pillar to be monitored in the p-column of the SJ MOS.

[0046] In this embodiment, the pillar to be monitored may be any one layer or any multiple layers of pillars of the p-column of the SJ MOS.

[0047] Step 2: Load voltage on the pad to test the resistance value of the exposed resistor strip and obtain the resistance detection value of the pillar to be monitored.

[0048] Step 3: Compare the resistance detection values ​​of the pillar to be monitored of the SJ MOS in wafers of different lots, and determine whether the BVDSS of the SJ MOS is stable based on the comparison results.

[0049] "Lot" refers to a group of wafers or a batch of products in the semiconductor manufacturing process. Usually, multiple wafers are put together for the same process during wafer manufacturing, and the group of these wafers is a "Lot". In this embodiment, when the difference in the resistance detection value of the pillar to be monitored of the SJ MOS in wafers of different Lots is greater than a preset threshold, the BVDSS of the SJ MOS is unstable.

[0050] Furthermore, the monitoring method of the power device PCM monitoring structure of this embodiment is described in detail through specific examples.

[0051] See also Figure 2 , Figure 2 Schematic diagram of monitoring the resistance value of the first layer of pillar in a p-pillar through a power device PCM monitoring structure provided by an embodiment of the present invention. Figure 2 As shown, for monitoring the doping of the first layer pillar 21 in the p-pillar, the resistor strip 10 corresponding to the first layer pillar 21 in the p-pillar, that is, the bottom layer resistor strip 10 is first exposed, and then a voltage is loaded on the pad 40 to test the resistance value of the bottom layer resistor strip 10, thereby obtaining the resistance detection value of the first layer pillar 21 in the p-pillar. The above method can be used to detect the resistance detection value of the first layer pillar 21 in the p-pillar of the SJ MOS in wafers of different lots, and then compare them. If the difference in the resistance detection value of the first layer pillar 21 of the SJ MOS in wafers of different lots is less than a preset threshold, then the first doping of the p-pillar 20 is stable, otherwise the first doping of the p-pillar 20 is unstable.

[0052] See also Figure 3 , Figure 3 Schematic diagram of monitoring the resistance value of the first layer pillar + the second layer pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention. Figure 3 As shown, for monitoring the doping of the first layer pillar21+the second layer pillar22 in the p-pillar, firstly, the resistor strips 10 corresponding to the first layer pillar21+the second layer pillar22 in the p-pillar, that is, the two resistor strips 10 at the bottom layer are exposed, and then a voltage is applied to the pad40 to test the resistance value of the two resistor strips 10 at the bottom layer, so as to obtain the resistance detection value of the first layer pillar21+the second layer pillar22 in the p-pillar. The above method can be used to detect the resistance detection value of the first layer pillar21+the second layer pillar22 in the p-pillar of the SJ MOS in wafers of different lots, and then compare them. If the difference in the resistance detection value of the first layer pillar21+the second layer pillar22 in the SJ MOS in wafers of different lots is less than a preset threshold, then the first and second doping superposition of the p-pillar 20 is stable, otherwise, the first and second doping superposition of the p-pillar 20 is unstable.

[0053] See also Figure 4 , Figure 4 Schematic diagram of monitoring the resistance value of the first layer pillar+the second layer pillar+the third layer pillar in a p-pillar through a power device PCM monitoring structure provided by an embodiment of the present invention. Figure 4As shown, for monitoring the doping of the first layer pillar21+the second layer pillar22+the third layer pillar23 in the p-column, the resistor strips 10 corresponding to the first layer pillar21+the second layer pillar22+the third layer pillar23 in the p-column, that is, the three resistor strips 10 at the bottom layer are first exposed, and then a voltage is loaded on pad40 to test the resistance value of the three resistor strips 10 at the bottom layer, thereby obtaining the resistance detection value of the first layer pillar21+the second layer pillar22+the third layer pillar23 in the p-column. The above method can be used to detect the resistance detection values ​​of the first layer pillar21+the second layer pillar22+the third layer pillar23 in the p-pillar of the SJ MOS in wafers of different lots, and then compare them. If the difference in the resistance detection values ​​of the first layer pillar21+the second layer pillar22+the third layer pillar23 of the SJ MOS in wafers of different lots is less than a preset threshold, then the first, second and third doping superpositions of the p-pillar 20 are stable; otherwise, the first, second and third doping superpositions of the p-pillar 20 are unstable.

[0054] See also Figure 5 , Figure 5 Schematic diagram of monitoring the resistance value of the first layer pillar + the second layer pillar + the third layer pillar + the fourth layer pillar in the p-pillar by the power device PCM monitoring structure provided by an embodiment of the present invention. Figure 5As shown, for monitoring the doping of the first layer pillar21+the second layer pillar22+the third layer pillar23+the fourth layer pillar24 in the p-column, the resistor strips 10 corresponding to the first layer pillar21+the second layer pillar22+the third layer pillar23+the fourth layer pillar24 in the p-column, that is, the four resistor strips 10 at the bottom layer are first exposed, and then a voltage is loaded on pad40 to test the resistance value of the four resistor strips 10 at the bottom layer, thereby obtaining the resistance detection value of the first layer pillar21+the second layer pillar22+the third layer pillar23+the fourth layer pillar24 in the p-column. The above method can be used to detect the resistance detection values ​​of the first layer pillar21+the second layer pillar22+the third layer pillar23+the fourth layer pillar24 in the p-column of the SJ MOS in wafers of different lots, and then compare them. If the difference in the resistance detection values ​​of the first layer pillar21+the second layer pillar22+the third layer pillar23+the fourth layer pillar24 of the SJ MOS in wafers of different lots is less than a preset threshold, then the first, second, third and fourth doping superpositions of the p-column 20 are stable; otherwise, the first, second, third and fourth doping superpositions of the p-column 20 are unstable.

[0055] See also Figure 6 , Figure 6 Schematic diagram of monitoring the resistance value of the first layer of pillar + the second layer of pillar + the third layer of pillar + the fourth layer of pillar + the fifth layer of pillar in a p-pillar by a power device PCM monitoring structure provided by an embodiment of the present invention. Figure 6As shown, for monitoring the doping of the first layer pillar21+the second layer pillar22+the third layer pillar23+the fourth layer pillar24+the fifth layer pillar25 in the p-column, firstly, the resistor strips 10 corresponding to the first layer pillar21+the second layer pillar22+the third layer pillar23+the fourth layer pillar24+the fifth layer pillar25 in the p-column, that is, the five resistor strips 10 at the bottom layer are exposed, and then a voltage is loaded on pad40 to test the resistance value of the five resistor strips 10 at the bottom layer, so as to obtain the resistance detection value of the first layer pillar21+the second layer pillar22+the third layer pillar23+the fourth layer pillar24+the fifth layer pillar25 in the p-column. The above method can be used to detect the resistance detection values ​​of the first layer pillar21+the second layer pillar22+the third layer pillar23+the fourth layer pillar24+the fifth layer pillar25 in the p-column of the SJ MOS in wafers of different lots, and then compare them. If the difference in the resistance detection values ​​of the first layer pillar21+the second layer pillar22+the third layer pillar23+the fourth layer pillar24+the fifth layer pillar25 of the SJ MOS in wafers of different lots is less than a preset threshold, then the first, second, third, fourth and fifth doping superpositions of the p-column 20 are stable; otherwise, the first, second, third, fourth and fifth doping superpositions of the p-column 20 are unstable.

[0056] Please refer to Figure 7 , Figure 7 Schematic diagram of monitoring the resistance value of the second pillar layer in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention. Figure 7 As shown, for monitoring the doping of the second layer pillar 22 in the p-pillar, firstly, the resistor bar 10 corresponding to the second layer pillar 22 in the p-pillar, that is, the second resistor bar 10 counted from the bottom to the top, is exposed, and then a voltage is loaded on the pad 40 to test the resistance value of the resistor bar 10, so as to obtain the resistance detection value of the second layer pillar 22 in the p-pillar. The above method can be used to detect the resistance detection value of the second layer pillar 22 in the p-pillar of the SJ MOS in wafers of different lots, and then compare them. If the difference in the resistance detection value of the second layer pillar 22 of the SJ MOS in wafers of different lots is less than a preset threshold, then the second doping of the p-pillar 20 is stable, otherwise the second doping of the p-pillar 20 is unstable.

[0057] Please refer to Figure 8 , Figure 8Schematic diagram of monitoring the resistance value of the second layer pillar + the third layer pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention. Figure 8 As shown, for monitoring the doping of the second layer pillar 22 + the third layer pillar 23 in the p-pillar, firstly, the resistor bars 10 corresponding to the second layer pillar 22 + the third layer pillar 23 in the p-pillar, that is, the second and third resistor bars 10 counted from the bottom to the top, are exposed, and then a voltage is loaded on the pad 40 to test the resistance values ​​of the two resistor bars 10, so as to obtain the resistance detection value of the second layer pillar 22 + the third layer pillar 23 in the p-pillar. The above method can be used to detect the resistance detection value of the second layer pillar 22 + the third layer pillar 23 in the p-pillar of the SJ MOS in wafers of different lots, and then compare them. If the difference in the resistance detection value of the second layer pillar 22 + the third layer pillar 23 of the SJ MOS in wafers of different lots is less than the preset threshold, then the second and third doping superposition of the p-pillar 20 is stable, otherwise the second and third doping superposition of the p-pillar 20 is unstable.

[0058] See also Fig. 9 , Fig. 9 Schematic diagram of monitoring the resistance value of the second layer pillar + the third layer pillar + the fourth layer pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention. Fig. 9 As shown, for monitoring the doping of the second layer pillar22+the third layer pillar23+the fourth layer pillar24 in the p-column, firstly, the resistor bars 10 corresponding to the second layer pillar22+the third layer pillar23+the fourth layer pillar24 in the p-column, that is, the second, third and fourth resistor bars 10 from bottom to top are exposed, and then a voltage is loaded on pad40 to test the resistance values ​​of these three resistor bars 10, so as to obtain the resistance detection value of the second layer pillar22+the third layer pillar23+the fourth layer pillar24 in the p-column. The above method can be used to detect the resistance detection values ​​of the second layer pillar22+the third layer pillar23+the fourth layer pillar24 in the p-pillar of the SJ MOS in wafers of different lots, and then compare them. If the difference in the resistance detection values ​​of the second layer pillar22+the third layer pillar23+the fourth layer pillar24 of the SJ MOS in wafers of different lots is less than a preset threshold, then the second, third and fourth doping superpositions of the p-pillar 20 are stable; otherwise, the second, third and fourth doping superpositions of the p-pillar 20 are unstable.

[0059] See also Fig.10, Fig.10 Schematic diagram of monitoring the resistance value of the third pillar layer in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention. Fig.10 As shown, for monitoring the doping of the third layer pillar 23 in the p-pillar, firstly, the resistor bar 10 corresponding to the third layer pillar 23 in the p-pillar, that is, the third resistor bar 10 from bottom to top, is exposed, and then a voltage is loaded on the pad 40 to test the resistance value of the resistor bar 10, so as to obtain the resistance detection value of the third layer pillar 23 in the p-pillar. The above method can be used to detect the resistance detection value of the third layer pillar 23 in the p-pillar of the SJ MOS in wafers of different lots, and then compare them. If the difference in the resistance detection value of the third layer pillar 23 of the SJ MOS in wafers of different lots is less than a preset threshold, then the third doping of the p-pillar 20 is stable, otherwise the third doping of the p-pillar 20 is unstable.

[0060] See also Fig.11 , Fig.11 Schematic diagram of monitoring the resistance value of the third layer pillar + the fourth layer pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention. Fig.11 As shown, for monitoring the doping of the third layer pillar 23 + the fourth layer pillar 24 in the p-pillar, firstly, the resistor bars 10 corresponding to the third layer pillar 23 + the fourth layer pillar 24 in the p-pillar, that is, the third and fourth resistor bars 10 counted from the bottom to the top, are exposed, and then a voltage is loaded on the pad 40 to test the resistance values ​​of the two resistor bars 10, so as to obtain the resistance detection value of the third layer pillar 23 + the fourth layer pillar 24 in the p-pillar. The above method can be used to detect the resistance detection value of the third layer pillar 23 + the fourth layer pillar 24 in the p-pillar of the SJ MOS in wafers of different lots, and then compare them. If the difference in the resistance detection value of the third layer pillar 23 + the fourth layer pillar 24 in the SJ MOS in wafers of different lots is less than the preset threshold, then the third and fourth doping superposition of the p-pillar 20 is stable, otherwise the third and fourth doping superposition of the p-pillar 20 is unstable.

[0061] Combined with the above examples, it can be seen that by using the power device PCM monitoring structure provided by the present invention for monitoring, by comparing the difference in the pillar resistance value of any layer or any multiple layers of the p-pillar of the SJ MOS in wafers of different Lots, the corresponding relationship between pillar doping and BVDSS stability can be confirmed. By comparing the results, the factors of BVDSS fluctuation can be accurately and quickly found, the stability of mass production process can be better achieved, BVDSS fluctuation can be reduced, and thus the economic losses caused by BVDSS fluctuation can be reduced.

[0062] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0063] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A power device PCM monitoring structure, characterized in that: include: A plurality of stacked resistor bars are located in a scribe line of a wafer, the resistor bars are connected to two adjacent p-columns in an SJ MOS, and the number of the resistor bars is the same as the number of p-type ion implantations of the p-columns.

2. The power device PCM monitoring structure according to claim 1, characterized in that: The resistor bar is a rectangular parallelepiped structure formed by epitaxial layer growth and p-type ion implantation.

3. The power device PCM monitoring structure according to claim 2, characterized in that: The width-to-length ratio of the resistor strip is 10 / 1000.

4. The power device PCM monitoring structure according to claim 1, characterized in that: The p-column includes a plurality of pillars stacked from bottom to top, and the pillars are formed by epitaxial layer growth and p-type ion implantation.

5. The power device PCM monitoring structure according to claim 4, characterized in that: The p-type ion implantation dosage of the resistor strip is the same as the p-type ion implantation dosage of the corresponding pillar in the p column.

6. The power device PCM monitoring structure according to claim 1, characterized in that: The invention also includes two contact holes arranged in the ILD layer, wherein the two contact holes correspond to positions of two adjacent p-columns in a one-to-one manner.

7. The power device PCM monitoring structure according to claim 6, characterized in that: A metal lead is arranged in the contact hole, one end of the metal lead is connected to the p-column, and the other end is connected to the pad.

8. A monitoring method for a power device PCM monitoring structure according to any one of claims 1 to 7, characterized in that: include: Expose the resistor strip corresponding to the pillar to be monitored in the p-column of the SJ MOS; Loading voltage on the pad to test the resistance value of the exposed resistor strip, and obtaining the resistance detection value of the pillar to be monitored; The resistance detection values ​​of the pillar to be monitored of the SJ MOS in wafers of different lots are compared, and whether the BVDSS of the SJ MOS is stable is determined according to the comparison result.

9. The monitoring method of the power device PCM monitoring structure according to claim 8, characterized in that: When the difference in resistance detection values ​​of the pillar to be monitored of the SJ MOS in wafers of different lots is greater than a preset threshold, the BVDSS of the SJ MOS is unstable.

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