On-time generating circuit, integrated circuit chip and switching circuit

Abstract

The invention discloses a turn-on time generating circuit, an integrated circuit chip and a switching circuit, the turn-on time generating circuit is applied to the switching circuit, and outputs a turn-off control signal for controlling the turn-off of a first power tube in the switching circuit so as to control the turn-on time of the first power tube. The first end of the first power tube receives input voltage, the second end of the first power tube is connected with a switch node, and the turn-on time generating circuit is connected with the switch node and generates a ramp signal of which the slope is proportional to the voltage of the switch node during the turn-on period of the first power tube according to the voltage of the switch node; and generating a first reference signal capable of representing the average value of the voltage of the switch node, and outputting the turn-off control signal according to a comparison result of the ramp signal and the first reference signal. A corresponding integrated circuit chip does not need to be provided with pins for receiving the input voltage and the output voltage of the switching circuit, and resources can be saved.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a conduction time generating circuit, an integrated circuit chip and a switch circuit. Background Art

[0002] An existing switch circuit with a constant on-time control mode, such as Figure 1 As shown, taking the Buck switch circuit as an example, the switch circuit receives an input voltage Vin, and outputs a voltage Vout at the output end, and includes a first power tube Q01, a freewheeling diode D01, a first inductor L01 and a control circuit 10. The control circuit 10 outputs a control signal CTL for controlling the on and off of the first power tube Q01, wherein the control circuit 10 includes a conduction time generating circuit 100, and the conduction time generating circuit 100 outputs a turn-off control signal Ton_rst for controlling the turn-off of the first power tube Q01, so as to control the conduction time of the first power tube Q01. An existing conduction time generating circuit 100 is as follows Figure 2 As shown, it includes a voltage-controlled current source U03, a first capacitor C01, a first comparison circuit U04 and a second switch K02. The current i generated by the voltage-controlled current source U03 is proportional to the input voltage Vin; the current i charges the first capacitor C01; the first input end of the first comparison circuit U04 receives the voltage of the first capacitor C01, the second input end receives the output voltage Vout, and the output end outputs a shutdown control signal Ton_rst; the second switch K02 is turned on when the first power tube Q01 is turned off to reset the voltage of the first capacitor C01. Figure 2 When the on-time generating circuit 100 is shown, the switching frequency of the switching circuit can be realized as a certain value, and when the input voltage Vin changes rapidly and instantly and greatly, the on-time can achieve a fast response through the current i generated by the voltage-controlled current source U03, which can meet the fast response requirements of the switching circuit to the input voltage Vin.

[0003] However, if Figure 2 The on-time generating circuit 100 shown needs to receive an input voltage Vin and an output voltage Vout. Accordingly, the integrated circuit chip including the on-time generating circuit 100 needs to have a pin connected to the input voltage Vin and a pin connected to the output voltage Vout. This integrated circuit chip includes but is not limited to a control chip including the control circuit 10. That is to say, the on-time generating circuit 100 cannot be used in an integrated circuit chip that does not have a pin connected to the input voltage Vin and a pin connected to the output voltage Vout. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a conduction time generating circuit, an integrated circuit chip and a switching circuit. The technical problem to be solved is to provide a conduction time generating circuit that does not need to directly receive input voltage and output voltage, while ensuring that the conduction time responds quickly to the input voltage.

[0005] The technical solution of the present invention is that, in a first aspect, a conduction time generating circuit is provided, which is applied to a switch circuit, and outputs a shutdown control signal for controlling the shutdown of a first power tube in the switch circuit to control the conduction time of the first power tube, wherein a first end of the first power tube receives an input voltage, and a second end is connected to a switch node,

[0006] The on-time generating circuit is connected to the switch node to receive the switch node voltage, and generates a ramp signal whose slope is proportional to the switch node voltage during the conduction period of the first power tube according to the switch node voltage, and generates a first reference signal that can characterize the average value of the switch node voltage, and outputs the shutdown control signal according to the comparison result of the ramp signal and the first reference signal.

[0007] Optionally, the on-time generating circuit includes:

[0008] a charging current generating circuit, receiving the switch node voltage and generating a charging current, wherein the magnitude of the charging current is proportional to the switch node voltage during the conduction period of the first power tube;

[0009] A first capacitor, a first end of which receives the charging current during the conduction period of the first power tube, a second end of which is connected to a reference ground, and generates the ramp signal according to the voltage of the first capacitor;

[0010] A first reference signal generating circuit, for outputting the first reference signal according to the switch node voltage;

[0011] The first comparison circuit has a first input terminal receiving the ramp signal and a second input terminal receiving the first reference signal, compares the ramp signal with the first reference signal and outputs the shutdown control signal according to the comparison result.

[0012] Optionally, the charging current generating circuit includes:

[0013] A sampling circuit, wherein the input end receives the switch node voltage, and the output end outputs a sampling voltage, wherein the sampling voltage is proportional to the switch node voltage during the conduction period of the first power tube;

[0014] The voltage-to-current conversion circuit receives the sampled voltage and generates a charging current proportional to the sampled voltage during the conduction period of the first power tube.

[0015] Optionally, the sampling circuit includes a first resistor, a second resistor and a first switch.

[0016] The first resistor and the first switch are connected in series between the switch node and the output end of the sampling circuit, wherein the first switch is turned on during the conduction period of the first power tube;

[0017] The second resistor is connected between the output terminal of the sampling circuit and a reference ground.

[0018] Optionally, the sampling circuit includes a first resistor, a second resistor and a first switch.

[0019] The first resistor and the second resistor are connected in series between the switch node and a reference ground;

[0020] The first switch is connected between a common node of the first resistor and the second resistor and an output end of the sampling circuit, wherein the first switch is turned on during a period in which the first power tube is turned on.

[0021] Optionally, the first reference signal generating circuit includes:

[0022] an averaging circuit, performing an averaging operation according to the switch node voltage to output an average voltage capable of representing an average value of the switch node voltage;

[0023] The first reference signal generating circuit outputs the first reference signal according to the average voltage.

[0024] Optionally, the averaging circuit comprises a filtering circuit.

[0025] Optionally, the on-time generating circuit further includes:

[0026] The second switch is coupled to both ends of the first capacitor, and the second switch is turned on before the first power tube is turned on, and is turned off during the conduction period of the first power tube.

[0027] Optionally, the on-time generating circuit adjusts the on-time according to a difference between a frequency of the shutdown control signal and a frequency of the first clock signal.

[0028] Optionally, the on-time generating circuit further includes:

[0029] The regulating circuit outputs a regulating signal according to the difference between the frequency of the shutdown control signal and the frequency of the first clock signal, and the on-time generating circuit adjusts the on-time according to the regulating signal.

[0030] Optionally, the regulating circuit includes:

[0031] A first trigger, a data input terminal receiving the first clock signal, and a clock input terminal receiving the shutdown control signal;

[0032] A shift register, wherein a data input terminal is connected to an output terminal of the first trigger, a clock input terminal receives the shutdown control signal, and an output terminal outputs the adjustment signal.

[0033] Optionally, the first reference signal generating circuit adjusts a ratio of the first reference signal to an average value of the switch node voltage according to the adjustment signal to adjust the on-time.

[0034] Optionally, the first reference signal generating circuit includes:

[0035] an averaging circuit, performing an averaging operation according to the switch node voltage to output an average voltage capable of representing an average value of the switch node voltage;

[0036] A ratio-adjustable circuit, which adjusts the ratio of a signal output from its output end to a signal input from its input end according to the adjustment signal;

[0037] The input end of the averaging circuit receives a signal representing the switch node voltage, the input end of the adjustable ratio circuit receives the average voltage, and the first reference signal generating circuit outputs the first reference signal according to the signal output by the adjustable ratio circuit;

[0038] Alternatively, the input end of the adjustable ratio circuit receives a signal representing the switch node voltage, the output end is connected to the input end of the averaging circuit, and the first reference signal generating circuit outputs the first reference signal according to the average voltage.

[0039] Optionally, the ratio adjustable circuit includes a first operational amplifier, a first resistor array, a second resistor array and a first transistor.

[0040] The first input terminal of the first operational amplifier is connected to the input terminal of the proportional adjustable circuit, and the output terminal is connected to the control terminal of the first transistor;

[0041] The first resistor array and the second resistor array are connected in series to form a first series branch, and the first series branch is connected in series with the first transistor;

[0042] The first series branch is connected to the second input terminal of the first operational amplifier and the output terminal of the proportional adjustable circuit;

[0043] The first resistor array and / or the second resistor array is controlled according to the adjustment signal.

[0044] Optionally, a connection scheme between the first series branch, the second input terminal of the first operational amplifier, and the output terminal of the proportional adjustable circuit is controlled according to the adjustment signal.

[0045] Optionally, the first capacitor includes a first capacitor array,

[0046] The first capacitor array is controlled according to the adjustment signal to adjust the capacitance of the first capacitor, thereby adjusting the on-time.

[0047] In a second aspect, the present invention further provides an integrated circuit chip, wherein the integrated circuit chip comprises the conduction time generating circuit.

[0048] In a third aspect, the present invention further provides a switching circuit, wherein the switching circuit comprises the integrated circuit chip.

[0049] The circuit structure of the present invention has the following advantages compared with the prior art: the on-time generating circuit of the present invention is connected to the switch node, and generates a ramp signal whose slope is proportional to the switch node voltage during the conduction period of the first power tube according to the switch node voltage, and generates a first reference signal capable of characterizing the average value of the switch node voltage, and outputs a shutdown control signal according to the comparison result of the ramp signal and the first reference signal to control the on-time of the first power tube. The on-time generating circuit of the present invention does not need to directly receive the input voltage and the output voltage, and can ensure the fast response of the on-time to the input voltage, and can be applied to an integrated circuit chip without pins connected to the input voltage and pins connected to the output voltage, and can avoid the waste of resources caused by adding pins connected to the input voltage and the output voltage under the premise of ensuring the fast response of the on-time to the input voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of the circuit structure of a switch circuit in the prior art;

[0051] Figure 2 A schematic diagram of the circuit structure of a conduction time generating circuit in the prior art;

[0052] Figure 3 is a schematic diagram of the circuit structure of a switch circuit according to an embodiment of the present invention;

[0053] Figure 4 It is a circuit structure schematic diagram of a first embodiment of a conduction time generating circuit of the present invention;

[0054] Figure 5 is a circuit structure schematic diagram of a second embodiment of a conduction time generating circuit of the present invention;

[0055] Figure 6 A schematic diagram of the circuit structure of an embodiment of the regulating circuit of the present invention;

[0056] Figure 7 Based on Figure 5 A schematic diagram of a circuit structure of an embodiment of a proportional adjustable circuit;

[0057] Figure 8 FIG. 4 is a schematic diagram of the circuit structure of a third embodiment of the conduction time generating circuit of the present invention. DETAILED DESCRIPTION

[0058] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any substitution, modification, equivalent method and scheme made within the spirit and scope of the present invention.

[0059] In order to make the public have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, but those skilled in the art can fully understand the present invention without these detailed descriptions.

[0060] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the accompanying drawings are all simplified and not in exact proportion, and are only used for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0061] Figure 3Taking the Buck topology switch circuit as an example, a circuit structure schematic diagram of the switch circuit of the embodiment of the present invention is shown. Taking the Buck switch circuit as an example, the switch circuit includes a first power tube Q01, a freewheeling diode D01, a first inductor L01 and a control circuit 20, wherein the freewheeling diode D01 can also be replaced by a synchronous rectifier tube; the first end of the first power tube Q01 receives the input voltage Vin, and the second end is connected to the switch node SW; one end of the first inductor L01 is connected to the switch node SW, and the other end is connected to the output end of the switch circuit; the control circuit 20 provides a control signal CTL for controlling the conduction and shutdown of the first power tube Q01; the switch circuit converts the input voltage Vin into an output voltage Vout by the conduction and shutdown of the first power tube Q01 (and the synchronous rectifier tube). Among them, the control circuit 20 includes a conduction time generation circuit 200, and the conduction time generation circuit 200 outputs a shutdown control signal Ton_rst for controlling the shutdown of the first power tube Q01 in the switch circuit to control the conduction time of the first power tube Q01. The on-time generating circuit 200 is connected to the switch node SW to receive the switch node voltage Vsw, and generates the shutdown control signal Ton_rst according to the switch node voltage Vsw. In this way, the integrated circuit chip including the on-time generating circuit 200 does not need to set a pin connected to the input voltage Vin and a pin connected to the output voltage Vout due to the on-time generating circuit, which can save resources.

[0062] Specifically, in conjunction with reference Figure 3 , Figure 4 , Figure 5 and Figure 8The on-time generating circuit 200 of the embodiment of the present invention generates a ramp signal V1 whose slope is proportional to the switch node voltage Vsw during the conduction period of the first power tube Q01 according to the switch node voltage Vsw, and generates a first reference signal Vref1 that can characterize the average value of the switch node voltage Vsw, and outputs a shutdown control signal Ton_set according to the comparison result of the ramp signal V1 and the first reference signal Vref1. Since the switch node voltage Vsw is pulled up to approximately equal to the input voltage Vin during the conduction period of the first power tube Q01, it can be approximately considered that the slope of the ramp signal V1 is proportional to the input voltage Vin during the conduction period of the first power tube Q01; according to the inductor volt-second balance principle, the average value of the switch node voltage Vsw can represent the output voltage Vout, and it can be approximately considered that the average value of the switch node voltage Vsw is equal to the output voltage Vout, so the first reference signal Vref1 can represent the output voltage Vout; and then the conduction time of the first power tube Q01 is controlled according to the comparison result of the ramp signal and the first reference signal, so that the switching circuit can be controlled to have a relatively fixed switching frequency, and when the input voltage Vin changes rapidly and instantly and greatly, the conduction time can achieve a fast response through the slope of the ramp signal, which can meet the fast response requirements of the switching circuit to the input voltage Vin.

[0063] Please refer again Figure 3, for example, the control circuit 20 further includes a digital logic circuit, which receives the shutdown control signal Ton_rst generated by the conduction time generating circuit 20, and outputs a control signal CTL, wherein the control signal CTL controls the first power tube Q01 to be turned off according to the shutdown control signal Ton_rst. For example, the digital logic circuit includes an RS trigger U01, and a reset terminal R of the RS trigger U01 receives the shutdown control signal Ton_rst. Further, the set end S of the RS trigger U01 receives the conduction control signal Ton_set, and the control signal CTL controls the first power tube Q01 to conduct according to the conduction control signal Ton_set. In one embodiment, the control circuit 20 also includes a second comparison circuit U02, the first input end of the second comparison circuit U02 receives the second reference signal Vref2, the second input end receives the feedback voltage FB, and the output end outputs the conduction control signal Ton_set. For example, the feedback voltage FB can be obtained by dividing the output voltage Vout using the resistors R21 and R22 outside the control circuit 20. It is easy to understand that the feedback voltage FB is equal to the second reference signal Vref2. By changing the resistance value of the resistor R21 and / or the resistor R22, the magnitude of the output voltage Vout can be changed. The conduction time generating circuit 200 cannot determine the magnitude of the output voltage Vout according to the feedback voltage FB. The present application does not limit the circuit for generating the conduction control signal Ton_set, and is not limited to using the second comparison circuit U02. Any type of circuit in the prior art can be used.

[0064] Figure 4The circuit structure diagram of the first embodiment of the conduction time generating circuit 200 of the present invention is shown. The conduction time generating circuit 200 includes a charging current generating circuit 201, a first capacitor C01, a first reference signal generating circuit 202 and a first comparison circuit U04. The charging current generating circuit 201 receives the switch node voltage Vsw and generates a charging current i1. The magnitude of the charging current i1 is proportional to the switch node voltage during the conduction period of the first power tube Q01. The first end of the first capacitor C01 receives the charging current i1 during the conduction period of the first power tube Q01, and the second end is connected to the reference ground. The ramp signal V1 is generated according to the voltage of the first capacitor C01. In this embodiment, the first capacitor C01 The voltage at the first end of 1 is the ramp signal V1. Since the charging current i1 charges the first capacitor during the conduction period of the first power tube Q01, and the magnitude of the charging current i1 is proportional to the switch node voltage Vsw, the slope of the ramp signal V1 during the conduction period of the first power tube Q01 is proportional to the switch node voltage Vsw; the first reference signal generating circuit 202 outputs the first reference signal Vref1 according to the switch node voltage Vsw; the first input end of the first comparison circuit U04 receives the ramp signal V1, the second input end receives the first reference signal Vref1, compares the ramp signal and the first reference signal, and outputs the shutdown control signal Ton_rst according to the comparison result.

[0065] Please continue to refer to Figure 4 , for example, the charging current generating circuit 201 includes a sampling circuit 2011 and a voltage-current conversion circuit 2012. The input end of the sampling circuit 2011 is connected to the switch node SW to receive the switch node voltage Vsw, and the output end outputs the sampling voltage Vins. The sampling voltage Vins is proportional to the switch node voltage Vsw during the conduction period of the first power tube Q01; the voltage-current conversion circuit 2012 receives the sampling voltage Vins and generates a charging current i1 proportional to the sampling voltage Vins during the conduction period of the first power tube Q01. Since the sampling voltage Vins is proportional to the switch node voltage Vsw and the charging current i1 is proportional to the sampling voltage Vins during the conduction period of the first power tube Q01, the charging current i1 is proportional to the switch node voltage Vsw during the conduction period of the first power tube Q01. In some embodiments, the sampling circuit 2011 can be set to sample the switch node voltage Vsw during the conduction period of the first power tube Q01. Specifically, in one embodiment, Figure 4As shown, the sampling circuit 2011 includes a first resistor R01, a second resistor R02 and a first switch K01, wherein the first resistor R01 and the first switch K01 are connected in series between the switch node SW and the output end of the sampling circuit 2011, wherein the first switch K01 is turned on during the conduction period of the first power tube Q01; the second resistor R02 is connected between the output end of the sampling circuit 2011 and the reference ground. For example, the control end of the first switch K01 can receive a signal such as Figure 3In another embodiment, the position of the first switch K01 can also be changed (not shown in the figure), so that the first resistor R01 and the second resistor R02 are connected in series between the switch node SW and the reference ground, and the first switch K01 is connected between the common node of the first resistor R01 and the second resistor R02 and the output end of the sampling circuit 2011. In one embodiment, the voltage-current conversion circuit 2012 includes a second operational amplifier U05, a second transistor M01, a third resistor R03 and a first current mirror, the second transistor M01 and the third resistor R03 are connected in series, the first input end of the second operational amplifier U05 receives the sampling voltage Vins, the second input end is connected to the common end of the second transistor M01 and the third resistor R03, the output end is connected to the control end of the second transistor M01, and the first current mirror performs proportional or proportional mirroring on the current i0 flowing through the second transistor M01 to obtain the charging current i1. By way of example, the first current mirror includes a third transistor M02 and a fourth transistor M03, for example, which are PMOS tubes. In one embodiment, the first reference signal generating circuit 202 includes an averaging circuit 2021, which performs an averaging operation according to the switch node voltage Vsw to output an average voltage Vos that can represent the average value of the switch node voltage; the first reference signal generating circuit 202 outputs the first reference signal Vref1 according to the average voltage Vos. In this embodiment, the first reference signal generating circuit 202 uses the average voltage Vos as the first reference signal Vref1. Of course, in other embodiments, the average voltage Vos can also be processed and then output as the first reference signal Vref1. For example, the first reference signal generating circuit 202 can also include a proportional circuit (not shown in the figure), which receives the average voltage Vos and outputs the first reference signal Vref1 proportional to the average voltage Vos. In one embodiment, the averaging circuit 2021 can receive the switch node voltage Vsw, perform an averaging operation on the switch node voltage Vsw to output the average voltage Vos; in another embodiment, the averaging circuit 2021 can also receive the sampled voltage Vins, perform an averaging operation on the sampled voltage Vins to output the average voltage Vos. In one embodiment, the averaging circuit 2021 includes a low-pass filtering circuit. For example, the low-pass filtering circuit includes a fourth resistor R04 and a second capacitor C02. The first end of the fourth resistor R04 receives the switching node voltage Vsw or the sampling voltage Vins, the second end is connected to the first end of the second capacitor C02, the second end of the second capacitor C02 is connected to the reference ground, and the common end of the fourth resistor R04 and the second capacitor C02 outputs the first reference signal Vref1.Further, the on-time generating circuit 200 further includes a second switch K02, the second switch K02 is coupled to both ends of the first capacitor C01, the second switch K02 is turned on for a period of time before the first power tube is turned on to reset the ramp signal V1, and is turned off during the on-time of the first power tube. For example, in one embodiment, the control end of the second switch K02 can receive the off control signal Ton_rst, and in another embodiment, the control end of the second switch K02 can also receive the off control signal Ton_rst. Figure 3 The control signal shown in FIG. 1 is a non-signal CTL.

[0066] However, in practical applications, using Figure 4 The conduction time generating circuit 200 shown can only realize the approximate fixed frequency control of the switch circuit. The reasons are as follows: 1) during the first power tube Q01 period, due to the conduction voltage drop of the first power tube Q01, there will be an error between the switch node voltage Vsw and the input voltage Vin; 2) there may be an error between the duration of the sampling circuit 2011 sampling the switch node voltage Vsw and the actual conduction duration of the first power tube Q01; 3) considering the actual cost and feasibility, the averaging circuit 2021 can adopt a low-pass filter circuit, and there will be an error between the average voltage Vos output by the low-pass filter circuit and the actual average value of the switch node voltage Vsw, that is, the first reference signal Vref1 has an error when representing the output voltage Vout; the above reasons will lead to the use of the following methods: Figure 4 When the control circuit of the on-time generating circuit 200 of the first embodiment shown controls the switch circuit, there is an error in the switching frequency of the switch circuit. In order to eliminate the switching frequency error of the switch circuit and realize the fixed frequency of the switch circuit, in some other embodiments, the on-time generating circuit 200 can be set to adjust the on-time according to the difference between the frequency of the off-control signal Ton_rst and the frequency of the first clock signal, and the frequency error is eliminated by dynamic adjustment to realize the fixed frequency control of the switch circuit, wherein the first clock signal can be a clock signal with a fixed frequency. In these embodiments, the on-time generating circuit also includes an adjustment circuit, which outputs an adjustment signal according to the difference between the frequency of the off-control signal Ton_rst and the frequency of the first clock signal, and the on-time generating circuit adjusts the on-time according to the adjustment signal.

[0067] refer to Figures 5 to 7, the circuit structure of the second embodiment of the on-time generating circuit 200 is basically the same as that of the first embodiment, and will not be repeated here. The main difference is that in this embodiment, the on-time generating circuit 200 also includes an adjustment circuit 203, and the adjustment circuit 203 outputs an adjustment signal according to the difference between the frequency of the shutdown control signal Ton_rst and the frequency of the first clock signal clk1. The on-time generating circuit 200 adjusts the ratio of the first reference signal Vref1 to the average value of the switch node voltage according to the adjustment signal to achieve the adjustment of the on-time. Specifically, compared with the first embodiment, the first reference signal generating circuit 202 in this embodiment includes not only the averaging circuit 2021, but also a proportional adjustable circuit 2022. The proportional adjustable circuit 2022 adjusts the ratio of the signal output from its output end to the signal input from its input end according to the adjustment signal. In one embodiment, as Figure 5 As shown, the input end of the averaging circuit 2021 receives a signal representing the switch node voltage (including but not limited to the switch node voltage Vsw or the sampling voltage Vins), performs an averaging operation to output an average voltage Vos that can represent the average value of the switch node voltage, the input end of the adjustable ratio circuit 2022 receives the average voltage Vos, and the first reference signal generating circuit 202 outputs a first reference signal Vref1 according to the signal output by the adjustable ratio circuit 202. By way of example, the signal output by the adjustable ratio circuit 202 can be used as the first reference signal Vref1. Of course, in another embodiment, the positions of the adjustable ratio circuit 2022 and the averaging circuit 2021 can also be exchanged (not shown in the figure), and the input end of the adjustable ratio circuit 2021 is configured to receive the signal representing the switch node voltage, and the output end is connected to the input end of the averaging circuit 2021. The averaging circuit 2021 performs an averaging operation to output an average voltage Vos that can represent the average value of the switch node voltage, and the first reference signal generating circuit 202 outputs a first reference signal Vref according to the average voltage Vos. By way of example, the reference Figure 6 The regulation circuit 203 includes a first trigger U06 and a shift register U07. The data input end of the first trigger U06 receives the first clock signal clk1, and the clock input end receives the shutdown control signal; the data input end of the shift register U07 is connected to the output end of the first trigger U06, the clock input end receives the shutdown control signal Ton_rst, and the output end outputs the regulation signal Q <n:0>. refer to Figure 7 , taking the example that the input end of the proportional adjustable circuit 2022 receives the average voltage Vos output by the averaging circuit, and the signal output by the output end is used as the first reference signal Vref1, in some embodiments, the proportional adjustable circuit 2022 includes a first operational amplifier U08, a first resistor array R05, a second resistor array R06 and a first transistor M04, the first input end of the first operational amplifier U08 is connected to the input end of the proportional adjustable circuit 2022 to receive the average voltage Vos, and the output end is connected to the control end of the first transistor M04; the first resistor array R05 and the resistor array R06 are connected in series to form a first series branch 20221, and the first series branch 20221 is connected in series with the first transistor U08; the first series branch The circuit 20221 is connected to the second input terminal of the first operational amplifier U08 and the output terminal of the ratio-adjustable circuit 2022, and the output terminal of the ratio-adjustable circuit 2022 outputs the first reference signal Vref1; the first resistor array R05 and / or the second resistor array R06 are controlled according to the adjustment signal output by the adjustment circuit 203 to adjust the resistance value of the first resistor array R05 and / or the resistance value of the second resistor array R06, thereby adjusting the ratio of the signal output from the output terminal of the ratio-adjustable circuit 2022 and the signal input to its input terminal, which is to adjust the ratio of the first reference signal Vref1 to the average voltage Vos in this embodiment, and then adjust the ratio of the first reference signal Vref1 to the average value of the switch node voltage. For example, the first series branch 20221 is coupled between the first transistor U08 and the reference ground. Specifically, in one embodiment, the second input terminal of the first operational amplifier U08 can be connected to the common terminal of the first resistor array R05 and the second resistor array R06, and the output terminal of the proportional adjustable circuit 2022 can be connected to the common terminal of the first resistor array R05 and the first transistor M04 (e.g. Figure 7 In another embodiment, the second input terminal of the first operational amplifier U08 may be connected to the common terminal of the first resistor array R05 and the first transistor M04, and the output terminal of the proportional adjustable circuit 2022 may be connected to the common terminal of the first resistor array R05 and the second resistor array R06 (as shown in the solid line in FIG. 1 ). Figure 7 In some other embodiments, the ratio adjustable circuit 2022 further controls the connection scheme between the first series branch 20221 and the second input terminal of the first operational amplifier U08, and the output terminal of the ratio adjustable circuit 2022 according to the adjustment signal output by the adjustment circuit 203. For example, in one embodiment, the connection scheme between the first series branch 20221 and the second input terminal of the first operational amplifier U08, and between the first series branch 20221 and the output terminal of the ratio adjustable circuit 2022 can be controlled according to the adjustment signal. Figure 7 Connect as shown by the solid line in Figure 7 The ratio of the signal output from the output end of the ratio adjustable circuit 2022 to the signal input to its input end is adjusted.

[0068] Figure 8 The circuit structure diagram of the third embodiment of the conduction time generating circuit 200 is shown. The circuit structure of this embodiment is basically the same as that of the first embodiment, and will not be described in detail here. The difference is that in this embodiment, the conduction time generating circuit 200 further includes an adjustment circuit 203, and the first capacitor C01 includes a first capacitor array. This embodiment controls the first capacitor array according to the adjustment signal output by the adjustment circuit 203 to adjust the capacitance of the first capacitor C01, thereby adjusting the slope of the ramp signal V1, and further adjusting the conduction time. Among them, the adjustment circuit 203 has been described in the second embodiment, and will not be described in detail here.

[0069] In summary, the on-time generating circuit 200 of the embodiment of the present invention is connected to the switch node SW, and outputs the off-control signal Ton_rst for controlling the first power tube Q01 in the switch circuit to turn off according to the switch node voltage Vsw, so as to control the on-time of the first power tube. It is not necessary to directly receive the input voltage Vin and the output voltage Vout, so as to realize the approximate fixed-frequency control of the switch circuit, and can ensure the fast response of the on-time to the input voltage Vin. Since it is not necessary to directly receive the input voltage Vin and the output voltage Vout, it can be applied to an integrated circuit chip in which there are no pins connected to the input voltage and the pins connected to the output voltage, and can avoid the waste of resources caused by adding the pins connected to the input voltage Vin and the pins connected to the output voltage Vout. When the on-time generating circuit 200 adjusts the on-time according to the difference between the frequency of the off-control signal Ton_rst and the frequency of the first clock signal, the switching frequency error of the switch circuit can be eliminated, so as to realize the fixed-frequency control of the switch circuit.

[0070] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A conduction time generating circuit, applied to a switch circuit, outputting a shutdown control signal for controlling the shutdown of a first power tube in the switch circuit to control the conduction time of the first power tube, wherein a first end of the first power tube receives an input voltage, and a second end is connected to a switch node, characterized in that: The on-time generating circuit is connected to the switch node to receive the switch node voltage, and generates a ramp signal whose slope is proportional to the switch node voltage during the conduction period of the first power tube according to the switch node voltage, and generates a first reference signal that can characterize the average value of the switch node voltage, and outputs the shutdown control signal according to the comparison result of the ramp signal and the first reference signal.

2. The on-time generating circuit according to claim 1, characterized in that: The on-time generating circuit comprises: a charging current generating circuit, receiving the switch node voltage and generating a charging current, wherein the magnitude of the charging current is proportional to the switch node voltage during the conduction period of the first power tube; A first capacitor, a first end of which receives the charging current during the conduction period of the first power tube, a second end of which is connected to a reference ground, and generates the ramp signal according to the voltage of the first capacitor; A first reference signal generating circuit, for outputting the first reference signal according to the switch node voltage; The first comparison circuit has a first input terminal receiving the ramp signal and a second input terminal receiving the first reference signal, compares the ramp signal with the first reference signal and outputs the shutdown control signal according to the comparison result.

3. The on-time generating circuit according to claim 2, characterized in that: The charging current generating circuit comprises: A sampling circuit, wherein the input end receives the switch node voltage, and the output end outputs a sampling voltage, wherein the sampling voltage is proportional to the switch node voltage during the conduction period of the first power tube; The voltage-to-current conversion circuit receives the sampled voltage and generates a charging current proportional to the sampled voltage during the conduction period of the first power tube.

4. The on-time generating circuit according to claim 3, characterized in that: The sampling circuit includes a first resistor, a second resistor and a first switch. The first resistor and the first switch are connected in series between the switch node and the output end of the sampling circuit, wherein the first switch is turned on during the conduction period of the first power tube; The second resistor is connected between the output terminal of the sampling circuit and a reference ground.

5. The on-time generating circuit according to claim 3, characterized in that: The sampling circuit includes a first resistor, a second resistor and a first switch. The first resistor and the second resistor are connected in series between the switch node and a reference ground; The first switch is connected between a common node of the first resistor and the second resistor and an output end of the sampling circuit, wherein the first switch is turned on during a period in which the first power tube is turned on.

6. The on-time generating circuit according to claim 2, characterized in that: The first reference signal generating circuit comprises: an averaging circuit, performing an averaging operation according to the switch node voltage to output an average voltage capable of representing an average value of the switch node voltage; The first reference signal generating circuit outputs the first reference signal according to the average voltage.

7. The on-time generating circuit according to claim 6, characterized in that: The averaging circuit includes a filtering circuit.

8. The on-time generating circuit according to claim 2, characterized in that: The on-time generating circuit further comprises: The second switch is coupled to both ends of the first capacitor, and the second switch is turned on before the first power tube is turned on, and is turned off during the conduction period of the first power tube.

9. The on-time generating circuit according to claim 1, characterized in that: The on-time generating circuit adjusts the on-time according to the difference between the frequency of the shutdown control signal and the frequency of the first clock signal.

10. The on-time generating circuit according to claim 2, characterized in that: The on-time generating circuit further comprises: The regulating circuit outputs a regulating signal according to the difference between the frequency of the shutdown control signal and the frequency of the first clock signal, and the on-time generating circuit adjusts the on-time according to the regulating signal.

11. The on-time generating circuit according to claim 10, characterized in that: The regulating circuit comprises: A first trigger, a data input terminal receiving the first clock signal, and a clock input terminal receiving the shutdown control signal; A shift register, wherein a data input terminal is connected to an output terminal of the first trigger, a clock input terminal receives the shutdown control signal, and an output terminal outputs the adjustment signal.

12. The constant on-time generating circuit according to claim 10, characterized in that: The first reference signal generating circuit adjusts the ratio of the first reference signal to the average value of the switch node voltage according to the adjustment signal to adjust the on-time.

13. The on-time generating circuit according to claim 12, characterized in that: The first reference signal generating circuit comprises: an averaging circuit, performing an averaging operation according to the switch node voltage to output an average voltage capable of representing an average value of the switch node voltage; A ratio-adjustable circuit, which adjusts the ratio of a signal output from its output end to a signal input from its input end according to the adjustment signal; The input end of the averaging circuit receives a signal representing the switch node voltage, the input end of the adjustable ratio circuit receives the average voltage, and the first reference signal generating circuit outputs the first reference signal according to the signal output by the adjustable ratio circuit; Alternatively, the input end of the adjustable ratio circuit receives a signal representing the switch node voltage, the output end is connected to the input end of the averaging circuit, and the first reference signal generating circuit outputs the first reference signal according to the average voltage.

14. The on-time generating circuit according to claim 13, characterized in that: The ratio adjustable circuit includes a first operational amplifier, a first resistor array, a second resistor array and a first transistor. The first input terminal of the first operational amplifier is connected to the input terminal of the proportional adjustable circuit, and the output terminal is connected to the control terminal of the first transistor; The first resistor array and the second resistor array are connected in series to form a first series branch, and the first series branch is connected in series with the first transistor; The first series branch is connected to the second input terminal of the first operational amplifier and the output terminal of the proportional adjustable circuit; The first resistor array and / or the second resistor array is controlled according to the adjustment signal.

15. The on-time generating circuit according to claim 14, characterized in that: The connection scheme between the first series branch, the second input terminal of the first operational amplifier, and the output terminal of the proportional adjustable circuit is controlled according to the adjustment signal.

16. The on-time generating circuit according to claim 10, characterized in that: The first capacitor includes a first capacitor array, The first capacitor array is controlled according to the adjustment signal to adjust the capacitance of the first capacitor, thereby adjusting the on-time.

17. An integrated circuit chip, characterized in that: It comprises the conduction time generating circuit as claimed in any one of claims 1 to 16.

18. A switch circuit, characterized in that: Comprising the integrated circuit chip as claimed in claim 17.

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