Parallel interface controller of satellite terminal, control method and satellite terminal

Abstract

The invention provides a parallel interface controller of a satellite terminal, a control method and the satellite terminal, and the controller comprises a clock module which comprises a standard timer and a slow timer; the bus interface is used for carrying out configuration and data transmission on the time sequence processing module through a baseband chip; the radio frequency interface module is connected between the time sequence processing module and the radio frequency chip; the storage module is used for storing uplink and downlink control instructions and related data configured by the baseband chip to the time sequence processing module; and the time sequence processing module is used for determining the time sequence of the uplink and downlink control instructions according to the time sequence configuration of the baseband chip, reading the corresponding uplink and downlink control instructions from the storage module according to the time sequence, determining an absolute time point and instruction starting time according to the currently started standard timer or slow timer, and starting the uplink and downlink control instructions when the corresponding instruction starting time is reached. And executing the uplink and downlink control instruction to realize transmission of related transmission data with the next-level interface module. The radio frequency controller of the baseband chip of the ground terminal can be adapted to different sampling rates.

Description

Technical Field

[0001] The present application relates to the field of satellite communication technology, and in particular to a parallel interface controller of a satellite terminal, a control method and a satellite terminal. Background Art

[0002] The RF controller of the traditional ground communication terminal baseband chip is mainly composed of a timer, a general timing processor, a data path, and a RF interface controller. The timer structure is mainly composed of a multi-bit counter, which counts the time point in the frame, frame number, super frame number, etc. by dividing the bit position. It is mainly used to provide an absolute time point synchronized with the base station and to start the general timing processor at a fixed time. The general timing processor is mainly composed of multiple general timing processing events, each of which can be started by a timer or a periodic interrupt, and is used to execute various event operations set at the time point set by the software. The data path is mainly composed of the standard JESD207 to complete the data interaction between the RF chip and the baseband chip. The RF control interface is mainly composed of a serial communication interface, a GPO (General Purpose Output) interface, and an RFFE (Radio Frequency Front-End) interface, so that users can configure the RX digital processor, the TX digital processor, the PLL (Phase Locked Loop), the ADC (Analog-to-digital converter), and the filter modules inside the RF chip through the serial communication interface of the baseband chip.

[0003] The low-orbit satellite communication system adopts a newly developed set of mobile communication protocol standard system. Different from the ground cellular mobile communication network (2G / 3G / 4G) standards, the mobile communication terminal chip RF controller is usually customized for different application protocols. The commercial GSM (Global System for Mobile Communications) / WCDMA (Wideband Code Division Multiple Access) / LTE (Long Term Evolution) baseband processing multi-mode RF controller can only carry out the principle verification of the low-orbit satellite protocol, but it cannot fully meet the personalized requirements of the low-orbit mobile communication terminal baseband chip RF controller for the symbol rate, transmission rate, and multi-level sampling rate of the low-orbit communication protocol. The performance of the RF controller largely determines the quality of voice communication, the stability and efficiency of data transmission. For the application of special frequency points, the ground terminal baseband chip RF controller can only use the inherent sampling rate for adaptation, which limits its use scenario. Summary of the invention

[0004] The present application provides a parallel interface controller, a control method and a satellite terminal of a satellite terminal, which are used to solve the problem that the existing ground terminal baseband chip radio frequency controller can only use an inherent sampling rate for adaptation, which limits its use scenario.

[0005] According to a first aspect of an embodiment of the present application, a parallel interface controller of a satellite terminal is provided, comprising:

[0006] A clock module, including a standard timer and a slow timer, starts the slow timer in the low power consumption mode according to the control of the baseband chip, and starts the standard timer when exiting the low power consumption mode, wherein the frequency of the slow timer is lower than the frequency of the standard timer;

[0007] A bus interface, connected between the timing processing module and the baseband chip, for configuring the timing processing module and transmitting data through the baseband chip, wherein the configuration includes timing configuration;

[0008] A radio frequency interface module is connected between the timing processing module and the radio frequency chip;

[0009] A storage module, used to store uplink and downlink control instructions and related data configured by the baseband chip to the timing processing module;

[0010] The timing processing module determines the timing of the uplink and downlink control instructions according to the timing configuration of the baseband chip, reads the corresponding uplink and downlink control instructions from the storage module according to the timing, determines the absolute time point and the instruction start time according to the currently started standard timer or slow timer, and executes the uplink and downlink control instructions when the corresponding instruction start time is reached to realize the transmission of related transmission data with the next-level interface module.

[0011] In one or more possible embodiments, the configuration further includes at least one of the following configurations:

[0012] Configure the JESD port for data communication between the baseband chip and the RF chip;

[0013] Configure the uplink and downlink paths between the timing processing module and the next-level interface module connected;

[0014] Configure the sending and receiving time windows for data transmission in the uplink and downlink channels corresponding to different application scenarios;

[0015] Configure the data transceiver links selected from the uplink and downlink paths corresponding to different application scenarios.

[0016] In one or more possible embodiments, the timing processing module includes an RXFIFO port unit connected to a next-level chip;

[0017] The RX FIFO port unit includes a receiving counter. Each time the RX FIFO port unit outputs a number, the count of the receiving counter is increased by one. By configuring the corresponding receiving start count value and receiving end count value, the corresponding data transmission receiving and sending time windows in different application scenarios are set;

[0018] Through the selector register, the data transceiver link selected from the uplink and downlink paths corresponding to different application scenarios is configured.

[0019] In one or more possible embodiments, the data communication port between the baseband chip and the radio frequency chip includes a port supporting a time division multiplexing TDD mode and a port supporting a frequency division multiplexing FDD mode, and the operating clock frequency of the baseband chip is N times higher than the port sampling clock frequency;

[0020] The configuration also includes TDD / FDD communication mode configured by registers.

[0021] In one or more possible embodiments, the timing processing module includes:

[0022] A timing processing control unit, used to determine the timing of the uplink and downlink control instructions according to the timing configuration of the baseband chip, determine the absolute time point and the instruction start time according to the currently started standard timer or slow timer, and notify the instruction prefetch unit of the timing and the instruction start time, and control the address generation unit to generate the storage address of the uplink and downlink control instructions in the storage module;

[0023] An instruction pre-fetch unit, configured to read the corresponding uplink and downlink control instructions from the storage module according to the timing and send them to the execution unit, and when determining that there is an interval time from the corresponding instruction start time, send the interval time parameter to the execution unit;

[0024] An address generating unit, used for generating storage addresses of uplink and downlink control instructions in the storage module under the control of the timing control unit;

[0025] An execution unit, configured to receive an uplink and downlink control instruction, and when determining that a corresponding interval time parameter exists, start an interval time counter to count, and when the count reaches the interval time parameter, execute the uplink and downlink control instruction, and when determining that no corresponding interval time parameter exists, execute the uplink and downlink control instruction;

[0026] An interval time counter, used to start counting according to the control of the execution unit, and to be cleared at the end of executing the uplink and downlink control instructions according to the control of the control unit;

[0027] A comparator is used to compare the count of the interval time counter with the interval time parameter, and to notify the execution unit when the count is equal to the interval time parameter.

[0028] In one or more possible embodiments, the standard timer / slow timer includes a 41-bit counter, wherein the lower 16 bits are used to count time points within a frame, the upper 15 bits are used to count frame numbers, and the highest 10 bits are used to count superframe numbers.

[0029] In one or more possible embodiments, the method further includes:

[0030] The calibration module is used to modify the count value of the switched slow timer / standard counter to compensate for the clock error according to the current count value and the periodic relationship between the standard counter and the slow timer when switching from the standard timer to the slow timer or from the slow timer to the standard timer.

[0031] In one or more possible embodiments, the calibration module is further configured to adjust the intra-frame counting phase of the current standard timer / slow timer according to the intra-frame counting phase in the phase register; or

[0032] The calibration module is also used to automatically adjust the intra-frame counting phase of the current standard timer / slow timer according to the timing value in the timing self-control register when the corresponding timing time is reached.

[0033] In one or more possible embodiments, the bus interface includes a bus slave device interface and a bus master device interface, wherein:

[0034] The bus slave device interface is used by the baseband chip to configure relevant registers in the timing processing module, and the bus master device interface is used by the baseband chip to transmit data with the timing processing module.

[0035] According to a second aspect of an embodiment of the present application, a satellite terminal is provided, including:

[0036] A baseband chip, integrated with the parallel interface controller of the satellite terminal provided by the first aspect above;

[0037] Radio frequency chip, used for transmitting radio frequency signals with satellites.

[0038] According to a third aspect of an embodiment of the present application, there is provided an interface control method of a parallel interface controller of a satellite terminal, comprising:

[0039] Configuring the timing processing module through the bus interface, wherein the configuration includes timing configuration;

[0040] Storing up and down control instructions and related data in the storage module;

[0041] Determine the timing of the uplink and downlink control instructions according to the timing configuration of the baseband chip, and read the corresponding uplink and downlink control instructions from the storage module according to the timing;

[0042] Determine the absolute time point and the instruction start time according to the currently started standard timer or slow timer, the frequency of the slow timer is lower than the frequency of the standard timer;

[0043] When the corresponding instruction start time is reached, the uplink and downlink control instructions are executed to realize the transmission of related transmission data with the next level interface module.

[0044] In one or more possible embodiments, the method further includes:

[0045] Configure the JESD port for data communication between the baseband chip and the RF chip;

[0046] Configure the uplink and downlink paths between the timing processing module and the next-level interface module connected;

[0047] Configure the sending and receiving time windows for data transmission in the uplink and downlink channels corresponding to different application scenarios;

[0048] Configure the data transceiver links selected from the uplink and downlink paths corresponding to different application scenarios.

[0049] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, which stores program instructions. When the computer-readable storage medium is run on a computer, the computer executes the above-mentioned various aspects of the embodiment of the present application and any possible method involved in each aspect.

[0050] According to a fifth aspect of an embodiment of the present application, a computer program product is provided. When the computer program product is run on an electronic device, the electronic device executes and implements the above-mentioned various aspects of the embodiment of the present application and any possible method involved in each aspect.

[0051] The parallel interface controller, control method and satellite terminal of the satellite terminal provided by the present application have the following beneficial effects:

[0052] The parallel interface controller, control method and satellite terminal of the satellite terminal provided in the present application, the timer includes a slow timer in low power consumption mode and a standard timer in non-low power consumption mode, so that the satellite terminal can adopt a low sampling rate for sampling in low power consumption mode and a high sampling rate for sampling in non-low power consumption mode, thereby meeting different sampling rate requirements and reducing the power consumption of the satellite terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0054] Figure 1 A schematic diagram of the architecture of a parallel interface controller of a satellite terminal, a control method, and a system for satellite terminal application provided in an embodiment of the present application;

[0055] Figure 2 A schematic diagram of the structure of a parallel interface controller of a satellite terminal provided in an embodiment of the present application;

[0056] Figure 3 A schematic diagram of the detailed structure of a parallel interface controller of a satellite terminal provided in an embodiment of the present application;

[0057] Figure 4 A detailed structural diagram of a timing processing module in a parallel interface controller of a satellite terminal provided in an embodiment of the present application;

[0058] Figure 5A schematic diagram of a data path configured in an embodiment of the present application;

[0059] Figure 6 This is a schematic diagram of a parallel interface control method for a satellite terminal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0061] Reference Figure 1 , is a schematic diagram of the architecture of a parallel interface controller, control method and system for satellite terminal application provided by the embodiment of the present application. Figure 1 As shown, the application environment includes multiple satellite base stations located on the orbital plane in the satellite communication system and terminals communicating with the satellite base stations, exemplarily including satellite base stations 102_1, 102_2, ..., 102_N in the figure, where N is a positive integer, and the size of N is determined according to specific needs and scenarios in practice. The satellite terminal 101 communicates with other destination satellite terminals 103 through the satellite base stations.

[0062] It should be noted that the above system architecture is only an example of the system architecture applicable to the embodiment of the present application. Figure 1 The system architecture shown may also include other entities or some entities may be reduced.

[0063] The low-orbit satellite communication system adopts a newly developed set of mobile communication protocol standard system. Different from the ground cellular mobile communication network (2G / 3G / 4G) standards, the mobile communication terminal chip RF controller is usually customized for different application protocols. The commercial GSM / WCDMA / LTE baseband processing multi-mode RF controller can only carry out the principle verification of the low-orbit satellite protocol, but it cannot fully meet the personalized requirements of the low-orbit mobile communication terminal baseband chip RF controller for the symbol rate, transmission rate, and multi-speed sampling rate of the low-orbit communication protocol. The performance of the RF controller largely determines the quality of voice communication, the stability and efficiency of data transmission. For special frequency applications, the ground terminal baseband chip RF controller can only use the inherent sampling rate for adaptation, which limits its use scenario.

[0064] Therefore, it is urgent and of great research value to study the low-power parallel interface controller based on the low-orbit communication baseband chip so that it has the characteristics of low power consumption, multi-speed sampling rate switching, and high performance, and adapts to the low-orbit communication waveform, in order to expand the application of satellite communications and meet the current application needs of low-orbit satellite communication system construction.

[0065] The technical problem to be solved by the present application is to provide a low-power parallel interface controller based on a low-orbit communication baseband chip, which has the characteristics of low power consumption, multi-speed sampling rate switching, and high performance, can adapt to the transmission of various speeds of low-orbit communication waveforms, and configure different low-power registers for low-power processing according to various application scenarios.

[0066] The present application embodiment provides a parallel interface controller for a satellite terminal. Figure 2 As shown, including:

[0067] The clock module 201 includes a standard timer and a slow timer. The slow timer is started in the low power consumption mode according to the control of the baseband chip, and the standard timer is started when the low power consumption mode is exited. The frequency of the slow timer is lower than that of the standard timer.

[0068] The timer in the embodiment of the present application supports two modes, and seamless switching can be achieved between the two modes. The low power consumption mode can be when the satellite terminal is in standby state. There is no data transmission in the standby state, and the slow timer can be used for timing. When there is data transmission when exiting the standby state, the standard timer can be used for timing.

[0069] The bus interface 202 is connected between the timing processing module and the baseband chip, and configures the timing processing module and transmits data through the baseband chip, wherein the configuration includes timing configuration;

[0070] The above bus interface includes a bus slave device interface and a bus master device interface, wherein:

[0071] The bus slave device interface is used by the baseband chip to configure relevant registers in the timing processing module, and the bus master device interface is used by the baseband chip to transmit data with the timing processing module.

[0072] The above bus interface serves as the bus interface of the baseband chip, so that the parallel interface controller of the satellite terminal can be connected to the baseband chip through the bus interface.

[0073] The radio frequency interface module 203 is connected between the timing processing module and the radio frequency chip;

[0074] The RF interface module can configure the data path, and configure the uplink path and downlink data path for data transmission between the baseband chip and the RF chip.

[0075] The storage module 204 is used to store the uplink and downlink control instructions and related data configured by the baseband chip to the timing processing module;

[0076] The storage module is respectively connected to the internal bus module and the timing processing module of the baseband chip. In the embodiment of the present application, the uplink and downlink control instructions and related data configured for the timing processing module are pre-stored in the storage module. The uplink and downlink control instructions can realize the uplink and downlink timing configuration of the timing processing module. In this way, on the entire timeline, for each timing processing module, the time processing order of different events can be clearly defined.

[0077] The timing processing module 205 determines the timing of the uplink and downlink control instructions according to the timing configuration of the baseband chip, reads the corresponding uplink and downlink control instructions from the storage module according to the timing, determines the absolute time point and the instruction start time according to the currently started standard timer or slow timer, and executes the uplink and downlink control instructions when the corresponding instruction start time is reached to realize the transmission of related transmission data with the next-level interface module, and the next-level interface module may include the above-mentioned radio frequency interface module.

[0078] The parallel interface controller, control method and satellite terminal of the satellite terminal provided in the present application, the timer includes a slow timer in low power consumption mode and a standard timer in non-low power consumption mode, so that the satellite terminal can adopt a low sampling rate for sampling in low power consumption mode and a high sampling rate for sampling in non-low power consumption mode, thereby meeting different sampling rate requirements and reducing the power consumption of the satellite terminal.

[0079] In one or more possible embodiments, the above configuration further includes at least one of the following configurations:

[0080] Configure the JESD port for data communication between the baseband chip and the RF chip. By configuring the JESD port for communication, the relevant data transmission between the baseband chip and the timing processing module can be realized;

[0081] Configure the uplink and downlink paths between the timing processing module and the next-level interface module connected thereto. The next-level interface module connected to the timing processing module may be a next-level chip inside the baseband chip or a radio frequency chip. The uplink and downlink paths may include multiple uplink paths and multiple downlink paths, which can be specifically configured as needed.

[0082] Configure the corresponding uplink and downlink channels for data transmission in different application scenarios. For each uplink channel or downlink channel, as mentioned above, the corresponding timing has been configured. When the uplink data or downlink data transmission is performed at the corresponding event execution time point, the data transmission and reception time window needs to be configured, so that the specific transmission time of the data can be limited;

[0083] Configure the data transceiver links selected from the uplink and downlink paths corresponding to different application scenarios. As mentioned above, when multiple paths such as different uplink paths or downlink paths are configured, it is also possible to configure which paths are selected for communication in which scenarios.

[0084] As a possible embodiment, the parallel interface controller of the satellite terminal also includes: a calibration module, which is used to modify the count value of the switched slow timer / standard counter to compensate for the clock error according to the current count value and the periodic relationship between the standard counter and the slow timer when switching from a standard timer to a slow timer, or from a slow timer to a standard timer.

[0085] like Figure 3 The figure shows a parallel interface controller of a satellite terminal in an embodiment of the present application, wherein the storage module is a data storage device 301, the timing processing module includes timing processors 0-6, wherein timing processors 0 and 1 are separate timing processors, and timing processors 2-6 are integrated timing processors, an arbitrator 302 is connected between the data storage device 301 and the timing processors 0-6, and the arbitrator 302 is used to determine the order of data transmission between the data storage device and the timing processing module, the bus interface includes a bus master device interface 303 and a bus slave device interface 304, and the timing processors 0-6 are connected to the arbitrator 302. The output end of is connected to an arbiter 305, which is used to decide the transmission order of the data output from the timing processing module. The next level interface module includes a general output GPO interface module, or a serial external device SPI interface module, or a radio frequency front end RFFE interface module, or a next level processing module interface module. The arbiter 305 transmits the signal output by the timing processor 0-6 to the general output GPO interface module 306, or a serial external device SPI interface module 307, or a radio frequency front end RFFE interface module 308, or a next level processing module interface module 309. In the embodiment of the present application, the clock module includes a mode x slow timer 310, a mode x timer 311, and a 32K calibration module 312. The implementation methods of each part are described below.

[0086] The standard timer / slow timer in the embodiment of the present application includes a 41-bit counter, of which the lower 16 bits are used to count the time points within the frame, the upper 15 bits are used to count the frame number, and the highest 10 bits are used to count the superframe number. Normal counting mode and slow timer mode are supported, and the two modes can achieve seamless switching. Specifically, the seamless switching can be performed by the calibration module, and the count value of the slow timer / standard counter after switching is modified according to the current count value and the periodic relationship between the standard counter and the slow timer to compensate for the clock error.

[0087] The above frame period and the maximum value of the frame number can be set by the timer period register. In this embodiment, the counting phase within the frame can be adjusted in two ways.

[0088] In a possible embodiment, the calibration module is further used to adjust the intra-frame counting phase of the current standard timer / slow timer according to the intra-frame counting phase in the phase register, that is, it is achieved by setting the phase register, and setting the phase register can adjust the value of the current intra-frame counter forward or backward; or

[0089] The calibration module is also used to automatically adjust the intra-frame counting phase of the current standard timer / slow timer according to the timing value in the timing self-control register when the corresponding timing time is reached. This method is suitable for the method that requires periodic intra-frame phase adjustment.

[0090] In the embodiment of the present application, the JESD port for data communication between the baseband chip and the RF chip includes a port supporting a time division multiplexing TDD mode and a port supporting a frequency division multiplexing FDD mode, and the operating clock frequency of the baseband chip is N times higher than the port sampling clock frequency.

[0091] The above configuration also includes TDD / FDD communication mode configured through registers.

[0092] In this way, the parallel data path supports two modes: standard JESD207 (TDD mode) and stream (FDD mode). The sampling clock frequency is determined by the phase-locked loop, and its interface working clock frequency is 6 times higher than the sampling clock. The sampling phase of each interface module, the data and data delay in the sending direction of the data path, and the working mode can all be adjusted by the corresponding registers.

[0093] like Figure 4 As shown, the timing processing module in the embodiment of the present application includes:

[0094] The timing processing control unit 401 is used to determine the timing of the uplink and downlink control instructions according to the timing configuration of the baseband chip, determine the absolute time point and the instruction start time according to the currently started standard timer or slow timer, and notify the timing and instruction start time to the instruction prefetch unit 402, and control the address generation unit 403 to generate the storage address of the uplink and downlink control instructions in the storage module;

[0095] The instruction pre-fetching unit 402 is used to read the corresponding uplink and downlink control instructions from the storage module according to the timing and send them to the execution unit 404, and when it is determined that there is an interval time from the corresponding instruction start time, send the interval time parameter to the execution unit;

[0096] The address generating unit 403 is used to generate the storage address of the uplink and downlink control instructions in the storage module under the control of the timing control unit. The default address of the address generating unit is 0 when it is just started, and any address can also be set by software before starting;

[0097] The execution unit 404 is used to receive the uplink and downlink control instructions, and when it is determined that there is a corresponding interval time parameter, start the interval time counter to count, and execute the uplink and downlink control instructions when the count reaches the interval time parameter, and when it is determined that there is no corresponding interval time parameter, execute the uplink and downlink control instructions;

[0098] An interval time counter 405 is used to start counting according to the control of the execution unit and to be cleared at the end of executing the uplink and downlink control instructions according to the control of the control unit;

[0099] The comparator 406 is used to compare the count of the interval time counter with the interval time parameter, and notify the execution unit when the count is equal to the interval time parameter.

[0100] The timing processor of the above structure provided in the embodiment of the present application supports multiple trigger instructions, mainly including no operation, disable operation, general output operation, trigger output operation, update operation, interrupt operation, SPI_RFFE operation, jump operation, conditional wait operation, register operation, data low-order assignment, data high-order assignment, conditional jump operation, conditional setting operation and other time operations. By configuring different register operations, specific modules can be controlled in a timely manner; through various conditional jumps, the timing processor event processing is made more flexible.

[0101] The embodiment of the present application realizes the data path by configuring the interface between the timing processing module and the next level interface module, and the interface between the timing processing module and the data storage. Figure 5The figure shows a schematic diagram of the structure of the data path of the embodiment of the present application, which mainly includes: a parallel interface, an R / TX FIFO port unit, an RX0FIFO path, an RX1 FIFO path, an RX2 FIFO path, a TX FIFO path, a DEBUG TX FIFO path, and a 4-way selector. There are two working modes, one is a standard JESD207, and the other is a stream mode. Both of them are parallel interfaces, corresponding to time division multiplexing and frequency division multiplexing. In time division multiplexing, only one jesd_data0[13:0] is used. In frequency division multiplexing, two jesd0_data0[13:0] and jesd0_data1[13:0] can be multiplexed. Other JESD ports, such as jesd_fclk is the transmit data path clock, jesd_mclk is the receive data path clock, jesd_enable is the 207 mode interface enable signal, jesd_txnrx is the 207 mode transmit and receive data control signal, jesd_txfm is the stream mode transmit and receive data control signal, and jesd_rxfm is the stream mode interface enable signal. These ports can be configured through registers.

[0102] The port interface Port interface RX is an interface of the timing processing module facing the data storage device. The timing processing module includes an RX FIFO (receive first-in first-out) port unit and a TX FIFO (transmit first-in first-out) port unit connected to the next-level interface module. As an optional implementation, the timing processing module includes an RX FIFO port unit connected to the next-level interface module;

[0103] The RX FIFO port unit includes a receiving counter. Each time the RX FIFO port unit outputs a number, the count of the receiving counter is increased by one. By configuring the corresponding receiving start count value and receiving end count value, the corresponding data transmission receiving and sending time windows in different application scenarios are set;

[0104] Through the selector register, the data transceiver link selected from the upstream and downstream paths corresponding to different application scenarios is configured. Among them, RX0 FIFO, RX1 FIFO, and RX2 FIFO are the three data paths in the receiving direction.

[0105] The next level interface modules include a DMA (Direct Memory Access) interface module and a DFE (Decision Feedback Equalizer) interface module.

[0106] A transmit data transmission path is formed between the RX FIFO port unit and the next-level interface module, including a TX FIFO path and a DEBUG TX FIFO path. The DEBUG TX FIFO path feeds data back to the receive data path for testing.

[0107] In the implementation, the receiving counter included in the RX FIFO port unit is a 32-bit counter RX timer. The output data of the RX FIFO can be configured with a data transmission direction by a 4-way selector register. By configuring the corresponding receiving start count value and receiving end count value, the RX FIFO can be flexibly set to receive data in a specific window.

[0108] The RX FIFO port unit sends data from the baseband chip to the next-level interface module. Its data output end is connected to the multiplexer, and the function of the multiplexer is to combine multiple data into one data.

[0109] The above-mentioned bus slave device interface and bus master device interface can be AHB bus interfaces. The data path and timing processing control unit are respectively equipped with AHB bus interfaces, which can be mounted in different power domain positions of the baseband chip architecture respectively, so as to facilitate low power consumption control processing of the chip.

[0110] The parallel interface controller of the satellite terminal provided by the embodiment of the present application can automatically compensate the clock error by hardware when switching the timer working mode. When the timer switches from the normal counting mode to the slow timer mode, the timer keeps counting until a rising edge of a 32.768KHz clock arrives, and the current count value of the timer is passed to the slow timer, and the timer stops counting at the same time. At this time, the timer works in the slow timer mode, and the counting clock of the slow timer is 32.768KHz, that is, a standard 32.768KHz clock cycle is equal to multiple normal timer clock cycles. This value can be obtained by the 32.768KHz calibration module, and therefore, the error of the 32.768KHz clock can be automatically compensated by hardware.

[0111] The data path and timing processing control unit are respectively equipped with AHB (Advanced High-performance Bus) bus interfaces, which can be mounted in different power domain locations (subsystems) of the baseband chip architecture. According to different application scenarios of the chip, the corresponding low-power registers can be configured to achieve low-power operation of the controller.

[0112] The parallel interface controller of the satellite terminal provided in the embodiment of the present application can configure different receive timing RXtimer register parameters to realize two sending windows with different parameters, realize multiple receive windows with different parameters, change the window length during the receiving process, receive an odd number of IQ pairs with a receive window length, delete the receive window and other functions, and the configuration of the receive window parameters is flexible.

[0113] Based on the same inventive concept, an embodiment of the present application further provides a satellite terminal, including:

[0114] A baseband chip, integrated with the parallel interface controller of the satellite terminal provided by the above embodiment;

[0115] Radio frequency chip, used for transmitting radio frequency signals with satellites.

[0116] The structure of the parallel interface controller of the satellite terminal is specifically described in the above embodiment and will not be described in detail here.

[0117] Based on the same inventive concept, the embodiment of the present application also provides an interface control method of a parallel interface controller of a satellite terminal, such as Figure 6 As shown, including:

[0118] Step 601, configuring the timing processing module through the bus interface, wherein the configuration includes timing configuration;

[0119] Step 602, storing the up and down control instructions and related data in the storage module;

[0120] Step 603, determining the timing of the uplink and downlink control instructions according to the timing configuration of the baseband chip, and reading the corresponding uplink and downlink control instructions from the storage module according to the timing;

[0121] Step 604, determining the absolute time point and the instruction start time according to the currently started standard timer or slow timer, wherein the frequency of the slow timer is lower than the frequency of the standard timer;

[0122] Step 605: When the corresponding instruction start time is reached, the uplink and downlink control instructions are executed to realize the transmission of related transmission data with the next level interface module.

[0123] In one or more possible embodiments, the method further includes:

[0124] Configure the JESD port for data communication between the baseband chip and the RF chip;

[0125] Configure the uplink and downlink paths between the timing processing module and the next-level interface module connected;

[0126] Configure the sending and receiving time windows for data transmission in the uplink and downlink channels corresponding to different application scenarios;

[0127] Configure the data transceiver links selected from the uplink and downlink paths corresponding to different application scenarios.

[0128] In implementation, the interface control of the parallel interface controller of the timing satellite terminal can be carried out through the following main steps:

[0129] Step A, initializing the uplink and downlink control instructions of the timing processor.

[0130] The timing processor can process events according to the corresponding timing only after completing the initialization of the uplink and downlink control instructions. It should be noted that after executing the uplink or downlink control instructions, the timing processor needs to send an interrupt notification to the baseband chip CPU;

[0131] Step B, configure and select the JESD port and the upstream (downstream) path configuration through the baseband chip;

[0132] Step C: Configure different receiving and sending time windows according to different application scenarios. However, each time you configure a new receiving window, reset the corresponding FIFO after the receiving counter is enabled and before the start time of receiving and sending, and clear the receiving and sending count value to ensure that the data in each new receiving window is not affected by the previous one.

[0133] Step D, enabling the transceiver counter, and flexibly setting the data transmission and reception in a specific window by configuring the corresponding receiving start count value and receiving end count value;

[0134] Step E: according to different application scenarios, configure different data transceiver links, such as the next-level module configuration or SPI configuration or DMA configuration;

[0135] Step F, enabling the timer and the timing processor, and the timing processor starts receiving data according to relevant configurations.

[0136] The present application discloses a design method for a low-power parallel interface controller of a low-orbit communication baseband chip with low power consumption, multi-speed sampling rate switching and high performance. The control circuit and the data path are implemented in different power domains to meet the low-power application scenario where the data interface is temporarily closed. By introducing a counter in the RX FIFO, the start and end time points of data reception are quantified, which facilitates the flexible configuration of the receiving window. The timing processor can provide a variety of instruction operations, interrupt unexecuted instructions, and add new instruction operations. At the same time, the timer can provide multi-speed sampling rates and high-precision time slot interrupts for the low-orbit communication protocol, solving the problem of low compatibility between the ground baseband chip RF controller and the low-orbit communication protocol.

[0137] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A parallel interface controller for a satellite terminal, characterized in that: include: A clock module, including a standard timer and a slow timer, starts the slow timer in the low power consumption mode according to the control of the baseband chip, and starts the standard timer when exiting the low power consumption mode, wherein the frequency of the slow timer is lower than the frequency of the standard timer; A bus interface, connected between the timing processing module and the baseband chip, for configuring the timing processing module and transmitting data through the baseband chip, wherein the configuration includes timing configuration; A radio frequency interface module is connected between the timing processing module and the radio frequency chip; A storage module, used to store uplink and downlink control instructions and related data configured by the baseband chip to the timing processing module; The timing processing module determines the timing of the uplink and downlink control instructions according to the timing configuration of the baseband chip, reads the corresponding uplink and downlink control instructions from the storage module according to the timing, determines the absolute time point and the instruction start time according to the currently started standard timer or slow timer, and executes the uplink and downlink control instructions when the corresponding instruction start time is reached to realize the transmission of related transmission data with the next-level interface module.

2. The parallel interface controller of the satellite terminal according to claim 1, characterized in that: The configuration also includes at least one of the following configurations: Configure the JESD port for data communication between the baseband chip and the RF chip; Configure the uplink and downlink paths between the timing processing module and the next-level interface module connected; Configure the sending and receiving time windows for data transmission in the uplink and downlink channels corresponding to different application scenarios; Configure the data transceiver links selected from the uplink and downlink paths corresponding to different application scenarios.

3. The parallel interface controller of the satellite terminal according to claim 2, characterized in that: The timing processing module includes an RX FIFO port unit connected to the next level chip; The RX FIFO port unit includes a receiving counter. Each time the RX FIFO port unit outputs a number, the count of the receiving counter is increased by one. By configuring the corresponding receiving start count value and receiving end count value, the corresponding data transmission receiving and sending time windows in different application scenarios are set; Through the selector register, the data transceiver link selected from the uplink and downlink paths corresponding to different application scenarios is configured.

4. The parallel interface controller of the satellite terminal according to claim 1, characterized in that: The data port between the baseband chip and the radio frequency chip includes a port supporting a time division multiplexing TDD mode and a port supporting a frequency division multiplexing FDD mode, and the operating clock frequency of the baseband chip is N times higher than the port sampling clock frequency; The configuration also includes TDD / FDD communication mode configured by registers.

5. The parallel interface controller of the satellite terminal according to claim 1, characterized in that: The timing processing module comprises: A timing processing control unit, used to determine the timing of the uplink and downlink control instructions according to the timing configuration of the baseband chip, determine the absolute time point and the instruction start time according to the currently started standard timer or slow timer, and notify the instruction prefetch unit of the timing and the instruction start time, and control the address generation unit to generate the storage address of the uplink and downlink control instructions in the storage module; An instruction pre-fetch unit, configured to read the corresponding uplink and downlink control instructions from the storage module according to the timing and send them to the execution unit, and when determining that there is an interval time from the corresponding instruction start time, send the interval time parameter to the execution unit; An address generating unit, used for generating storage addresses of uplink and downlink control instructions in the storage module under the control of the timing control unit; An execution unit, configured to receive an uplink and downlink control instruction, and when determining that a corresponding interval time parameter exists, start an interval time counter to count, and when the count reaches the interval time parameter, execute the uplink and downlink control instruction, and when determining that no corresponding interval time parameter exists, execute the uplink and downlink control instruction; An interval time counter, used to start counting according to the control of the execution unit, and to be cleared at the end of executing the uplink and downlink control instructions according to the control of the control unit; A comparator is used to compare the count of the interval time counter with the interval time parameter, and to notify the execution unit when the count is equal to the interval time parameter.

6. The parallel interface controller of the satellite terminal according to claim 1, characterized in that: The standard timer / slow timer includes a 41-bit counter, wherein the lower 16 bits are used for counting time points within a frame, the upper 15 bits are used for counting frame numbers, and the highest 10 bits are used for counting superframe numbers.

7. The parallel interface controller for a satellite terminal according to any one of claims 1 to 6, characterized in that: Also includes: The calibration module is used to modify the count value of the switched slow timer / standard counter to compensate for the clock error according to the current count value and the periodic relationship between the standard counter and the slow timer when switching from the standard timer to the slow timer or from the slow timer to the standard timer.

8. The parallel interface controller of the satellite terminal according to claim 7, characterized in that: The calibration module is further configured to adjust the intra-frame counting phase of the current standard timer / slow timer according to the intra-frame counting phase in the phase register; or The calibration module is also used to automatically adjust the intra-frame counting phase of the current standard timer / slow timer according to the timing value in the timing self-control register when the corresponding timing time is reached.

9. The parallel interface controller of a satellite terminal according to claim 1, characterized in that: The bus interface includes a bus slave device interface and a bus master device interface, wherein: The bus slave device interface is used by the baseband chip to configure relevant registers in the timing processing module, and the bus master device interface is used by the baseband chip to transmit data with the timing processing module.

10. A satellite terminal, characterized in that: include: A baseband chip, integrated with the parallel interface controller of the satellite terminal according to any one of claims 1 to 9; Radio frequency chip, used for transmitting radio frequency signals with satellites.

11. An interface control method for a parallel interface controller of a satellite terminal, characterized in that: include: Configuring the timing processing module through the bus interface, wherein the configuration includes timing configuration; Storing up and down control instructions and related data in the storage module; Determine the timing of the uplink and downlink control instructions according to the timing configuration of the baseband chip, and read the corresponding uplink and downlink control instructions from the storage module according to the timing; Determine the absolute time point and the instruction start time according to the currently started standard timer or slow timer, the frequency of the slow timer is lower than the frequency of the standard timer; When the corresponding instruction start time is reached, the uplink and downlink control instructions are executed to realize the transmission of related transmission data with the next level interface module.

12. The method according to claim 11, characterized in that Also includes: Configure the JESD port for data communication between the baseband chip and the RF chip; Configure the uplink and downlink paths between the timing processing module and the next-level interface module connected; Configure the sending and receiving time windows for data transmission in the uplink and downlink channels corresponding to different application scenarios; Configure the data transceiver links selected from the uplink and downlink paths corresponding to different application scenarios.

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