PAL external synchronization video display control method for realizing anti-interference based on composite synchronization CSYNC

Abstract

The invention relates to a PAL external synchronization video display control method for realizing anti-interference based on composite synchronization CSYNC, and belongs to the technical field of development of logic gate arrays such as aerospace and the like and image transmission and video superposition of airborne pod display control components. According to the invention, an EP4CE115F23I7 FPGA (Field Programmable Gate Array) is used as a master controller, only a CYSNC composite synchronizing signal generated by an EL1883 line-field separation chip is analyzed, and a pixel clock PCLK, 8-bit pixel data PIXDATA, line synchronization hsync and odd-even field indication field signals required by a physical layer video encoder GM7121 are generated. According to the method, only a small part of registers of an encoder GM7121 need to be configured, and videos generated by a control box are stably superposed on an airborne display screen by generating a time sequence conforming to BT.656. The hardware circuit adopted by the invention is low in design cost, and the FPGA logic software can be flexibly upgraded to adapt to various picture scenes on the machine. According to the invention, the display control of the airborne equipment is suitable for more different scenes, the control is more flexible, the anti-interference performance of video transmission is stronger, and the hardware cost is lower.

Description

Technical Field

[0001] The present invention belongs to the field of development of logic gate arrays in aerospace and the like, and the technical field of image transmission and video superposition of airborne pod display and control components, in particular to the field of synchronous display control of airborne pod images and videos, and specifically relates to a PAL external synchronous video display control method based on composite synchronous CSYNC to achieve anti-interference. Background Art

[0002] The video image display of each onboard device is extremely important for the coordinated work of each device and the command instructions to the operator. The onboard personnel judge the next operation to be performed based on the peripheral buttons on the display screen and the central analog video screen, which involves the superposition of local video and external video and external synchronization control.

[0003] The current aviation airborne analog video adopts the PAL format. Video overlay refers to the external video control device superimposing the PAL analog video in the central area of ​​the onboard display screen, while the surrounding areas of the display screen are simulated images of peripheral buttons generated locally by the display control components. This is a technology that realizes displaying specific video images in the central area by operating the peripheral buttons on the display screen; therefore, it involves an external synchronization control method for PAL analog video.

[0004] The traditional PAL external synchronization display control solution includes: using a DSP processor or FPGA to parse the line-field separation chip to generate the line synchronization HSYNC and field synchronization VSYNC signals to ensure that the local video encoding timing is consistent with the timing generated by the onboard display control, and the external analog video is seamlessly embedded in the onboard display control screen; however, the electromagnetic environment on the aircraft is complex, and the analog signal generated by the display control component often needs to be routed over a long distance through the cable to the external control box device, so it is very susceptible to electromagnetic interference, resulting in distortion of the quality and timing of the image analog signal. Therefore, it is particularly important to implement an interference-resistant PAL external synchronization video display control technology. Summary of the invention

[0005] 1. Technical issues to be resolved

[0006] The technical problem to be solved by the present invention is to provide a PAL external synchronous video display control method capable of realizing anti-interference.

[0007] (II) Technical solution

[0008] In order to solve the above technical problems, the present invention provides a PAL external synchronous video display control method based on composite synchronous CSYNC to achieve anti-interference. The method is implemented based on a line-field separation chip EL1883, an FPGA, and an image encoder GM7121; the FPGA receives the CSYNC synchronization timing signal generated by the EL1883, and performs logic filtering and analysis on the CSYNC synchronization timing signal to obtain the pixel driving clock PCLK, 8-bit pixel data PIX_DATA, line synchronization signal hsync, and odd and even field indication filed control signal required to drive the GM7121, and the CSYNC synchronization timing signal is referred to as CSYNC; GM7121 realizes DAC conversion of encoded data; the FPGA also realizes the BT.656 timing driven in the external synchronization mode through a finite state machine, and the finite state machine realized by the FPGA includes an encoder state machine and a CSYNC timing state machine, the encoder state machine is used to control the BT.656 encoding process, and the CSYNC timing state machine is used to control the process of desynchronizing the CSYNC synchronization.

[0009] (III) Beneficial effects

[0010] The present invention adopts EP4CE115F23I7 FPGA as the main control, and only parses the CYSNC composite synchronization signal generated by the EL1883 line field separation chip to generate the pixel clock PCLK, 8-bit pixel data PIX_DATA, and line synchronization hsync and odd and even field indication filed signals required to drive the physical layer video encoder GM7121. The method only needs to configure a small part of the registers of the encoder GM7121, and by generating a timing that complies with BT.656, the video generated by the control box is stably superimposed on the onboard display screen. The hardware circuit design adopted by the present invention is low in cost, and the FPGA logic software can be flexibly upgraded to adapt to various screen scenes on the aircraft. The present invention makes the display control of the airborne equipment suitable for more different scenarios, the control is more flexible, the video transmission is more resistant to interference, and the hardware cost is lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a block diagram of a scheme for realizing a PAL external synchronous video display control method for realizing anti-interference based on composite synchronous CSYNC of the present invention;

[0012] Figure 2 It is a CSYNC timing state machine operation flow chart designed in the present invention;

[0013] Figure 3 The present invention discloses an encoder algorithm flow chart of a PAL external synchronous video display control method for realizing anti-interference based on composite synchronous CSYNC. DETAILED DESCRIPTION

[0014] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0015] The invention provides a display control method for realizing video superposition with an externally input CVBS video analog source based on an EL1883 line-field separation chip of INTERSIL Company equipped with an EP4CE115F23I7FPGA logic gate array and a physical encoder chip GM7121.

[0016] The present invention provides a PAL external synchronous video display control method based on composite synchronous CSYNC to achieve anti-interference. The method is implemented based on the line field separation chip EL1883, FPGA, and image encoder GM7121. Figure 1 , FPGA receives CSYNC synchronization timing signal (abbreviated as CSYNC) generated by EL1883, and performs logic filtering and analysis on CSYNC synchronization timing signal to obtain pixel drive clock PCLK, 8-bit pixel data PIX_DATA, line synchronization signal hsync and odd and even field indication filed control signal required to drive GM7121, GM7121 realizes DAC conversion of coded data; FPGA also realizes BT.656 timing driven in external synchronization mode through finite state machine, and the finite state machine realized by FPGA includes encoder state machine and CSYNC timing state machine, encoder state machine is used to control BT.656 encoding process, and CSYNC timing state machine is used to control the process of desynchronizing CSYNC synchronization. The key design points are described below.

[0017] 1. FPGA receives the CSYNC synchronization timing signal generated by EL1883

[0018] The EL1883 can parse both PAL analog signals and NTSC analog signals. The specific type of analog signal to be parsed depends entirely on the external input of the EL1883. There is no difference between the two in the hardware circuit: the EL1883 is powered by a single 5V power supply, and the input is a CVBS analog synchronization signal (voltage swing range: 0.5-2V), a timing configuration pin Rset (680KΩ resistance to ground, accuracy 1%), and the Rf pin is used to simulate the pre-low-pass filtering of the video source signal; the EL1883 can output the horizontal synchronization HSYNC, the field synchronization VSYNC, and the composite video synchronization signal, namely the CSYNC synchronization timing signal; in the present invention, the FPGA only receives the CSYNC synchronization timing signal, and compares the phase period of the CSYNC synchronization timing signal with the CVBS analog synchronization signal input to the EL1883 from the external airborne display and control system. When the phase difference between the two is constant and the period is consistent, it proves that the EL1883 has successfully separated the external synchronization signal required by the FPGA.

[0019] 2. FPGA performs logical filtering and analysis on CSYNC synchronization timing signal

[0020] Since the CVBS analog synchronization signal emitted by the onboard display and control system has a long cable route on the aircraft and is susceptible to electromagnetic interference signals superimposed on the normal signal, it is necessary for the FPGA to perform software logic filtering on the CSYNC synchronization timing signal output by the EL1883.

[0021] In the laboratory, spectrum analyzer analysis shows that the interference pulse width range superimposed on the CSYNC synchronization timing signal is below 100ns, and the interference cannot be avoided in hardware and is random interference. Therefore, 5-beat filtering is performed on the FPGA with reference to the 27MHz clock cycle: if the CSYNC synchronization timing signal is 1 within 5 beats, the effective level of the CSYNC synchronization timing signal at this time is judged to be 1; if the CSYNC synchronization timing signal is logic 0 within 5 beats, the effective value of the current CSYNC synchronization timing signal is judged to be 0; if the level of the CSYNC synchronization timing signal fluctuates within 5 beats, it is treated as a glitch, that is, the logic value of the CSYNC synchronization timing signal in the previous state is maintained to ensure the accuracy of the CYSNC synchronization timing signal.

[0022] Parsing the CSYNC synchronization timing signal means that the FPGA determines the pixel information of the field, row, and column of the video being encoded by the video encoder of the current airborne display and control system based on the timing characteristics of the CSYNC synchronization timing signal (CSYNC high-level pulse width), and generates the line synchronization signal hsync recognized by GM7121, the odd and even field indication field control signal, and the 27MHz pixel drive clock PCLK based on this pixel information; the CSYNC synchronization timing signal is an LVTTL signal, which is composed of pulses with different pulse widths and duty cycles. Different high-level pulse widths reflect the different stages of encoding of the current upstream video encoder; according to CCIR BT.656 image transmission protocol, lines 624 to 625 are the even field blanking porch, lines 1 to 22 are the odd field blanking porch, lines 23 to 310 are the odd field effective image coding lines, lines 311 to 312 are the odd field blanking porch; lines 313 to 335 are the even field blanking porch, and lines 336 to 623 are the even field effective image coding lines.

[0023] The timing characteristics of the CSYNC synchronization timing signal are: assuming that T represents the duration of one cycle of the 27MHz clock, Wh represents the high level pulse width of the CSYNC synchronization timing signal, and Wl represents the low level interval of the CSYNC synchronization timing signal, then:

[0024] (1) The timing characteristics when encoding rows 1 to 2.5 are: Wh = 144T, Wl = 720T;

[0025] (2) The timing characteristics when encoding lines 2.5 to 5 are: Wh = 720T, Wl = 144T;

[0026] (3) The timing characteristics when encoding rows 6 to 310 are: Wh = 1440T, Wl = 288T;

[0027] (4) The timing characteristics when encoding lines 311 to 312.5 are: Wh = 720T, Wl = 144T;

[0028] (5) The timing characteristics when encoding lines 312.5 to 315 are: Wh = 144T, Wl = 720T;

[0029] (6) The timing characteristics when encoding lines 316 to 317 are: Wh = 720T, Wl = 144T;

[0030] (7) The timing characteristics when encoding rows 318 to 622 are: Wh = 1440T, Wl = 288T;

[0031] In view of the above-mentioned timing characteristics of the CSYNC synchronization timing signal, taking into account that the CSYNC synchronization timing signal may be affected by electromagnetic noise in the transmission path and produce glitches and delays, a high-level pulse width range is set for the CSYNC synchronization timing signal in each stage of the upstream video encoder in the FPGA, and the counter detection implemented by FPGA is used. As long as the filtered CSYNC synchronization timing signal is within the range set in each stage, the CSYNC timing state machine will operate normally; by operating the CSYNC timing state machine normally, the line synchronization signal hsync and the odd and even field indication filed control signal (field mark field signal) that drive GM7121 can be obtained.

[0032] According to the different timing characteristics (different high-level pulse widths) of the CSYNC synchronization timing signal, the stage in which the upstream video encoder is currently encoding the image is identified. In the present invention, the video encoder working stage of the upstream airborne display and control system is divided into the following 23 stages, which are operated under the control of the CSYNC synchronization timing signal to ensure that the timing of the downstream GM7121 is consistent with the upstream airborne display and control system, as follows:

[0033] (1) CSYNC_IDLE stage: The initial state of the CSYNC timing state machine execution, used to assign initial values ​​to the hsync and field control signals;

[0034] (2) WAIT_FOR_LINE1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies Wh>1200T (approximately the encoding time width of 1 line);

[0035] (3) LINE1_1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 100T < Wh < 600T (much less than the encoding time width of half a line);

[0036] (4) LINE1_2 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 100T < Wh < 600T (much less than the encoding time width of half a line);

[0037] (5) LINE2_1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 100T < Wh < 600T (much less than the encoding time width of half a line);

[0038] (6) LINE2_2 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 100T < Wh < 600T (much less than the encoding time width of half a line);

[0039] (7) LINE3_1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 100T < Wh < 600T (much less than the encoding time width of half a line);

[0040] (8) LINE3_2 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 600T < Wh < 1200T (approximate to the encoding time width of half a line);

[0041] (9) LINE4_1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 600T < Wh < 1200T (approximate to the encoding time width of half a line);

[0042] (10) LINE4_2 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 600T < Wh < 1200T (approximate to the encoding time width of half a line);

[0043] (11) LINE5_1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 600T < Wh < 1200T (approximate to the encoding time width of half a line);

[0044] (12) LINE5_2 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 600T < Wh < 1200T (approximate to the encoding time width of half a line);

[0045] (13) WAIT_FOR_LINE313: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies Wh > 1200T (approximate to the encoding time width of one line);

[0046] (14) LINE313_1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 600T < Wh < 1200T (approximately the coding time width of half a line);

[0047] (15) LINE313_2 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 100T < Wh < 600T (much less than the coding time width of half a line);

[0048] (16) LINE314_1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 100T < Wh < 600T (much less than the coding time width of half a line);

[0049] (17) LINE314_2 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 100T < Wh < 600T (much less than the coding time width of half a line);

[0050] (18) LINE315_1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 100T < Wh < 600T (much less than the coding time width of half a line);

[0051] (19) LINE315_2 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 100T < Wh < 600T (much less than the coding time width of half a line);

[0052] (20) LINE316_1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 600T < Wh < 1200T (approximately the coding time width of half a line);

[0053] (21) LINE316_2 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 600T < Wh < 1200T (approximately the coding time width of half a line);

[0054] (22) LINE317_1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 600T < Wh < 1200T (approximately the coding time width of half a line);

[0055] (23) LINE317_2 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies 600T < Wh < 1200T (approximately the coding time width of half a line);

[0056] 3. Register configuration of the image encoder GM7121

[0057] Image encoder configuration refers to the register configuration of the internal working mode of GM7121 completed by FPGA through the I2C interface (baud rate 400K). The specific registers that need to be configured are: 0x3A (master-slave mode of the image encoder, configured as: 03h slave mode), 0x5B (U component gain control, configured as: 21h), 0x5C (V component gain control, configured as: AFh), 0x5D (black level gain control, configured as: 0x0E), 0x61 (image encoder output video format, configured as 06h, PAL format), 0x63~0x66 (subcarrier frequency selection: configured as CBh, 8Ah, 09h, 2Ah), 0x6B (RCV port configuration, configured as 60h, 7121 receives line synchronization hsync and field mark field signal), 0x6C, 0x6D, 0x75 (horizontal and vertical trigger positions of the image, all configured as 00h), and the remaining registers are not critical registers and do not need to be configured.

[0058] 4. FPGA generates BT.656 timing driven in external synchronization mode based on finite state machine

[0059] The BT.656 timing refers to the timing that FPGA sends out in accordance with the image coding protocol, so that GM7121 can complete reliable reception and achieve the expected DAC conversion effect. For the encoding of the standard definition PAL format, the resolution is 720*576. Since the YCbCr (4:2:2) encoding format is to be generated, that is, each pixel is described by two brightness components Y1, Y2 and a chrominance component CbCr, that is, a Cb-Y1-Cr-Y2 pixel group signal is generated within four pixel clock pclk cycles; therefore, each row needs to provide 1440 chrominance and brightness pixel information, plus the time occupied by the line blanking, a total of 1728 PCLK cycles are required to encode a row of images. The present invention uses the variable Pixels to count the sequence number of the pclk in the current row as the column index of the current encoding. However, the scanning of a frame of PAL standard image is composed of: the number of even field scanning lines (288) + the number of odd field scanning lines (288) + the number of field blanking lines (49), so the variable Lines (maximum 625) is used as the line index of the current encoding in the present invention.

[0060] In addition, the present invention uses the CSYNC synchronization timing signal to generate three variables, START_PIXEL, LINE_1ST and LINE_313TH, through internal logic processing of the FPGA to determine the line encoding starting point, odd and even field encoding starting point, and their respective encoding end points of the encoder state machine. At the same time, the GM7121 is driven by counting in the form of a synchronization code to achieve strict timing synchronization with the analog video signal provided by the airborne display and control system.

[0061] The system processor in this design uses TI's TMS320F28377, which is used to complete the upper computer reception of image and video instructions and the instruction control of the lower computer. The image processing main control chip uses ALTERA's EP4CE115F23I7 chip to complete the configuration of the encoding chip, the composite synchronization signal CSYNC reception and processing, and the implementation of the bt656 encoding state machine. The line-field separation chip uses EL1883 to generate composite synchronization CSYNC, and the physical layer encoder chip uses Chengdu Zhenxin Company's GM7121 to realize the DAC conversion of encoded data.

[0062] The I2C bus in this design complies with the Philips standard. It is a simple, bidirectional two-wire synchronous serial bus SCL, SDA. The SDA data is updated during the low level of SCL, and can be reliably sampled during the high level of SCL. The interface circuit is an open-drain output. Both the master and slave devices have control over the bus. Generally, a write operation needs to go through three stages: (sending the destination device address-sending the device internal register address-writing the register configuration content). Each stage requires 9 I2C clock cycles. In the 9th clock cycle of each stage, the host releases the bus control right (high impedance state) and switches to the slave for generating an ACK response. In this embodiment, the FPGA gives the configuration data of certain registers of GM7121 in turn through the I2C bus, and reads back certain key registers to ensure successful configuration.

[0063] The GM7121 in this design is a physical layer encoder chip compatible with the BT656 transmission protocol. It integrates an I2C slave interface to obtain the host's configuration data to determine the working mode (external synchronization, receiving the hsync and odd and even field signals from the host). The output of the GM7121 is usually paired with the SGM9111 video driver to enhance the driving capability of the DAC video signal output by the 7121 to the aviation plug connector.

[0064] like Figure 1 As shown, it is a block diagram of a method for realizing anti-interference PAL external synchronous video display control based on composite synchronous CSYNC.

[0065] The system processor in this embodiment adopts TI's TMS320F28377, which is used to complete the upper computer reception of image and video instructions and the display control of the lower computer. The image processing main control chip uses ALTERA's EP4CE115F23I7 chip to complete the configuration of the encoding chip, the synchronization signal reception and processing of the line and field chip EL1883, and the implementation of the bt656 algorithm. The line and field separation chip adopts EL1883 to generate the external synchronization signal CSYNC. The encoder chip adopts GM7121 to realize the DAC conversion of the encoded data and amplifies and drives the analog signal through SGM9111, thereby completing the flexible control of the pod display screen by the onboard upper computer equipment.

[0066] like Figure 2 As shown, it is the operation flow chart of CSYNC timing state machine.

[0067] In this design, according to the 23 different timing characteristics of the CSYNC synchronization timing signal, the 23 different working stages of the encoder of the current airborne display and control system are identified, and the work completed in each stage and the state transfer conditions are clearly shown in the flow chart.

[0068] like Figure 3 As shown, an encoder algorithm flow chart of a PAL external synchronous video display control method for achieving anti-interference based on composite synchronous CSYNC.

[0069] In particular, the states that the encoder state machine needs to encode are as follows:

[0070] (1) IDLE state: complete pixel row and column pointer initialization, default value initialization of all pixels in the image, GM7121 configuration, synchronization processing of CSYNC generated by EL1883, deburring, filtering and initialization;

[0071] (2) WORK state: detect the line coding starting point START_PIXEL, the coding line 1 mark LINE_1ST, the coding line 313 mark LINE_313TH and the line pointer increment trigger condition.

[0072] (3) EAV state (pixel pointer Pixels <= 4): end (not start) synchronization code state, including:

[0073] Output even field blanking rear shoulder end synchronization code EAV1 = 8'hB6;

[0074] Output even field data end synchronization code EAV2 = 8'h9D;

[0075] Output even field blanking front shoulder end synchronization code EAV3 = 8'hB6;

[0076] Output the shoulder sync code EAV4 = 8'hF1 after the odd field blanking ends;

[0077] Output the sync code EAV5 = 8'hDA at the end of the odd field data;

[0078] Output the shoulder sync code EAV6 = 8'hF1 before the odd field blanking ends;

[0079] (4) VBLANKING state (pixel pointer 4 <Pixels <= 284): Line blanking state, including:

[0080] Output the fill code BLANK_ODD = 8'h10 at the odd pixel position in the line blanking area;

[0081] Output the fill code BLANK_EVEN = 8'h80 at the even pixel position in the line blanking area;

[0082] (5) SAV state (pixel pointer 284 <Pixels <= 288): Start sync code state, including:

[0083] The start sync code SAV1 = 8'hAB after the even field blanking;

[0084] The start sync code SAV2 = 8'h80 for the even field data;

[0085] The start sync code SAV3 = 8'hAB before the even field blanking;

[0086] The start sync code SAV4 = 8'hEC after the odd field blanking;

[0087] The start sync code SAV5 = 8'hC7 for the odd field data;

[0088] The start sync code SAV6 = 8'hEC before the odd field blanking;

[0089] (6) DATA state (pixel pointer 288 <Pixels <= 1728): Picture data encoding state, including:

[0090] Chrominance component Cb encoding state: EVEN;

[0091] Luminance component Y1 encoding state: Y_DATA1;

[0092] Chrominance component Cr encoding state: ODD;

[0093] Luminance component Y2 encoding state: Y_DATA2;

[0094] (7) END state: The state where the picture has completed 1 frame and 2 fields of scanning. It will jump back to the WORK state and continuously loop to refresh the encoded picture.

[0095] When the 27M pixel clock pclk generated by the internal PLL of the FPGA has been locked and the I2C configuration timing of the GM7121 has been completed, the START_ENCODING flag signal is pulled high to trigger the GM7121 to work. The specific process is as follows:

[0096] Step 1: The encoder state machine implemented in FPGA is in IDLE state, the pixel pointer Pixels = 0, the line pointer Lines = 0, the GM7121 data state is in the blanking end code state EAV by default, when START_ENCODING = 1, jump to step 2;

[0097] Step 2: The encoder state machine is in the WORK state. When START_PIXEL=1 is detected, the pixel column pointer Pixels is set to 11'd1, and the first pixel data is printed at the same time: 8'hFF. In addition, it is necessary to detect whether the first row flag LINE_1ST is pulled high in the same clock cycle of pclk. If it is not pulled high, it means that the external analog source input state is abnormal or the EL1883 analysis is abnormal. At this time, the row pointer should keep the previous state unchanged, and drive GM7121 to give the blanking black level data 8'h10. If LINE_1ST is already pulled high at this time, the row pointer is set to 1; the pixel pointer Pixels accumulates 1 continuously on the falling edge of pclk. When the EAV state is (Pixels<=4), the leading code is generated respectively: 8'hff, 8'h00, 8'h00, EAVx. When the pixel pointer Pixels>4, jump to step 3;

[0098] Step 3: The encoder state machine enters the line blanking area. When the pixel pointer satisfies 5<=Pixels<=283, a fill code 8'h10 is generated when the value of the Pixels pointer is an odd number, and a fill code 8'h80 is generated when the value of the Pixels pointer is an even number. When the pixel pointer satisfies Pixels>=284, jump to step 4;

[0099] Step 4: The encoder state machine enters the SAV state. According to the number of lines currently encoded, it enters the even field blanking start SAV1, even field data start SAV2, odd field blanking start SAV4, and odd field data start SAV5 states. Similar to step 2, the leading code is generated: 8'hff, 8'h00, 8'h00, SAVx. When the pixel index Pixels>288, jump to step 5.

[0100] Step 5: The encoder state machine enters the data encoding DATA state. According to the YCbCr422 encoding format, it enters the EVEN state, Y_DATA1 state, ODD state, and Y_DATA2 state in sequence. When it is detected that the pixel pointer Pixels>=1728, the data state is transferred to EAV, the line index Lines is increased by 1, the pixel pointer Pixels is set to 1, and the process jumps to step 2. When it is detected that the current number of encoding lines is 625, the encoding of one frame of the image has been completed, the data state datadone is pulled high, and the process jumps to step 2 to determine whether the line pointer should be kept or set to 2 in the next cycle; this cycle is repeated continuously, and the screen is continuously refreshed to produce a video effect.

[0101] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A PAL external synchronous video display control method based on composite synchronous CSYNC to achieve anti-interference, characterized in that: The method is implemented based on the line-field separation chip EL1883, FPGA and image encoder GM7121; FPGA receives the CSYNC synchronization timing signal generated by EL1883, and performs logic filtering and analysis on the CSYNC synchronization timing signal to obtain the pixel driving clock PCLK, 8-bit pixel data PIX_DATA, line synchronization signal hsync and odd-even field indication filed control signal required to drive GM7121, and the CSYNC synchronization timing signal is referred to as CSYNC; GM7121 realizes DAC conversion of encoded data; FPGA also realizes the BT.656 timing driven in external synchronization mode through a finite state machine, and the finite state machine realized by FPGA includes an encoder state machine and a CSYNC timing state machine, the encoder state machine is used to control the encoding process of BT.656, and the CSYNC timing state machine is used to control the process of desynchronizing CSYNC synchronization.

2. The method according to claim 1, characterized in that FPGA only receives CSYNC synchronization timing signal, and compares the phase period of CSYNC synchronization timing signal with the CVBS analog synchronization signal input to EL1883 from the external airborne display and control system. When the phase difference between the two is constant and the period is consistent, it proves that EL1883 has successfully separated the external synchronization signal required by FPGA.

3. The method according to claim 1, characterized in that The FPGA performs 5-beat filtering with reference to the 27MHz clock cycle: if the CSYNC synchronization timing signal is 1 within 5 beats, the effective level of the CSYNC synchronization timing signal at this time is judged to be 1; if the CSYNC synchronization timing signal is logic 0 within 5 beats, the effective value of the current CSYNC synchronization timing signal is judged to be 0; if the level of the CSYNC synchronization timing signal fluctuates within 5 beats, it is treated as a glitch, that is, the logic value of the CSYNC synchronization timing signal in the previous state is maintained.

4. The method according to claim 1, characterized in that Parsing the CSYNC synchronization timing signal means that the FPGA determines the pixel information of the field, row, and column of the video being encoded by the video encoder of the current airborne display and control system according to the timing characteristics of the CSYNC synchronization timing signal, and generates the line synchronization signal hsync recognized by GM7121, the odd and even field indication field control signal, and the 27MHz pixel drive clock PCLK according to this pixel information; The CSYNC synchronization timing signal is an LVTTL signal, which is composed of pulses with different pulse widths and duty cycles. Different high-level pulse widths reflect the different stages of encoding of the current video encoder. According to the CCIR BT.656 image transmission protocol, lines 624 to 625 are the even field blanking back porch, lines 1 to 22 are the odd field blanking front porch, lines 23 to 310 are the odd field effective image coding lines, and lines 311 to 312 are the odd field blanking back porch; lines 313 to 335 are the even field blanking front porch, and lines 336 to 623 are the even field effective image coding lines.

5. The method according to claim 1, characterized in that The timing characteristics of the CSYNC synchronization timing signal refer to: assuming that T represents the duration of one cycle of the 27MHz clock, Wh represents the high-level pulse width of the CSYNC synchronization timing signal, and Wl represents the low-level interval of the CSYNC synchronization timing signal, then: (1) The timing characteristics when encoding rows 1 to 2.5 are: Wh = 144T, Wl = 720T; (2) The timing characteristics when encoding lines 2.5 to 5 are: Wh = 720T, Wl = 144T; (3) The timing characteristics when encoding rows 6 to 310 are: Wh = 1440T, Wl = 288T; (4) The timing characteristics when encoding lines 311 to 312.5 are: Wh = 720T, Wl = 144T; (5) The timing characteristics when encoding lines 312.5 to 315 are: Wh = 144T, Wl = 720T; (6) The timing characteristics when encoding lines 316 to 317 are: Wh = 720T, Wl = 144T; (7) The timing characteristics when encoding rows 318 to 622 are: Wh = 1440T, Wl = 288T; In FPGA, a high-level pulse width range is set for the CSYNC synchronization timing signal at each stage of the video encoder. The counter detection implemented by FPGA is used. As long as the filtered CSYNC synchronization timing signal is within the range set at each stage, the CSYNC timing state machine will operate normally. By operating the CSYNC timing state machine normally, the line synchronization signal hsync and the odd and even field indication filed control signal that drive GM7121 can be obtained.

6. The method according to claim 5, characterized in that According to the different timing characteristics of the CSYNC synchronization timing signal, the stage in which the video encoder is currently encoding the image is identified. The video encoder working stage of the airborne display and control system is divided into the following 23 stages, which are operated under the control of the CSYNC synchronization timing signal to ensure that the timing of the GM7121 is consistent with the airborne display and control system. The details are as follows: (1) CSYNC_IDLE stage: The initial state of the CSYNC timing state machine, used to assign initial values ​​to the hsync and odd and even field indication field control signals; (2) WAIT_FOR_LINE1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies Wh>1200T; (3) LINE1_1 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 100T <Wh<600T; (4) LINE1_2 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 100T <Wh<600T; (5) LINE2_1 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 100T <Wh<600T; (6) LINE2_2 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 100T <Wh<600T; (7) LINE3_1 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 100T <Wh<600T; (8) LINE3_2 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 600T <Wh<1200T; (9) LINE4_1 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 600T <Wh<1200T; (10) LINE4_2 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 600T <Wh<1200T; (11) LINE5_1 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 600T <Wh<1200T; (12) LINE5_2 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 600T <Wh<1200T; (13) WAIT_FOR_LINE313: In this stage, the CSYNC high level pulse width of the synchronization timing signal satisfies Wh>1200T; (14) LINE313_1 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 600T <Wh<1200T; (15) LINE313_2 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 100T <Wh<600T; (16) LINE314_1 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 100T <Wh<600T; (17) LINE314_2 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 100T <Wh<600T; (18) LINE315_1 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 100T <Wh<600T; (19) LINE315_2 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 100T <Wh<600T; (20) LINE316_1 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 600T <Wh<1200T; (21) LINE316_2 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 600T <Wh<1200T; (22) LINE317_1 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 600T <Wh<1200T; (23) LINE317_2 stage: In this stage, the high level pulse width of the CSYNC synchronization timing signal meets 600T <Wh<1200T。 7. The method according to claim 1, characterized in that FPGA completes the register configuration of the internal working mode of GM7121 through the I2C interface. The specific registers that need to be configured are: 0x3A: master-slave mode of the image encoder, configured as 03h slave mode; 0x5B: U component gain control, configured as 21h; 0x5C: V component gain control, configured as AFh; 0x5D: black level gain control, configured as 0x0E; 0x61: image encoder output video format, configured as 06h, PAL format: 0x63~0x66: subcarrier frequency selection: configured as CBh, 8Ah, 09h, 2Ah; 0x6B: RCV port configuration, configured as 60h, 7121 receives line synchronization hsync and field mark field signal: 0x6C, 0x6D, 0x75: horizontal and vertical trigger positions of the image, all configured as 00h.

8. The method according to claim 1, characterized in that The BT.656 timing driven in the external synchronization mode generated by the FPGA through the finite state machine refers to the timing that the FPGA sends out in accordance with the image encoding protocol, so that the GM7121 can complete reliable reception and achieve the expected DAC conversion effect; for the standard definition PAL format encoding, the resolution is 720*576, and each pixel is described by two brightness components Y1, Y2 and a chrominance component CbCr, that is, the Cb-Y1-Cr-Y2 pixel group signal is generated within four pixel clock pclk cycles; therefore, each row needs to provide 1440 chrominance and brightness pixel information, plus the time occupied by line blanking, encoding a line of image requires a total of 1728 PCLK cycles, and the variable Pixels is used to count the sequence number of pclk in the current row as the column index of the current encoding; however, the scanning of a frame of PAL format image consists of: the number of even field scanning lines + the number of odd field scanning lines + the number of field blanking lines, so the variable Lines is used as the line index for the current encoding.

9. The method according to claim 1, characterized in that The three variables START_PIXEL, LINE_1ST and LINE_313TH generated by the CSYNC synchronization timing signal through the internal logic processing of the FPGA are used to determine the line encoding start point, odd and even field encoding start point, and their respective encoding end points of the encoder state machine. At the same time, the GM7121 is driven by counting in the form of synchronization code to achieve strict timing synchronization with the analog video signal given by the airborne display and control system.

10. The method according to claim 1, characterized in that The states that the encoder state machine needs to encode are as follows: (1) IDLE state: complete pixel row and column pointer initialization, default value initialization of all pixels in the image, GM7121 configuration, synchronization processing of CSYNC generated by EL1883, deburring, filtering and initialization; (2) WORK state: detect the line coding starting point START_PIXEL, the first line of coding mark LINE_1ST, the 313th line of coding mark LINE_313TH, and the line pointer increment trigger condition; (3) When the pixel pointer Pixels <= 4, it is in EAV state: end synchronization code state, including: Output even field blanking rear shoulder end synchronization code EAV1 = 8'hB6; The end synchronization code of the output even field data EAV2 = 8'h9D; The end synchronization code of the output even field pre - blanking front porch EAV3 = 8'hB6; The end synchronization code of the output odd field blanking back porch EAV4 = 8'hF1; The end synchronization code of the output odd field data EAV5 = 8'hDA; The end synchronization code of the output odd field blanking front porch EAV6 = 8'hF1; (4) When 4 < Pixels <= 284, it is in the VBLANKING state: the line blanking state, including: The filling code for odd pixel positions in the line blanking area BLANK_ODD = 8'h10; The filling code for even pixel positions in the line blanking area BLANK_EVEN = 8'h80; (5) When 284 < Pixels <= 288, it is in the SAV state: the start synchronization code state, including: The start synchronization code of the even field blanking back porch SAV1 = 8'hAB; The start synchronization code of the even field data SAV2 = 8'h80; The start synchronization code of the even field pre - blanking front porch SAV3 = 8'hAB; The start synchronization code of the odd field blanking back porch SAV4 = 8'hEC; The start synchronization code of the odd field data SAV5 = 8'hC7; The start synchronization code of the odd field pre - blanking front porch SAV6 = 8'hEC; (6) When 288 < Pixels <= 1728, it is in the DATA state: the picture data encoding state, including: The encoding state of the chrominance component Cb: EVEN; The encoding state of the luminance component Y1: Y_DATA1; The encoding state of the chrominance component Cr: ODD; The encoding state of the luminance component Y2: Y_DATA2; (7) END state: The end state of the picture after 1 frame and 2 fields of scanning is completed, and it will jump back to the WORK state and continuously loop to refresh the encoded picture.

11. The method according to claim 1, characterized in that When the 27M pixel clock pclk generated by the internal PLL of the FPGA is locked, and at this time the I2C configuration timing of GM7121 has been completed, then raise the START_ENCODING flag signal to trigger the operation of GM7121. The specific process is as follows: Step 1: The encoder state machine implemented in the FPGA is in the IDLE state, initialize the pixel pointer Pixels = 0, the line pointer Lines = 0, and the data state of GM7121 is default in the blanking end code state EAV. When START_ENCODING = 1, then jump to Step 2; Step 2: The encoder state machine is in the WORK state. When START_PIXEL=1 is detected, the pixel column pointer Pixels is set to 11'd1, and the first pixel data is printed at the same time: 8'hFF. In addition, the first row flag LINE_1ST is detected to be pulled high in the same clock cycle of pclk. If it is not pulled high, it means that the external analog source input state is abnormal or the EL1883 analysis is abnormal. At this time, the row pointer remains unchanged in the previous state, and GM7121 is driven to give the blanking black level data 8'h10. If LINE_1ST is already pulled high at this time, the row pointer is set to 1; the pixel pointer Pixels accumulates 1 continuously on the falling edge of pclk. When the EAV state is Pixels<=4, the leading code is generated respectively: 8'hff, 8'h00, 8'h00, EAVx. When the pixel pointer Pixels>4, jump to step 3; Step 3: The encoder state machine enters the line blanking area. When the pixel pointer satisfies 5<=Pixels<=283, a fill code 8'h10 is generated when the value of the Pixels pointer is an odd number, and a fill code 8'h80 is generated when the value of the Pixels pointer is an even number. When the pixel pointer satisfies Pixels>=284, jump to step 4; Step 4: The encoder state machine enters the SAV state, and according to the number of lines currently encoded, enters the even field blanking start SAV1, even field data start SAV2, odd field blanking start SAV4, odd field data start SAV5 states, and generates the leading code: 8'hff, 8'h00, 8'h00, SAVx. When the pixel index Pixels>288, jump to step 5; Step 5: The encoder state machine enters the data encoding DATA state. According to the YCbCr422 encoding format, it enters the EVEN state, Y_DATA1 state, ODD state, and Y_DATA2 state in sequence. When it detects that the pixel pointer Pixels>=1728, the data state is transferred to EAV, the line index Lines is increased by 1, the pixel pointer Pixels is set to 1, and the process jumps to step 2. When it is detected that the current number of encoding lines is 625, the encoding of one frame of the image has been completed, the data state datadone is pulled high, and the process jumps to step 2 to determine whether the line pointer should be maintained or set to 2 in the next cycle. This cycle is repeated continuously to continuously refresh the screen to produce a video effect.

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