Display device and method of manufacturing same

Abstract

The invention provides a display device and a method of manufacturing the same. The display device includes a substrate including a main pixel region and an auxiliary pixel region adjacent to the main pixel region; a main transistor over the substrate and overlapping the main pixel region; an auxiliary transistor over the substrate and overlapping the auxiliary pixel region; a lower electrode over the main transistor, connected to the main transistor, and overlapping the main pixel region; a pixel defining layer over the substrate, covering a side portion of the lower electrode, overlapping the auxiliary pixel region, and defining a cutout portion; and an auxiliary lower electrode filling the cutout portion, connected to the auxiliary transistor, and having the same height as the cutout portion.

Description

Technical Field

[0001] Embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0002] An organic light emitting display device may include pixels. Each of the pixels may include a light emitting element. The light emitting element may include an anode, a cathode, and an organic light emitting layer located between the anode and the cathode.

[0003] Adjacent pixels may be separated by a pixel defining layer (or embankment). The pixel defining layer may include or define openings corresponding to pixel allocations, respectively. The area corresponding to the opening may be defined as a light-emitting area, and the other area may be defined as a non-light-emitting area. In order to realize a high-resolution organic light-emitting display device, it may be appropriate to minimize the non-light-emitting area. Summary of the invention

[0004] The embodiment provides a display device with improved display quality.

[0005] The embodiment provides a method of manufacturing a display device.

[0006] A display device according to one or more embodiments includes: a substrate including a main pixel area and an auxiliary pixel area adjacent to the main pixel area; a main transistor above the substrate and overlapping with the main pixel area; an auxiliary transistor above the substrate and overlapping with the auxiliary pixel area; a lower electrode above the main transistor, connected to the main transistor, and overlapping with the main pixel area; a pixel defining layer above the substrate, covering a side of the lower electrode, overlapping with the auxiliary pixel area, and defining a cutout portion; and an auxiliary lower electrode filling the cutout portion, connected to the auxiliary transistor, and having the same height as the cutout portion.

[0007] The auxiliary lower electrode may partially overlap the lower electrode.

[0008] The cutout portion may expose an upper surface of the auxiliary lower electrode.

[0009] The pixel defining layer may include a first portion overlapping the cutout portion and a second portion not overlapping the cutout portion.

[0010] An upper surface of the second portion of the pixel defining layer and an upper surface of the auxiliary lower electrode may be located on the same plane.

[0011] The main pixel region may include a first main pixel region and a second main pixel region spaced apart from the first main pixel region, and the auxiliary pixel region is interposed between the first main pixel region and the second main pixel region.

[0012] The second main pixel region can be separated from the first main pixel region in the first direction, wherein the width of the second portion of the pixel defining layer adjacent to the first main pixel region in the first direction is substantially equal to the width of the second portion of the pixel defining layer adjacent to the second main pixel region in the first direction.

[0013] The lower electrode and the auxiliary lower electrode may include the same material.

[0014] The main pixel regions and the auxiliary pixel regions may be repeatedly and alternately arranged in a plan view.

[0015] Each of the lower electrode and the auxiliary lower electrode may be an anode electrode.

[0016] The display device may further include a light emitting layer over the lower electrode and covering the pixel defining layer.

[0017] The light emitting layer may cover an upper surface of the auxiliary lower electrode.

[0018] The light emitting layer may not contact the side surface of the auxiliary lower electrode.

[0019] The display device may further include an upper electrode over the light emitting layer.

[0020] According to one or more embodiments, a method for manufacturing a display device includes: forming a substrate, the substrate including a main pixel area and an auxiliary pixel area adjacent to the main pixel area; forming a main transistor overlapping the main pixel area above the substrate; forming an auxiliary transistor overlapping the auxiliary pixel area above the substrate; forming a lower electrode connected to the main transistor and overlapping the main pixel area above the main transistor; forming a first preliminary pixel defining layer above the lower electrode; forming an auxiliary lower electrode overlapping the auxiliary pixel area above the first preliminary pixel defining layer; forming a second preliminary pixel defining layer above the first preliminary pixel defining layer and the auxiliary lower electrode; removing a portion of the second preliminary pixel defining layer; and removing a portion of the first preliminary pixel defining layer overlapping the main pixel area and a portion of the second preliminary pixel defining layer overlapping the main pixel area.

[0021] The removing of the portion of the second preliminary pixel defining layer may include removing the second preliminary pixel defining layer up to an upper surface of the auxiliary lower electrode.

[0022] The auxiliary lower electrode may partially overlap the lower electrode.

[0023] Removing the portion of the first preliminary pixel defining layer overlapping the main pixel area and the portion of the second preliminary pixel defining layer overlapping the main pixel area may include forming a pixel defining layer covering a side of the lower electrode and including a first portion overlapping the auxiliary lower electrode and a second portion not overlapping the auxiliary lower electrode.

[0024] The method may further include forming a light emitting layer over the lower electrode, covering the pixel defining layer, covering an upper surface of the auxiliary lower electrode, and not contacting a side surface of the auxiliary lower electrode.

[0025] The method may further include forming an upper electrode on the light emitting layer.

[0026] The display device according to one or more embodiments may include a substrate. The substrate may include a first main pixel area, a second main pixel area, and a first auxiliary pixel area between the first main pixel area and the second main pixel area. The first pixel electrode may be located on the substrate. The first pixel electrode may overlap with the first main pixel area. In addition, the second pixel electrode may be located on the substrate. The second pixel electrode may overlap with the second main pixel area. In addition, a pixel defining layer may be located on the substrate. The pixel defining layer may overlap with the first auxiliary pixel area. The pixel defining layer may define a cutout portion. The auxiliary pixel electrode may fill the cutout portion.

[0027] The first pixel electrode may partially overlap with the auxiliary pixel electrode. Accordingly, the distance between the first main pixel region and the first auxiliary pixel region may be reduced. In addition, the second pixel electrode may partially overlap with the auxiliary pixel electrode. Accordingly, the distance between the second main pixel region and the first auxiliary pixel region may be reduced. Therefore, the resolution of the display device may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a plan view illustrating a display device according to one or more embodiments.

[0030] Figure 2 is along Figure 1 The line I-I' intercepts Figure 1 A cross-sectional view of a display device.

[0031] Figure 3 It is a graphic Figure 2 A cross-sectional view of an XY portion of a display device.

[0032] Figure 4 It is a graphic Figure 1 A plan view of a display device.

[0033] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 It is a graphic manufacturing Figure 1A cross-sectional view of a method for displaying a device. DETAILED DESCRIPTION

[0034] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and their implementation methods. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects of the present disclosure will be fully conveyed to those skilled in the art. Accordingly, redundant, irrelevant or unrelated to the description of the embodiments or processes, elements and techniques that are not necessary for a complete understanding of the aspects of the present disclosure by those of ordinary skill in the art can be omitted. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore their repeated descriptions can be omitted.

[0035] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can", "may" or "may not" in describing the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and alternatives within the scope of the ideas and techniques of the present disclosure. In addition, the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocks and drives in technology are possible. The various embodiments may be implemented independently of each other, or may be implemented together in combination.

[0036] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between illustrated elements, and / or any other characteristic, attribute, property, etc. of an element.

[0037] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are contemplated. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the illustrations of elements, layers, or regions, but will include shape deviations caused by, for example, manufacturing.

[0038] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0039] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "under", "above", "upper side" and the like may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to include different orientations of the device in use or in operation. For example, if the device in the figure is turned over, the element described as "below", "below" or "under" other elements or features will be oriented "above" other elements or features. Therefore, the example terms "below" and "under" may include both upper and lower orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first component is described as being arranged "on" a second component, this means that the first component is arranged on the upper or lower side of the second component, without being limited to being on its upper side based on the direction of gravity.

[0040] In addition, the phrase "in a plan view" refers to when the object portion is observed from above, and the phrase "in a schematic cross-sectional view" refers to when the schematic cross-section taken by vertically cutting the object portion is observed from the side. The term "overlap" or "overlapping" means that the first object can be above or below the second object or on the side of the second object, and vice versa. In addition, the term "overlap" can include stacking, facing, extending thereon, covering or partially covering or any other suitable term that a person of ordinary skill in the art will recognize and understand. The expression "non-overlapping" can include the meaning of any other suitable equivalent such as "separated from..." or "set on the side of..." or "deviation from..." and any other suitable equivalent that a person of ordinary skill in the art will recognize and understand. The term "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, although the first object and the second object are still facing each other, the first object and the second object can be understood to be indirectly opposite to each other.

[0041] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be formed directly on, directly on, directly connected to, or coupled to, or indirectly formed on, indirectly on, indirectly connected to, or coupled to, such that there may be one or more intervening elements, layers, regions, or components. Additionally, this may collectively represent direct or indirect coupling or connection, as well as integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or coupled to, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors and / or capacitors, etc. In describing the embodiments, unless explicitly described as directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on" means that one component is directly connected or coupled to another component or is directly on another component without intervening components.

[0042] For example, in this specification, when a part of a layer, film, zone or plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, zone or plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between parts, such as "between...", "immediately between..." or "adjacent to..." and "directly adjacent to...", can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0043] For the purposes of this disclosure, expressions such as "at least one of" or "any one of" or "one or more of" when following a list of elements modify the entire list of elements without modifying the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of", "a plurality of...", "one of", and other prepositional phrases when preceding or following a list of elements modify the entire list of elements without modifying the individual elements of the list.

[0044] It will be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or segments, these elements, components, regions, layers and / or segments should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, region, area, layer, segment or part from another element, member, component, region, area, layer, segment or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or segment described below can be referred to as the second element, component, region, layer or segment. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish elements of different categories or sets. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first set)", "second category (or second set)", etc.

[0045] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first, second and / or third directions.

[0046] The terms used herein are only used for the purpose of describing the embodiments, and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form "one" is intended to also include the plural form, and the plural form is also intended to include the singular form. It will be further understood that when used in this specification, the terms "include", "have" and "include" and their variants specify the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or combinations thereof.

[0047] When one or more embodiments may be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described successively may be performed substantially simultaneously or in an order opposite to the described order.

[0048] As used herein, the terms "substantially", "approximately", "approximately" and similar terms are used as approximate terms rather than terms of degree, and are intended to illustrate the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "approximately" as used herein include the stated value and mean within an acceptable deviation range of the particular value determined by a person of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0050] Figure 1 is a plan view illustrating a display device according to one or more embodiments.

[0051] refer to Figure 1 , the display device DD may include a display area DA and a non-display area NDA. The display area DA may be defined as an area that emits light. In addition, a component that transmits a signal to the display area DA may be located in the non-display area NDA.

[0052] The main pixel area may be located in the display area DA. For example, the first main pixel area MPX1 and the second main pixel area MPX2 may be located in the display area DA. In one or more embodiments, an auxiliary pixel area may be further provided in the display area DA. The auxiliary pixel area may be adjacent to the main pixel area.

[0053] For example, the first auxiliary pixel area SPX1 may be located in the display area DA. The first auxiliary pixel area SPX1 may be adjacent to the first main pixel area MPX1 in the first direction DR1. In addition, the first auxiliary pixel area SPX1 may be adjacent to the second main pixel area MPX2 in a direction opposite to the first direction DR1. That is, the first auxiliary pixel area SPX1 may be located between the first main pixel area MPX1 and the second main pixel area MPX2.

[0054] The second main pixel region MPX2 may be spaced apart from the first main pixel region MPX1 in the first direction DR1. For example, the second main pixel region MPX2 may be spaced apart from the first main pixel region MPX1 with the first auxiliary pixel region SPX1 interposed therebetween.

[0055] The first main pixel region MPX1 may be a region where the first light emitting element (eg, Figure 2 The first light emitting element LED1) emits light to an area outside the display device DD.

[0056] In addition, the second main pixel region MPX2 may be a region where the second light emitting element (eg, Figure 2 The second light emitting element LED2) in the display device DD emits light to an area outside the display device DD.

[0057] In addition, the first auxiliary pixel region SPX1 may be a region in which an auxiliary light emitting element (eg, Figure 2 An auxiliary light emitting element SLED in the display device DD emits light to an area outside the display device DD.

[0058] The non-display area NDA may be located around the display area DA. For example, the non-display area NDA may surround at least a portion of the display area DA (e.g., in a plan view). A driver may be located in the non-display area NDA. The driver may provide a signal or voltage to each of the main pixel area and the auxiliary pixel area. The driver may include a data driver and a gate driver, etc. The non-display area NDA may not display an image.

[0059] Figure 2 is along Figure 1 The line I-I' intercepts Figure 1 A cross-sectional view of a display device. Figure 3 It is a graphic Figure 2 A cross-sectional view of an XY portion of a display device. Figure 4 It is a graphic Figure 1 A plan view of a display device.

[0060] refer to Figure 2 The display device DD may include a substrate SUB, an insulating layer IL, a passivation layer PVX, a through-hole insulating layer VIA, a first gate insulating layer GI1, a second gate insulating layer GI2, a third gate insulating layer GI3, a first main transistor MT1, a second main transistor MT2, an auxiliary transistor ST, a first pixel electrode PE1, a second pixel electrode PE2, an auxiliary pixel electrode SPE, a first light-emitting layer EML1, a second light-emitting layer EML2, a third light-emitting layer EML3, a first common electrode CE1, a second common electrode CE2, a third common electrode CE3, a pixel defining layer PDL, and an encapsulation layer TFE.

[0061] The substrate SUB may be a silicon substrate. In detail, the substrate SUB may be a p-type silicon substrate or an n-type silicon substrate. In this case, p may represent a hole, and n may represent an electron. The substrate SUB may include a first well region W1, a second well region W2, and a third well region W3.

[0062] The first well region W1 may overlap the first main pixel region MPX1. The first well region W1 may be a p-well or an n-well according to the type of the first main transistor MT1 and the type of the substrate SUB.

[0063] In addition, the second well region W2 may overlap the first auxiliary pixel region SPX1. The second well region W2 may be a p-well or an n-well according to the type of the auxiliary transistor ST and the type of the substrate SUB.

[0064] In addition, the third well region W3 may overlap the second main pixel region MPX2. The third well region W3 may be a p-well or an n-well according to the type of the second main transistor MT2 and the type of the substrate SUB.

[0065] The substrate SUB may include a first source region SA1 and a first drain region DA1. Each of the first source region SA1 and the first drain region DA1 may partially overlap the first main pixel region MPX1.

[0066] In one or more embodiments, the first source region SA1 and the first drain region DA1 may be an n source region and an n drain region, respectively. In one or more other embodiments, the first source region SA1 and the first drain region DA1 may be a p source region and a p drain region, respectively.

[0067] In addition, the substrate SUB may include a second source region SA2 and a second drain region DA2. Each of the second source region SA2 and the second drain region DA2 may partially overlap the first auxiliary pixel region SPX1.

[0068] In one or more embodiments, the second source region SA2 and the second drain region DA2 may be an n source region and an n drain region, respectively. In one or more other embodiments, the second source region SA2 and the second drain region DA2 may be a p source region and a p drain region, respectively.

[0069] In addition, the substrate SUB may include a third source region SA3 and a third drain region DA3. Each of the third source region SA3 and the third drain region DA3 may partially overlap the second main pixel region MPX2.

[0070] In one or more embodiments, the third source region SA3 and the third drain region DA3 may be an n source region and an n drain region, respectively. In one or more other embodiments, the third source region SA3 and the third drain region DA3 may be a p source region and a p drain region, respectively.

[0071] The first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3 may be located on the substrate SUB. The first gate insulating layer GI1 may be located on the first well region W1. In addition, the second gate insulating layer GI2 may be located on the second well region W2. In addition, the third gate insulating layer GI3 may be located on the third well region W3.

[0072] Each of the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3 may include silicon oxide ("SiO x ”), silicon nitride (“SiN x ”), Silicon Carbide (“SiC x ”), silicon oxynitride (“SiO x N y ”) or silicon oxycarbide (“SiO x C y ”), etc. These materials can be used alone or in combination with each other.

[0073] The first gate electrode GE1 may be located on the first gate insulating layer GI1. In addition, the second gate electrode GE2 may be located on the second gate insulating layer GI2. In addition, the third gate electrode GE3 may be located on the third gate insulating layer GI3. Each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like.

[0074] Examples of the metal may include silver ("Ag"), molybdenum ("Mo"), aluminum ("Al"), tungsten ("W"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), or scandium ("Sc"), etc. These materials may be used alone or in combination with each other.

[0075] Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide, etc. In addition, examples of metal nitrides may include aluminum nitride (“AlN x ”), tungsten nitride (“WN x ”) or chromium nitride (“CrN x ”), etc. These materials can be used alone or in combination with each other.

[0076] The insulating layer IL may be located on the substrate SUB. The insulating layer IL may sufficiently cover the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3.

[0077] For example, the insulating layer IL may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide, etc. These materials may be used alone or in combination with each other.

[0078] The first source electrode SE1 and the first drain electrode DE1 may be located on the insulating layer IL. The first source electrode SE1 may be connected to the first source region SA1 through a first contact hole penetrating the insulating layer IL. Also, the first drain electrode DE1 may be connected to the first drain region DA1 through a second contact hole penetrating the insulating layer IL.

[0079] In addition, the second source electrode SE2 and the second drain electrode DE2 may be located on the insulating layer IL. The second source electrode SE2 may be connected to the second source region SA2 through a third contact hole penetrating the insulating layer IL. In addition, the second drain electrode DE2 may be connected to the second drain region DA2 through a fourth contact hole penetrating the insulating layer IL.

[0080] In addition, the third source electrode SE3 and the third drain electrode DE3 may be located on the insulating layer IL. The third source electrode SE3 may be connected to the third source region SA3 through a fifth contact hole penetrating the insulating layer IL. In addition, the third drain electrode DE3 may be connected to the third drain region DA3 through a sixth contact hole penetrating the insulating layer IL.

[0081] The first main transistor MT1 may include a first source area SA1 , a first source electrode SE1 , a first gate electrode GE1 , a first drain area DA1 , and a first drain electrode DE1 .

[0082] In addition, the second main transistor MT2 may include a third source area SA3 , a third source electrode SE3 , a third gate electrode GE3 , a third drain area DA3 , and a third drain electrode DE3 .

[0083] In addition, the auxiliary transistor ST may include a second source area SA2 , a second source electrode SE2 , a second gate electrode GE2 , a second drain area DA2 , and a second drain electrode DE2 .

[0084] In one or more embodiments, each of the first main transistor MT1, the second main transistor MT2, and the auxiliary transistor ST may be a MOSFET. However, the present disclosure is not limited thereto, and in one or more other embodiments, each of the first main transistor MT1, the second main transistor MT2, and the auxiliary transistor ST may be a TFT. In this case, the substrate SUB may be a glass substrate or a polyimide substrate, etc.

[0085] The passivation layer PVX may be on the insulating layer IL. The passivation layer PVX may substantially cover the first source electrode SE1, the second source electrode SE2, the third source electrode SE3, the first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3.

[0086] The passivation layer PVX may include an inorganic insulating material. Examples of materials that can be used as the passivation layer PVX may include silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other.

[0087] The through hole insulating layer VIA may be located on the passivation layer PVX. The through hole insulating layer VIA may include an organic material. For example, the through hole insulating layer VIA may include an organic material such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, siloxane resin or epoxy resin. These materials may be used alone or in combination with each other.

[0088] The first pixel electrode PE1 and the second pixel electrode PE2 may be located on the via hole insulating layer VIA.

[0089] The first pixel electrode PE1 may be connected to the first main transistor MT1. For example, the first pixel electrode PE1 may be connected to the first drain electrode DE1 through a seventh contact hole penetrating the through-hole insulating layer VIA and the passivation layer PVX. The first pixel electrode PE1 may overlap with the first main pixel region MPX1. In one or more embodiments, the first pixel electrode PE1 may partially overlap with the first auxiliary pixel region SPX1.

[0090] The second pixel electrode PE2 may be connected to the second main transistor MT2. For example, the second pixel electrode PE2 may be connected to the third drain electrode DE3 through an eighth contact hole penetrating the through-hole insulating layer VIA and the passivation layer PVX. The second pixel electrode PE2 may overlap the second main pixel region MPX2. In one or more embodiments, the second pixel electrode PE2 may partially overlap the first auxiliary pixel region SPX1.

[0091] Each of the first pixel electrode PE1 and the second pixel electrode PE2 may be referred to as a lower electrode. In addition, each of the first pixel electrode PE1 and the second pixel electrode PE2 may be an anode electrode.

[0092] The pixel defining layer PDL may be located on the first pixel electrode PE1, the second pixel electrode PE2 and the through hole insulating layer VIA. The pixel defining layer PDL may overlap with the first auxiliary pixel region SPX1. In addition, the pixel defining layer PDL may cover the side of the first pixel electrode PE1. In addition, the pixel defining layer PDL may cover the side of the second pixel electrode PE2.

[0093] The pixel defining layer PDL may define a cutout portion COP. The cutout portion COP may be a portion obtained by removing at least a portion of the pixel defining layer PDL from an upper surface of the pixel defining layer PDL. The cutout portion COP may overlap the first auxiliary pixel region SPX1.

[0094] In one or more embodiments, the pixel defining layer PDL may include an organic material. For example, the pixel defining layer PDL may include a photoresist, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin (e.g., a polyacrylic resin) or an epoxy resin, etc. These materials may be used alone or in combination with each other. In one or more other embodiments, the pixel defining layer PDL may include an inorganic material.

[0095] The auxiliary pixel electrode SPE may fill the cutout portion COP and may have the same height as the cutout portion COP. That is, the auxiliary pixel electrode SPE may overlap the first auxiliary pixel region SPX1. The upper surface of the auxiliary pixel electrode SPE may be exposed through the cutout portion COP. The auxiliary pixel electrode SPE may be connected to the auxiliary transistor ST. For example, the auxiliary pixel electrode SPE may be connected to the second drain electrode DE2 through a ninth contact hole penetrating the pixel defining layer PDL, the through-hole insulating layer VIA, and the passivation layer PVX.

[0096] In one or more embodiments, the first pixel electrode PE1, the second pixel electrode PE2 and the auxiliary pixel electrode SPE may include the same material. In one or more other embodiments, the first pixel electrode PE1, the second pixel electrode PE2 and the auxiliary pixel electrode SPE may include different materials. In addition, the auxiliary pixel electrode SPE may be referred to as an auxiliary lower electrode. In addition, the auxiliary pixel electrode SPE may be an anode electrode.

[0097] The first light emitting layer EML1 may be located on the first pixel electrode PE1. The first light emitting layer EML1 may overlap the first main pixel region MPX1. Holes provided by the first pixel electrode PE1 and electrons provided by the first common electrode CE1 may be recombined in the first light emitting layer EML1 to form first excitons. As the first excitons change from an excited state to a ground state, light may be emitted from the first light emitting layer EML1.

[0098] In addition, the second light-emitting layer EML2 may be located on the pixel defining layer PDL. The second light-emitting layer EML2 may overlap with the first auxiliary pixel area SPX1. The second light-emitting layer EML2 may cover the upper surface of the auxiliary pixel electrode SPE. Holes provided by the auxiliary pixel electrode SPE and electrons provided by the second common electrode CE2 may be recombined in the second light-emitting layer EML2 to form second excitons. As the second excitons change from an excited state to a ground state, light may be emitted from the second light-emitting layer EML2.

[0099] In addition, the third light emitting layer EML3 may be located on the second pixel electrode PE2. The third light emitting layer EML3 may overlap with the second main pixel region MPX2. Holes provided by the second pixel electrode PE2 and electrons provided by the third common electrode CE3 may be recombined in the third light emitting layer EML3 to form third excitons. As the third excitons change from an excited state to a ground state, light may be emitted from the third light emitting layer EML3.

[0100] In one or more embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 may be connected to each other. In addition, the second light-emitting layer EML2 and the third light-emitting layer EML3 may be connected to each other. That is, the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may be integrally formed to form a single light-emitting layer. In this case, the light-emitting layer may completely cover the pixel defining layer PDL.

[0101] In one or more other embodiments, the first light emitting layer EML1 and the second light emitting layer EML2 may be separated from each other. In addition, the second light emitting layer EML2 and the third light emitting layer EML3 may be separated from each other.

[0102] The first common electrode CE1 may be located on the first light emitting layer EML1. In addition, the second common electrode CE2 may be located on the second light emitting layer EML2. In addition, the third common electrode CE3 may be located on the third light emitting layer EML3.

[0103] In one or more embodiments, the first common electrode CE1 and the second common electrode CE2 may be connected to each other. In addition, the second common electrode CE2 and the third common electrode CE3 may be connected to each other. That is, the first common electrode CE1, the second common electrode CE2 and the third common electrode CE3 may be integrally formed to form a single common electrode.

[0104] In one or more other embodiments, the first common electrode CE1 and the second common electrode CE2 may be separated from each other. In addition, the second common electrode CE2 and the third common electrode CE3 may be separated from each other.

[0105] Each of the first common electrode CE1, the second common electrode CE2 and the third common electrode CE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide or a transparent conductive material, etc. These materials may be used alone or in combination with each other. Each of the first common electrode CE1, the second common electrode CE2 and the third common electrode CE3 may be referred to as an upper electrode. In addition, each of the first common electrode CE1, the second common electrode CE2 and the third common electrode CE3 may be a cathode electrode.

[0106] The first light emitting element LED1 may include a first pixel electrode PE1, a first light emitting layer EML1 and a first common electrode CE1. The second light emitting element LED2 may include a second pixel electrode PE2, a third light emitting layer EML3 and a third common electrode CE3. The auxiliary light emitting element SLED may include an auxiliary pixel electrode SPE, a second light emitting layer EML2 and a second common electrode CE2.

[0107] The encapsulation layer TFE may be located on the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3. The encapsulation layer TFE may reduce or prevent the possibility of impurities and moisture etc. penetrating into the first light emitting element LED1, the second light emitting element LED2, and the auxiliary light emitting element SLED.

[0108] The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the inorganic layer may include silicon oxide, silicon nitride, silicon oxynitride, etc. These materials may be used alone or in combination with each other. The organic layer may include a polymer cured product such as polyacrylate.

[0109] refer to Figure 3 and Figure 4 , the pixel defining layer PDL may include a first portion PDL1 and a second portion PDL2. The first portion PDL1 may overlap the cutout portion COP. That is, the first portion PDL1 may overlap the auxiliary pixel electrode SPE.

[0110] The second portion PDL2 may not overlap with the cutout portion COP (eg, may not completely overlap). That is, the second portion PDL2 may not overlap with the auxiliary pixel electrode SPE (eg, may not completely overlap). The second portion PDL2 may surround the first portion PDL1.

[0111] The auxiliary pixel electrode SPE may have a first upper surface US1. The first upper surface US1 may be a surface in contact with the second light emitting layer EML2. In addition, the second portion PDL2 may have a second upper surface US2. The second upper surface US2 may be a surface in contact with the second light emitting layer EML2.

[0112] In one or more embodiments, the first upper surface US1 and the second upper surface US2 may be located on the same plane. That is, the width of the cutout portion COP in the third direction DR3 and the width of the auxiliary pixel electrode SPE in the third direction DR3 may be the same.

[0113] In one or more embodiments, the second light emitting layer EML2 may be in contact with the first upper surface US1. In addition, the second light emitting layer EML2 may not be in contact with the side surface of the auxiliary pixel electrode SPE.

[0114] Since the second light-emitting layer EML2 does not contact the side surface of the auxiliary pixel electrode SPE, and since the first upper surface US1 and the second upper surface US2 are located in the same plane, a step may not appear in the portion of the second light-emitting layer EML2 overlapping the side surface of the auxiliary pixel electrode SPE. That is, the thickness of the portion of the second light-emitting layer EML2 overlapping the side surface of the auxiliary pixel electrode SPE in the third direction DR3 may not be reduced (for example, may not change). Therefore, it is possible to reduce or prevent the possibility of a discharge phenomenon due to excessive accumulation of charges in the portion of the second light-emitting layer EML2 and the second common electrode CE2 overlapping the side surface of the auxiliary electrode SPE.

[0115] In one or more embodiments, the first pixel electrode PE1 and the auxiliary pixel electrode SPE may partially overlap. That is, a first overlapping region OR1 in which the first pixel electrode PE1 and the auxiliary pixel electrode SPE overlap may be defined. Accordingly, the distance between the first main pixel region MPX1 and the first auxiliary pixel region SPX1 may be reduced. Accordingly, the resolution of the display device DD may be improved.

[0116] In one or more embodiments, the second pixel electrode PE2 and the auxiliary pixel electrode SPE may partially overlap. That is, a second overlapping region OR2 in which the second pixel electrode PE2 and the auxiliary pixel electrode SPE overlap may be defined. Accordingly, the distance between the first auxiliary pixel region SPX1 and the second main pixel region MPX2 may be reduced. Accordingly, the resolution of the display device DD may be improved.

[0117] In one or more embodiments, a width WH1 of the second portion PDL2 adjacent to the first main pixel region MPX1 in the first direction DR1 and a width WH2 of the second portion PDL2 adjacent to the second main pixel region MPX2 in the first direction DR1 may be substantially the same. That is, a distance between the first main pixel region MPX1 and the first auxiliary pixel region SPX1 (equal to the width WH1) and a distance between the second main pixel region MPX2 and the first auxiliary pixel region SPX1 (equal to the width WH2) may be substantially the same as each other.

[0118] In one or more other embodiments, a width WH1 of the second portion PDL2 adjacent to the first main pixel region MPX1 in the first direction DR1 and a width WH2 of the second portion PDL2 adjacent to the second main pixel region MPX2 in the first direction DR1 may be different.

[0119] In one or more embodiments, in a plan view, the main pixel region and the auxiliary pixel region may be repeatedly and alternately arranged.

[0120] For example, the first auxiliary pixel region SPX1 may be disposed adjacent to the first main pixel region MPX1 in the first direction DR1. In addition, the second main pixel region MPX2 may be disposed adjacent to the first auxiliary pixel region SPX1 in the first direction DR1. Figure 4 As shown in FIG. 1 , the second auxiliary pixel region SPX2 may be disposed adjacent to the second main pixel region MPX2 in the first direction DR1 .

[0121] In addition, the third auxiliary pixel area SPX3 may be disposed adjacent to the first main pixel area MPX1 in a direction opposite to the second direction DR2. In addition, the third main pixel area MPX3 may be disposed adjacent to the third auxiliary pixel area SPX3 in the first direction DR1. That is, the third main pixel area MPX3 may be disposed adjacent to the first auxiliary pixel area SPX1 in a direction opposite to the second direction DR2.

[0122] A pixel electrode including the same material as the first pixel electrode PE1 and the second pixel electrode PE2 and located at the same layer as the first pixel electrode PE1 and the second pixel electrode PE2 may be located in each of the main pixel regions. In addition, an auxiliary pixel electrode including the same material as the auxiliary pixel electrode SPE and located at the same layer as the auxiliary pixel electrode SPE may be located in each of the auxiliary pixel regions.

[0123] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 It is a graphic manufacturing Figure 1 A cross-sectional view of a method for displaying a device.

[0124] refer to Figure 5 , a first well region W1 may be formed in the substrate SUB. The first well region W1 may overlap with the first main pixel region MPX1. In addition, a second well region W2 may be formed in the substrate SUB. The second well region W2 may overlap with the first auxiliary pixel region SPX1. In addition, a third well region W3 may be formed in the substrate SUB. The third well region W3 may overlap with the second main pixel region MPX2.

[0125] A first source region SA1 and a first drain region DA1 may be formed in the substrate SUB. Each of the first source region SA1 and the first drain region DA1 may partially overlap the first main pixel region MPX1.

[0126] In addition, a second source region SA2 and a second drain region DA2 may be formed in the substrate SUB. Each of the second source region SA2 and the second drain region DA2 may partially overlap the first auxiliary pixel region SPX1.

[0127] In addition, a third source region SA3 and a third drain region DA3 may be formed in the substrate SUB. Each of the third source region SA3 and the third drain region DA3 may partially overlap the second main pixel region MPX2.

[0128] A first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3 may be formed on the substrate SUB. The first gate insulating layer GI1 may be formed on the first well region W1. In addition, the second gate insulating layer GI2 may be formed on the second well region W2. In addition, the third gate insulating layer GI3 may be formed on the third well region W3.

[0129] The first gate electrode GE1 may be formed on the first gate insulating layer GI1. In addition, the second gate electrode GE2 may be formed on the second gate insulating layer GI2. In addition, the third gate electrode GE3 may be formed on the third gate insulating layer GI3.

[0130] An insulating layer IL may be formed on the substrate SUB. The insulating layer IL may sufficiently cover the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3.

[0131] A first source electrode SE1 and a first drain electrode DE1 may be formed on the insulating layer IL. The first source electrode SE1 may be connected to the first source region SA1 through a first contact hole penetrating the insulating layer IL. Also, the first drain electrode DE1 may be connected to the first drain region DA1 through a second contact hole penetrating the insulating layer IL.

[0132] In addition, a second source electrode SE2 and a second drain electrode DE2 may be formed on the insulating layer IL. The second source electrode SE2 may be connected to the second source region SA2 through a third contact hole penetrating the insulating layer IL. In addition, the second drain electrode DE2 may be connected to the second drain region DA2 through a fourth contact hole penetrating the insulating layer IL.

[0133] In addition, a third source electrode SE3 and a third drain electrode DE3 may be formed on the insulating layer IL. The third source electrode SE3 may be connected to the third source region SA3 through a fifth contact hole penetrating the insulating layer IL. In addition, the third drain electrode DE3 may be connected to the third drain region DA3 through a sixth contact hole penetrating the insulating layer IL.

[0134] The first main transistor MT1 may include a first source area SA1 , a first source electrode SE1 , a first gate electrode GE1 , a first drain area DA1 , and a first drain electrode DE1 .

[0135] In addition, the second main transistor MT2 may include a third source area SA3 , a third source electrode SE3 , a third gate electrode GE3 , a third drain area DA3 , and a third drain electrode DE3 .

[0136] In addition, the auxiliary transistor ST may include a second source area SA2 , a second source electrode SE2 , a second gate electrode GE2 , a second drain area DA2 , and a second drain electrode DE2 .

[0137] A passivation layer PVX may be formed on the insulating layer IL. The passivation layer PVX may sufficiently cover the first to third source electrodes SE1, SE2, SE3, the first to third drain electrodes DE1, DE2, and DE3.

[0138] refer to Figure 6 , a through hole insulating layer VIA may be formed on the passivation layer PVX. For example, a first pixel electrode PE1 and a second pixel electrode PE2 may be formed on the through hole insulating layer VIA.

[0139] The first pixel electrode PE1 may be connected to the first main transistor MT1. For example, the first pixel electrode PE1 may be connected to the first drain electrode DE1 through a seventh contact hole penetrating the through-hole insulating layer VIA and the passivation layer PVX. The first pixel electrode PE1 may overlap with the first main pixel region MPX1. In one or more embodiments, the first pixel electrode PE1 may partially overlap with the first auxiliary pixel region SPX1.

[0140] The second pixel electrode PE2 may be connected to the second main transistor MT2. For example, the second pixel electrode PE2 may be connected to the third drain electrode DE3 through an eighth contact hole penetrating the through-hole insulating layer VIA and the passivation layer PVX. The second pixel electrode PE2 may overlap the second main pixel region MPX2. In one or more embodiments, the second pixel electrode PE2 may partially overlap the first auxiliary pixel region SPX1.

[0141] refer to Figure 7 , a first preliminary pixel defining layer DLA may be formed on the first pixel electrode PE1 , the through hole insulating layer VIA and the second pixel electrode PE2 .

[0142] refer to Figure 8 , an auxiliary pixel electrode SPE may be formed on the first preliminary pixel defining layer DLA. The auxiliary pixel electrode SPE may overlap the first auxiliary pixel region SPX1.

[0143] The auxiliary pixel electrode SPE may be connected to the auxiliary transistor ST. For example, the auxiliary pixel electrode SPE may be connected to the second drain electrode DE2 through a ninth contact hole penetrating the first preliminary pixel defining layer DLA, the via insulating layer VIA, and the passivation layer PVX.

[0144] refer to Fig. 9 , a second preliminary pixel defining layer DLB may be formed on the first preliminary pixel defining layer DLA and the auxiliary pixel electrode SPE.

[0145] refer to Fig.10 , a portion of the second preliminary pixel defining layer DLB may be removed. In one or more embodiments, the second preliminary pixel defining layer DLB may be removed until the top surface of the auxiliary pixel electrode SPE. For example, the portion of the second preliminary pixel defining layer DLB may be removed by a chemical mechanical polishing process.

[0146] refer to Fig.11 and Fig.12 , the first portion of the first preliminary pixel defining layer DLA and the first portion of the second preliminary pixel defining layer DLB may be removed. Each of the first portion of the first preliminary pixel defining layer DLA and the first portion of the second preliminary pixel defining layer DLB may overlap the first main pixel area MPX1.

[0147] In addition, the second portion of the first and second preliminary pixel defining layers DLA and DLB may be removed. Each of the second portion of the first and second preliminary pixel defining layers DLA and DLB may overlap the second main pixel region MPX2.

[0148] Accordingly, a first pixel defining layer PDLA may be formed. In addition, a second pixel defining layer PDLB located on the first pixel defining layer PDLA may be formed. That is, a pixel defining layer PDL including the first pixel defining layer PDLA and the second pixel defining layer PDLB may be formed. The pixel defining layer PDL may cover the side of the first pixel electrode PE1. In addition, the pixel defining layer PDL may cover the side of the second pixel electrode PE2.

[0149] The pixel defining layer PDL may include a first portion (eg, Figure 3 The first part PDL1) and the second part (for example, Figure 3 The second portion PDL2 of the pixel defining layer PDL may overlap the auxiliary pixel electrode SPE. In addition, the second portion of the pixel defining layer PDL may not overlap the auxiliary pixel electrode SPE.

[0150] refer to Fig.12, a light emitting layer EML may be formed. In detail, a light emitting layer EML may be formed on the first pixel electrode PE1. In addition, a light emitting layer EML may be formed on the second pixel electrode PE2. In addition, the light emitting layer EML may cover the pixel defining layer PDL. In addition, the light emitting layer EML may cover the upper surface of the auxiliary pixel electrode SPE. In addition, the light emitting layer EML may be formed not to contact the side surface of the auxiliary pixel electrode SPE.

[0151] A common electrode CE may be formed on the light emitting layer EML.

[0152] The present disclosure can be applied to various display devices. For example, the present disclosure is applicable to various display devices such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for exhibitions or information transmission, and medical display devices.

[0153] The foregoing is an illustration of the embodiments and should not be construed as limiting them. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the embodiments without substantially departing from the novel teachings and aspects of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the disclosed embodiments, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims, and their functional equivalents will be included therein.

Claims

1. A display device, comprising: A substrate, comprising a main pixel region and an auxiliary pixel region adjacent to the main pixel region; a main transistor, located above the substrate and overlapping the main pixel region; an auxiliary transistor, located above the substrate and overlapping the auxiliary pixel region; a lower electrode, above the main transistor, connected to the main transistor, and overlapping the main pixel region; a pixel defining layer, above the substrate, covering a side of the lower electrode, overlapping the auxiliary pixel region, and defining a cutout portion; as well as An auxiliary lower electrode fills the cutout portion, is connected to the auxiliary transistor, and has the same height as the cutout portion.

2. The display device according to claim 1, wherein: The auxiliary lower electrode partially overlaps the lower electrode.

3. The display device according to claim 1, wherein: The cutout portion exposes an upper surface of the auxiliary lower electrode.

4. The display device according to claim 1, wherein: The pixel defining layer includes a first portion overlapping the cutout portion and a second portion not overlapping the cutout portion.

5. The display device according to claim 4, wherein: An upper surface of the second portion of the pixel defining layer and an upper surface of the auxiliary lower electrode are located on the same plane.

6. The display device according to claim 1, wherein: The main pixel regions and the auxiliary pixel regions are repeatedly and alternately arranged in a plan view.

7. The display device according to any one of claims 1 to 6, wherein: Each of the lower electrode and the auxiliary lower electrode is an anode electrode.

8. A method for manufacturing a display device, comprising: forming a substrate, the substrate comprising a main pixel region and an auxiliary pixel region adjacent to the main pixel region; forming a main transistor overlapping the main pixel region over the substrate; forming an auxiliary transistor over the substrate to overlap the auxiliary pixel region; forming a lower electrode connected to the main transistor and overlapping the main pixel region over the main transistor; forming a first preliminary pixel defining layer above the lower electrode; forming an auxiliary lower electrode overlapping the auxiliary pixel region on the first preliminary pixel defining layer; forming a second preliminary pixel defining layer over the first preliminary pixel defining layer and the auxiliary lower electrode; removing a portion of the second preliminary pixel defining layer; as well as A portion of the first preliminary pixel defining layer overlapping the main pixel region and a portion of the second preliminary pixel defining layer overlapping the main pixel region are removed.

9. The method according to claim 8, wherein: The removing of the portion of the second preliminary pixel defining layer includes removing the second preliminary pixel defining layer up to an upper surface of the auxiliary lower electrode.

10. The method according to claim 9, wherein: The auxiliary lower electrode partially overlaps the lower electrode.

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