Display device

Abstract

A display device includes: a substrate including a display area in which a plurality of sub-pixels are disposed and a non-display area located outside the display area; an insulating laminate on the substrate and having an outer side surface; a cathode on the insulating laminate and disposed to extend from the display area to the non-display area; a first inorganic layer on the cathode and disposed to extend from the display area to the non-display area; an organic layer on a portion of the first inorganic layer and having an outer inclined surface; and a second inorganic layer on the organic layer, disposed to extend from the display area to the non-display area, and disposed to extend along an outer slope of the organic layer, and the limiting part is positioned on the insulating laminated layer and is arranged outside the organic layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0101832, filed on August 3, 2023, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] An embodiment of the present disclosure relates to a display device. Background Art

[0004] The display panel of the display device may include a display area where an image is displayed and a non-display area where no image is displayed. Various structures, circuits, and lines may be disposed in the non-display area (also referred to as a "frame") of the display panel. Due to this fact, it is not easy to reduce the frame of the display panel. Summary of the invention

[0005] Embodiments of the present disclosure may provide a display device having an extremely narrow frame structure.

[0006] Embodiments of the present disclosure may provide a display device having an organic layer overflow prevention structure capable of achieving an extremely narrow frame.

[0007] Embodiments of the present disclosure may provide a display device including an in-panel gate circuit structure capable of achieving an extremely narrow frame.

[0008] Embodiments of the present disclosure may provide a display device having a touch routing structure capable of achieving an extremely narrow frame.

[0009] A display device according to an embodiment of the present disclosure may include: a substrate, including a display area in which a plurality of sub-pixels are arranged and a non-display area located outside the display area; an insulating stack located on the substrate and having an outer side surface in the non-display area; a limiter located on the insulating stack; a cathode located on the insulating stack and extending from the display area to a portion of the non-display area and overlapping with at least a portion of the top surface of the limiter; a first inorganic layer located on the cathode and arranged to extend from the display area to the non-display area; an organic layer located on a portion of the first inorganic layer and having an outer inclined surface; and a second inorganic layer located on the organic layer, arranged to extend from the display area to the non-display area, and arranged to extend along the outer inclined surface of the organic layer.

[0010] The stopper may be disposed in the non-display area and may be located outside the organic layer. The outer side surface of the stopper may have a steeper slope than the inner side surface of the stopper.

[0011] The end of the common middle layer and the end of the cathode may be located on the stopper. The end of the cathode may protrude further outward than the upper layer portion of the outer side surface of the stopper and the end of the common middle layer.

[0012] A display device according to an embodiment of the present disclosure may include: a substrate; an insulating stack on the substrate; a plurality of light emitting elements on the insulating stack; an organic layer on the plurality of light emitting elements; and a stopper disposed outside the organic layer.

[0013] The stopper may be disposed on an outer side of the outermost light emitting element among the plurality of light emitting elements, and the stopper may have a thickness thicker than the anode of the outermost light emitting element.

[0014] According to the embodiments of the present disclosure, a display device having an extremely narrow frame structure can be provided.

[0015] According to the embodiments of the present disclosure, it is possible to provide a display device having an organic layer overflow prevention structure capable of achieving an extremely narrow frame.

[0016] According to the embodiments of the present disclosure, it is possible to provide a display device including a gate circuit structure within a panel that can achieve an extremely narrow frame.

[0017] According to the embodiments of the present disclosure, it is possible to provide a display device having a touch routing structure capable of achieving an extremely narrow frame.

[0018] According to the embodiments of the present disclosure, the weight of the display device can be reduced by having an extremely narrow frame structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0020] Figure 2 A display panel according to an embodiment of the present disclosure is shown.

[0021] Figure 3 A substrate of a display panel according to an embodiment of the present disclosure is shown.

[0022] Figure 4 and Figure 5 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0023] Figure 6 is a cross-sectional view of an outer area of ​​a display panel according to an embodiment of the present disclosure.

[0024] Figure 7 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0025] Figure 8 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0026] Fig. 9 is a plan view illustrating a touch sensor included in a display panel according to an embodiment of the present disclosure.

[0027] Fig.10 A partial area of ​​a touch sensor included in a display panel according to an embodiment of the present disclosure is illustrated in detail as an example.

[0028] Fig.11 A substrate and an encapsulation layer of a display panel according to an embodiment of the present disclosure are shown.

[0029] Fig.12 and Fig.13 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0030] Fig.14 A gate driving circuit of a display device according to an embodiment of the present disclosure is shown.

[0031] Fig.15 A vertical structure of a display panel according to an embodiment of the present disclosure is shown when an in-panel gate circuit is provided on the entire display area of ​​the display panel.

[0032] Fig.16 is a cross-sectional view of a display area of ​​a display panel according to an embodiment of the present disclosure.

[0033] Fig.17 and Fig.18 A vertical structure and a planar structure of a display panel according to an embodiment of the present disclosure are shown when an in-panel gate circuit is provided in a portion of a display region of the display panel.

[0034] Fig.19 is a plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0035] Fig. 20 The corresponding relationship between the sub-pixel circuits and the light-emitting elements in the display panel according to the embodiment of the present disclosure is shown.

[0036] Fig.21 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and the same reference numerals and symbols in the accompanying drawings may be used to represent the same or similar parts, even if they are shown in different drawings from each other. In addition, in the following description of examples or embodiments of the present disclosure, when it is determined that a detailed description of well-known functions and components incorporated herein may make the subject matter in some embodiments of the present disclosure unclear, the description may be omitted. Terms such as "including", "having", "comprising", "constituting", "comprising" and "forming" used herein are generally intended to allow the addition of other components unless these terms are used with the term "only". As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0038] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, quantity, etc. of an element, but is only used to distinguish the corresponding element from other elements.

[0039] When it is mentioned that a first element is “connected or coupled to” a second element, “contacts or overlaps” the second element, etc., it should be interpreted that not only the first element can be “directly connected or coupled to” the second element, or “directly contact or overlaps” the second element, but also a third element can be “interposed” between the first element and the second element, or the first element and the second element can be “connected or coupled to”, “contacts or overlaps”, etc., with each other via a fourth element. Here, the second element can be included in at least one of the two or more elements that are “connected or coupled to”, “contacts or overlaps”, etc., with each other.

[0040] When time relative terms such as "after", "subsequently", "next", "before" are used to describe a process or operation of an element or configuration, or a process or step in an operation, process, or manufacturing method, these terms may be used to describe non-sequential or non-sequential processes or operations unless these terms are used with the terms "directly" or "immediately".

[0041] Furthermore, when any dimension, relative size, etc. is mentioned, it should be considered that even if no relevant description is specified, the numerical value or corresponding information (e.g., level, range, etc.) for the element or feature also includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully includes all meanings of the term "can".

[0042] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0043] Figure 1is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0044] Reference Figure 1 The display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit as a circuit for driving the display panel 110 may include a data driving circuit 120, a gate driving circuit 130, and a display controller 140.

[0045] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111 .

[0046] The substrate 111 of the display panel 110 may include a display area DA capable of displaying an image and a non-display area NDA located outside the display area DA.

[0047] A plurality of sub-pixels SP for displaying an image may be disposed in the display area DA, and the non-display area NDA may include a pad area arranged along a first direction from the display area DA.

[0048] In the display panel 110 according to the embodiment of the present disclosure, the non-display area NDA may be very small. In this specification, the non-display area NDA may also be referred to as a "frame".

[0049] For example, the non-display area NDA may include a first non-display area located outside the display area DA in a first direction, a second non-display area located outside the display area DA in a second direction intersecting the first direction, a third non-display area located outside the display area DA in a direction opposite to the first direction, and a fourth non-display area located outside the display area DA in a direction opposite to the second direction. One or two of the first to fourth non-display areas may include a pad area connected or joined to the data driving circuit 120. Two or three of the first to fourth non-display areas that do not include the pad area may be very small in size.

[0050] For another example, the boundary area between the display area DA and the non-display area NDA may be curved, and thus the non-display area NDA may be located below the display area DA. In this case, when the user views the display device 100 from the front, little or no non-display area NDA is visible to the user.

[0051] Various types of signal lines for driving the plurality of sub-pixels SP may be disposed on the substrate 111 of the display panel 110 .

[0052] The display device 100 according to the embodiment of the present disclosure may be a liquid crystal display device, etc., or may be a self-luminous display device in which the display panel 110 emits light. When the display device 100 according to the embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light emitting element.

[0053] For example, the display device 100 according to the embodiment of the present disclosure may be an organic light-emitting display device that uses an organic light-emitting diode (OLED) to realize a light-emitting element. For another example, the display device 100 according to the embodiment of the present disclosure may be an inorganic light-emitting display device that uses an inorganic-based light-emitting diode to realize a light-emitting element. For another example, the display device 100 according to the embodiment of the present disclosure may be a quantum dot display device that uses quantum dots as self-luminous semiconductor crystals to realize a light-emitting element.

[0054] The structure of each of the plurality of subpixels SP may vary according to the type of the display device 100. For example, when the display device 100 is a self-luminous display device in which each subpixel SP emits light, each subpixel SP may include a self-luminous light emitting element, at least one transistor, and at least one capacitor.

[0055] For example, the various types of signal lines may include a plurality of data lines DL transmitting data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL transmitting gate signals (also referred to as scan signals).

[0056] For example, a plurality of data lines DL and a plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged to extend along a first direction, and each of the plurality of gate lines GL may be arranged to extend along a second direction. The first direction may be a column direction, and the second direction may be a row direction. Alternatively, the first direction may be a row direction, and the second direction may be a column direction. Below, for ease of explanation, it will be described by taking as an example that each of the plurality of data lines DL is arranged in a column direction and each of the plurality of gate lines GL is arranged in a row direction.

[0057] The data driving circuit 120 , which is a circuit for driving the plurality of data lines DL, may output data signals to the plurality of data lines DL.

[0058] The data driving circuit 120 may receive the digital type image data DATA from the display controller 140 , may convert the received image data DATA into an analog type data signal, and may output the data signal to a plurality of data lines DL.

[0059] For example, the data driving circuit 120 can be connected to the display panel 110 in a tape automated bonding (TAB) method, can be connected to a bonding pad of the display panel 110 in a chip on glass (COG) or chip on panel (COP) method, or can be connected to the display panel 110 by being implemented in a chip on film (COF) method.

[0060] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Differently, the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to at least two of the four sides of the display panel 110, depending on a driving method, a panel design method, etc.

[0061] The data driving circuit 120 may be connected to the outside of the display area DA of the display panel 110 , but differently therefrom, may be disposed in the display area DA of the display panel 110 .

[0062] The gate driving circuit 130 , which is a circuit for driving the plurality of gate lines GL, may output gate signals to the plurality of gate lines GL.

[0063] The gate driving circuit 130 may be supplied with a first gate voltage corresponding to an on-level voltage, a second gate voltage corresponding to an off-level voltage, and various gate driving control signals GCS, may generate gate signals, and may supply the generated gate signals to a plurality of gate lines GL.

[0064] In the display device 100 according to an embodiment of the present disclosure, the gate driving circuit 130 may be embedded in the display panel 110 in a gate-in-panel (GIP) type. When the gate driving circuit 130 is a gate-in-panel (GIP) type, the gate driving circuit 130 may be formed on a substrate 111 of the display panel 110 during a manufacturing process of the display panel 110.

[0065] In the display device 100 according to the embodiment of the present disclosure, the gate driving circuit 130 may be disposed in the display area DA of the display panel 110. For example, the gate driving circuit 130 may be disposed in a first partial area in the display area DA (e.g., a left area or a right area in the display area DA). For another example, the gate driving circuit 130 may be disposed in a first partial area in the display area DA (e.g., a left area or a right area in the display area DA) and a second partial area in the display area DA (e.g., a right area or a left area in the display area DA).

[0066] In the present disclosure, the gate driving circuit 130 embedded in the display panel 110 in a gate-in-panel (GIP) type is referred to as a 'gate-in-panel circuit'.

[0067] The display controller 140 , which is a device for controlling the data driving circuit 120 and the gate driving circuit 130 , may control driving timings of the plurality of data lines DL and driving timings of the plurality of gate lines GL.

[0068] The display controller 140 may supply a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120 , and may supply a gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130 .

[0069] The display controller 140 may receive input image data from the host system 150 , and may supply image data DATA to the data driving circuit 120 based on the input image data.

[0070] The display controller 140 may be implemented as a separate component from the data driving circuit 120 , or may be implemented as an integrated circuit by being integrated with the data driving circuit 120 .

[0071] The display controller 140 may be a timing controller used in general display technology, a control device including a timing controller and capable of further performing other control functions, a control device different from a timing controller, or a circuit in a control device. The display controller 140 may be implemented by various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and a processor.

[0072] The display controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, or the like.

[0073] The display controller 140 may send and receive signals to and from the data driving circuit 120 according to at least one predetermined interface. For example, the interface may include a low voltage differential signaling (LVDS) interface, an EPI (embedded clock point-to-point interface), a serial peripheral interface (SPI), etc.

[0074] In order to further provide touch sensing function and image display function, the display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit, and the touch sensing circuit detects whether a touch event has occurred through a touch object such as a finger or a pen or detects a touch position by sensing the touch sensor.

[0075] The touch sensing circuit may include a touch driving circuit and a touch controller. The touch driving circuit generates and outputs touch sensing data by driving and sensing the touch sensor. The touch controller can detect the occurrence of a touch event or detect a touch position using the touch sensing data.

[0076] The touch sensor may include a plurality of touch electrodes and may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes with a touch driving circuit.

[0077] The touch sensor may exist outside the display panel 110 in the form of a touch panel, or may exist inside the display panel 110. In the case where the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor may be referred to as an external type. When the touch sensor is an external type, the touch panel and the display panel 110 may be manufactured separately and combined during an assembly process. The external type touch panel may include a substrate for a touch panel and a plurality of touch electrodes on the substrate for a touch panel.

[0078] When the touch sensor exists inside the display panel 110 , the touch sensor may be formed on the substrate 111 together with signal lines and electrodes related to display driving in a process of manufacturing the display panel 110 .

[0079] The touch driving circuit may supply a touch driving signal to at least one of the plurality of touch electrodes, and may generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0080] The touch sensing circuit may perform touch sensing in a self-capacitance sensing method or a mutual capacitance sensing method.

[0081] In the case where the touch sensing circuit performs touch sensing in a self-capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.). According to the self-capacitance sensing method, each of the plurality of touch electrodes may be used as both a driving touch electrode and a sensing touch electrode. The touch drive circuit may drive all or part of the plurality of touch electrodes, and may sense all or part of the plurality of touch electrodes.

[0082] In the case where the touch sensing circuit performs touch sensing in a mutual capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between the touch electrodes. According to the mutual capacitance sensing method, a plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit may drive the driving touch electrodes and sense the sensing touch electrodes.

[0083] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented as separate devices or may be implemented as a single device. In addition, the touch driving circuit and the data driving circuit 120 may be implemented as separate devices or may be implemented as a single device.

[0084] The display device 100 may further include a power circuit that supplies various types of power to the display driving circuit and / or the touch sensing circuit.

[0085] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal such as a smartphone and a tablet computer or a display or a television (TV) of various sizes. However, the display device 100 according to an embodiment of the present disclosure is not limited thereto and may be a display of various types and sizes capable of displaying information or images.

[0086] The display device 100 according to an embodiment of the present disclosure may further include electronic devices such as a camera (image sensor) and a sensing sensor. For example, the sensing sensor may be a sensor that detects an object or a human body by receiving light such as infrared light, ultrasonic light, and ultraviolet light.

[0087] Figure 2 A display panel 110 according to an embodiment of the present disclosure is shown.

[0088] Reference Figure 2 The display panel 110 may include a substrate 111 on which a plurality of sub-pixels SP are disposed, and an encapsulation layer 200 on the substrate 111. The encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation component.

[0089] Reference Figure 2 In the case where the display device 100 according to an embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP disposed on the substrate 111 may include a light emitting element ED and a sub-pixel circuit SPC for driving the light emitting element ED.

[0090] Reference Figure 2 , the sub-pixel circuit SPC may include a plurality of pixel driving transistors for driving the light emitting element ED and at least one capacitor. In the present disclosure, the sub-pixel circuit SPC may drive the light emitting element ED by supplying a driving current to the light emitting element ED at a predetermined timing. The light emitting element ED may be driven by the driving current to emit light.

[0091] The plurality of pixel driving transistors may include a driving transistor DT for driving the light emitting element ED and a scanning transistor ST which is turned on or off according to a scanning signal SC.

[0092] The driving transistor DT may supply a driving current to the light emitting element ED.

[0093] The scan transistor ST may be configured to control an electrical state of a corresponding node in the sub-pixel circuit SPC or to control a state or operation of the drive transistor DT.

[0094] The at least one capacitor may include a storage capacitor Cst for maintaining a constant voltage during a frame.

[0095] To drive the subpixel SP, a data signal VDATA as an image signal, a scan signal SC as a gate signal, etc. may be applied to the subpixel SP. In addition, to drive the subpixel SP, a common pixel driving voltage including a first common driving voltage VDD and a second common driving voltage VSS may be applied to the subpixel SP.

[0096] The light emitting element ED may include an anode AND, a light emitting element intermediate layer EL, and a cathode CAT. The light emitting element intermediate layer EL may be disposed between the anode AND and the cathode CAT.

[0097] In the case where the light emitting element ED is an organic light emitting element, the light emitting element intermediate layer EL may include a light emitting layer EML, a first common intermediate layer COM1 between the anode AND and the light emitting layer EML, and a second common intermediate layer COM2 between the light emitting layer EML and the cathode CAT. The light emitting layer EML may be disposed in each sub-pixel SP. In contrast, the first common intermediate layer COM1 and the second common intermediate layer COM2 may be disposed together in a plurality of sub-pixels SP. The light emitting layer EML may be disposed in each light emitting region, and the first common intermediate layer COM1 and the second common intermediate layer COM2 may be disposed together in a plurality of light emitting regions and non-light emitting regions. The first common intermediate layer COM1 and the second common intermediate layer COM2 are collectively referred to as a common intermediate layer EL_COM.

[0098] For example, the first common intermediate layer COM1 may include a hole injection layer (HIL) and a hole transport layer (HTL). The second common intermediate layer COM2 may include an electron transport layer (ETL) and an electron injection layer (EIL). The hole injection layer may inject holes from the anode into the hole transport layer, and the hole transport layer may transport holes to the light-emitting layer EML. The electron injection layer may inject electrons from the cathode CAT into the electron transport layer, and the electron transport layer may transport electrons to the light-emitting layer EML.

[0099] For example, the cathode CAT may be electrically connected to a second common driving voltage line VSSL. A second common driving voltage VSSS (as a common pixel driving voltage) may be applied to the cathode CAT through the second common driving voltage line VSSL. The anode AND may be electrically connected to a first node N1 of a driving transistor DT of each sub-pixel SP. In the present disclosure, the second common driving voltage VSS may also be referred to as a base voltage VSS, and the second common driving voltage line VSSL may also be referred to as a base voltage line VSSL.

[0100] For example, the anode AND may be a pixel electrode provided in each sub-pixel SP, and the cathode CAT may be a common electrode provided in a plurality of sub-pixels SP. For another example, the cathode CAT may be a pixel electrode provided in each sub-pixel SP, and the anode AND may be a common electrode provided in a plurality of sub-pixels SP. Hereinafter, for ease of explanation, it is assumed that the anode AND is a pixel electrode and the cathode CAT is a common electrode.

[0101] Each light emitting element ED may be composed of an overlapping portion of an anode AND, a light emitting element intermediate layer EL, and a cathode CAT. A predetermined light emitting region may be formed by each light emitting element ED. For example, the light emitting region of each light emitting element ED may include an overlapping region of the anode AND, the light emitting element intermediate layer EL, and the cathode CAT.

[0102] For example, the light emitting element ED may be an organic light emitting diode (OLED), an inorganic-based light emitting diode (LED), or a quantum dot light emitting element. For example, when the light emitting element ED is an organic light emitting diode (OLED), the light emitting element intermediate layer EL in the light emitting element ED may include a light emitting element intermediate layer EL including an organic material.

[0103] The driving transistor DT may be a driving transistor for supplying a driving current to the light emitting element ED. The driving transistor DT may be connected between the first common driving voltage line VDDL and the light emitting element ED.

[0104] The driving transistor DT may include a first node N1 electrically connected to the light emitting element ED, a second node N2 to which the data signal VDATA may be applied, and a third node N3 to which the driving voltage VDD from the first common driving voltage line VDDL may be applied.

[0105] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of explanation, an example will be described in which the second node N2 is a gate node, the first node N1 is a source node, and the third node N3 is a drain node in the driving transistor DT.

[0106] Included in Figure 2 The scan transistor ST in the sub-pixel circuit SPC shown in FIG. 4 may be a switching transistor for transmitting the data signal VDATA, which is an image signal, to the second node N2, which is a gate node of the driving transistor DT.

[0107] The scanning transistor ST may be turned on and off by a scanning signal SC as a gate signal applied through a scanning line SCL (as a kind of gate line GL), and thus, the electrical connection between the second node N2 of the driving transistor DT and the data line DL may be controlled. The drain or source of the scanning transistor ST may be electrically connected to the data line DL, the source or drain of the scanning transistor ST may be electrically connected to the second node N2 of the driving transistor DT, and the gate of the scanning transistor ST may be electrically connected to the scanning line SCL.

[0108] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may include a first capacitor electrode electrically connected to or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the driving transistor DT.

[0109] The storage capacitor Cst may not be a parasitic capacitor (eg, Cgs or Cgd) as an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DT, but an external capacitor intentionally designed outside the driving transistor DT.

[0110] Each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor.

[0111] The display panel 110 may have a top emission structure or a bottom emission structure.

[0112] When the display panel 110 has a top emission structure, at least a portion of the sub-pixel circuit SPC may overlap at least a portion of the light emitting element ED in the vertical direction. In contrast, when the display panel 110 has a bottom emission structure, the sub-pixel circuit SPC may not overlap with the light emitting element ED in the vertical direction.

[0113] like Figure 2 As shown, the sub-pixel circuit SPC may have a 2T (transistor) 1C (capacitor) structure including two transistors DT and ST and one capacitor Cst. Depending on the circumstances, the sub-pixel circuit SPC may further include at least one transistor and may further include at least one capacitor.

[0114] For example, the sub-pixel circuit SPC may have an 8T1C structure including eight transistors and one capacitor. For another example, the sub-pixel circuit SPC may have a 6T2C structure including six transistors and two capacitors. For another example, the sub-pixel circuit SPC may have a 7T1C structure including seven transistors and one capacitor.

[0115] The type and number of gate signals supplied to the sub-pixel SP and the type and number of gate lines may vary according to the structure of the sub-pixel circuit SPC.

[0116] In addition, the type and amount of the common pixel driving voltage supplied to the sub-pixel SP may vary according to the structure of the sub-pixel circuit SPC.

[0117] Because the circuit element in each sub-pixel SP (particularly, the light emitting element ED implemented by an organic light emitting diode (OLED) including an organic material) is susceptible to external moisture or oxygen, an encapsulation layer 200 for preventing external moisture or oxygen from penetrating into the circuit element (particularly, the light emitting element ED) may be provided. The encapsulation layer 200 may be configured in various shapes to prevent the light emitting element ED from contacting moisture or oxygen.

[0118] Reference Figure 2 In order to sense the user's touch, the display device 100 according to an embodiment of the present disclosure may further include a touch sensor layer TSL having a plurality of sensor electrodes, and a touch sensing circuit 210 configured to sense the plurality of sensor electrodes to determine whether a touch event or touch coordinates has occurred.

[0119] The touch sensor layer TSL may be embedded in the display panel 110. For example, the touch sensor layer TSL may be disposed on the encapsulation layer 200 in the display panel 110.

[0120] The display panel 110 not only includes a touch sensor layer TSL, but may also include a plurality of touch pads TP and a plurality of touch routing lines TL, wherein the plurality of touch pads TP are electrically connected to the touch sensing circuit 210, and the plurality of touch routing lines TL are used to electrically connect a plurality of sensor electrodes included in the touch sensor layer TSL and a plurality of touch pads TP connected to the touch sensing circuit 210.

[0121] Meanwhile, the display device 100 according to the embodiment of the present disclosure may have an extremely narrow frame structure in which the non-display area NDA of the display panel 110 is very small or almost non-existent. Next, the extremely narrow frame structure of the display panel 110 of the display device 100 according to the embodiment of the present disclosure will be described.

[0122] Figure 3 A substrate 111 of a display panel 110 according to an embodiment of the present disclosure is shown.

[0123] Reference Figure 3 , the substrate 111 of the display panel 110 according to an embodiment of the present disclosure may include a display area DA where an image may be displayed and a non-display area NDA where no image is displayed.

[0124] Reference Figure 3 , the non-display area NDA may include a first non-display area NDA1 arranged along a first direction from the display area DA, a second non-display area NDA2 arranged along a second direction from the display area DA, a third non-display area NDA3 arranged along a direction opposite to the first direction from the display area DA, and a fourth non-display area NDA4 arranged along a direction opposite to the second direction from the display area DA. For example, the first direction may be a column direction (Y-axis direction), and the second direction intersecting the first direction may be a row direction (X-axis direction).

[0125] Reference Figure 3 , the first non-display area NDA1 may include a pad area PA in which a plurality of pads are disposed.

[0126] In the pad area PA, a plurality of pads electrically connected to the drive circuit may be provided. A plurality of drive circuits or printed circuit boards may be electrically connected. For example, the plurality of pads may include a plurality of display pads and a plurality of touch pads. A plurality of data lines DL, a first common drive voltage line VDDL, and a second common drive voltage line VSSL may be electrically connected to the plurality of display pads. A plurality of touch routing lines TL may be electrically connected to the plurality of touch pads.

[0127] Reference Figure 3 , the first non-display area NDA1 may further include the bending area BA. In this case, the substrate 111 may be a flexible substrate. As the case may be, the first non-display area NDA1 may not include the bending area BA.

[0128] Reference Figure 3 The display panel 110 may further include a ground line disposed in the non-display area NDA of the substrate 111. The ground line may be disposed from one point of the pad area PA to another point of the pad area PA via the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4.

[0129] Reference Figure 3 In the display panel 110 according to the embodiment of the present disclosure, the encapsulation layer 200 may have a structure in which an inorganic layer and an organic layer are stacked. In this case, the edge of the encapsulation layer 200 may be regarded as the edge of the organic layer.

[0130] Reference Figure 3, the display panel 110 according to an embodiment of the present disclosure may include a stopper STP as an organic layer overflow prevention structure for preventing an organic layer included in the encapsulation layer 200 from overflowing.

[0131] Reference Figure 3 , in the display panel 110 according to an embodiment of the present disclosure, the stopper STP may be disposed in the non-display area NDA, and may be disposed in a ring shape surrounding a periphery of the organic layer.

[0132] Reference Figure 3 , the limiting member STP may be located between the display area DA and the pad area PA.

[0133] Reference Figure 3 In the display panel 110 according to the embodiment of the present disclosure, the stopper STP may be disposed in the non-display area NDA. In this way, even if the stopper STP is disposed in the non-display area NDA, the size of the non-display area NDA will not increase due to the presence of the stopper STP.

[0134] In the display panel 110 according to an embodiment of the present disclosure, the stopper STP may have a structure for reducing the non-display area NDA while preventing the organic layer from overflowing.

[0135] Hereinafter, the stopper STP, which serves not only as an organic layer overflow prevention structure capable of preventing an organic layer included in the encapsulation layer 200 from overflowing but also as one of the extremely narrow bezel structures capable of reducing a bezel size, will be described in more detail.

[0136] Figure 4 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure. Figure 4 yes Figure 3 A cross-sectional view of a region 320 including a second non-display area NDA2 in FIG. Figure 3 , a vertical structure of each of the region 330 including the third non-display area NDA3 and the region 340 including the fourth non-display area NDA4 may be the same as a vertical structure of the region 320 including the second non-display area NDA2.

[0137] Reference Figure 4 According to an embodiment of the present disclosure, the display panel 110 may include a substrate 111, an insulating stack INS on the substrate 111, a plurality of light emitting elements ED1, ED2, and ED3 on the insulating stack INS, an organic layer PCL on the plurality of light emitting elements ED1, ED2, and ED3, and a stopper STP disposed on the outside of the organic layer PCL.

[0138] The substrate 111 may include a display area DA and a non-display area NDA, and the non-display area NDA may include a second non-display area NDA2 arranged in a second direction from the display area DA.

[0139] The insulating stack INS may include a plurality of insulating layers between the substrate 111 and the plurality of light emitting elements ED1 , ED2 , and ED3 .

[0140] The insulating stack INS may be located on the substrate 111 and may have an outer side SIDE_INS in the non-display area NDA. The insulating stack INS may include a plurality of insulating layers.

[0141] The insulating stack INS may include a plurality of insulating layers necessary for forming a transistor. The insulating stack INS may include an organic insulating stack including at least one organic insulating layer and an inorganic insulating stack including at least one inorganic insulating layer. For example, the organic insulating stack may include at least one planarization layer, and the inorganic insulating stack may include at least one buffer layer, at least one gate insulating layer, or at least one interlayer insulating layer.

[0142] In order to form a plurality of light emitting elements ED1, ED2 and ED3 on the insulating stack INS, the display panel 110 may include a dam BK located on the insulating stack INS as a sub-pixel defining layer for dividing the plurality of light emitting areas EA1, EA2 and EA3 and having a plurality of openings, a plurality of anodes AND1, AND2 and AND3 located on the insulating stack INS and overlapping with the plurality of openings of the dam BK, a plurality of light emitting layers EML1, EML2 and EML3 located on the plurality of anodes AND1, AND2 and AND3, and a cathode CAT located on the plurality of light emitting layers EML1, EML2 and EML3 and arranged to extend from the display area DA to a portion of the non-display area NDA.

[0143] The plurality of light emitting elements ED1 , ED2 , and ED3 may be configured such that a plurality of anodes AND1 , AND2 , and AND3 , a plurality of light emitting layers EML1 , EML2 , and EML3 , and a cathode CAT overlap.

[0144] Reference Figure 4 The insulating stack INS may include a plurality of insulating layers disposed between the substrate 111 and the plurality of anodes AND1 , AND2 , and AND3 .

[0145] Reference Figure 4 , the display panel 110 according to an embodiment of the present disclosure may include a stopper STP which is not only an organic layer overflow prevention structure but also one of the extremely narrow bezel structures.

[0146] Reference Figure 4The stopper STP may be located on the insulating laminate INS, may be disposed in the non-display area NDA, and may be located outside the organic layer PCL. The cathode CAT may be located on the insulating laminate INS, and may extend from the display area DA to a portion of the non-display area NDA, and overlap at least a portion of the top surface of the stopper STP.

[0147] In the display panel 110 according to an embodiment of the present disclosure, the stopper STP may be disposed outside the third light emitting element ED3 which is the outermost light emitting element ED among the plurality of light emitting elements ED1, ED2, and ED3. The stopper STP may be disposed on the outer side surface of the third light emitting element ED3 which is the outermost light emitting element ED among the plurality of light emitting elements ED1, ED2, and ED3. The stopper STP may be disposed outside the dam BK.

[0148] The stopper STP may include an organic material.

[0149] The stopper STP may have a thickness thicker than the anode AND3 of the third light emitting element ED3 as the outermost light emitting element ED. For example, the stopper STP may have a thickness thicker than the sum of the thicknesses of the anode AND3, the light emitting element intermediate layer EL, and the cathode CAT of the third light emitting element ED3 as the outermost light emitting element ED. The light emitting element intermediate layer EL of the third light emitting element ED3 as the outermost light emitting element ED may include a first common intermediate layer COM1, a third light emitting layer EML3, and a second common intermediate layer COM2.

[0150] For example, in the light emitting areas EA1, EA2 and EA3, the uppermost surface of the stopper STP may be located higher than the top surface of the cathode CAT. Therefore, the cathode CAT may be disposed along the inner side of the stopper STP and extend upward to the top of the stopper STP.

[0151] Reference Figure 4 For example, the plurality of light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 located in a first light emitting area EA1, a second light emitting element ED2 located in a second light emitting area EA2, and a third light emitting element ED3 located in a third light emitting area EA3.

[0152] The first light emitting element ED1 may include a first anode AND1 , a first light emitting element intermediate layer EL, and a cathode CAT, and the first light emitting element intermediate layer EL of the first light emitting element ED1 may include a first common intermediate layer COM1 , a first light emitting layer EML1 , and a second common intermediate layer COM2 .

[0153] The second light emitting element ED2 may include a second anode AND2 , a second light emitting element intermediate layer EL, and a cathode CAT, and the second light emitting element intermediate layer EL of the second light emitting element ED2 may include a first common intermediate layer COM1 , a second light emitting layer EML2 , and a second common intermediate layer COM2 .

[0154] The third light emitting element ED3 may include a third anode AND3 , a third light emitting element intermediate layer EL, and a cathode CAT, and the third light emitting element intermediate layer EL of the third light emitting element ED3 may include a first common intermediate layer COM1 , a third light emitting layer EML3 , and a second common intermediate layer COM2 .

[0155] The first anode AND1 , the second anode AND2 , and the third anode AND3 may be disposed in the first light emitting area EA1 , the second light emitting area EA2 , and the third light emitting area EA3 , respectively.

[0156] The first, second, and third light emitting layers EML1, EML2, and EML3 may be disposed in the first, second, and third light emitting regions EA1, EA2, and EA3, respectively.

[0157] The first common intermediate layer COM1, the second common intermediate layer COM2 and the cathode CAT may be disposed in the entire display area DA and may extend from the display area DA to at least a portion of the non-display area NDA. In the embodiment of the present disclosure, the first common intermediate layer COM1 and the second common intermediate layer COM2 may also be collectively referred to as a common intermediate layer EL_COM.

[0158] Reference Figure 4 , the display panel 110 according to an embodiment of the present disclosure may include a first inorganic layer PAS1 , an organic layer PCL, and a second inorganic layer PAS2 .

[0159] Reference Figure 4 , the first inorganic layer PAS1 may be located on the cathode electrode CAT, and may be disposed to extend from the display area DA to the non-display area NDA including the second non-display area NDA2.

[0160] Reference Figure 4 , the organic layer PCL may be located on a portion of the first inorganic layer PAS1 and may have an outer slope SLP_PCL.

[0161] Reference Figure 4 The second inorganic layer PAS2 may be located on the organic layer PCL, may be disposed to extend from the display area DA to the non-display area NDA, and may be disposed to extend along an outer inclined surface SLP_PCL of the organic layer PCL.

[0162] The first inorganic layer PAS1 , the organic layer PCL, and the second inorganic layer PAS2 may be layers constituting the encapsulation layer 200 .

[0163] The stopper STP may be located on the insulating stack INS and may be disposed outside the organic layer PCL.

[0164] The first inorganic layer PAS1 may extend along the top and the outer side of the stopper STP to the outer side surface SIDE_INS of the insulating stack INS.

[0165] The second inorganic layer PAS2 may extend to the outside of the outer slope SLP_PCL of the organic layer PCL, and may be located on the first inorganic layer PAS1 extending to the outer side surface SIDE_INS of the insulating stack INS along the top and outside of the stopper STP.

[0166] The bank BK may be located on the insulating stack INS and may have a first opening, a second opening, and a third opening. The first opening, the second opening, and the third opening may correspond to the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0167] The first anode AND1 , the second anode AND2 , and the third anode AND3 may be located on the insulating stack INS, and may overlap the first opening, the second opening, and the third opening of the bank BK, respectively.

[0168] The first common intermediate layer COM1 may be commonly disposed on the first anode AND1 , the second anode AND2 , and the third anode AND3 , and may also be disposed on the bank BK.

[0169] The first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may be located on the first common intermediate layer COM1 and may overlap the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3. The first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may correspond to the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3.

[0170] The second common intermediate layer COM2 may be commonly disposed on the first, second, and third light emitting layers EML1, EML2, and EML3, and may also be disposed on the bank BK.

[0171] The common intermediate layer EL_COM including the first common intermediate layer COM1 and the second common intermediate layer COM2 may exist on the bank BK and may be disposed throughout the display area DA. The common intermediate layer EL_COM including the first common intermediate layer COM1 and the second common intermediate layer COM2 may include an organic material.

[0172] The cathode electrode CAT may be located on the second common intermediate layer COM2.

[0173] Reference Figure 4 , the common intermediate layer EL_COM and the cathode CAT may extend to the top of the stopper STP and overlap with at least a portion of the stopper STP.

[0174] For example, the common intermediate layer EL_COM and the cathode CAT may extend to the top and outer side of the stopper STP. When the common intermediate layer EL_COM and the cathode CAT extend further, the common intermediate layer EL_COM and the cathode CAT may pass over the top and outer side of the stopper STP and extend to the outer side SIDE_INS of the insulating stack INS.

[0175] Reference Figure 4 The display panel 110 may further include a cover layer CPL located between the cathode electrode CAT and the first inorganic layer PAS1 and arranged to extend from the display area DA to the non-display area NDA. The cover layer CPL may extend along the top and outside of the stopper STP to the outer side surface SIDE_INS of the insulating stack INS.

[0176] Reference Figure 4 , the common intermediate layer EL_COM, the cathode CAT and the cover layer CPL may be disposed on the outer side SIDE_INS of the insulating stack INS.

[0177] As described above, the limiter STP can be disposed on the outer side surface of the third light-emitting element ED3 which is the outermost light-emitting element ED among the multiple light-emitting elements ED1, ED2 and ED3 corresponding to the multiple sub-pixels SP, and can have a thickness thicker than the third anode AND3 of the third light-emitting element ED3 which is the outermost light-emitting element ED.

[0178] Reference Figure 4 , the bottom surface of the stopper STP may have a larger area than the top surface of the stopper STP. The stopper STP may include a first stopper on the insulating laminate INS and a second stopper on the first stopper. The first stopper may include the same material as the bank BK, and the second stopper may include the same material as the spacer on the bank BK. The bank BK and the spacer may include organic materials.

[0179] Each of the first inorganic layer PAS1 and the second inorganic layer PAS2 may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide.

[0180] For example, the organic layer PCL may be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The organic layer PCL may be applied in a liquid form through an inkjet process, and then, may be formed through a curing process.

[0181] Figure 5 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure, Figure 6 is a cross-sectional view of an outer area of ​​a display panel 110 according to an embodiment of the present disclosure. Figure 6 1 is an enlarged cross-sectional view showing the area where the stopper STP is located.

[0182] and Figure 4 The cross-sectional view is similar to Figure 5 The cross-sectional view of FIG. 1 is a cross-sectional view of a region 320 including the second non-display area NDA2 and the display area DA adjacent thereto.

[0183] Figure 5 The cross-sectional view of Figure 4 The cross-sectional view of FIG. 1 is different only in the shape and structure of the stopper STP and the patterned shape and position of the common intermediate layer EL_COM and the cathode CAT, and is the same as FIG. 1 in all other aspects. Figure 4 Therefore, the following will mainly focus on Figure 4 The differences in the cross-sectional views are described below.

[0184] Reference Figure 5 and Figure 6 , the outer side surface of the stopper STP may be an etched surface. Therefore, the inner side surface and the outer side surface of the stopper STP may have different shapes and slopes.

[0185] Reference Figure 5 and Figure 6 , the outer side surface OS of the stopper STP may have an almost vertical slope, and the inner side surface IS of the stopper STP may have a gentler slope than the outer side surface OS of the stopper STP. In other words, the outer side surface OS of the stopper STP may have a steeper slope than the inner side surface IS of the stopper STP.

[0186] Reference Figure 5 and Figure 6 The stopper STP may include a first stopper STP1 on the insulating laminate INS and a second stopper STP2 on the first stopper STP1.

[0187] The first stopper STP1 may include the same material as the bank BK, and the second stopper STP2 may include the same material as the spacer ( Fig.16In other words, the first stopper STP1 may be located at the same material layer as the bank BK, and the second stopper STP2 may be located at the same material layer as the spacer. The bank BK and the spacer may include organic materials.

[0188] Reference Figure 5 and Figure 6 , the end of the common intermediate layer EL_COM and the end of the cathode CAT may be located on the stopper STP. That is, the common intermediate layer EL_COM and the cathode CAT may terminate at the top of the stopper STP and may not extend to the outer side surface OS of the stopper STP.

[0189] Reference Figure 5 and Figure 6 Although the common intermediate layer EL_COM and the cathode CAT terminate at the top of the stopper STP, the cover layer CPL, the first inorganic layer PAS1 and the second inorganic layer PAS2 may not terminate at the top of the stopper STP and may extend beyond the outer side surface OS of the stopper STP to the outer side surface SIDE_INS of the insulating stack INS.

[0190] Reference Figure 5 and Figure 6 , the second stopper STP2 and the common intermediate layer EL_COM may include organic materials, and the cathode CAT may include inorganic materials. Therefore, during the manufacture of the panel, when the second stopper STP2, the common intermediate layer EL_COM, and the cathode CAT are etched by an etching process (e.g., a dry etching process), the features based on which the second stopper STP2 and the common intermediate layer EL_COM are etched may be different from the features based on which the cathode CAT is etched. Therefore, the end of the cathode CAT may protrude more outward than the outer side surface OS of the second stopper STP2 and the end of the common intermediate layer EL_COM.

[0191] Reference Figure 5 and Figure 6 , an end portion of the common intermediate layer EL_COM may be located above the insulating laminate INS. An end portion of the common intermediate layer EL_COM may overlap with the insulating laminate INS.

[0192] Reference Figure 5 The stopper STP may include a cliff portion STP_CLF having a gentle slope from the top to the outer side surface OS to a point below a predetermined level or to a point where a step exists.

[0193] Reference Figure 5 , a value H2 obtained by summing a height Hc of the cliff portion STP_CLF of the stopper STP and a height H1 of the common intermediate layer EL_COM may be greater than a sum of a thickness of the first inorganic layer PAS1 and a thickness of the second inorganic layer PAS2 .

[0194] For example, a value H2 obtained by summing the height Hc of the cliff portion STP_CLF of the stopper STP and the height H1 of the common intermediate layer EL_COM may be equal to or greater than 1.3 times the sum of the thickness of the first inorganic layer PAS1 and the thickness of the second inorganic layer PAS2 (H2≥(T1+T2)*1.3).

[0195] Reference Figure 5 Since the outer side surface OS of the stopper STP is etched, the width of the bottom surface of the stopper STP may be greater than the width of the top surface of the stopper STP.

[0196] Reference Figure 5 and Figure 6 , the slope of the outer side surface of the cliff portion STP_CLF of the stopper STP can be almost vertical. The height Hc of the cliff portion STP_CLF of the stopper STP can be adjusted according to the dry etching time. The longer the dry etching time, the higher the height Hc of the cliff portion STP_CLF of the stopper STP can be.

[0197] Reference Figure 6 , the lower end of the outer side surface of the first limiting member STP1 may protrude further outward than the upper end of the outer side surface of the second limiting member STP2.

[0198] For example, if the dry etching time is set to be shorter than the first time, only a portion of the outer side surface of the second stopper STP2 may be etched, and the outer side surface of the first stopper STP1 may not be etched. In this case, the cliff height Hc of the stopper STP may correspond to a portion of the thickness of the second stopper STP2.

[0199] For another example, if the dry etching time is set to the first time, the entire outer side surface of the second stopper STP2 may be etched, but the outer side surface of the first stopper STP1 may not be etched. In this case, the cliff height Hc of the stopper STP may be the thickness of the second stopper STP2.

[0200] For another example, if the dry etching time is set to a second time longer than the first time, both the outer side surface of the second stopper STP2 and the outer side surface of the first stopper STP1 can be etched. In this case, the cliff height Hc of the stopper STP can be a value obtained by summing the thickness of the second stopper STP2 and the thickness of the first stopper STP1.

[0201] For another example, if the dry etching time is set to be longer than the first time and shorter than the second time, as Figure 6 As shown, the entire outer side surface of the second stopper STP2 may be etched, and only a portion of the outer side surface of the first stopper STP1 may be etched. Figure 6As shown, the cliff height Hc of the stopper STP may be a value obtained by summing the thickness of the second stopper STP2 and the etching depth of the first stopper STP1. In addition, the outer side surface of the first stopper STP1 may protrude further outward than the outer side surface of the second stopper STP2.

[0202] For another example, if the dry etching time is set to be longer than the second time, both the outer side surface of the second stopper STP2 and the outer side surface of the first stopper STP1 may be etched, and a portion of the upper layer portion of the insulating laminate INS may also be etched. In this case, the cliff height Hc of the stopper STP may be a value obtained by summing the thickness of the second stopper STP2, the thickness of the first stopper STP1, and the etching depth of the insulating laminate INS.

[0203] Reference Figure 6 Since the outer side surface OS of the limiting member STP is etched, the width W1 of the bottom surface of the first limiting member STP1 may be greater than the width W2 of the top surface of the second limiting member STP2.

[0204] Figure 7 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure.

[0205] Figure 7 yes Figure 3 FIG. 3 is a cross-sectional view of a region 310 including a first non-display region NDA1 and a display region DA adjacent thereto. Figure 5 The description of the cross-sectional structure with the same features as Figure 6 The differences in cross-sectional structure are described.

[0206] Reference Figure 7 , the first non-display area NDA1 may include a bending area BA and a pad area PA.

[0207] The bending area BA may include a bending layer 730 disposed on the substrate 111. The bending layer 730 may be a bending organic layer including an organic material.

[0208] The pad area PA may include a display pad DP electrically connected to a circuit for display driving (e.g., a data driving circuit) or a printed circuit board. The display pad DP may be electrically connected to a display signal line (e.g., a data line, a first common driving voltage line, or a second common driving voltage line) disposed in the display area DA.

[0209] In the display panel 110 , a display connection line 710 that electrically connects a display signal line (eg, a data line, a first common driving voltage line, or a second common driving voltage line) disposed in the display area DA and a display pad DP may be disposed.

[0210] The display connection line 710 may pass through the bending area BA and extend to the pad area PA. To this end, when the display connection line 710 passes through the bending area BA, the display connection line 710 may pass under the bending layer 730 of the bending area BA.

[0211] The display connection line 710 may overlap the bending layer 730 of the bending area BA. The insulating layer 720 may be disposed between the display connection line 710 and the bending layer 730. The insulating layer 720 may be a layer extending from the display area DA, and may be a layer included in the insulating stack INS.

[0212] The display connection line 710 may include the same material as a source and a drain of a transistor (eg, DT or ST) disposed in the display area DA.

[0213] Alternatively, the display connection line 710 may be composed of a first touch connection pattern comprising the same material as the source and drain of a transistor (e.g., DT or ST) disposed in the display area DA and a second touch connection pattern comprising the same material as the gate or gate line GL of the transistor (e.g., DT or ST).

[0214] The bending layer 730 may be disposed in the bending area BA, and may be disposed to cover a portion of the display connection line 710. The bending layer 730 may prevent the display connection line 710 from being exposed to the outside in the bending area BA where the substrate 111 is bent, and may play a role in protecting the display connection line 710. An opening hole exposing the top of the bending layer 730 may be defined. That is, by removing an inorganic layer (e.g., a first inorganic layer PAS1, a second inorganic layer PAS2, etc.) that may be disposed on the bending layer 730, an opening hole may be formed. In the case where an inorganic layer is disposed on the bending layer 730, when the bending area BA is bent, cracks may be generated in the inorganic layer, and moisture, etc. may penetrate into the inorganic layer that has cracks. Therefore, the inorganic layer defined on the bending layer 730 is removed.

[0215] The pattern protection layer 731 may be disposed to surround the end of the display connection line 710 , thereby protecting the end of the touch connection pattern 1200 disposed at the edge of the first non-display area NDA1 .

[0216] The bending layer 730 and the pattern protection layer 731 may be disposed at the same layer as the planarization layer included in the insulation stack INS, and may be made of the same material as the planarization layer.

[0217] For example, the bending layer 730 and the pattern protection layer 731 may be formed as organic layers made of acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0218] Figure 8 is a cross-sectional view of another display panel 110 according to an embodiment of the present disclosure.

[0219] Reference Figure 8 According to an embodiment of the present disclosure, the display panel 110 may further include a patterned organic material MPL, and the patterned organic material MPL is disposed outside the stopper STP.

[0220] On the outer side SIDE_INS of the insulation stack INS, the patterned organic material MPL may be disposed between the outer side SIDE_INS of the insulation stack INS and the cover layer CPL.

[0221] A patterned organic material MPL may also be disposed on the substrate 111 .

[0222] like Figures 5 to 7 As shown, the cathode electrode CAT only exists on the top portion from the display area DA to the stopper STP, but does not exist on the outer side of the stopper STP.

[0223] The reason why the cathode CAT is disposed in this manner is because the cathode CAT is related to the method of the cathode patterning process.

[0224] The cathode patterning process can be performed as follows.

[0225] The patterned organic material MPL is deposited in an area where the cathode CAT is not provided (ie, an outer area of ​​the stopper STP), and a cathode material is deposited thereon. For example, the patterned organic material MPL may include an organic material. The cathode material may include a magnesium-silver (Mg-Ag) alloy.

[0226] The cathode material may be deposited only in the region where the patterned organic material MPL does not exist. Therefore, the cathode CAT may be formed only in the desired region (region where the patterned organic material MPL does not exist).

[0227] The patterned organic material MPL may have low adhesion properties with metal due to the low surface energy of its material or the high interface energy with the cathode material (metal). Therefore, when the cathode material (metal) is deposited, the probability of the cathode material (metal) being desorbed from the surface of the patterned organic material MPL may be very high. Due to this fact, nucleation of the cathode material (metal) does not occur. Therefore, the cathode material can be deposited only in the area where the patterned organic material MPL does not exist.

[0228] At the same time, if Figure 5 and Figure 7 As shown, the display panel 110 after the manufacturing process is completed may be in a state where the patterned organic material MPL is completely removed.

[0229] In contrast, Figure 8As shown, the display panel 110 that completes the manufacturing process may be in a state where all or a portion of the patterned organic material MPL remains.

[0230] As mentioned above, Figures 5 to 8 As shown, in the display panel 110 according to the embodiment of the present disclosure, the stopper STP as the organic layer overflow prevention structure is not arranged on the side surface of the insulating laminate INS but is arranged on the insulating laminate INS. Thus, it is possible to prevent the frame from increasing due to the presence of the stopper STP (as the organic layer overflow prevention structure). In other words, in the display panel 110 according to the embodiment of the present disclosure, the stopper STP can be not only the organic layer overflow prevention structure but also one of the extremely narrow frame structures.

[0231] exist Figure 4 In the case of the display panel 110, the outer side of the stopper STP is not etched, and the common intermediate layer EL_COM and the cathode CAT are arranged to extend to the outside of the stopper STP. If the common intermediate layer EL_COM, which is an organic layer included in the light emitting element intermediate layer EL, is arranged to extend to the outside of the stopper STP, the characteristics of the common intermediate layer EL_COM may change in the area outside the stopper STP due to external factors. Therefore, if the common intermediate layer EL_COM is arranged to extend to the outside of the stopper STP, there is a possibility that the reliability of the light emitting element ED is likely to deteriorate.

[0232] like Figure 4 As shown, since the outer side surface of the stopper STP is not etched and the common intermediate layer EL_COM and the cathode CAT are configured to extend to the outside of the stopper STP, the frame may be slightly increased.

[0233] In contrast, Figures 5 to 8 In the case of the display panel 110, the outer side surface of the stopper STP is etched, and the common intermediate layer EL_COM and the cathode CAT are not arranged to extend to the outside of the stopper STP.

[0234] Therefore, in Figures 5 to 8 In the case of the display panel 110, when Figure 4 Compared with the display panel 110, the reliability of the light emitting element ED can be relatively increased, and a smaller frame can be formed.

[0235] In the above, the position limiting member STP as an extremely narrow frame structure has been described. Figures 9 to 13 An internal touch routing structure is described as another extremely narrow bezel structure.

[0236] Fig. 9 is a plan view illustrating a touch sensor included in the display panel 110 according to an embodiment of the present disclosure.

[0237] Reference Fig. 9 , the substrate 111 of the display panel 110 according to an embodiment of the present disclosure may include a display area DA where a plurality of sub-pixels SP are provided, and a non-display area NDA which is an outer area of ​​the display area DA.

[0238] Reference Fig. 9 The non-display area NDA may include a first non-display area NDA1 arranged along a first direction from the display area DA, a second non-display area NDA2 arranged along a second direction from the display area DA, a third non-display area NDA3 arranged along a direction opposite to the first direction from the display area DA, and a fourth non-display area NDA4 arranged along a direction opposite to the second direction from the display area DA. The first non-display area NDA1 may include a pad area PA provided with a plurality of touch pads TP.

[0239] Reference Fig. 9 , the display panel 110 according to an embodiment of the present disclosure may include a touch sensor layer TSL disposed on the second inorganic layer PAS2 and including a plurality of sensor electrodes SE disposed in the display area DA. The display panel 110 according to an embodiment of the present disclosure may also include a plurality of touch routing lines TL for electrically connecting the plurality of sensor electrodes SE with the plurality of touch pads TP. The plurality of touch routing lines TL may be regarded as a component included in the touch sensor.

[0240] Reference Fig. 9 , the plurality of sensor electrodes SE may include a first sensor electrode SE1 , a second sensor electrode SE2 , a third sensor electrode SE3 , a fourth sensor electrode SE4 , and a fifth sensor electrode SE5 .

[0241] Each of the first sensor electrode SE1 , the second sensor electrode SE2 , the third sensor electrode SE3 , and the fifth sensor electrode SE5 may extend in a second direction. The second direction may correspond to a direction in which the gate line GL extends.

[0242] The fourth sensor electrode SE4 may extend in a first direction. The first direction may correspond to a direction in which the data line DL extends.

[0243] Reference Fig. 9The multiple touch routing lines TL may include a first touch routing line TL1 for electrically connecting the first sensor electrode SE1 to the first touch pad TP1 set in the pad area PA, a second touch routing line TL2 for electrically connecting the second sensor electrode SE2 to the second touch pad TP2 set in the pad area PA, a third touch routing line TL3 for electrically connecting the third sensor electrode SE3 to the third touch pad TP3 set in the pad area PA, a fourth touch routing line TL4 for electrically connecting the fourth sensor electrode SE4 to the fourth touch pad TP4 set in the pad area PA, and a fifth touch routing line TL5 for electrically connecting the fifth sensor electrode SE5 to the fifth touch pad TP5 set in the pad area PA.

[0244] Reference Fig. 9 , the first touch routing line TL1 , the second touch routing line TL2 , the third touch routing line TL3 , and the fifth touch routing line TL5 may be respectively connected to the sensor electrodes SE1 , SE2 , SE3 , and SE5 extending in the second direction (row direction).

[0245] Reference Fig. 9 , each of the first touch routing line TL1, the second touch routing line TL2, the third touch routing line TL3, and the fifth touch routing line TL5 can extend to the first non-display area NDA1 by passing through the display area DA in the first direction without bypassing the second non-display area NDA2 and the fourth non-display area NDA4. In an embodiment of the present disclosure, the fact that the touch routing line does not bypass the second non-display area NDA2 and the fourth non-display area NDA4 means that the touch routing line does not pass through the second non-display area NDA2 and the fourth non-display area NDA4.

[0246] Reference Fig. 9 The plurality of sensor electrodes SE may include a plurality of transmitting sensor electrodes SE_TX and a plurality of receiving sensor electrodes SE_RX. The plurality of touch routing lines TL may include a plurality of transmitting touch routing lines TL_TX and a plurality of receiving touch routing lines TL_RX. The plurality of touch pads TP may include a plurality of transmitting touch pads TP_TX and a plurality of receiving touch pads TP_RX.

[0247] The touch drive signal output from the touch sensing circuit 210 may be applied to at least one of the plurality of transmission sensor electrodes SE_TX. The touch drive signal may be a signal whose voltage level changes. For example, the touch drive signal may be a pulse signal having a predetermined frequency and amplitude, or may be a signal having various signal waveforms such as a triangular wave, a square wave, or a sine wave.

[0248] Reference Fig. 9, the plurality of transmission sensor electrodes SE_TX and the plurality of reception sensor electrodes SE_RX may be arranged to cross each other. For example, each of the plurality of transmission sensor electrodes SE_TX may be arranged to extend in a first direction. Each of the plurality of reception sensor electrodes SE_RX may be arranged to extend in a second direction different from the first direction.

[0249] The shape of each of the plurality of transmitting sensor electrodes SE_TX and the plurality of receiving sensor electrodes SE_RX may be changed in various ways. For example, each of the plurality of transmitting sensor electrodes SE_TX and the plurality of receiving sensor electrodes SE_RX may be in a bar shape. For another example, each of the plurality of receiving sensor electrodes SE_RX may be composed of a plurality of electrically connected sub-sensor electrodes, or each of the plurality of transmitting sensor electrodes SE_TX may be composed of a plurality of electrically connected sub-sensor electrodes. For example, each of the plurality of sub-sensor electrodes may have various shapes, such as a square, a diamond, or a comb pattern.

[0250] Reference Fig. 9 , the display panel 110 according to an embodiment of the present disclosure may include an internal touch routing structure as an extremely narrow bezel structure.

[0251] The internal touch routing structure may be a structure in which the touch routing line TL is not disposed in the second to fourth non-display areas NDA2 to NDA4 except the first non-display area NDA1 including the pad area PA among the first to fourth non-display areas NDA1 to NDA4.

[0252] According to the internal touch routing structure, among the multiple transmitting touch routing lines TL_TX and the multiple receiving touch routing lines TL_RX, the multiple touch routing lines extending in the column direction (first direction) (for example, the multiple receiving touch routing lines TL_RX) can extend to the pad area PA in the first non-display area NDA1 by passing through the display area DA without bypassing the second non-display area NDA2 to the fourth non-display area NDA4 outside the display area DA.

[0253] For example, among the multiple transmitting touch routing lines TL_TX and the multiple receiving touch routing lines TL_RX, each of the multiple receiving touch routing lines TL_RX extending in the first direction can extend to the pad area PA in the first non-display area NDA1 by passing through the display area DA without bypassing the second non-display area NDA2 to the fourth non-display area NDA4 outside the display area DA.

[0254] When the plurality of receiving touch routing lines TL_RX pass through the display area DA, the plurality of receiving touch routing lines TL_RX may be arranged to bypass the light emitting area of ​​each of the plurality of sub-pixels SP in the display area DA. Therefore, the internal touch routing structure can be designed without reducing the light emitting performance.

[0255] In this case, the plurality of reception touch routing lines TL_RX may intersect the plurality of reception sensor electrodes SE_RX. In other words, the plurality of reception touch routing lines TL_RX may be located in a metal layer different from the plurality of reception sensor electrodes SE_RX and may overlap the plurality of reception sensor electrodes SE_RX.

[0256] According to the internal touch routing structure of the display panel 110 of the embodiment of the present disclosure, the size of the non-display area NDA can be significantly reduced. That is, the sizes of the second non-display area NDA2, the third non-display area NDA3 and the fourth non-display area NDA4 excluding the pad area PA can be significantly reduced.

[0257] Reference Fig. 9 , when the internal touch routing structure of the display panel 110 according to the embodiment of the present disclosure is applied, among the first to fourth non-display areas NDA1 to NDA4, a plurality of touch routing lines TL may be provided in the first non-display area NDA1 including the pad area PA, but a plurality of touch routing lines TL may not be provided in the second to fourth non-display areas NDA2 to NDA4. Therefore, the sizes of the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4 among the first to fourth non-display areas NDA1 to NDA4 may be reduced to the limit.

[0258] Reference Fig. 9 , the plurality of transmitting sensor electrodes SE_TX and the plurality of receiving sensor electrodes SE_RX may include sensor metal.

[0259] A plurality of transmission touch routing lines TL_TX or a plurality of reception touch routing lines TL_RX may intersect a plurality of transmission sensor electrodes SE_TX or a plurality of reception sensor electrodes SE_RX. Therefore, a plurality of transmission touch routing lines TL_TX or a plurality of reception touch routing lines TL_RX may include a bridge metal different from a sensor metal included in a plurality of transmission sensor electrodes SE_TX or a plurality of reception sensor electrodes SE_RX.

[0260] For example, Fig. 9 As shown, among the plurality of transmission touch routing lines TL_TX and the plurality of reception touch routing lines TL_RX, the plurality of reception touch routing lines TL_RX may intersect the plurality of reception sensor electrodes SE_RX while passing through the display area DA.

[0261] In this case, the plurality of reception touch routing lines TL_RX may include a bridge metal different from the sensor metal. At this time, the plurality of transmission touch routing lines TL_TX may include the sensor metal or the bridge metal.

[0262] For another example, among the plurality of transmission touch routing lines TL_TX and the plurality of reception touch routing lines TL_RX, the plurality of transmission touch routing lines TL_TX may intersect with the plurality of transmission sensor electrodes SE_TX while passing through the display area DA. In this case, the plurality of transmission touch routing lines TL_TX may include a bridge metal different from the sensor metal. At this time, the plurality of reception touch routing lines TL_RX may include the sensor metal or the bridge metal.

[0263] Meanwhile, outside the display area DA (i.e., the first non-display area NDA1), the touch routing line TL may be changed from the sensor metal to the bridge metal or from the bridge metal to the sensor metal. Depending on the occasion, a third metal different from the sensor metal and the bridge metal may be used as the metal of a portion of the touch routing line TL.

[0264] Fig.10 A partial area 900 of the touch sensor included in the display panel 110 according to an embodiment of the present disclosure is illustrated in detail as an example. Fig.10 An enlarged view of a unit sensor 1000 in a partial area 900 of the touch sensor is shown. The unit sensor 1000 may refer to an area where one transmitting touch sensor electrode SE_TX and one receiving touch sensor electrode SE_RX intersect.

[0265] Fig.10 yes Fig. 9 900 is an enlarged plan view of a partial area 900 of the touch sensor, and shows that each of the sensor electrodes SE included in the touch sensor has a comb-teeth shape as an example.

[0266] Reference Fig.10 , one sensor electrode SE may be composed of one integrated electrode or may be composed of several electrically connected sub-sensor electrodes.

[0267] Reference Fig.10 ,exist Fig. 9 In the partial area 900 of the touch sensor, the first receiving sensor electrode SE_RX1 and the second receiving sensor electrode SE_RX2 respectively extending in the second direction (e.g., the row direction) may be provided, and the first transmitting sensor electrode SE_TX1, the second transmitting sensor electrode SE_TX2, and the third transmitting sensor electrode SE_TX3 respectively extending in the first direction (e.g., the column direction) may be provided. The first direction and the second direction may be directions intersecting each other.

[0268] Reference Fig.10 ,exist Fig. 9 In the partial area 900 of the touch sensor, a first receiving touch routing line TL_RX1 electrically connected to the first receiving sensor electrode SE_RX1 and a second receiving touch routing line TL_RX2 electrically connected to the second receiving sensor electrode SE_RX2 may be further provided.

[0269] Reference Fig.10 , in the first non-display area NDA1 or in an area adjacent thereto, the first transmission sensor electrode SE_TX1, the second transmission sensor electrode SE_TX2, and the third transmission sensor electrode SE_TX3 may be electrically connected to the first transmission touch routing line TL_TX1, the second transmission touch routing line TL_TX2, and the third transmission touch routing line TL_TX3, respectively.

[0270] Hereinafter, the first receiving sensor electrode SE_RX1 is also referred to as the first sensor electrode SE1, the second receiving sensor electrode SE_RX2 is also referred to as the second sensor electrode SE2, and the first sending sensor electrode SE_TX1 is also referred to as the fourth sensor electrode SE4. In addition, the first receiving touch routing line TL_RX1 is also referred to as the first touch routing line TL1, the second receiving touch routing line TL_RX2 is also referred to as the second touch routing line TL2, and the first sending touch routing line TL_TX1 is also referred to as the fourth touch routing line TL4. The first receiving touch pad TP_RX connected to the first receiving sensor electrode SE_RX1 through the first receiving touch routing line TL_RX1 is also referred to as the first touch pad TP1, the second receiving touch pad TP_RX connected to the second receiving sensor electrode SE_RX2 through the second receiving touch routing line TL_RX2 is also referred to as the second touch pad TP2, and the first sending touch pad TP_RX connected to the first sending sensor electrode SE_TX1 through the first sending touch routing line TL_RX2 is also referred to as the fourth touch pad TP4.

[0271] Similarly, the third receiving sensor electrode SE_RX disposed adjacent to the second receiving sensor electrode SE2 in the first direction is also referred to as the third sensor electrode SE3, and the receiving sensor electrode SE_RX disposed closest to the pad area PA among the plurality of receiving sensor electrodes SE_RX is also referred to as the fifth sensor electrode SE5. The receiving touch routing line TL_RX connected to the third sensor electrode SE3 is also referred to as the third touch routing line TL3, and the receiving touch routing line TL_RX connected to the fifth sensor electrode SE5 is also referred to as the fifth touch routing line TL5. The receiving touch pad TP_RX connected to the third sensor electrode SE3 through the third touch routing line TL3 is also referred to as the third touch pad TP3, and the receiving touch pad TP_RX connected to the fifth sensor electrode SE5 through the fifth touch routing line TL5 is also referred to as the fifth touch pad TP5.

[0272] Each of the first transmission sensor electrode SE_TX1, the second transmission sensor electrode SE_TX2, and the third transmission sensor electrode SE_TX3 may be composed of one integrated electrode. The first reception sensor electrode SE_RX1 may be composed of a plurality of first sub-sensor electrodes SUB1a, SUB1b, SUB1c, and SUB1d electrically connected through the first bridge BRG1. The second reception sensor electrode SE_RX2 may be composed of a plurality of second sub-sensor electrodes SUB2a, SUB2b, SUB2c, and SUB2d electrically connected through the second bridge BRG2.

[0273] The first bridge BRG1 may overlap the first, second, and third transmission sensor electrodes SE_TX1, SE_TX2, and SE_TX3. The second bridge BRG2 may overlap the first, second, and third transmission sensor electrodes SE_TX1, SE_TX2, and SE_TX3.

[0274] Reference Fig.10 , the first transmission sensor electrode SE_TX1 may pass between two first sub sensor electrodes SUB1a and SUB1b included in the first reception sensor electrode SE_RX1 and between two second sub sensor electrodes SUB2a and SUB2b included in the second reception sensor electrode SE_RX2.

[0275] The first bridge BRG1 electrically connecting the two first sub sensor electrodes SUB1a and SUB1b included in the first reception sensor electrode SE_RX1 may overlap the first transmission sensor electrode SE_TX1.

[0276] The second bridge BRG2 electrically connecting the two second sub sensor electrodes SUB2a and SUB2b included in the second reception sensor electrode SE_RX2 may overlap the first transmission sensor electrode SE_TX1.

[0277] Reference Fig.10 , the second transmission sensor electrode SE_TX2 may pass between the two first sub sensor electrodes SUB1b and SUB1c included in the first reception sensor electrode SE_RX1 and between the two second sub sensor electrodes SUB2b and SUB2c included in the second reception sensor electrode SE_RX2.

[0278] The first bridge BRG1 electrically connecting the two first sub sensor electrodes SUB1b and SUB1c included in the first reception sensor electrode SE_RX1 may overlap the second transmission sensor electrode SE_TX2.

[0279] The second bridge BRG2 electrically connecting the two second sub sensor electrodes SUB2b and SUB2c included in the second reception sensor electrode SE_RX2 may overlap the second transmission sensor electrode SE_TX2.

[0280] Reference Fig.10 , the third transmission sensor electrode SE_TX3 may pass between the two first sub sensor electrodes SUB1c and SUB1d included in the first reception sensor electrode SE_RX1 and between the two second sub sensor electrodes SUB2c and SUB2d included in the second reception sensor electrode SE_RX2.

[0281] The first bridge BRG1 electrically connecting the two first sub sensor electrodes SUB1c and SUB1d included in the first reception sensor electrode SE_RX1 may overlap the third transmission sensor electrode SE_TX3.

[0282] The second bridge BRG2 electrically connecting the two second sub sensor electrodes SUB2c and SUB2d included in the second reception sensor electrode SE_RX2 may overlap the third transmission sensor electrode SE_TX3.

[0283] Reference Fig.10 , the first receiving touch routing line TL_RX1 may be electrically connected to at least one (eg, SUB1a) of the plurality of first sub sensor electrodes SUB1a, SUB1b, SUB1c, and SUB1d constituting the first receiving sensor electrode SE_RX1 through the contact hole CNT.

[0284] The second reception touch routing line TL_RX2 may be electrically connected to at least one (eg, SUB2a) of the plurality of second sub sensor electrodes SUB2a, SUB2b, SUB2c, and SUB2d constituting the second reception sensor electrode SE_RX2 through the contact hole CNT.

[0285] Reference Fig.10 , the first transmission sensor electrode SE_TX1 may be electrically connected to the first transmission touch routing line TL_TX1 at a position closest to the first non-display area NDA1. Different from this, the first transmission sensor electrode SE_TX1 may extend to the first non-display area NDA1. A portion of the first transmission sensor electrode SE_TX1 extending to the first non-display area NDA1 may correspond to the first transmission touch routing line TL_TX1.

[0286] The second transmission sensor electrode SE_TX2 may be electrically connected to the second transmission touch routing line TL_TX2 at a position closest to the first non-display area NDA1. Differently, the second transmission sensor electrode SE_TX2 may extend to the first non-display area NDA1. A portion of the second transmission sensor electrode SE_TX2 extending to the first non-display area NDA1 may correspond to the second transmission touch routing line TL_TX2.

[0287] The third transmission sensor electrode SE_TX3 may be electrically connected to the third transmission touch routing line TL_TX3 at a position closest to the first non-display area NDA1. Differently, the third transmission sensor electrode SE_TX3 may extend to the first non-display area NDA1. A portion of the third transmission sensor electrode SE_TX3 extending to the first non-display area NDA1 may correspond to the third transmission touch routing line TL_TX3.

[0288] Reference Fig.10 , the plurality of first sub sensor electrodes SUB1a, SUB1b, SUB1c, and SUB1d included in the first reception sensor electrode SE_RX1 and the plurality of second sub sensor electrodes SUB2a, SUB2b, SUB2c, and SUB2d included in the second reception sensor electrode SE_RX2 may be formed of a sensor metal disposed in a sensor metal layer.

[0289] The first bridge BRG1 and the second bridge BRG2 may be formed of a bridge metal provided in a bridge metal layer which is a metal layer different from the sensor metal layer.

[0290] There may be an insulating layer between the bridge metal layer and the sensor metal layer.

[0291] Reference Fig.10, the first receiving touch routing line TL_RX1 may overlap with the first transmitting sensor electrode SE_TX1 and / or the second receiving sensor electrode SE_RX2 which are disposed in the sensor metal layer and should be electrically separated. Therefore, the first receiving touch routing line TL_RX1 should be disposed in a bridge metal layer different from the sensor metal layer. That is, the first receiving touch routing line TL_RX1 may include a bridge metal.

[0292] The second receiving touch routing line TL_RX2 may overlap with the first transmitting sensor electrode SE_TX1 and / or the first receiving sensor electrode SE_RX1 which are disposed in the sensor metal layer and should be electrically separated. Therefore, the second receiving touch routing line TL_RX2 should be disposed in a bridge metal layer different from the sensor metal layer. In other words, the second receiving touch routing line TL_RX2 may include a bridge metal.

[0293] Reference Fig.10 , the first transmission touch routing line TL_TX1, the second transmission touch routing line TL_TX2, and the third transmission touch routing line TL_TX3 may be set in the sensor metal layer or the bridge metal layer. That is, the first transmission touch routing line TL_TX1, the second transmission touch routing line TL_TX2, and the third transmission touch routing line TL_TX3 may include sensor metal or bridge metal.

[0294] For example, in the first non-display area NDA1, when at least one of the first sending touch routing line TL_TX1, the second sending touch routing line TL_TX2 and the third sending touch routing line TL_TX3 crosses or overlaps with at least one of the first receiving touch routing line TL_RX1 and the second receiving touch routing line TL_RX2, the first sending touch routing line TL_TX1, the second sending touch routing line TL_TX2 and the third sending touch routing line TL_TX3 should be set in a metal layer different from the first receiving touch routing line TL_RX1 and the second receiving touch routing line TL_RX2.

[0295] Therefore, in the first non-display area NDA1, in the case where at least one of the first transmission touch routing line TL_TX1, the second transmission touch routing line TL_TX2, and the third transmission touch routing line TL_TX3 crosses or overlaps at least one of the first reception touch routing line TL_RX1 and the second reception touch routing line TL_RX2, the first transmission touch routing line TL_TX1, the second transmission touch routing line TL_TX2, and the third transmission touch routing line TL_TX3 may be disposed in the sensor metal layer. That is, the first transmission touch routing line TL_TX1, the second transmission touch routing line TL_TX2, and the third transmission touch routing line TL_TX3 may be composed of sensor metal.

[0296] Reference Fig.10 , the first sensor electrode SE1 may include a first bridge BRG1 and at least two of the first sub sensor electrodes SUB1a, SUB1b, SUB1c, and SUB1d arranged along the second direction and electrically connecting the first sub sensor electrodes SUB1a, SUB1b, SUB1c, and SUB1d. For example, the first sensor electrode SE1 may be a first reception sensor electrode SE_RX1.

[0297] Reference Fig.10 , the first touch routing line TL1 may electrically connect the first sensor electrode SE1 and the first touch pad TP1. One point of the first touch routing line TL1 may be electrically connected to at least one of at least two of the first sub sensor electrodes SUB1a, SUB1b, SUB1c, and SUB1d included in the first sensor electrode SE1, and another point of the first touch routing line TL1 may be electrically connected to the first touch pad TP1.

[0298] Reference Fig.10 The second sensor electrode SE2 may include a second bridge BRG2 electrically connecting at least two of the second sub sensor electrodes SUB2a, SUB2b, SUB2c, and SUB2d arranged along the second direction and at least two second sub sensor electrodes SUB2a, SUB2b, SUB2c, and SUB2d. For example, the second sensor electrode SE2 may be a second reception sensor electrode SE_RX2.

[0299] Reference Fig.10 , the second touch routing line TL2 may electrically connect the second sensor electrode SE2 and the second touch pad TP2. One point of the second touch routing line TL2 may be electrically connected to at least one of at least two of the second sub-sensor electrodes SUB2a, SUB2b, SUB2c, and SUB2d included in the second sensor electrode SE2, and another point of the second touch routing line TL2 may be electrically connected to the second touch pad TP2.

[0300] Reference Fig.10 , the fourth sensor electrode SE4 may be disposed to pass between the two first sub sensor electrodes SUB1a and SUB1b included in the first sensor electrode SE1 and between the two second sub sensor electrodes SUB2a and SUB2b included in the second sensor electrode SE2.

[0301] Reference Fig.10 , the fourth sensor electrode SE4 may overlap the first bridge BRG1 and the second bridge BRG2.

[0302] The fourth touch routing line TL4 may electrically connect the fourth touch pad TP4 provided in the pad area PA included in the first non-display area NDA1 and the fourth sensor electrode SE4 provided in the display area DA.

[0303] Reference Fig.10 The sensor electrodes SE1 and SE4 of the touch sensor included in the display panel 110 according to an embodiment of the present disclosure may be a mesh sensor metal formed with an opening OA. The opening OA formed in the sensor electrodes SE1 and SE4 may overlap the light emitting region of the sub-pixel SP.

[0304] In this case, the first touch routing line TL1 connected to the first sensor electrode SE1 and / or the first bridge BRG1 included in the first sensor electrode SE1 may be disposed along the mesh sensor metal constituting the first sensor electrode SE1. In other words, the first bridge BRG1 may be disposed to bend along the mesh sensor metal of the fourth sensor electrode SE4.

[0305] Therefore, the first touch routing line TL1 connected to the first sensor electrode SE1 and / or the first bridge BRG1 included in the first sensor electrode SE1 may overlap the mesh sensor metal constituting the first sensor electrode SE1 .

[0306] Due to this fact, since the opening OA formed in the first and fourth sensor electrodes SE1 and SE4 is not covered by the first touch routing line TL1 and / or the first bridge BRG1 , the light emitting area of ​​the sub-pixel SP may be widened and light emitting efficiency may be improved.

[0307] Fig.11 A substrate 110 and an encapsulation layer 200 of a display panel 110 according to an embodiment of the present disclosure are shown.

[0308] Reference Fig.11 The non-display area NDA may include a first non-display area NDA1 arranged along a first direction from the display area DA, a second non-display area NDA2 arranged along a second direction from the display area DA, a third non-display area NDA3 arranged along a direction opposite to the first direction from the display area DA, and a fourth non-display area NDA4 arranged along a direction opposite to the second direction from the display area DA.

[0309] Reference Fig.11 , the encapsulation layer 200 may be disposed in the display area DA, and may extend to a partial area of ​​the non-display area NDA.

[0310] Reference Fig.11, the encapsulation layer 200 may include a first inclined surface SLP1 located outside in a first direction relative to the center of the encapsulation layer 200, a second inclined surface SLP2 located outside in a second direction intersecting the first direction relative to the center of the encapsulation layer 200, a third inclined surface SLP3 located outside in a direction opposite to the first direction relative to the center of the encapsulation layer 200, and a fourth inclined surface SLP4 located outside in a direction opposite to the second direction relative to the center of the encapsulation layer 200. In this case, the edge of the encapsulation layer 200 may be regarded as an edge of the organic layer PCL, and the first inclined surface SLP1, the second inclined surface SLP2, the third inclined surface SLP3, and the fourth inclined surface SLP4 of the encapsulation layer 200 may be inclined surfaces of the organic layer PCL. The inclinations of the first inclined surface SLP1, the second inclined surface SLP2, the third inclined surface SLP3, and the fourth inclined surface SLP4 of the encapsulation layer 200 may be the inclinations of the organic layer PCL.

[0311] Reference Fig.11 , the first inclined surface SLP1 , the second inclined surface SLP2 , the third inclined surface SLP3 , and the fourth inclined surface SLP4 of the encapsulation layer 200 may be located in the non-display area NDA.

[0312] Reference Fig.11 Among the first slope SLP1, the second slope SLP2, the third slope SLP3 and the fourth slope SLP4 of the encapsulation layer 200, metal (e.g., a touch routing line) is not set on the second slope SLP2 and the fourth slope SLP4, and the touch routing line TL set to extend in the first direction can pass through the first slope SLP1.

[0313] For example, the first touch routing line TL1 may not be disposed on the second and fourth slopes SLP2 and SLP4 but may descend along the first slope SLP1 to be electrically connected to the second touch pad TP2 in the pad area PA.

[0314] The first touch routing line TL1 may extend to the first non-display area NDA1 included in the pad area PA by passing through the display area DA in the first direction without detouring the second non-display area NDA2 and the fourth non-display area NDA4. A portion of the first touch routing line TL1 extending to the first non-display area NDA1 may overlap with the stopper STP in the first non-display area NDA1.

[0315] Fig.12 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure, and is Fig.11 A cross-sectional view of a region 1120 including a second non-display area NDA2 in FIG. Fig.11, a vertical structure of each of the region 1130 including the third non-display area NDA3 and the region 1140 including the fourth non-display area NDA4 may be the same as a vertical structure of the region 1120 including the second non-display area NDA2.

[0316] Reference Fig.12 , the vertical structure of the area including the second non-display area NDA2 and a portion of the display area DA adjacent thereto will be described. To this end, the vertical cross-sectional structure of the area where the first sensor electrode SE1 and the first touch routing line TL1 are connected will be described as an example. In the following description, the vertical cross-sectional structure of the area where the first sensor electrode SE1 and the first touch routing line TL1 are connected will be omitted. Figure 5 The vertical cross-section structure of the same structure is described, and will mainly focus on Figure 5 The differences in the vertical cross-sectional structures are described.

[0317] Reference Fig.12 , the second non-display area NDA2, which is an area (eg, a right area) arranged along the second direction from the display area DA, does not include the bending area BA and the pad area PA.

[0318] Reference Fig.12 , the touch sensor layer TSL may be formed on the encapsulation layer 200 .

[0319] Reference Fig.12 The touch sensor layer TSL may include a touch buffer layer T-BUF on the encapsulation layer 200 , a touch interlayer insulating layer T-ILD on the touch buffer layer T-BUF, and a touch protection layer PAC on the touch interlayer insulating layer T-ILD.

[0320] Reference Fig.12 , the touch sensor layer TSL may include a bridge metal layer between the touch buffer layer T-BUF and the touch interlayer insulating layer T-ILD, and a sensor metal layer between the touch interlayer insulating layer T-ILD and the touch protection layer PAC.

[0321] Reference Fig.12 , the touch buffer layer T-BUF may be omitted. The touch buffer layer T-BUF may be an inorganic buffer layer or an organic buffer layer.

[0322] Reference Fig.12 The touch interlayer insulating layer T-ILD, which is an insulating layer electrically separating the bridge metal layer and the sensor metal layer, may be an organic buffer layer or an inorganic buffer layer.

[0323] Reference Fig.12The touch protection layer PAC can protect the touch sensor by blocking harmful environments from the outside, and can maintain the stability of the characteristics of the display device 100. For example, the touch protection layer PAC can be an organic layer. The touch protection layer PAC can be arranged to extend to the non-display area NDA.

[0324] Reference Fig.12 , the first sensor electrode SE1 disposed in the display area DA and extending in the second direction (eg, the row direction) may be disposed on the encapsulation layer 200 .

[0325] Reference Fig.12 , the first sensor electrode SE1 may include a plurality of first sub sensor electrodes SUB1a and SUB1b and a first bridge BRG1 that electrically connects the plurality of first sub sensor electrodes SUB1a and SUB1b.

[0326] The first bridge BRG1 of the first sensor electrode SE1 extending in the second direction (eg, the row direction) may overlap the fourth sensor electrode SE4 extending in the first direction (eg, the column direction).

[0327] The plurality of first sub sensor electrodes SUB1a and SUB1b included in the first and fourth sensor electrodes SE1 and SE4 may be disposed in the sensor metal layer SML. In other words, the plurality of first sub sensor electrodes SUB1a and SUB1b included in the first and fourth sensor electrodes SE1 and SE4 may include sensor metal.

[0328] The first bridge BRG1 may be provided in the bridge metal layer BML. In other words, the first bridge BRG1 may be made of a bridge metal.

[0329] A first touch routing line TL1 electrically connected to one (eg, SUB1a) of the plurality of first sub sensor electrodes SUB1a and SUB1b included in the first sensor electrode SE1 may be disposed in the bridge metal layer BML. In other words, the first touch routing line TL1 may be made of a bridge metal.

[0330] The first touch routing line TL1 may extend to the first non-display area NDA1 by passing through the display area DA in the first direction without bypassing the second non-display area NDA2 , and may be connected to the first touch pad TP1 included in the pad area PA in the first non-display area NDA1 .

[0331] Therefore, the first touch routing line TL1 may not be disposed on the second slope SLP2 of the encapsulation layer 200 , may extend to the first non-display area NDA1 through the display area DA, and may be disposed along the first slope SLP1 of the encapsulation layer 200 to extend to the pad area PA.

[0332] Reference Fig.12 , when the first touch routing line TL1 passes through the display area DA without bypassing the second non-display area NDA2, the first touch routing line TL1 may be arranged to avoid the light emitting area EA of each of the plurality of sub-pixels SP in the display area DA. That is, the first touch routing line TL1 may not overlap with the light emitting area EA of each of the plurality of sub-pixels SP and may overlap with the bank BK. Therefore, it is possible to design an internal touch routing structure without reducing light emitting performance.

[0333] Reference Fig.12 Not only the first touch routing line TL1 may not overlap with the light emitting area of ​​each of the plurality of sub-pixels SP and may overlap with the embankment BK, but also the first sensor electrode SE1 electrically connected to the first touch routing line TL1 may not overlap with the light emitting area of ​​each of the plurality of sub-pixels SP and may overlap with the embankment BK.

[0334] Fig.13 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure. Fig.13 yes Fig.11 A cross-sectional view of a region 1110 including the first non-display region NDA1 in FIG. Figure 7 The vertical cross-section structure of the same structure is described, and will mainly focus on Figure 7 The differences in the vertical cross-sectional structures are described.

[0335] Reference Fig.13 , the substrate 111 may include a display area DA and a first non-display area NDA1 which is an outer area of ​​the display area DA in the first direction, and the first non-display area NDA1 may include a bending area BA and a pad area PA.

[0336] according to Fig.13 For example, a fifth bridge BRG5 made of a bridge metal may be disposed on the encapsulation layer 200. A touch interlayer insulating layer T-ILD may be disposed on the fifth bridge BRG5. A fourth sensor electrode SE4 made of a sensor metal may be disposed on the touch interlayer insulating layer T-ILD.

[0337] Reference Fig.13 , a portion of the fourth sensor electrode SE4 extending to the first non-display area NDA1 may be a fourth touch routing line TL4. Therefore, the fourth touch routing line TL4 may be made of a sensor metal.

[0338] The fourth touch routing line TL4 may descend along the first inclined surface SLP1 of the encapsulation layer 200 and extend to the pad area PA of the first non-display area NDA1.

[0339] The touch protection layer PAC may be disposed on the sensor electrodes SE including the fourth sensor electrode SE4 and the fifth sensor electrode SE5. The touch protection layer PAC may protect the touch sensor by blocking harmful environments from the outside, and may maintain the stability of the characteristics of the display device 100. For example, the touch protection layer PAC may be an organic layer. The touch protection layer PAC may be disposed to extend to the non-display area NDA.

[0340] The fourth touch routing line TL4 may extend along the first slope SLP1 of the encapsulation layer 200 and may further extend over the stopper STP to be disposed along the outer side SIDE_INS of the insulation laminate INS. The fourth touch routing line TL4 may overlap the organic layer PCL of the encapsulation layer 200 and may overlap the stopper STP.

[0341] Reference Fig.13 , the fourth touch pad TP4 may be disposed in the pad area PA. The fourth touch pad TP4 may be electrically connected to the fourth touch routing line TL4 and may be electrically connected to the touch sensing circuit 210.

[0342] Reference Fig.13 The bending area BA may include a bending layer 730 disposed on the substrate 111 and a touch connection pattern 1200 located under the bending layer 730 and electrically connecting the fourth touch routing line TL4 and the fourth touch pad TP4. An insulating layer 720 may be disposed on the touch connection pattern 1200.

[0343] Reference Fig.13 , the fourth touch routing line TL4 may not be disposed in the bending area BA. Therefore, the fourth touch routing line TL4 may be electrically connected to the fourth touch pad TP4 through the touch connection pattern 1200 disposed in the bending area BA.

[0344] Reference Fig.13 The fourth touch routing line TL4 may be electrically connected to a portion of the touch connection pattern 1200 through the first contact hole CNT1 of the insulating layer 720. The fourth touch pad TP4 may be electrically connected to another portion of the touch connection pattern 1200 through the second contact hole CNT2 of the insulating layer 720.

[0345] Reference Fig.13 , the touch connection pattern 1200 may include the same material as the source region and the drain region of the transistor (eg, DT or ST) disposed in the display area DA.

[0346] The touch connection pattern 1200 may be composed of a first touch connection pattern including the same material as the source and drain of a transistor (eg, DT or ST) disposed in the display area DA and a second touch connection pattern including the same material as the gate or gate line GL of the transistor (eg, DT or ST).

[0347] The bending layer 730 may be disposed in the bending area BA and may be disposed to cover the top of a portion of the touch connection pattern 1200. The bending layer 730 may prevent the touch connection pattern 1200 from being exposed to the outside in the bending area BA where the substrate 111 is bent, and may play a role in protecting the touch connection pattern 1200. An opening hole exposing the top of the bending layer 730 may be defined. That is, an opening hole may be formed by removing an inorganic layer (e.g., a first inorganic layer PAS1, a second inorganic layer PAS2, and a touch interlayer insulating layer T-ILD) that may be disposed on the bending layer 730. In the case where an inorganic layer is disposed on the bending layer 730, cracks may be generated in the inorganic layer when the bending area BA is bent, and moisture or the like may penetrate into the inorganic layer where cracks have been generated. Therefore, the inorganic layer defined on the bending layer 730 is removed.

[0348] The pattern protection layer 731 may be disposed to surround the end portion of the touch connection pattern 1200 , thereby protecting the end portion of the touch connection pattern 1200 disposed at the edge of the first non-display area NDA1 .

[0349] The bending layer 730 and the pattern protection layer 731 may be disposed at the same layer as the planarization layer included in the insulation stack INS, and may be made of the same material as the planarization layer.

[0350] For example, the bending layer 730 and the pattern protection layer 731 may be formed as organic layers made of acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0351] In the above, the limiting member STP and the internal touch routing structure as the extremely narrow frame structure are described. Figures 14 to 21 The gate driving circuit 130 disposed in the display area DA is described as another extremely narrow bezel structure.

[0352] Fig.14 A gate driving circuit 130 of a display device 110 according to an embodiment of the present disclosure is shown.

[0353] Reference Fig.14 , the display panel 110 according to an embodiment of the present disclosure may include an intra-panel gate circuit GIPC configured to supply a gate signal to the plurality of sub-pixels SP and overlap the organic layer PCL of the encapsulation layer 200 .

[0354] Reference Fig.14 , the in-panel gate circuit GIPC is a gate driving circuit 130 embedded in the display panel 110. In other words, the in-panel gate circuit GIPC may be a gate driving circuit 130 of an in-panel gate type.

[0355] Reference Fig.14 The in-panel gate circuit GIPC may include an output buffer 1410 configured to output a gate signal Vout and a control circuit 1420 configured to control the output buffer 1410 .

[0356] The output buffer 1410 may include a pull-up transistor Tu connected between a clock node Nclk to which a clock signal CLK is input and an output node Nout to which a gate signal Vout is output, and a pull-down transistor Td connected between the output node Nout to which a second gate voltage VGL is input and a low voltage node Nvgl.

[0357] The gate signal Vout can be Figure 2 The scanning signal SC.

[0358] The output node Nout may be electrically connected to a gate line GL such as a scan line SCL.

[0359] A gate node of the pull-up transistor Tu may correspond to the Q node. According to a voltage level of the Q node, the pull-up transistor Tu may be turned on or off.

[0360] A gate node of the pull-down transistor Td may correspond to the QB node. The pull-down transistor Td may be turned on or off according to a voltage level of the QB node.

[0361] The voltage level of the Q node and the voltage level of the QB node may be opposite to each other. That is, when the voltage level of the Q node is high, the voltage level of the QB node may be low. When the voltage level of the Q node is low, the voltage level of the QB node may be high.

[0362] Since the voltage level of the Q node and the voltage level of the QB node are opposite to each other, the on-off state of the pull-up transistor Tu and the on-off state of the pull-down transistor Td may be different from each other. That is, when the pull-up transistor Tu is in the on state, the pull-down transistor Td may be in the off state. When the pull-up transistor Tu is in the off state, the pull-down transistor Td may be in the on state.

[0363] The control circuit 1420 may be input with control signals such as a start signal STR and a reset signal RST, and may control a voltage level of the Q node and a voltage level of the QB node.

[0364] The control circuit 1420 may include a plurality of transistors.

[0365] When the voltage level of the Q node is changed to a high level and the voltage level of the QB node is changed to a low level by the control circuit 1420 , the pull-up transistor Tu may be turned on and the gate signal Vout having a high level voltage of the clock signal CLK may be output to the output node Nout.

[0366] When the voltage level of the Q node is changed to a low level and the voltage level of the QB node is changed to a high level by the control circuit 1420, the pull-down transistor Td may be turned on and the gate signal Vout having the second gate voltage VGL corresponding to a low level voltage may be output to the output node Nout.

[0367] The transistors Tu and Td included in the output buffer 1410 and the plurality of transistors included in the control circuit 1420 are referred to as “gate driving transistors.” Meanwhile, the driving transistor DT and the scanning transistor ST included in the sub-pixel circuit SPC are referred to as “pixel driving transistors.”

[0368] Fig.15 1 shows a vertical structure of the display panel 110 according to an embodiment of the present disclosure when the in-panel gate circuit GIPC is provided in the entire display area DA of the display panel 110 .

[0369] Reference Fig.15 , the display panel 110 according to an embodiment of the present disclosure may include a substrate 111 , a basic circuit layer 1510 , a pixel array layer 1530 , and an encapsulation layer 200 .

[0370] Reference Fig.15 , a pixel array layer 1530, which is a layer in which a plurality of sub-pixels SP are formed, may be located over the substrate 111. The pixel array layer 1530 may include a plurality of sub-pixels SP disposed in a display area DA displaying an image.

[0371] Reference Fig.15 The basic circuit layer 1510 may be a layer in which an intra-panel gate circuit GIPC of the gate driving circuit 130 as an intra-panel gate type is formed, and may be located between the substrate 111 and the pixel array layer 1530. That is, the basic circuit layer 1510 may include an intra-panel gate circuit GIPC of the gate driving circuit 130 as an intra-panel gate type.

[0372] For example, the basic circuit layer 1510 may include an intra-panel gate circuit GIPC (see FIG. Fig.15 and Fig.16For another example, the basic circuit layer 1510 may include an intra-panel gate circuit GIPC (see Figures 17 to 21 ).exist Fig.15 and Fig.16 In the description, a case where the in-panel gate circuit GIPC included in the basic circuit layer 1510 is disposed in the entire display area DA will be taken as an example for description.

[0373] Reference Fig.15 , the base circuit layer 1510 may be a layer in which at least two types of power supply lines to which at least two types of common pixel driving voltages to be supplied to the pixel array layer 1530 are applied are formed. That is, the base circuit layer 1510 may also include at least two types of power supply lines to which at least two types of common pixel driving voltages to be supplied to the pixel array layer 1530 are applied.

[0374] For example, at least two types of common pixel driving voltages may include a first common driving voltage VDD and a second common driving voltage VSS supplied to the pixel array layer 1530. At least two types of power lines may include a first common driving voltage line VDDL and a second common driving voltage line VSSL. At least two types of power lines may be electrically connected to a pattern (metal) in the pixel array layer 1530. In addition, at least two types of power lines may include a pattern (metal) in the pixel array layer 1530.

[0375] Reference Fig.15 , the encapsulation layer 200 may be located on the pixel array layer 1530. The encapsulation layer 200 may prevent an organic layer disposed in the pixel array layer 1530 from being exposed to moisture or oxygen.

[0376] As described above, in a conventional display device, the gate driving circuit is connected to the non-display area (border) or formed in the non-display area (border), but in the display device 100 according to an embodiment of the present disclosure, since the intra-panel gate circuit GIPC is set in the display area DA, the size of the non-display area NDA can be significantly reduced.

[0377] Furthermore, in a conventional display device, various power lines are disposed in the non-display area NDA, but in the display device 100 according to an embodiment of the present disclosure, since various power lines are disposed in the display area DA, the size of the non-display area NDA may be further reduced.

[0378] In addition, even if the intra-panel gate circuit GIPC and / or various power lines are disposed in the display area DA, the space for disposing a plurality of sub-pixels SP is not reduced because the intra-panel gate circuit GIPC and / or various power lines are disposed to overlap with the pixel array layer 1530 in the vertical direction. Therefore, even if the aperture ratio of the display area DA of the display panel 110 is not reduced, the size of the non-display area NDA can be reduced.

[0379] Reference Fig.15 According to an embodiment of the present disclosure, the display panel 110 may further include a shielding layer 1520 located between the basic circuit layer 1510 and the pixel array layer 1530 .

[0380] The shielding layer 1520 may shield the electric field between the base circuit layer 1510 and the pixel array layer 1530. Therefore, the base circuit layer 1510 and the pixel array layer 1530 may not generate an undesirable electrical effect on each other.

[0381] Reference Fig.15 In order to improve the shielding performance of the shielding layer 1520 , the shielding layer 1520 may be electrically connected to the power line located in the basic circuit layer 1510 .

[0382] For example, the shielding layer 1520 may be electrically connected to a first power line among at least two types of power lines located in the base circuit layer 1510. The first power line may be a power line to which a first common driving voltage VDD to be supplied to the pixel array layer 1530 is applied. Therefore, the first power line may be electrically connected to a first common driving voltage line VDDL provided in the pixel array layer 1530.

[0383] For another example, the shielding layer 1520 may be electrically connected to a second power line among at least two types of power lines located in the base circuit layer 1510. The second power line may be a power line to which a second common driving voltage VSS to be supplied to the pixel array layer 1530 is applied. Therefore, the second power line may be electrically connected to a second common driving voltage line VSSL provided in the pixel array layer 1530.

[0384] Reference Fig.15 In order to improve the shielding performance of the shielding layer 1520 , the shielding layer 1520 may be electrically connected to the metal located in the pixel array layer 1530 .

[0385] For example, the shielding layer 1520 may be electrically connected to a first metal located in the pixel array layer 1530. The first metal may be a metal to which the first common driving voltage VDD is applied. The first metal as a metal to which the first common driving voltage VDD is applied may be a first common driving voltage line VDDL or a connection pattern connected to the first common driving voltage line VDDL.

[0386] For another example, the shielding layer 1520 may be electrically connected to the second metal in the pixel array layer 1530. The second metal as the metal to which the second common driving voltage VSS is applied may be the second common driving voltage line VSSL or a connection pattern connected to the second common driving voltage line VSSL.

[0387] Reference Fig.15 The shielding layer 1520 can electrically connect the metal located in the pixel array layer 1530 and the metal located in the basic circuit layer 1510 .

[0388] For example, the shielding layer 1520 may electrically connect the first metal located in the pixel array layer 1530 with the first power line located in the base circuit layer 1510. The first metal may be a metal to which the first common driving voltage VDD is applied. The first metal as a metal to which the first common driving voltage VDD is applied may be a first common driving voltage line VDDL or a connection pattern connected to the first common driving voltage line VDDL. The first power line may be a power line to which the first common driving voltage VDD to be supplied to the pixel array layer 1530 is applied.

[0389] In this example, the shielding layer 1520 may be electrically connected to the light emitting element ED included in each of the plurality of sub-pixels SP and a source or drain of one pixel driving transistor among the plurality of pixel driving transistors. Figure 2 , the shielding layer 1520 may be electrically connected to a third node N3 of a driving transistor DT among a plurality of pixel driving transistors included in each of the plurality of sub-pixels SP. The third node N3 of the driving transistor DT may be a drain or a source.

[0390] For another example, the shielding layer 1520 may electrically connect the second metal located in the pixel array layer 1530 with the second power line located in the base circuit layer 1510. The second metal as the metal to which the second common driving voltage VSS is applied may be the second common driving voltage line VSSL or a connection pattern connected to the second common driving voltage line VSSL. The second power line may be a power line to which the second common driving voltage VSS to be supplied to the pixel array layer 1530 is applied.

[0391] In this example case, the shielding layer 1520 may be electrically connected to the cathode CAT of the light emitting element ED included in each of the plurality of sub-pixels SP.

[0392] Reference Fig.15According to an embodiment of the present disclosure, the display panel 110 may include a substrate 111, a pixel array layer 1530 located on the substrate 111 and in which a plurality of sub-pixels SP are arranged in a display area DA for displaying an image, a basic circuit layer 1510 located between the substrate 111 and the pixel array layer 1530, and a shielding layer 1520 located between the basic circuit layer 1510 and the pixel array layer 1530.

[0393] The basic circuit layer 1510 may include an organic layer disposed on a gate driving transistor included in the in-panel gate circuit GIPC. The basic circuit layer 1510 may include at least two types of power lines to which at least two types of common pixel driving voltages to be supplied to the pixel array layer 1530 are applied.

[0394] The shielding layer 1520 may electrically connect a metal disposed in the pixel array layer 1530 and a metal (power supply line) disposed in the base circuit layer 1510 .

[0395] The pixel array layer 1530 may include a sub-pixel circuit layer SPCL in which a plurality of sub-pixel circuits SPC are disposed and a light emitting element layer EDL in which a plurality of light emitting elements ED are disposed.

[0396] Reference Fig.15 , the display panel 110 according to an embodiment of the present disclosure may include an in-panel gate circuit GIPC configured to supply a gate signal to a plurality of sub-pixels SP and overlap the organic layer PCL of the encapsulation layer 200 .

[0397] Reference Fig.15 According to an embodiment of the present disclosure, the display panel 110 may further include a basic circuit layer 1510 on the substrate 111, a light emitting element layer EDL located on the basic circuit layer 1510 and including a plurality of light emitting elements DE included in a plurality of sub-pixels SP, and a shielding layer 1520 located between the basic circuit layer 1510 and the light emitting element layer ELL.

[0398] Reference Fig.15 The sub-pixel circuit layer SPCL may be disposed between the shielding layer 1520 and the light emitting element layer EDL. The sub-pixel circuit layer SPCL and the light emitting element layer EDL may constitute a pixel array layer 1530.

[0399] Reference Fig.15 , the basic circuit layer 1510 may include an in-panel gate circuit GIPC disposed in the display area DA.

[0400] Fig.16 is a cross-sectional view of a display area DA of a display panel 110 according to an embodiment of the present disclosure.

[0401] Reference Fig.16, the display area DA of the display panel 110 may include a substrate 111 , a basic circuit layer 1510 , a shielding layer 1520 , a pixel array layer 1530 and an encapsulation layer 200 .

[0402] The substrate 111 may include a first substrate 1601, an intermediate layer 1602, and a second substrate 1603. The intermediate layer 1602 may be disposed between the first substrate 1601 and the second substrate 1603. For example, at least one of the first substrate 1601 and the second substrate 1603 may be a substrate including polyimide (PI).

[0403] The base circuit layer 1510 may be located on the substrate 111 .

[0404] The base circuit layer 1510 may include a lower shield metal 1605 , a plurality of gate driving transistors Tg constituting the gate driving circuit 130 , and a plurality of insulating layers 1610 , 1620 , and 1621 for forming the plurality of gate driving transistors Tg.

[0405] Each of the plurality of gate driving transistors Tg may include a first active layer ACT1 , a first source A, a first drain B, and a first gate C.

[0406] The plurality of insulating layers 1611 , 1612 , 1620 , and 1621 may include a first buffer layer 1610 , a first gate insulating layer 1620 , and a first interlayer insulating layer 1621 .

[0407] The lower shield metal 1605 may be disposed on the substrate 111 .

[0408] The first buffer layer 1610 may be disposed on the lower shield metal 1605 .

[0409] The first buffer layer 1610 may include a multi-buffer layer 1611 and an active buffer layer 1612. The multi-buffer layer 1611 may be disposed on the lower shield metal 1605, and the active buffer layer 1612 may be disposed on the multi-buffer layer 1611.

[0410] The first active layer ACT1 may be disposed on the active buffer layer 1612 .

[0411] The first gate insulating layer 1620 may be disposed on the first active layer ACT1 , and the first gate C may be disposed on the first gate insulating layer 1620 and may overlap a portion of the first active layer ACT1 .

[0412] A portion of the first active layer ACT1 overlapping the first gate C may be a channel region.

[0413] A first interlayer insulating layer 1621 may be disposed on the first gate C.

[0414] The first source electrode A and the first drain electrode B may be disposed on the first interlayer insulating layer 1621. The first source electrode A may be directly or indirectly connected to the first portion of the first active layer ACT1 through the first hole of the first interlayer insulating layer 1621. The first drain electrode B may be directly or indirectly connected to the second portion of the first active layer ACT1 through the second hole of the first interlayer insulating layer 1621. A region between the first portion and the second portion in the first active layer ACT1 may be a channel region.

[0415] The transistor included in the gate driving circuit 130 is referred to as a gate driving transistor Tg. The transistor included in the gate driving circuit 130 may include a pull-up transistor Tu and a pull-down transistor Td included in the output buffer 1410 , and a plurality of transistors included in the control circuit 1420 .

[0416] In the basic circuit layer 1510, not only the gate driving circuit 130 but also a plurality of power lines PL1 to PLm to which a plurality of pixel driving voltages to be supplied to the pixel array layer 1530 are applied may be provided. The plurality of power lines PL1 to PLm may include a second power line PL2 to which a second driving voltage VSS to be supplied to the pixel array layer 1530 is applied.

[0417] The base circuit layer 1510 may include an intermediate organic layer 1622 disposed on a plurality of gate driving transistors Tg included in the gate driving circuit 130 .

[0418] The intermediate organic layer 1622 may be disposed on the plurality of gate driving transistors Tg and the plurality of power lines PL1 to PLm included in the gate driving circuit 130 to reduce a step in the base circuit layer 1510 .

[0419] In addition, the intermediate organic layer 1622 may reduce unnecessary parasitic capacitance between a metal disposed on the base circuit layer 1510 and a metal disposed in the base circuit layer 1510 .

[0420] A top surface of the middle organic layer 1622 may have a smaller step than a bottom surface of the middle organic layer 1622 .

[0421] The intermediate organic layer 1622 may have a thickness T thicker than a thickness of the first gate insulating layer 1620 between the first gate C of each of the plurality of gate driving transistors Tg and the first active layer ACT1 .

[0422] The shielding layer 1520 may be disposed on the base circuit layer 1510, and the pixel array layer 1530 may be disposed on the shielding layer 1520. That is, the shielding layer 1520 may be located between the base circuit layer 1510 and the pixel array layer 1530. Therefore, the electric field between the base circuit layer 1510 and the pixel array layer 1530 may be shielded.

[0423] The shielding layer 1520 may be electrically connected to a second power line PL2 of one of the at least two types of power lines PL1 to PLm through the hole of the middle organic layer 1622. The second power line PL2 may be a power line to which the second driving voltage VSS is applied.

[0424] The plurality of power lines PL1 to PLm disposed in the base circuit layer 1510 may include the same material as the first source A and the first drain B of the gate driving transistor Tg.

[0425] The pixel array layer 1530 may include a plurality of pixel driving transistors Tp, a plurality of storage capacitors Cst, and a plurality of light emitting elements ED.

[0426] The pixel array layer 1530 may include a second buffer layer 1630, a second interlayer insulating layer 1631, a third interlayer insulating layer 1632, a second gate insulating layer 1633, a fourth interlayer insulating layer 1634, a planarization layer 1640, a bank BK, and a spacer SPCR. The planarization layer 1640 may include a first planarization layer 1641 and a second planarization layer 1642.

[0427] Each of the plurality of pixel driving transistors Tp may include a second active layer ACT2 , a second source electrode D, a second drain electrode E, and a second gate electrode F.

[0428] Each of the plurality of storage capacitors Cst may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2 .

[0429] Each of the plurality of light emitting elements ED may include an anode AND1 or AND2 , an element intermediate layer EL, and a cathode CAT.

[0430] The second buffer layer 1630 may be disposed on the shielding layer 1520 .

[0431] The first capacitor electrode PLT1 may be disposed on the second buffer layer 1630 , the second interlayer insulating layer 1631 may be disposed on the first capacitor electrode PLT1 , and the second capacitor electrode PLT2 may be disposed on the second interlayer insulating layer 1631 .

[0432] The first capacitor electrode PLT1 and the second capacitor electrode PLT2 may overlap each other to constitute a storage capacitor Cst.

[0433] A third interlayer insulating layer 1632 may be disposed on the second capacitor electrode PLT2 .

[0434] The second active layer ACT2 may be disposed on the third interlayer insulating layer 1632 .

[0435] The second gate insulating layer 1633 may be disposed on the second active layer ACT2, and the second gate F may be disposed on the second gate insulating layer 1633. The second gate F may overlap a portion of the second active layer ACT2. The portion of the second active layer ACT2 overlapping the second gate F may be a channel region.

[0436] A fourth interlayer insulating layer 1634 may be disposed on the second gate F, and a second source E and a second drain D may be disposed on the fourth interlayer insulating layer 1634 .

[0437] The second source electrode E may be electrically connected to the first portion of the second active layer ACT2 through the first hole of the fourth interlayer insulating layer 1634, and the second drain electrode D may be electrically connected to the second portion of the second active layer ACT2 through the second hole of the fourth interlayer insulating layer 1634. A region between the first portion and the second portion in the second active layer ACT2 may be a channel region.

[0438] The planarization layer 1640 may be disposed on the second source electrode E and the second drain electrode D. The anode AND1 or AND2 may be disposed on the planarization layer 1640 , and may be electrically connected to the second source electrode E or the second drain electrode D through a hole of the planarization layer 1640 .

[0439] When the planarization layer 1640 includes the first planarization layer 1641 and the second planarization layer 1642, the first planarization layer 1641 may be disposed on the second source electrode E and the second drain electrode D, and the relay electrode RE may be disposed on the first planarization layer 1641 and may be electrically connected to the second source electrode E or the second drain electrode D through a hole of the first planarization layer 1641. The second planarization layer 1642 may be disposed on the relay electrode RE. The anode AND1 or AND2 may be disposed on the second planarization layer 1642 and may be electrically connected to the relay electrode RE through a hole of the second planarization layer 1642.

[0440] When the sub-pixel SP has Figure 2 When the structure shown in Fig.16 The pixel driving transistor Tp shown in FIG. 1 includes a second source electrode E electrically connected to the anode electrode AND1 or AND2 of the light emitting element ED. Therefore, Fig.16 The pixel driving transistor Tp shown in FIG. 1 may be Figure 2 The driving transistor DT in.

[0441] The bank BK may be disposed on the anodes AND1 and AND2 and may have an opening corresponding to the emission area EA.

[0442] The element intermediate layer EL may be disposed on the bank BK and may contact the anodes AND1 and AND2 at the opening of the bank BK. The spacer SPCR may be located on the bank BK at some position (eg, a position where the spacer SPCR overlaps with the anodes AND1 and AND2 or a boundary position of the emission area EA).

[0443] The cathode CAT may be provided on the element intermediate layer EL.

[0444] The overlapping regions of the anodes AND1 and AND2, the element intermediate layer EL, and the cathode CAT can form light emitting regions EA1 and EA2. Fig.16 , the common intermediate layer EL_COM is illustrated by combining the first common intermediate layer COM1 and the second common intermediate layer COM2 included in the element intermediate layer EL, and the first light emitting layer EML1 and the second light emitting layer EML2 are omitted.

[0445] The encapsulation layer 200 may be disposed on the pixel array layer 1530 .

[0446] The encapsulation layer 200 may include a first inorganic layer PAS1, an organic layer PCL, and a second inorganic layer PAS2. For example, the first inorganic layer PAS1 and the second inorganic layer PAS2 may be inorganic layers, and the organic layer PCL may be an organic layer.

[0447] The first metal GA in the base circuit layer 1510 and the second metal GB in the pixel array layer 1530 may be electrically connected through the opening of the shielding layer 1520 .

[0448] In addition, the first metal GA in the base circuit layer 1510 and the second metal GB in the pixel array layer 1530 may be electrically connected through a connection metal GCP separated from the shielding layer 1520. The connection metal GCP may include the same material as the shielding layer 1520 and may be located at the same layer as the shielding layer 1520. The connection metal GCP is also called a gate link line GCP.

[0449] The second metal GB in the pixel array layer 1530 may be disposed on the second gate insulating layer 1633. The second metal GB may include the same material as the second gate F and may be located at the same layer as the second gate F.

[0450] The first metal GA in the base circuit layer 1510 may be disposed on the first interlayer insulating layer 1621. The second metal GB in the pixel array layer 1530 may be electrically connected to the first metal GA in the base circuit layer 1510 through holes of the second buffer layer 1630, the second interlayer insulating layer 1631, the third interlayer insulating layer 1632, the second gate insulating layer 1633, the shielding layer 1520, and the organic layer 1622.

[0451] The first metal GA in the base circuit layer 1510 may be electrically corresponding to Fig.11 and Fig.12 The metal of the output nodes Nout1a, Nout1b, Nout1 and Nout2 in the base circuit layer 1510.

[0452] The second metal GB in the pixel array layer 1530 may be electrically corresponding to Fig.11 and Fig.12 The second metal GB in the pixel array layer 1530 may be one of the first scan line SCL1, the second scan line SCL2, the third scan line SCL3, the first emission control line EML1, and the second emission control line EML2.

[0453] Reference Fig.16 , the base circuit layer 1510 may include a gate driving transistor Tg including a first active layer ACT1, and the pixel array layer 1530 may include a pixel driving transistor Tp including a second active layer ACT2.

[0454] The first active layer ACT1 and the second active layer ACT2 may include different semiconductor materials. For example, the first active layer ACT1 may include a silicon-based semiconductor material. The second active layer ACT2 may include an oxide-based semiconductor material.

[0455] For example, the silicon-based semiconductor material may include amorphous silicon (a-Si) or low temperature polycrystalline silicon (LTPS). For example, the oxide-based semiconductor material may include indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), cadmium oxide (CdO), indium oxide (InO), zinc tin oxide (ZTO), zinc indium tin oxide (ZITO), etc., or may also include low temperature polycrystalline oxide (LTPO).

[0456] The first active layer ACT1 and / or the second active layer ACT2 may be a single layer or multiple layers. For example, when the first active layer ACT1 and / or the second active layer ACT2 are multiple layers, the multiple layers may be composed of the same semiconductor material or may be composed of at least two different semiconductor materials.

[0457] Reference Fig.16 , the encapsulation layer 200 and the cathode CAT may overlap with the gate driving circuit 130 .

[0458] Reference Fig.16, the cathode CAT may be an electrode capable of transmitting light. The anodes AND1 and AND2 may be reflective electrodes and may overlap at least a portion of the gate driving circuit 130. Therefore, the display panel 110 may have a structure capable of top emission.

[0459] Reference Fig.16 , according to an embodiment of the present disclosure, the second driving voltage VSS may be applied to the shielding layer 1510 included in the display panel 110 .

[0460] Reference Fig.16 , the shielding layer 1520 may be electrically connected to the cathode CAT to which the second driving voltage VSS (as a kind of pixel driving voltage) is applied.

[0461] The cathode CAT and the shielding layer 1520 may be electrically connected through a first connection pattern CP1 and a second connection pattern CP2. The first connection pattern CP1 may be a metal disposed on the fourth interlayer insulating layer 1634. The first connection pattern CP1 may be connected to the shielding layer 1520 through holes of the second buffer layer 1630, the second interlayer insulating layer 1631, the third interlayer insulating layer 1632, the second gate insulating layer 1633, and the fourth interlayer insulating layer 1634. The second connection pattern CP2 may be a metal disposed on the first planarizing layer 1641. The second connection pattern CP2 may be connected to the first connection pattern CP1 through holes of the first planarizing layer 1641.

[0462] The first and second connection patterns CP1 and CP2 may be electrically connected to a second driving voltage line VSSL disposed in the pixel array layer 1530. At least one of the first and second connection patterns CP1 and CP2 may be a second driving voltage line VSSL disposed in the pixel array layer 1530.

[0463] The cathode electrode CAT in the pixel array layer 1530 and the second power line PL2 in the base circuit layer 1510 may be electrically connected through the first connection pattern CP1 , the second connection pattern CP2 , and the shielding layer 1520 .

[0464] Reference Fig.16 , a second common driving voltage line VSSL may be disposed on the substrate 111 and may supply a second common pixel driving voltage VSS to the cathode CAT.

[0465] The second common driving voltage line VSSL may be disposed in the display area DA. The cathode electrode CAT may be electrically connected to the second common driving voltage line VSSL in the display area DA. Therefore, the size of the non-display area NDA may be further reduced.

[0466] Reference Fig.16, a voltage having a predetermined voltage level may be applied to the shielding layer 1520. For example, the second common pixel driving voltage VSS may be applied to the shielding layer 1520. To this end, the shielding layer 1520 may be electrically connected to the cathode CAT and may be electrically connected to the second common driving voltage line VSSL.

[0467] Reference Fig.16 The bank BK may be located on the insulating stack INS and may have a first opening and a second opening.

[0468] The first anode AND1 and the second anode AND2 may be located on the insulating stack INS and may overlap the first opening and the second opening, respectively.

[0469] The first common intermediate layer COM1 may be commonly disposed on the first anode AND1 and the second anode AND2 .

[0470] The first and second light emitting layers EML1 and EML2 may be located on the first common intermediate layer COM1 and may overlap the first and second anodes AND1 and AND2 .

[0471] The second common intermediate layer COM2 may be commonly disposed on the first light emitting layer EML1 and the second light emitting layer EML2 .

[0472] exist Fig.16 , the common intermediate layer EL_COM including the first common intermediate layer COM1 and the second common intermediate layer COM2 is shown, and the first light emitting layer EML1 and the second light emitting layer EML2 are omitted.

[0473] Reference Fig.16 , the cathode CAT can be located on the common intermediate layer EL_COM.

[0474] Reference Fig.16 The cathode CAT and the second common driving voltage line VSSL may be electrically connected through a hole penetrating at least a portion of the common intermediate layer EL_COM including the first and second common intermediate layers COM1 and COM2 , the bank BK, and the insulating stack INS.

[0475] The sub-pixel circuit layer SPCL may be located between the shielding layer 1520 and the light emitting element layer EDL, and may include a plurality of sub-pixel circuits SPC for driving a plurality of light emitting elements ED.

[0476] Reference Fig.16 The gate link line GCP may connect the in-panel gate circuit GIPC and the plurality of sub-pixel circuits SPC disposed in the base circuit layer 1520. The gate link line GCP may overlap the organic layer PCL of the encapsulation layer 200.

[0477] Fig.17 and Fig.18 1 and 2 show a vertical structure and a planar structure of the display panel 110 according to an embodiment of the present disclosure when the gate in-panel circuit GIPC is disposed in a portion of the display area DA of the display panel 110 .

[0478] Reference Fig.17 and Fig.18 , the display area DA of the display panel 110 may include a first display area DA1 and a second display area DA2. Fig.17 and Fig.18 As shown, the first display area DA1 may be disposed on both one side and the other side of the second display area DA2. Different from this, the first display area DA1 may be disposed on only one of the one side and the other side of the second display area DA2.

[0479] Reference Fig.17 and Fig.18 , the display panel 110 according to an embodiment of the present disclosure may include a substrate 111 , a base circuit layer 1710 , a light emitting element layer EDL, and an encapsulation layer 200 .

[0480] Reference Fig.17 and Fig.18 The basic circuit layer 1710 may be located on the substrate 111 and may include an intra-panel gate circuit GIPC. In addition to the intra-panel gate circuit GIPC, the basic circuit layer 1710 may also include a sub-pixel circuit array SPCA, which includes a plurality of sub-pixel circuits SPC for driving a plurality of light emitting elements ED.

[0481] Reference Fig.17 and Fig.18 , the light emitting element layer EDL may be located above the base circuit layer 1710. A plurality of light emitting elements ED may be provided in the light emitting element layer EDL.

[0482] Reference Fig.17 and Fig.18 , the in-panel gate circuit GIPC may be disposed in the first display area DA1, and the sub-pixel circuit array SPCA may be disposed in the second display area DA2. In the first display area DA1, the in-panel gate circuit GIPC may overlap the organic layer PCL.

[0483] Reference Fig.17 and Fig.18 , the plurality of light emitting elements ED disposed in the light emitting element layer EDL may include at least two first light emitting elements ED disposed in the first display area DA1 and at least two second light emitting elements ED disposed in the second display area DA2 .

[0484] Reference Fig.17 and Fig.18 At least a portion of at least two first light emitting elements ED disposed in the first display area DA1 may overlap at least a portion of the in-panel gate circuit GIPC. At least a portion of at least two second light emitting elements ED disposed in the second display area DA2 may overlap at least a portion of the sub-pixel circuit array SPCA.

[0485] Reference Fig.17 , the display panel 110 according to the embodiment of the present disclosure may further include an anode extension link layer 1730 between the base circuit layer 1710 and the light emitting element layer EDL.

[0486] In the anode extension link layer 1730, an anode extension link (also referred to as an extension link or a connection pattern) may be provided ( Fig. 20 The anode extension link may electrically connect the sub-pixel circuit SPC included in the sub-pixel circuit array SPCA disposed in the second display area DA2 and the first light emitting element ED disposed in the first display area DA1.

[0487] As described above, in the display panel 110 according to an embodiment of the present disclosure, since the intra-panel gate circuit GIPC is not disposed in the non-display area NDA but in the first display area DA1 included in the display area DA, the frame corresponding to the non-display area NDA can be made smaller.

[0488] Reference Fig.17 The display panel 110 according to the embodiment of the present disclosure may further include a shielding layer 1720 located between the in-panel gate circuit GIPC included in the base circuit layer 1710 and the light emitting element layer EDL.

[0489] Reference Fig.17 , the shielding layer 1720 may be disposed in the first display area DA1 and may be located between the anode extension link layer 1730 and the intra-panel gate circuit GIPC.

[0490] At least a portion of the shielding layer 1720 may overlap the extension link (anode extension link) and the intra-panel gate circuit GIPC provided in the anode extension link layer 1730. Therefore, the anode extension link AEL electrically connected to the anode AND and the intra-panel gate circuit GIPC does not exert an undesirable electrical influence on each other. Due to this fact, image quality can be improved.

[0491] Fig.19 yes Fig.18 FIG. 1 is a plan view of a partial area 1800 of the display panel 110 .

[0492] Reference Fig.19, the display panel 110 may include a display area DA and a non-display area NDA, and the display area DA may include a first display area DA1 and a second display area DA2. The non-display area NDA is also referred to as a bezel.

[0493] Reference Fig.19 , the first display area DA1 may be located between the non-display area NDA and the second display area DA2.

[0494] Reference Fig.19 The display area DA may include a plurality of light emitting elements ED. For example, the plurality of light emitting elements ED may include a red light emitting element ED_R for emitting red light, a green light emitting element ED_G for emitting green light, and a blue light emitting element ED_B for emitting blue light.

[0495] Reference Fig.19 , the plurality of light emitting elements ED disposed in the display area DA may include a plurality of first light emitting elements ED1 disposed in the first display area DA1 and a plurality of second light emitting elements ED2 disposed in the second display area DA2.

[0496] Reference Fig.19 , the sub-pixel circuit array SPCA may be disposed in the second display area DA2. The sub-pixel circuit array SPCA may include a plurality of sub-pixel circuits SPC.

[0497] The plurality of sub-pixel circuits SPC may include at least one first sub-pixel circuit SPC for driving a plurality of first light emitting elements ED1 disposed in the first display area DA1 and a plurality of second sub-pixel circuits SPC for driving a plurality of second light emitting elements ED2 disposed in the second display area DA2.

[0498] All or a portion of the in-panel gate circuit GIPC may be disposed in the first display area DA1 .

[0499] In other words, the plurality of light emitting elements ED may include a first light emitting element ED1 disposed in the first display area DA1 and overlapping with at least a portion of the in-panel gate circuit GIPC, and a second light emitting element ED2 disposed in the second display area DA2 and overlapping with at least a portion of the sub-pixel circuit array SPCA.

[0500] Reference Fig.19The multiple sub-pixel circuits SPC included in the sub-pixel circuit array SPCA may include a first sub-pixel circuit SPC configured to drive a first light-emitting element ED1 set in the first display area DA1 and set in the second display area DA2, and at least two second sub-pixel circuits SPC configured to drive a second light-emitting element ED2 set in the second display area DA2 and set in the second display area DA2.

[0501] Reference Fig.19 , the display panel 110 according to an embodiment of the present disclosure may include a link area LKA, in which a link for transmitting various gate signals output from the intra-panel gate circuit GIPC to the sub-pixel circuit array SPCA is provided. For example, the link provided in the link area LKA may electrically connect the output point of the intra-panel gate circuit GIPC with the gate line GL. In the case where the output point of the intra-panel gate circuit GIPC is a first metal layer and the gate line GL is a second metal layer different from the first metal layer, the link may include a jumping metal connecting the first metal layer and the second metal layer to each other.

[0502] Reference Fig.19 The link area LKA may be located between the intra-panel gate circuit GIPC and the sub-pixel circuit array SPCA. The link area LKA may be included in the first display area DA1.

[0503] Reference Fig.19 , the display panel 110 according to an embodiment of the present disclosure may include a crack management area CRA provided with a crack detection line and / or a crack stop pattern.

[0504] For example, refer to Fig.19 , the crack management area CRA may be included in the non-display area NDA. In this case, the crack detection line and / or the crack stop pattern may not overlap with the first light emitting element ED1 disposed in the first display area DA1.

[0505] For another example, the crack management area CRA may be included in the first display area DA1. In this case, the crack detection line and / or the crack stop pattern may overlap with the first light emitting element ED1 disposed in the first display area DA1.

[0506] Reference Fig.19 , the display panel 110 according to an embodiment of the present disclosure may further include a base voltage line area VSSA where a base voltage line VSSL is provided.

[0507] Reference Fig.19In the display panel 110 according to an embodiment of the present disclosure, the base voltage line VSSL may be provided in the display area DA. For example, the base voltage line VSSL may be provided in at least one of the first display area DA1 and the second display area DA2 included in the display area DA. Therefore, the cathode CAT may be electrically connected to the base voltage line VSSL in at least one of the first display area DA1 and the second display area DA2 included in the display area DA.

[0508] Therefore, the base voltage line area VSSA may not exist in the non-display area NDA. Due to this fact, the size of the frame between the trimming line TRL and the display area DA may be reduced.

[0509] Fig. 20 The corresponding relationship between the sub-pixel circuits SPC1 , SPC2_TRANS and SPC2 and the light emitting elements ED1 and ED2 in the display panel 110 according to an embodiment of the present disclosure is shown.

[0510] Reference Fig. 20 In terms of a planar structure, the display panel 110 may include a display area DA and a non-display area NDA. The display area DA may include a first display area DA1 and a second display area DA2.

[0511] Reference Fig. 20 In terms of a vertical structure, the display panel 110 may include a basic circuit layer 1710 and a light emitting element layer EDL.

[0512] Reference Fig. 20 In the basic circuit layer 1710, all or most of the intra-panel gate circuit GIPC may be disposed in the first display area DA1. In the basic circuit layer 1710, a sub-pixel circuit array SPCA including sub-pixel circuits SPC1, SPC2_TRANS, and SPC2 may be disposed in the second display area DA2.

[0513] Reference Fig. 20 , in the basic circuit layer 1710 , the link area LKA may be disposed in the first display area DA1 or the second display area DA2 , or may be disposed in both the first display area DA1 and the second display area DA2 .

[0514] Reference Fig. 20 The plurality of light emitting elements ED disposed in the light emitting element layer EDL may be disposed in the display area DA. The plurality of light emitting elements ED disposed in the light emitting element layer EDL may include a plurality of first light emitting elements ED1 disposed in the first display area DA1 and a plurality of second light emitting elements ED2 disposed in the second display area DA2.

[0515] Reference Fig. 20The multiple sub-pixel circuits SPC included in the sub-pixel circuit array SPCA may include at least one first sub-pixel circuit SPC1 configured to drive a plurality of first light-emitting elements ED1 set in the first display area DA1, and a plurality of second sub-pixel circuits SPC2 configured to drive a plurality of second light-emitting elements ED2 set in the second display area DA2.

[0516] Reference Fig. 20 , a plurality of sub-pixel circuits SPC included in the sub-pixel circuit array SPCA may be classified into a first group GR1 [1:n], a transition group GR_TRANS [1:n], and a second group GR2 [1:1].

[0517] Reference Fig. 20 , the second group GR2[1:1] may include a plurality of second sub-pixel circuits SPC2. The second group GR2[1:1] may drive one second light emitting element ED2 disposed in the second display area DA2 in a "one-to-one (1:1) driving method".

[0518] Each of the plurality of second sub-pixel circuits SPC2 included in the second group GR2[1:1] can drive one second light emitting element ED2 provided in the second display area DA2. In other words, one second sub-pixel circuit SPC2 included in the second group GR2[1:1] can drive one second light emitting element ED2 provided in the second display area DA2. Therefore, the second anode AND2 of one second light emitting element ED2 can be connected to one second sub-pixel circuit SPC2 one by one.

[0519] Reference Fig. 20 , the first group GR1[1:n] may include a plurality of first sub-pixel circuits SPC1. The first group GR1[1:n] may drive at least two first light emitting elements ED1 disposed in the first display area DA1 in a "one-to-many driving method or a common driving method".

[0520] Each of the plurality of first sub-pixel circuits SPC1 included in the first group GR1[1:n] can drive at least two first light emitting elements ED1 disposed in the first display area DA1 together. That is, one first sub-pixel circuit SPC1 included in the first group GR1[1:n] can drive at least two first light emitting elements ED1 disposed in the first display area DA1 together.

[0521] For example, Fig. 20 As shown, one first sub-pixel circuit SPC1 included in the first group GR1 [1:n] may drive two first light emitting elements ED1 disposed in the first display area DA1 together.

[0522] Reference Fig. 20 In order to enable a first sub-pixel circuit SPC1 set in the second display area DA2 to drive at least two first light-emitting elements ED1 set in the first display area DA1 together, the display panel 110 according to an embodiment of the present disclosure may also include an anode extension link AEL for connecting a first sub-pixel circuit SPC1 set in the second display area DA2 to at least two first light-emitting elements ED1 set in the first display area DA1.

[0523] The anode extension link AEL may be provided in the anode extension link layer 1730 between the base circuit layer 1710 and the light emitting element layer EDL. Therefore, the anode extension link AEL may include a metal (anode extension link layer metal) between the base circuit layer 1710 and the light emitting element layer EDL.

[0524] Reference Fig. 20 , a portion of the plurality of first sub-pixel circuits SPC1 included in the first group GR1 [1:n] may be connected to one scan line SCL and may be supplied with a scan signal SC from the one scan line SCL.

[0525] Reference Fig. 20 , at least two first light emitting elements ED1 driven together by one first sub-pixel circuit SPC1 included in the first group GR1 [1:n] may emit light of the same color.

[0526] Reference Fig. 20 , one first sub-pixel circuit SPC1 included in the first group GR1 [1:n] may be supplied with the scan signal SC and the data signal VDATA, and at least two first light emitting elements ED1 may be driven together based on the scan signal SC and the data signal VDATA.

[0527] Reference Fig. 20 , the transition group GR_TRANS[1:n] may include a plurality of transition sub-pixel circuits SPC2_TRANS. The transition group GR_TRANS[1:n] may also drive at least two second light emitting elements ED2 disposed in the second display area DA2 in a "one-to-many driving method or a common driving method".

[0528] Each of the plurality of transition sub-pixel circuits SPC2_TRANS included in the transition group GR_TRANS[1:n] can drive at least two second light emitting elements ED2 disposed in the second display area DA2. That is, one transition sub-pixel circuit SPC2_TRANS included in the transition group GR_TRANS[1:n] can drive at least two second light emitting elements ED2 disposed in the second display area DA2.

[0529] Reference Fig. 20 , at least two second light emitting elements ED2 driven together by one transition sub-pixel circuit SPC2_TRANS according to the one-to-many driving method may be adjacent light emitting elements ED emitting light of the same color.

[0530] At least two second light-emitting elements ED2 driven together by one transition sub-pixel circuit SPC2_TRANS according to the one-to-many driving method are configured with light-emitting elements ED emitting light of the same color and arranged adjacent to each other, and the at least two second light-emitting elements ED2 exhibit similar light-emitting characteristics. Therefore, the image quality based on the one-to-many driving can be at the same level as the image quality based on the one-to-one driving.

[0531] Reference Fig. 20 In order to enable a transition sub-pixel circuit SPC2_TRANS set in the second display area DA2 to drive at least two second light-emitting elements ED2 set in the second display area DA2 together, the display panel 110 according to an embodiment of the present disclosure may also include a transition anode extension link AEL for connecting a transition sub-pixel circuit SPC2_TRANS set in the second display area DA2 to at least two second light-emitting elements ED2 set in the second display area DA2.

[0532] Reference Fig. 20 , the second light emitting element ED2 driven by the transition sub-pixel circuit SPC2_TRANS included in the transition group GR_TRANS[1:n] may be disposed adjacent to the first light emitting element ED1 driven by the first sub-pixel circuit SPC1 included in the first group GR1[1:n].

[0533] Reference Fig. 20 , the second light-emitting element ED2 driven by the transition sub-pixel circuit SPC2_TRANS included in the transition group GR_TRANS[1:n] can be set between the first light-emitting element ED1 driven by the first sub-pixel circuit SPC1 included in the first group GR1[1:n] and the second light-emitting element ED2 driven by the second sub-pixel circuit SPC2 included in the second group GR2[1:n].

[0534] Reference Fig. 20 , the transition group GR_TRANS[1:n] may be disposed between the first group GR1[1:n] and the second group GR2[1:1].

[0535] As described above, the extended link AEL may connect the first sub-pixel circuit SPC1 disposed in the second display area DA2 to the first light emitting element ED1 disposed in the first display area DA1. At least a portion of the extended link AEL may overlap at least a portion of the in-panel gate circuit GIPC, and the extended link AEL may overlap the organic layer PCL.

[0536] Fig.21 is a cross-sectional view illustrating a vertical structure of a display panel 110 according to an embodiment of the present disclosure.

[0537] Reference Fig.21 , the display panel 110 according to an embodiment of the present disclosure may include a display area DA and a non-display area NDA. The display area DA may include a first display area DA1 and a second display area DA2. The first display area DA1 may be located between the second display area DA2 and the non-display area NDA.

[0538] Reference Fig.21 , the display panel 110 according to an embodiment of the present disclosure may include a substrate 111 , a basic circuit layer 1710 on the substrate 111 , and a light emitting element layer EDL on the basic circuit layer 1710 .

[0539] The display panel 110 according to an embodiment of the present disclosure may further include at least one insulating layer disposed between the base circuit layer 1710 and the light emitting element layer EDL.

[0540] For example, Fig.21 As shown, the first insulating layer INS1, the second insulating layer INS2 and the third insulating layer INS3 may be disposed between the base circuit layer 1710 and the light emitting element layer EDL. For example, the first insulating layer INS1 may be an inorganic layer or an organic layer. The second insulating layer INS2 and the third insulating layer INS3 may serve as a planarization layer and may be an organic layer.

[0541] Reference Fig.21 In the basic circuit layer 1710, a sub-pixel circuit array SPCA, a link area LKA and an intra-panel gate circuit GIPC may be provided.

[0542] The sub-pixel circuit array SPCA may be disposed in the second display area DA2 , the link area LKA may be disposed in the first display area DA1 , and the in-panel gate circuit GIPC may be disposed in the first display area DA1 .

[0543] Reference Fig.21A plurality of light emitting elements ED may be disposed in the light emitting element layer EDL. The plurality of light emitting elements ED disposed in the light emitting element layer EDL may include a plurality of first light emitting elements ED1 disposed in the first display area DA1 and a plurality of second light emitting elements ED2 disposed in the second display area DA2.

[0544] At least two first light emitting elements ED1 disposed in the first display area DA1 may be driven in a one-to-many driving method (common driving method) by at least one first sub-pixel circuit SPC1 among a plurality of sub-pixel circuits SPC included in the sub-pixel circuit array SPCA.

[0545] Most of the plurality of second light emitting elements ED2 disposed in the second display area DA2 may be driven by a second sub-pixel circuit SPC2 among a plurality of sub-pixel circuits SPC included in the sub-pixel circuit array SPCA in a one-to-one driving method.

[0546] A portion of the plurality of second light emitting elements ED2 disposed in the second display area DA2 may be driven in a common driving method by a transition sub-pixel circuit SPC2_TRANS among a plurality of sub-pixel circuits SPC included in the sub-pixel circuit array SPCA.

[0547] Reference Fig.21 The light emitting element layer EDL may include at least two first anodes AND1 disposed in the first display area DA1, and at least two first light emitting layers EML1 disposed in the first display area DA1 and respectively located on the at least two first anodes AND1.

[0548] Reference Fig.21 The light emitting element layer EDL may include at least two second anodes AND2 disposed in the second display area DA2, and at least two second light emitting layers EML2 disposed in the second display area DA2 and respectively located on the at least two second anodes AND2.

[0549] Reference Fig.21 The light emitting element layer EDL may include a cathode CAT disposed in the first and second display areas DA1 and DA2 and located on at least two first light emitting layers EML1 and at least two second light emitting layers EML2. A base voltage VSS as a second driving voltage may be applied to the cathode CAT.

[0550] Reference Fig.21 At least two first light emitting elements ED1 may be configured in the first display area DA1 through at least two first anodes AND1 , at least two first light emitting layers EML1 , and a cathode CAT.

[0551] Reference Fig.21At least two second light emitting elements ED2 may be configured in the second display area DA2 through at least two second anodes AND2, at least two second light emitting layers EML2, and a cathode CAT.

[0552] Reference Fig.21 , the first common intermediate layer COM1 and the second common intermediate layer COM2 can be disposed in the entire display area DA. The first common intermediate layer COM1 can be disposed in the entire display area DA and is located between the anodes AND1 and AND2 and the light-emitting layers EML1 and EML2. The second common intermediate layer COM2 can be disposed in the entire display area DA and is located between the light-emitting layers EML1 and EML2 and the cathode CAT.

[0553] Reference Fig.21 In the display area DA, the light emitting areas of the light emitting elements ED1 and ED2 may be defined by the opening of the bank BK. The bank BK may be located on the anodes AND1 and AND2 and may have an opening exposing a portion of the anodes AND1 and AND2. The opening of the bank BK may be a light emitting area. The bank BK may also be referred to as a light emitting portion defining layer.

[0554] Reference Fig.21 , the display panel 110 according to an embodiment of the present disclosure may include a connection metal structure for connection between the base circuit layer 1710 and the light emitting element layer EDL.

[0555] Reference Fig.21 According to an embodiment of the present disclosure, the connection metal structure of the display panel 110 may include a first metal layer disposed between the first insulating layer INS1 and the second insulating layer INS2, a second metal layer disposed between the second insulating layer INS2 and the third insulating layer INS3, and a third metal layer disposed between the third insulating layer INS3 and the light emitting element layer EDL.

[0556] Reference Fig.21 The display panel 110 according to an embodiment of the present disclosure may include a second anode connection structure for electrically connecting the second anode AND2 provided in the light emitting element layer EDL and the second sub-pixel circuit SPC2 provided in the base circuit layer 1710 in a one-to-one manner.

[0557] Reference Fig.21 The second anode connection structure of the display panel 110 according to the embodiment of the present disclosure may include a second anode connection pattern CP_AND2. Each of the at least two second anodes AND2 may be electrically connected to a second sub-pixel circuit SPC2 disposed in the base circuit layer 1710 through the second anode connection pattern CP_AND2.

[0558] Reference Fig.21, the second anode connection pattern CP_AND2 may include a second metal connection pattern CP2_AND2 and a first metal connection pattern CP1_AND2.

[0559] Reference Fig.21 , at least two second anodes AND2 may be disposed in the third metal layer. One second anode AND2 may be electrically connected to a second metal connection pattern CP2_AND2 in the second metal layer through a hole in the third insulating layer INS3, the second metal connection pattern CP2_AND2 may be electrically connected to a first metal connection pattern CP1_AND2 in the first metal layer through a hole in the second insulating layer INS2, and the first metal connection pattern CP1_AND2 may be electrically connected to a second sub-pixel circuit SPC2 disposed in the base circuit layer 1710 through a hole in the first insulating layer INS1.

[0560] Reference Fig.21 , at least two first anodes AND1 may be electrically connected to the first sub-pixel circuit SPC1 disposed in the base circuit layer 1710 through an anode extension link AEL disposed in the anode extension link layer 1730 .

[0561] Reference Fig.21 The display panel 110 according to an embodiment of the present disclosure may include a first anode connection structure for electrically connecting at least two first anodes AND1 provided in the light emitting element layer EDL and a first sub-pixel circuit SPC1 provided in the base circuit layer 1710 .

[0562] Reference Fig.21 , the first anode connection structure of the display panel 110 according to an embodiment of the present disclosure may include an anode extension link AEL and an anode connection pattern CP1_AND1.

[0563] Reference Fig.21 , at least two first anodes AND1 may be disposed in the third metal layer. The anode extension link layer 1730 may be a second metal layer on the second insulating layer INS2. The anode connection pattern CP1_AND1 may include a first metal connection pattern CP1_AND1 in a first metal layer on the first insulating layer INS1.

[0564] Reference Fig.21 In the first display area DA1 , each of the at least two first anodes AND1 may be electrically connected to an anode extension link AEL located in the second metal layer through a hole of the third insulating layer INS3 . The second metal layer may be an anode extension link layer 1730 .

[0565] Reference Fig.21The anode extension link AEL can be electrically connected to the first metal connection pattern CP1_AND1 located in the first metal layer through the hole of the second insulating layer INS2, and the first metal connection pattern CP1_AND1 can be electrically connected to the first sub-pixel circuit SPC1 set in the basic circuit layer 1710 through the hole of the first insulating layer INS1.

[0566] Reference Fig.21 , the anode extension link AEL may include a first portion electrically connected to at least two first anodes AND1 in the light emitting element layer EDL in the first display area DA1, and a second portion connected to the first sub-pixel circuit SPC1 in the base circuit layer 1710 in the second display area DA2. The first portion may be located in the first display area DA1, and the second portion may be located in the second display area DA2.

[0567] Reference Fig.21 The anode extension link AEL may be provided to extend from the first display area DA1 to the second display area DA2 when viewed in a plan view. The first anode connection structure including the anode extension link AEL may be arranged from the base circuit layer 1710 to the light emitting element layer EDL in a vertical direction.

[0568] Reference Fig.21 , in the basic circuit layer 1710 , the link area LKA may be located between the sub-pixel circuit array SPCA and the intra-panel gate circuit GIPC.

[0569] Reference Fig.21 , the shielding layer 1720 may be located between the in-panel gate circuit GIPC included in the base circuit layer 1710 and the light emitting element layer EDL.

[0570] The shielding layer 1720 may be disposed in the first display area DA1.

[0571] The shielding layer 1720 may be electrically connected to the cathode connection pattern CP_VSS. Therefore, the base voltage VSS to be applied to the cathodes CAT of the light emitting elements ED1 and ED2 may be applied to the shielding layer 1720.

[0572] The shielding layer 1720 may be disposed in the first display area DA1 and may be located between the intra-panel gate circuit GIPC and the anode extension link AEL. The shielding layer 1720 may overlap the intra-panel gate circuit GIPC and may overlap the anode extension link AEL.

[0573] Therefore, the anode extension link AEL may not be electrically affected by the in-panel gate circuit GIPC. The in-panel gate circuit GIPC may not be electrically affected by the anode extension link AEL.

[0574] Reference Fig.21 According to an embodiment of the present disclosure, the display panel 110 may include: a substrate 111 including a display area DA and a non-display area NDA outside the display area DA, the display area DA including a first display area DA1 and a second display area DA2; at least two first light-emitting elements ED1 arranged in the first display area DA1; at least two second light-emitting elements ED2 arranged in the second display area DA2; a first sub-pixel circuit SPC1 commonly connected to the at least two first light-emitting elements ED1; and at least two second sub-pixel circuits SPC2 respectively connected to the at least two second light-emitting elements ED2.

[0575] Reference Fig.21 , the display panel 110 according to the embodiment of the present disclosure may further include an in-panel gate circuit GIPC disposed in the first display area DA1.

[0576] Reference Fig.21 According to an embodiment of the present disclosure, the display panel 110 may further include an anode extension link AEL for electrically connecting at least two first light emitting elements ED1 and one first sub-pixel circuit SPC1.

[0577] Reference Fig.21 According to an embodiment of the present disclosure, the display panel 110 may further include a shielding layer 1720 disposed between the intra-panel gate circuit GIPC and the anode extension link AEL.

[0578] Reference Fig.21 In the display panel 110 according to an embodiment of the present disclosure, the base voltage line VSSL may be provided in the display area DA. For example, the base voltage line VSSL may be provided in at least one of the first display area DA1 and the second display area DA2 included in the display area DA. Therefore, the cathode CAT may be electrically connected to the base voltage line VSSL in at least one of the first display area DA1 and the second display area DA2 included in the display area DA.

[0579] Therefore, the base voltage line area VSSA may not exist in the non-display area NDA. Due to this fact, a frame as the non-display area NDA may become smaller.

[0580] Reference Fig.21 In the display panel 110 according to an embodiment of the present disclosure, the base voltage line VSSL may be located in the display area DA. The display panel 110 according to an embodiment of the present disclosure may include a cathode connection structure for electrically connecting the cathode CAT with the base voltage line VSSL, and the cathode connection structure may be located in the display area DA.

[0581] For example, the base voltage line VSSL may be provided in at least one of the first display area DA1 and the second display area DA2 included in the display area DA. Therefore, the cathode CAT may be electrically connected to the base voltage line VSSL through a cathode connection structure located in at least one of the first display area DA1 and the second display area DA2 included in the display area DA.

[0582] Reference Fig.21 , a cathode connection pattern CP_VSS as a cathode connection structure for connecting the cathode CAT to the base voltage line VSSL may be located in the display area DA. That is, the cathode connection pattern CP_VSS may be located in at least one of the first display area DA1 and the second display area DA2 included in the display area DA.

[0583] Reference Fig.21 , the cathode CAT may be electrically connected to the cathode connection pattern CP_VSS located under the bank BK through a hole of the bank BK located between the at least two second anodes AND2 .

[0584] Reference Fig.21 , the base voltage line VSSL may be located in a first metal layer on the first insulating layer INS1. The cathode connection pattern CP_VSS may include a first cathode connection pattern CP2_VSS located in a second metal layer on the second insulating layer INS2.

[0585] The cathode electrode CAT may be electrically connected to the first cathode connection pattern CP2_VSS through the through holes of the second common intermediate layer COM2 , the first common intermediate layer COM1 , the bank BK, and the third insulating layer INS3 .

[0586] The first cathode connection pattern CP2_VSS may be electrically connected to the base voltage line VSSL on the first insulating layer INS1 through the hole of the second insulating layer INS2 .

[0587] Reference Fig.21 The through holes of the second common intermediate layer COM2, the first common intermediate layer COM1, the bank BK, and the third insulating layer INS3 may be formed by a laser drilling process.

[0588] According to the above description, the base voltage line VSSL and the cathode connection pattern CP_VSS as the cathode connection structure do not need to be provided in the non-display area NDA. Therefore, the frame can be further reduced to the extreme.

[0589] The display panel 110 according to an embodiment of the present disclosure may include three insulating layers INS1 to INS3 and three metal layers between the base circuit layer 1710 and the light emitting element layer EDL as a connection metal structure for connection between the base circuit layer 1710 and the light emitting element layer EDL. The three insulating layers INS1 to INS3 may be included in the insulating stack INS. The three metal layers may include a first metal layer disposed between the first insulating layer INS1 and the second insulating layer INS2, a second metal layer disposed between the second insulating layer INS2 and the third insulating layer INS3, and a third metal layer disposed between the third insulating layer INS3 and the light emitting element layer EDL. The third metal layer may be a metal layer in which the anodes AND1 and AND2 are disposed.

[0590] The display panel 110 according to an embodiment of the present disclosure may have a connection metal structure different from the connection metal structure (three insulating layers and three metal layers) between the base circuit layer 1710 and the light emitting element layer EDL.

[0591] Reference Fig.21 , a voltage having a predetermined voltage level may be applied to the shielding layer 1720 .

[0592] Reference Fig.21 The display panel 110 may further include a base voltage line VSSL which is disposed on the substrate 111 and is a second common driving voltage line for supplying a base voltage VSS as a second common pixel driving voltage to the cathode CAT.

[0593] A base voltage line VSSL as a second common driving voltage line may be provided in the display area DA. In the display area DA, the cathode CAT may be electrically connected to the base voltage line VSSL as the second common driving voltage line.

[0594] The bank BK may be located on the insulating stack INS, and may have a first opening and a second opening.

[0595] The first anode AND1 and the second anode AND2 may be located on the insulating stack INS and may overlap the first opening and the second opening, respectively.

[0596] The first common intermediate layer COM1 may be commonly disposed on the first anode AND1 and the second anode AND2 .

[0597] The first and second light emitting layers EML1 and EML2 may be located on the first common intermediate layer COM1 and may overlap the first and second anodes AND1 and AND2 .

[0598] The second common intermediate layer COM2 may be commonly disposed on the first light emitting layer EML1 and the second light emitting layer EML2 .

[0599] The first common intermediate layer COM1 and the second common intermediate layer COM2 may be collectively referred to as a common intermediate layer EL_COM.

[0600] The cathode CAT may be located on the common intermediate layer EL_COM.

[0601] The cathode CAT and the second base voltage line VSSL as the second common driving voltage line may be electrically connected through a hole penetrating at least a portion of the second common intermediate layer COM2 , the first common intermediate layer COM1 , the bank BK, and the insulating stack INS.

[0602] The first anode AND1 , the first common intermediate layer COM1 , the first light emitting layer EML1 , the second common intermediate layer COM2 , and the cathode CAT may overlap to constitute the first light emitting element ED1 .

[0603] The second anode AND2 , the first common intermediate layer COM1 , the second light emitting layer EML2 , the second common intermediate layer COM2 , and the cathode CAT may overlap to constitute the second light emitting element ED2 .

[0604] exist Figures 17 to 21 In the embodiment, one of the plurality of first light emitting elements ED1 disposed in the first display area DA1 may be the outermost light emitting element ED.

[0605] Reference Fig.21 The stopper STP can be arranged on the outer side of the first light emitting element ED1 as the outermost light emitting element ED. The stopper STP and its surrounding structure can be connected with Figure 5 Same as in.

[0606] Reference Fig.21 The stopper STP may be disposed outside the organic layer PCL of the encapsulation layer 200. The stopper STP may be disposed outside the bank BK.

[0607] Reference Fig.21 , at least a portion of the stopper STP may overlap at least a portion of the intra-panel gate circuit GIPC disposed on the base circuit layer 1710 .

[0608] A brief description of the embodiments of the present disclosure described above is as follows.

[0609] According to an embodiment of the present disclosure, a display device may include: a substrate, including a display area in which a plurality of sub-pixels are arranged and a non-display area located outside the display area; an insulating stack located on the substrate and having an outer side surface in the non-display area; a limiter located on the insulating stack; a cathode located on the insulating stack and extending from the display area to a portion of the non-display area and overlapping with at least a portion of the top surface of the limiter; a first inorganic layer located on the cathode and arranged to extend from the display area to the non-display area; an organic layer located on a portion of the first inorganic layer and having an outer inclined surface; and a second inorganic layer located on the organic layer, arranged to extend from the display area to the non-display area, and arranged to extend along the outer inclined surface of the organic layer.

[0610] In the display device according to the embodiment of the present disclosure, the stopper may be provided in the non-display area and may be located outside the organic layer.

[0611] The display device according to an embodiment of the present disclosure may further include: a bank on the insulating stack and having a plurality of openings; a plurality of anodes on the insulating stack and overlapping the plurality of openings; and a plurality of light emitting layers on the plurality of anodes.

[0612] The cathode may be located on the plurality of light emitting layers, and the plurality of light emitting elements may be configured such that the plurality of anodes, the plurality of light emitting layers and the cathode overlap. The stopper may be disposed outside the bank.

[0613] The first inorganic layer may extend along the top and the outer side of the stopper to the outer side surface of the insulating stack.

[0614] The second inorganic layer may extend to an outer side surface of the insulating stack through an outer slope of the organic layer.

[0615] The outer side surface of the limiting member may have a steeper slope than the inner side surface of the limiting member.

[0616] The display device according to an embodiment of the present disclosure may also include: a dam, which is located on the insulating stack and has first to third openings; first to third anodes, which are located on the insulating stack and overlap with the first to third openings, respectively; a first common intermediate layer, which is jointly arranged on the first to third anodes; first to third light-emitting layers, which are located on the first common intermediate layer and overlap with the first to third anodes; and a second common intermediate layer, which is jointly arranged on the first to third light-emitting layers.

[0617] The first common intermediate layer and the second common intermediate layer may include an organic material, the common intermediate layer may include the first common intermediate layer and the second common intermediate layer, the cathode may be located on the second common intermediate layer, and the common intermediate layer and the cathode may extend to the top of the stopper.

[0618] The display device according to an embodiment of the present disclosure may further include a covering layer, which is located between the cathode and the first inorganic layer and is arranged to extend from the display area to the non-display area. The covering layer may extend along the top and outer side of the stopper to the outer side of the insulating stack.

[0619] The stopper may include a first stopper on the insulating laminate, and a second stopper on the first stopper. The first stopper may include the same material as the bank, and the second stopper may include the same material as the spacer on the bank.

[0620] The end of the common intermediate layer and the end of the cathode may be located on the stopper, and the end of the cathode may protrude further outward than the upper portion of the outer side of the stopper (eg, the outer side of the second stopper) and the end of the common intermediate layer.

[0621] The lower end portion of the outer side surface of the first limiting member may protrude further outward than the upper end portion of the outer side surface of the second limiting member.

[0622] The stopper may include a cliff portion whose slope from the top to the outer side surface is gentle to a point below a predetermined level or to a point where a step exists. A value obtained by summing the height of the cliff portion of the stopper and the height of the common intermediate layer may be greater than the sum of the thickness of the first inorganic layer and the thickness of the second inorganic layer.

[0623] The stopper may be disposed on a side surface of an outermost light emitting element among the plurality of light emitting elements corresponding to the plurality of sub-pixels, and the stopper may have a thickness thicker than an anode of the outermost light emitting element.

[0624] The width of the bottom surface of the limiting member may be greater than the width of the top surface of the limiting member.

[0625] The display device according to an embodiment of the present disclosure may further include: a display signal line disposed in the display area; a display connection line electrically connecting the display signal line and a display pad disposed in the pad area; and a curved organic layer located between the display area and the pad area.

[0626] A portion of the display connection line may overlap with the curved organic layer.

[0627] The non-display area may include: a first non-display area arranged along a first direction from the display area; a second non-display area arranged along a second direction from the display area; a third non-display area arranged along a direction opposite to the first direction from the display area; and a fourth non-display area arranged along a direction opposite to the second direction from the display area. The pad area may be included in the first non-display area.

[0628] The stopper may be disposed in the non-display area and may be disposed in a ring shape surrounding the periphery of the organic layer. The stopper is located between the display area and the pad area.

[0629] The display device according to an embodiment of the present disclosure may further include: a first sensor electrode disposed on the second inorganic layer and extending in the second direction; and a first touch routing line for electrically connecting the first sensor electrode to a first touch pad disposed in the pad region.

[0630] The first touch routing line may extend to the first non-display area by passing through the display area in the first direction without detouring the second non-display area and the fourth non-display area.

[0631] A portion of the first touch routing line extending to the first non-display area may overlap with the stopper in the first non-display area.

[0632] The display device according to an embodiment of the present disclosure may further include an in-panel gate circuit configured to supply a gate signal to the plurality of sub-pixels. The in-panel gate circuit may be disposed on the substrate and may overlap the organic layer.

[0633] The display device according to an embodiment of the present disclosure may further include: a basic circuit layer on a substrate; a light-emitting element layer located on the basic circuit layer and including a plurality of light-emitting elements included in a plurality of sub-pixels; and a shielding layer located between the basic circuit layer and the light-emitting element layer.

[0634] The base circuit layer may include an in-panel gate circuit disposed in the display area.

[0635] A voltage having a predetermined voltage level may be applied to the shielding layer.

[0636] The display device according to an embodiment of the present disclosure may further include a common driving voltage line disposed on the substrate and supplying a common pixel driving voltage to the cathode. The common driving voltage line may be disposed in the display area, and the cathode may be electrically connected to the common driving voltage line in the display area.

[0637] According to an embodiment of the present disclosure, the display device may further include: a sub-pixel circuit layer, which is located between the shielding layer and the light-emitting element layer and includes multiple sub-pixel circuits for driving multiple light-emitting elements; and a gate link line, which connects the gate circuit in the panel set in the basic circuit layer with the multiple sub-pixel circuits.

[0638] The gate link line may overlap the organic layer.

[0639] The display area may include a first display area and a second display area.

[0640] The basic circuit layer may include, in addition to the gate circuit in the panel, a sub-pixel circuit array, wherein the sub-pixel circuit array includes a plurality of sub-pixel circuits for driving a plurality of light-emitting elements.

[0641] The in-panel gate circuit may be disposed in the first display region, and the sub-pixel circuit array may be disposed in the second display region.

[0642] The plurality of light emitting elements may include: a first light emitting element disposed in the first display region and overlapping at least a portion of the in-panel gate circuit; and a second light emitting element disposed in the second display region and overlapping at least a portion of the sub-pixel circuit array.

[0643] The plurality of sub-pixel circuits may include: a first sub-pixel circuit configured to drive a first light emitting element and disposed in the second display area; and at least two second sub-pixel circuits configured to drive a second light emitting element and disposed in the second display area.

[0644] The display device according to an embodiment of the present disclosure may further include an extension link connecting the first sub-pixel circuit disposed in the second display area to the first light emitting element disposed in the first display area.

[0645] At least a portion of the extended link may overlap at least a portion of the gate circuit within the panel. The extended link may overlap the organic layer.

[0646] A display device according to an embodiment of the present disclosure may include: a substrate; an insulating stack on the substrate; a plurality of light emitting elements on the insulating stack; an organic layer on the plurality of light emitting elements; and a stopper disposed outside the organic layer.

[0647] The stopper may be disposed on an outer side of the outermost light emitting element among the plurality of light emitting elements, and the stopper may have a thickness greater than that of the anode of the outermost light emitting element.

[0648] The display device according to the embodiment of the present disclosure may further include: a bank for dividing the plurality of light emitting elements; and a spacer located on the bank.

[0649] The stopper may include a first stopper on the insulating laminate and a second stopper on the first stopper. The first stopper may include the same material as the bank, and the second stopper may include the same material as the spacer.

[0650] The outer side surface of the limiting member may have a steeper slope than the inner side surface of the limiting member.

[0651] According to the embodiments of the present disclosure described above, a display device having an extremely narrow bezel structure can be provided.

[0652] According to the embodiments of the present disclosure, it is possible to provide a display device having an organic layer overflow prevention structure capable of achieving an extremely narrow frame.

[0653] According to the embodiments of the present disclosure, it is possible to provide a display device including a gate circuit structure within a panel that can achieve an extremely narrow frame.

[0654] According to the embodiments of the present disclosure, it is possible to provide a display device having a touch routing structure capable of achieving an extremely narrow frame.

[0655] According to the embodiments of the present disclosure, the weight of the display device can be reduced by having an extremely narrow frame structure.

[0656] The above description has been presented to enable any person skilled in the art to make and use the technical concepts of the present disclosure, and the above description has been provided in the context of specific applications and their requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical concepts of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the present disclosure.

Claims

1. A display device, comprising: A substrate, the substrate comprising a display area provided with a plurality of sub-pixels and a non-display area located outside the display area; an insulating stack, the insulating stack being located on the substrate and having an outer side surface in the non-display area; A limiting member, the limiting member being located on the insulating laminate; a cathode, the cathode being located on the insulating stack and extending from the display area to a portion of the non-display area and overlapping at least a portion of a top surface of the stopper; a first inorganic layer, the first inorganic layer being located on the cathode and arranged to extend from the display area to the non-display area; an organic layer, the organic layer being located on a portion of the first inorganic layer and having an outer slope; as well as a second inorganic layer, the second inorganic layer being located on the organic layer and being arranged to extend from the display area to the non-display area and being arranged to extend along the outer inclined surface of the organic layer, Wherein, the limiting member is arranged in the non-display area and located outside the organic layer.

2. The display device according to claim 1, further comprising: a bank, the bank being located on the insulating stack and dividing a plurality of light emitting regions, Wherein, the limiting member is arranged on the outside of the embankment.

3. The display device according to claim 1, wherein: The first inorganic layer extends along the top and the outside of the stopper to the outer side of the insulating stack, and Wherein, the second inorganic layer extends to the outer side surface of the insulating stack through the outer inclined surface of the organic layer.

4. The display device according to claim 1, wherein: The outer side surface of the limiting member has a steeper slope than the inner side surface of the limiting member.

5. The display device according to claim 1, further comprising: A bank, the bank is located on the insulating stack and has first to third openings; A first anode to a third anode are located on the insulating stack and overlap with the first opening to the third opening respectively; A first common intermediate layer, commonly disposed on the first anode to the third anode; The first to third light-emitting layers are located on the first common intermediate layer and overlap with the first to third anodes; as well as A second common intermediate layer is disposed on the first light-emitting layer to the third light-emitting layer. Wherein, the first common intermediate layer and the second common intermediate layer contain organic materials, and the common intermediate layer includes the first common intermediate layer and the second common intermediate layer, wherein the cathode is located on the second common intermediate layer, and Wherein, the common intermediate layer and the cathode extend to the top of the limiting member.

6. The display device according to claim 5, further comprising: a covering layer, the covering layer being located between the cathode and the first inorganic layer and being arranged to extend from the display area to the non-display area, Wherein, the covering layer extends along the top and the outer side of the limiting member to the outer side surface of the insulating stack.

7. The display device according to claim 5, wherein: The end of the common intermediate layer and the end of the cathode are located on the stopper, and The end of the cathode protrudes outward more than an upper layer portion of an outer side surface of the stopper and the end of the common intermediate layer.

8. The display device according to claim 5, wherein: The stopper includes a cliff portion, the slope of the cliff portion from the top to the outer side surface is gentle to a point below a predetermined level or to a point where a step exists, and A value obtained by summing the height of the cliff portion of the stopper and the height of the common intermediate layer is greater than the sum of the thickness of the first inorganic layer and the thickness of the second inorganic layer.

9. The display device according to claim 5, wherein: The limiting member comprises: A first stopper on the insulating laminate; and a second stopper on the first stopper, wherein the first stopper comprises the same material as the embankment, and Wherein, the second limiting member comprises the same material as the spacer located on the bank.

10. The display device according to claim 9, wherein: The lower end portion of the outer side surface of the first limiting member protrudes outward further than the upper end portion of the outer side surface of the second limiting member.

11. The display device according to claim 1, wherein: The stopper is disposed on a side surface of an outermost light emitting element among a plurality of light emitting elements corresponding to the plurality of sub-pixels, and has a thickness thicker than an anode of the outermost light emitting element.

12. The display device according to claim 1, wherein: The width of the bottom surface of the limiting member is greater than the width of the top surface of the limiting member.

13. The display device according to claim 1, wherein: The non-display area includes: a first non-display area arranged along a first direction from the display area; From the display area to a second non-display area arranged along a second direction; a third non-display area arranged from the display area in a direction opposite to the first direction; and a fourth non-display area arranged from the display area in a direction opposite to the second direction, Wherein, the first non-display area includes a pad area, and The limiting member is disposed in the non-display area in a ring shape and surrounds the periphery of the organic layer, and the limiting member is located between the display area and the pad area.

14. The display device according to claim 13, further comprising: A display signal line, wherein the display signal line is arranged in the display area; a display connection line, wherein the display connection line electrically connects the display signal line and a display pad disposed in the pad area; as well as a curved organic layer, wherein the curved organic layer is located between the display area and the pad area, Wherein, a portion of the display connection line overlaps with the curved organic layer.

15. The display device according to claim 14, further comprising: The pattern protection layer is configured to surround the end of the display connection line.

16. The display device according to claim 1, further comprising: The patterned organic material is arranged outside the limiting member.

17. The display device according to claim 13, further comprising: a first sensor electrode, disposed on the second inorganic layer and extending along the second direction; as well as a first touch routing line, for electrically connecting the first sensor electrode to a first touch pad disposed in the pad area; wherein the first touch routing line extends to the first non-display area by passing through the display area in the first direction without bypassing the second non-display area and the fourth non-display area, and Wherein, a portion of the first touch routing line extending to the first non-display area overlaps with the limiting member in the first non-display area.

18. The display device according to claim 1, further comprising: an in-panel gate circuit configured to supply a gate signal to the plurality of sub-pixels, Wherein, the gate circuit in the panel is arranged on the substrate and overlaps with the organic layer.

19. The display device according to claim 18, further comprising: A basic circuit layer, on the substrate; a light emitting element layer, located on the basic circuit layer and comprising a plurality of light emitting elements included in the plurality of sub-pixels; as well as a shielding layer, located between the basic circuit layer and the light-emitting element layer, Wherein, the basic circuit layer includes the in-panel gate circuit arranged in the display area.

20. The display device according to claim 19, wherein: A voltage having a predetermined voltage level is applied to the shielding layer.

21. The display device according to claim 19, further comprising: a common driving voltage line, which is disposed on the substrate and supplies a common pixel driving voltage to the cathode, The common driving voltage line is disposed in the display area, and the cathode is electrically connected to the common driving voltage line in the display area.

22. The display device according to claim 19, further comprising: a sub-pixel circuit layer, located between the shielding layer and the light-emitting element layer, and comprising a plurality of sub-pixel circuits for driving a plurality of light-emitting elements; as well as A gate link line connects the panel gate circuit disposed in the basic circuit layer and the plurality of sub-pixel circuits, Wherein, the gate link line overlaps with the organic layer.

23. The display device according to claim 19, wherein: The display area includes a first display area and a second display area, The basic circuit layer includes, in addition to the gate circuit in the panel, a sub-pixel circuit array, and the sub-pixel circuit array includes a plurality of sub-pixel circuits for driving the plurality of light-emitting elements. Wherein, the gate circuit in the panel is arranged in the first display area, Wherein, the sub-pixel circuit array is arranged in the second display area, Wherein, the plurality of light emitting elements include: a first light emitting element disposed in the first display region and overlapping at least a portion of the in-panel gate circuit; and a second light emitting element disposed in the second display area and overlapping at least a portion of the sub-pixel circuit array, and Wherein, the plurality of sub-pixel circuits include: a first sub-pixel circuit configured to drive the first light emitting element and disposed in the second display area; and At least two second sub-pixel circuits are configured to drive the second light emitting element and are disposed in the second display area.

24. The display device according to claim 23, further comprising: an extension link connecting the first sub-pixel circuit disposed in the second display area to the first light-emitting element disposed in the first display area, Wherein, at least a portion of the extended link overlaps with at least a portion of the gate circuit within the panel, and the extended link overlaps with the organic layer.

25. The display device according to claim 23, further comprising: a base voltage line located in at least one of the first display area and the second display area; as well as A cathode connection pattern connects the cathode and the base voltage line and is located in at least one of the first display area and the second display area.

26. A display device comprising: substrate; an insulating laminate on the substrate; A plurality of light emitting elements are disposed on the insulating laminate; an organic layer on the plurality of light emitting elements; as well as A stopper is arranged on the outer side of the organic layer, Wherein, the limiting member is arranged on the outer side surface of the outermost light emitting element among the plurality of light emitting elements, and has a thickness thicker than the anode of the outermost light emitting element.

27. The display device according to claim 26, further comprising: a bank, the bank being used to divide the plurality of light emitting elements; as well as a spacer, located on the bank, Wherein, the limiting member includes a first limiting member on the insulating laminate and a second limiting member on the first limiting member, wherein the first stopper comprises the same material as the embankment, and Wherein, the second limiting member comprises the same material as the spacer.

28. The display device according to claim 26, wherein: The outer side surface of the limiting member has a steeper slope than the inner side surface of the limiting member.

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