MIM capacitor and manufacturing method thereof

Abstract

The invention provides an MIM capacitor and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate which is provided with a first metal wire and a metal bonding pad, and an insulating layer covers the first metal wire and the metal bonding pad; forming a groove in the insulating layer to expose the first metal wire; sequentially forming a first electrode material layer, a first dielectric material layer and a second electrode material layer to cover the surface of the insulating layer and the inner wall of the groove, and executing photoetching to sequentially form a second electrode, a first dielectric layer and a first electrode so as to form a groove capacitor; forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode; forming a first opening to expose the second electrode and a second opening to expose the metal pad; and forming a second metal wire to electrically connect the second electrode and the metal bonding pad. In the invention, the first electrode is led out through the first metal wire at the bottom of the groove, and the second electrode is led out through the second opening between the grooves to be electrically connected with the metal bonding pad, so that the forming, leading-out and electric connection processes of the MIM capacitor are optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a MIM capacitor and a manufacturing method thereof. Background Art

[0002] With the continuous development of semiconductor technology, the application of MIM capacitors (Metal-Insulator-Meta, referred to as MIM) integrated between back-end metal layers is becoming more and more widespread. The application of MIM capacitor structure can reduce the volume of semiconductor devices and make the functions of semiconductor devices more abundant. However, the preparation process of semiconductor devices with MIM capacitor structure is cumbersome, which makes the production efficiency of semiconductor devices with MIM capacitor structure low.

[0003] MIM planar capacitors require a large area to obtain large capacitance, which will sacrifice design area. For this reason, MIM trench capacitors become the best choice for large capacitance.

[0004] In the related art, taking the formation of MIM trench capacitors as an example, trench capacitors (for example, including upper and lower electrodes) are usually formed in a dielectric layer, and then the dielectric layer is opened multiple times (multiple photolithography etching) to form a number of openings to expose the upper and lower electrodes of the trench capacitors, as well as metal wires or metal pads corresponding to the trench capacitors, and then metal aluminum is deposited to form aluminum wires to connect the upper and lower electrodes of the trench capacitors and the corresponding metal wires and metal pads. It is not difficult to see that the process of forming MIM trench capacitors in the related art has a large number of mask layers (number of photolithography times), the process is complicated, and the cost is high. Summary of the invention

[0005] The object of the present invention is to provide a MIM capacitor and a manufacturing method thereof, so as to optimize the formation, lead-out and electrical connection process of the MIM capacitor.

[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a MIM capacitor, comprising:

[0007] Providing a substrate, including a device area and a peripheral area, wherein the device area has a first metal line, the peripheral area has a metal pad arranged in the same layer as the first metal line, and the first metal line and the metal pad are covered with an insulating layer;

[0008] forming a trench in the insulating layer on the first metal line to expose the first metal line;

[0009] Forming a first electrode material layer, a first dielectric material layer, and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the groove, and performing photolithography and etching in sequence to form a second electrode, a first dielectric layer, and an insulating layer covering the groove and its surroundings of the first electrode to form a MIM capacitor, wherein the first electrode is electrically connected to the first metal wire via the groove;

[0010] forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode and fill the trench;

[0011] Forming a first opening in the second dielectric layer to expose the second electrode, and forming a second opening in the second dielectric layer and the insulating layer to expose the metal pad;

[0012] A second metal line is formed to electrically connect the second electrode and the metal pad using the first opening and the second opening.

[0013] Optionally, a dielectric barrier layer is further provided between the first metal line and the metal pad and the insulating layer.

[0014] Optionally, the step of forming the first groove includes:

[0015] forming a first mask to cover the surface of the insulating layer, wherein the first mask has a plurality of openings;

[0016] Performing a first etching process on the insulating layer and the dielectric barrier layer to form the trenches using the openings, wherein at least one of the trenches exposes the first metal line;

[0017] The first mask is removed.

[0018] Optionally, the step of forming the second electrode, the first dielectric layer and the first electrode includes:

[0019] forming a second mask to cover the trench and the second electrode material layer on the surrounding insulating layer;

[0020] Using the second mask, performing a second etching process to sequentially etch the second electrode material layer, the first dielectric material layer, and the first electrode material layer to form the second electrode, the first dielectric layer, and the first electrode;

[0021] The second mask is removed.

[0022] Optionally, the step of forming the second electrode, the first dielectric layer and the first electrode includes:

[0023] forming a second mask to cover the trench and the second electrode material layer on the surrounding insulating layer, and exposing a portion of the second electrode material layer between the trenches;

[0024] Using the second mask, performing a second etching process to sequentially etch the second electrode material layer, the first dielectric material layer, and the first electrode material layer to form a plurality of second electrodes, a plurality of first dielectric layers, and a plurality of first electrodes to form a plurality of trench capacitors connected in parallel to the first metal line;

[0025] The second mask is removed.

[0026] Optionally, the step of forming the first opening includes:

[0027] forming a third mask to cover the surface of the second dielectric layer and expose at least a portion of the second dielectric layer between the grooves;

[0028] Performing a third etching process using the third mask to etch the exposed second dielectric layer to expose a surface of the second electrode;

[0029] The third mask is removed.

[0030] Optionally, the step of forming the second opening includes:

[0031] forming a fourth mask to cover the surface of the second dielectric layer and expose at least a portion of the second dielectric layer above the metal pad;

[0032] Performing a fourth etching process using the fourth mask to sequentially etch the second dielectric layer and the insulating layer to expose the surface of the metal pad;

[0033] The fourth mask is removed.

[0034] Optionally, the step of forming the second metal line includes:

[0035] forming a metal material layer to cover the surface of the second dielectric layer, the first opening and the inner wall of the second opening;

[0036] forming a fifth mask to cover the first opening, the second opening and the metal material layer on the second dielectric layer therebetween;

[0037] A fifth etching process is performed using the fifth mask to remove the exposed metal material layer, and the remaining metal material layer serves as the second metal line.

[0038] Optionally, after forming the second metal line, a third dielectric layer is further formed to cover the second metal line and the second dielectric layer.

[0039] According to another aspect of the present invention, a MIM capacitor is provided, comprising:

[0040] A substrate having a device region and a peripheral region;

[0041] A first metal line and a metal pad, wherein the first metal line is disposed in the device region, and the metal pad and the first metal line are arranged in the peripheral region in the same layer;

[0042] an insulating layer, covering the first metal line and the metal pad, wherein a groove is formed in the insulating layer to expose the first metal line;

[0043] The MIM capacitor comprises a first electrode, a first dielectric layer and a second electrode which sequentially conformally cover the groove and the surrounding insulating layer, wherein the first electrode is electrically connected to the first metal line via the groove;

[0044] a second dielectric layer covering the surfaces of the insulating layer and the second electrode and filling the grooves, wherein the second dielectric layer between the grooves is provided with a first opening to expose the second electrode, and the second dielectric layer and the insulating layer on the metal pad are provided with a second opening to expose the metal pad;

[0045] The second metal wire covers the surface of the second dielectric layer, the first opening and the inner wall of the second opening to electrically connect the second electrode and the metal pad.

[0046] In summary, the present invention exposes the first metal wire in the trench in the insulating layer on the first metal wire, forms a trench capacitor consisting of a first electrode, a first dielectric layer and a second electrode on the trench and the insulating layer on the periphery of the trench, uses the bottom of the trench to expose the first metal wire to complete the lead-out and electrical connection between the first electrode of the trench capacitor and the first metal wire, and uses the second opening provided on the metal pad to expose the metal pad and the first opening above the second electrode provided between the trenches to expose the second electrode to lead out and electrically connect the metal pad and the second electrode, so that the present embodiment only needs five photolithography processes (five masks) to complete the formation, lead-out and electrical connection of the MIM trench capacitor with the first metal wire and the metal pad, thereby having a simple and efficient process flow, which is conducive to reducing costs. Compared with the use of metal materials (such as aluminum) in the related art to fill the gap in the trench capacitor for lead-out, the present invention uses the second dielectric layer to fill the gap in the trench, which is not only conducive to saving electrode materials, but also conducive to reducing the corresponding process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0048] Figure 1 is a flow chart of a method for manufacturing a MIM capacitor provided in Example 1;

[0049] Figure 2a to Figure 2hA schematic structural diagram corresponding to corresponding steps of the method for manufacturing a MIM capacitor provided in Example 1;

[0050] Figure 3a to Figure 3c This is a schematic structural diagram corresponding to the corresponding steps of the method for manufacturing the MIM capacitor provided in Example 2.

[0051] In the attached figure:

[0052] 10-substrate; 11-first metal wire; 12-metal pad; AA-device area; BB-peripheral area; 21-dielectric barrier layer; 22-insulating layer; 23-groove; 31-first electrode material layer; 31a-first electrode; 32-first dielectric material layer; 32a-first dielectric layer; 33-second electrode material layer; 33a-second electrode; 34-gap; 35-second dielectric layer; 36a-first opening; 36b-second opening; 37-second metal wire; 38-third dielectric layer. DETAILED DESCRIPTION

[0053] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0054] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0055] Embodiment 1

[0056] Embodiment 1 provides a method for manufacturing a MIM capacitor.

[0057] Figure 1 4 is a flow chart of a method for manufacturing a MIM capacitor provided in Example 1.

[0058] like Figure 1 As shown, the manufacturing method of the MIM capacitor provided in this embodiment includes:

[0059] S01: providing a substrate, comprising a device region and a peripheral region, wherein the device region has a first metal line, and the peripheral region has a metal pad arranged in the same layer as the first metal line, and the first metal line and the metal pad are covered with an insulating layer;

[0060] S02: forming a groove in the insulating layer on the first metal line to expose the first metal line;

[0061] S03: forming a first electrode material layer, a first dielectric material layer and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the groove, and performing photolithography and etching in sequence to form a second electrode, a first dielectric layer and an insulating layer covering the groove and its surroundings of the first electrode to form a MIM capacitor, wherein the first electrode is electrically connected to the first metal wire via the groove;

[0062] S04: forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode, and filling the groove;

[0063] S05: forming a first opening in the second dielectric layer to expose the second electrode, and forming a second opening in the second dielectric layer and the insulating layer to expose the metal pad;

[0064] S06: forming a second metal line to electrically connect the second electrode and the metal pad using the first opening and the second opening.

[0065] Figure 2a to Figure 2f The structural schematic diagram corresponding to the corresponding steps of the manufacturing method of the MIM capacitor provided in this embodiment, next, Figure 2a to Figure 2f A method for manufacturing the MIM capacitor will be described in detail.

[0066] First, please refer to Figure 2a , perform step S01, provide a substrate 10, including a device area AA and a peripheral area BB, the device area AA has a first metal line 11, the peripheral area BB has a metal pad 12 arranged in the same layer as the first metal line 11, and the first metal line 11 and the metal pad 12 are covered with an insulating layer 22.

[0067] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator, and germanium on insulator, etc. In this embodiment, the material of the substrate 10 is described by taking silicon (silicon substrate) as an example.

[0068] The substrate 10 may include a device area AA and a peripheral area BB, wherein the device area AA is used to form a semiconductor device, and the peripheral area BB is used to form a peripheral circuit, and an interconnection layer is formed on both the semiconductor device and the peripheral circuit. Among them, the first metal line 11 may be a metal wiring of the Nth layer (N is greater than or equal to 1) in the interconnection layer of the device area AA, which can be used to connect to the lower electrode of the MIM trench capacitor, and the metal pad 12 may be a metal wiring arranged in the same layer as the first metal line 11 in the interconnection layer of the peripheral area BB, which is used to connect to the upper electrode of the MIM trench capacitor. In one example, the metal pad 12 may be, for example, a common ground terminal (VSS).

[0069] A dielectric barrier layer 21 and an insulating layer 22 are sequentially covered on the first metal line 11 and the metal pad 12. The material of the dielectric barrier layer 21 is different from that of the insulating layer 22. The material of the dielectric barrier layer 21 can be used to block the escape of metal ions and serve as an etching stop layer during etching. The material of the dielectric barrier layer 21 can include, for example, silicon nitride or silicon carbonitride. In this embodiment, the first metal line 11 and the metal pad 12 can be top-layer metal wiring, and the material can include copper. The material of the dielectric barrier layer 21 can include silicon nitride or silicon oxynitride, and the material of the insulating layer 22 can include silicon oxide.

[0070] In addition, in other examples of this embodiment, as needed, multiple (at least two) first metal wires 11 and multiple metal pads 12 can be set to form multiple trench capacitors connected in parallel to one or at least two metal pads 12, and each trench capacitor can also include one or at least two first metal wires 11.

[0071] Next, please refer to Figure 2b , performing step S02 , forming a trench 23 in the insulating layer 22 on the first metal line 11 to expose the first metal line 11 .

[0072] Specifically, a first mask may be formed to cover the surface of the insulating layer 22, wherein the first mask has a plurality of openings; the first mask is used to perform a first etching process on the insulating layer 22 and the dielectric barrier layer 21, and a plurality of grooves 23 are formed to penetrate the insulating layer 22 and the dielectric barrier layer 21 using the first openings 36a to expose the surface of the first metal line 11; and the first mask is then removed. At least one groove 23 (or a portion thereof) is located above the first metal line 11 to expose the surface of the first metal line 11, and a portion of the grooves 23 may also be located in the insulating layer 22 around the first metal line 11.

[0073] Next, step S03 is performed to sequentially form a first electrode material layer 31, a first dielectric material layer 32 and a second electrode material layer 33 to conformally cover the surface of the insulating layer 22 and the inner wall of the groove 23, and photolithography is performed to sequentially form a second electrode 33a, a first dielectric layer 32a and a first electrode 31a to cover the groove 23 and the insulating layer 22 around it to form a trench capacitor. The first electrode 31a is electrically connected to the first metal line 11 via the groove 23.

[0074] For details, please refer to Figure 2c , forming the first electrode material layer 31, the first dielectric material layer 32 and the second electrode material layer 33 in sequence to conformally cover the surface of the substrate 10, that is, the surface of the insulating layer 22 and the inner wall of the groove 23. Any suitable process can be used to form a thin film conductive layer as the first electrode material layer 31, which may include one or more thin film conductive layers, and its material may include, for example, one or more of titanium, titanium nitride, tantalum or tantalum nitride, and its formation process may include physical vapor deposition, chemical vapor deposition or atomic layer deposition. The thickness of the first electrode material layer 31 may be, for example, 100 angstroms to 400 angstroms. The material of the first dielectric material layer 32 may be a dielectric material with a relatively high dielectric constant, and its dielectric constant may be, for example, greater than or equal to 3.9, and its material may be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide or rhodium oxide. The material of the second electrode material layer 33 may be similar to that of the first electrode material layer 31.

[0075] Next, please refer to Figure 2d , forming a second mask to cover the trench 23 and the second electrode material layer 33 on the surrounding insulating layer 22, and using the second mask, performing a second etching process to sequentially etch the second electrode material layer 33, the first dielectric material layer 32 and the first electrode material layer 31 to form the second electrode 33a, the first dielectric layer 32a and the first electrode 31a, and then removing the second mask. The second electrode 33a, the first dielectric layer 32a and the first electrode 31a may have nearly the same coverage area (coverage area) to form a trench capacitor, and the first metal line 11 at the bottom of the trench 23 is used to lead out the first electrode 31a of the trench capacitor and electrically connect it to the first metal line 11.

[0076] Next, please refer to Figure 2e , step S04 is performed to form a second dielectric layer 35 to cover the surfaces of the insulating layer 22 and the second electrode 33 a and fill the trench 23 .

[0077] The material of the second dielectric layer 35 can be any suitable passivation layer material, such as silicon oxide and / or silicon nitride. The second dielectric layer 35 can also fill the gap 34 in the groove 23 until it is substantially flush with the surface of the second dielectric layer 35 around it. Compared with the use of metal materials (such as aluminum) in the related art to fill the gap 34 in the trench capacitor for extraction, the second dielectric layer 35 is used to fill the gap 34 in the trench 23 in this embodiment, which is not only conducive to saving electrode materials, but also conducive to reducing the difficulty of the corresponding process (such as aluminum filling). It should be understood that since metal aluminum is usually formed by sputtering process, it has high requirements for aluminum sputtering process when filling the gap 34 (relatively long and narrow space), and the trench capacitor in this embodiment does not lead the electrode out of the trench 23, so it is not necessary to use metal materials to fill the gap 34 in the trench 23, that is, the gap 34 is allowed to exist in the trench capacitor in this embodiment (the second dielectric layer 35 is used to fill the gap 34).

[0078] Next, step S05 is performed to form a first opening 36 a in the second dielectric layer 35 to expose the second electrode 33 a , and to form a second opening 36 b in the second dielectric layer 35 and the insulating layer 22 to expose the metal pad 12 .

[0079] Please refer to Figure 2f , a first opening 36a can be formed in the second dielectric layer 35 to expose the second electrode 33a, and the specific steps include: first, forming a third mask to cover the surface of the second dielectric layer 35, the third mask having a plurality of openings to expose at least a portion of the second dielectric layer 35 between the grooves 23; then, using the third mask to perform a third etching process to etch the exposed second dielectric layer 35 to form the first opening 36a to expose the surface of the second electrode 33a between the grooves 23; and then removing the third mask.

[0080] Please refer to Figure 2g , forming a second opening 36b in the second dielectric layer 35 and the insulating layer 22 to expose the metal pad 12, and the specific steps include: first, forming a fourth mask to cover the surface of the second dielectric layer 35, the fourth mask having a plurality of openings to expose at least a portion of the second dielectric layer 35 above the metal pad 12; using the fourth mask to perform a fourth etching process to sequentially etch the second dielectric layer 35, the insulating layer 22 and the dielectric barrier layer 21 to form a second opening 36b to expose the surface of the metal pad 12; and then removing the fourth mask.

[0081] In addition, the present embodiment does not limit the order of forming the first opening 36a and the second opening 36b, that is, it is also feasible to first form the second opening 36b in the second dielectric layer 35 and the insulating layer 22 to expose the metal pad 12, and then form the first opening 36a in the second dielectric layer 35 to expose the second electrode 33a.

[0082] Next, please refer to Figure 2h, step S06 is executed to form a second metal line 37 to electrically connect the second electrode 33a and the metal pad 12 using the first opening 36a and the second opening 36b.

[0083] The specific steps may include: first, forming a metal material layer to cover the surface of the second dielectric layer 35, the inner wall of the first opening 36a and the second opening 36b. The metal material layer may be a metal material suitable for electrical connection with the metal pad 12, such as aluminum. In the present embodiment, the metal material layer includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer and a titanium nitride layer formed in sequence conformally, and all of them may be formed by a sputtering process. Next, a fifth mask is formed to cover the first opening 36a, the second opening 36b and the metal material layer on the second dielectric layer 35 therebetween. The fifth mask is then used to perform a fifth etching process to remove the exposed metal material layer, and the remaining metal material layer is used as the second metal wire 37, which extends from the device area AA to the peripheral area BB and electrically connects the second electrode 33a of the trench capacitor to the metal pad 12.

[0084] Thus, a trench capacitor consisting of a first electrode 31a, a first dielectric layer 32a and a second electrode 33a is formed on the trench 23 and the insulating layer 22 on the periphery of the trench 23. The first metal line 11 is exposed at the bottom of the trench 23 to complete the lead-out and electrical connection between the first electrode 31a of the trench capacitor and the first metal line 11. The metal pad 12 is exposed by the second opening 36b provided on the metal pad 12 and the second electrode 33a is exposed by the first opening 36a above the second electrode 33a provided between the trenches 23 to lead out and electrically connect the metal pad 12 and the second electrode 33a. This embodiment only requires five photolithography processes (five masks) to complete the formation, lead-out and electrical connection of the trench capacitor with the first metal line 11 and the metal pad 12, thereby having a simple and efficient process flow, which is conducive to reducing costs.

[0085] In addition, please continue to refer to Figure 2h After forming the second metal line 37, a third dielectric layer 38 may be formed to cover the second metal line 37 and the second dielectric layer 35 as a protective layer. The third dielectric layer 38 may be made of any suitable passivation layer material, such as silicon oxide and / or silicon nitride.

[0086] Embodiment 2

[0087] Embodiment 2 provides a method for manufacturing a MIM capacitor.

[0088] Figure 1 It is a flow chart of the method for manufacturing the MIM capacitor provided in the second embodiment.

[0089] like Figure 1 As shown, the manufacturing method of the MIM capacitor provided in this embodiment includes:

[0090] S01: providing a substrate, comprising a device region and a peripheral region, wherein the device region has a first metal line, and the peripheral region has a metal pad arranged in the same layer as the first metal line, and the first metal line and the metal pad are covered with an insulating layer;

[0091] S02: forming a groove in the insulating layer on the first metal line to expose the first metal line;

[0092] S03: forming a first electrode material layer, a first dielectric material layer and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the groove, and performing photolithography and etching in sequence to form a second electrode, a first dielectric layer and an insulating layer covering the groove and its surroundings of the first electrode to form a MIM capacitor, wherein the first electrode is electrically connected to the first metal wire via the groove;

[0093] S04: forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode, and filling the groove;

[0094] S05: forming a first opening in the second dielectric layer to expose the second electrode, and forming a second opening in the second dielectric layer and the insulating layer to expose the metal pad;

[0095] S06: forming a second metal line to electrically connect the second electrode and the metal pad using the first opening and the second opening.

[0096] The manufacturing method of the MIM capacitor provided in the second embodiment is similar to the method provided in the first embodiment, and the difference lies mainly in the step of forming the second mask in step S03 of the second embodiment. Figure 3a to Figure 3c A method for manufacturing the MIM capacitor will be described in detail.

[0097] In step S03, please refer to Figure 3a First, a first electrode material layer 31 , a first dielectric material layer 32 and a second electrode material layer 33 are formed in sequence to conformally cover the surface of the substrate 10 , that is, the surface of the insulating layer 22 and the inner wall of the groove 23 .

[0098] Please refer to Figure 3b, forming a second mask to cover the second electrode material layer 33 on the trench 23 and the surrounding insulating layer 22, and using the second mask, performing a second etching process to sequentially etch the second electrode material layer 33, the first dielectric material layer 32 and the first electrode material layer 31 to form the second electrode 33a, the first dielectric layer 32a and the first electrode 31a, and then removing the second mask. Wherein, different from the first embodiment using one second mask to form a trench capacitor, in this embodiment, at least two second masks are used to form a trench capacitor, and adjacent second masks have a gap 34 on the second electrode material layer 33 between the trenches 23, so that after the second etching process, at least two trench capacitors are formed in parallel between the first metal line 11 and the metal pad 12, for improving the overall performance of the capacitor. That is, in this embodiment, at least two first electrodes 31a, at least two first dielectric layers 32a and at least two second electrodes 33a are formed above the first metal line 11 to form at least two trench capacitors, and the first electrode 31a of each trench capacitor is led out using the first metal line 11. It should be understood that, compared with a trench capacitor with the same capacitance, using at least two trench capacitors connected in parallel can have performance advantages such as lower parasitic inductance, and this technical effect is very easy to achieve in the above manufacturing process.

[0099] Next, please refer to Figure 3c , step S06 is performed to form a second metal line 37 to electrically connect the second electrode 33a and the metal pad 12 using the first opening 36a and the second opening 36b. After at least two trench capacitors are formed above the first metal line 11, at least one first opening 36a can be formed above the second electrode 33a of each trench capacitor.

[0100] Embodiment 3

[0101] Embodiment 3 provides a MIM capacitor.

[0102] Figure 2h and Figure 3c A schematic diagram of the structure of a MIM capacitor provided in Example 2.

[0103] The MIM capacitor provided in this embodiment can be formed by the method provided in the first embodiment or the second embodiment. Figure 2h or Figure 3cAs shown, the MIM capacitor may include a substrate 10, a first metal line 11, a metal pad 12, an insulating layer 22, a MIM capacitor, a second dielectric layer 35 and a second metal line 37. The substrate 10 has a device area AA and a peripheral area BB, the device area AA is used to form a semiconductor device, and the peripheral area BB is used to form a peripheral circuit. The first metal line 11 is arranged in the device area AA of the substrate 10, and the metal pad 12 is arranged in the peripheral area BB of the substrate 10 in the same layer as the metal line. The insulating layer 22 covers the surface of the substrate 10, that is, covers the first metal line 11 and the metal pad 12, and a plurality of grooves 23 are formed in the insulating layer 22 on the first metal line 11 to expose the first metal line 11. The MIM capacitor (MIM trench capacitor) is formed on the trench 23 and the insulating layer 22 around it, including a first electrode 31a, a first dielectric layer 32a and a second electrode 33a that sequentially conformally covers the trench 23 and the insulating layer 22 around it, and the first electrode 31a is electrically connected to the first metal line 11 by the trench 23. The second dielectric layer 35 covers the surface of the insulating layer 22 and the second electrode 33a, and fills the trench 23. The second dielectric layer 35 between the trenches 23 is provided with a first opening 36a penetrating the second dielectric layer 35 to expose the second electrode 33a of the trench capacitor. The second dielectric layer 35 and the insulating layer 22 on the metal pad 12 are provided with a second opening 36b penetrating the second dielectric layer 35 and the insulating layer 22 to expose the metal pad 12. The second metal wire 37 covers the surface of the second dielectric layer 35, the inner wall of the first opening 36a and the second opening 36b to electrically connect the second electrode 33a and the metal pad 12.

[0104] In summary, the present invention exposes the first metal wire in the trench in the insulating layer on the first metal wire, forms a trench capacitor consisting of a first electrode, a first dielectric layer and a second electrode on the trench and the insulating layer on the periphery of the trench, uses the bottom of the trench to expose the first metal wire to complete the lead-out and electrical connection between the first electrode of the trench capacitor and the first metal wire, and uses the second opening provided on the metal pad to expose the metal pad and the first opening above the second electrode provided between the trenches to expose the second electrode to lead out and electrically connect the metal pad and the second electrode, so that the present embodiment only needs five photolithography processes (five masks) to complete the formation, lead-out and electrical connection of the MIM trench capacitor with the first metal wire and the metal pad, thereby having a simple and efficient process flow, which is conducive to reducing costs. Compared with the use of metal materials (such as aluminum) in the related art to fill the gap in the trench capacitor for lead-out, the present invention uses the second dielectric layer to fill the gap in the trench, which is not only conducive to saving electrode materials, but also conducive to reducing the corresponding process difficulty.

[0105] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a MIM capacitor, characterized in that: include: Providing a substrate, including a device area and a peripheral area, wherein the device area has a first metal line, the peripheral area has a metal pad arranged in the same layer as the first metal line, and the first metal line and the metal pad are covered with an insulating layer; forming a trench in the insulating layer on the first metal line to expose the first metal line; Forming a first electrode material layer, a first dielectric material layer, and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the groove, and performing photolithography and etching in sequence to form a second electrode, a first dielectric layer, and an insulating layer covering the groove and its surroundings of the first electrode to form a MIM capacitor, wherein the first electrode is electrically connected to the first metal wire via the groove; forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode and fill the trench; Forming a first opening in the second dielectric layer to expose the second electrode, and forming a second opening in the second dielectric layer and the insulating layer to expose the metal pad; A second metal line is formed to electrically connect the second electrode and the metal pad using the first opening and the second opening.

2. The method for manufacturing a MIM capacitor according to claim 1, characterized in that: A dielectric barrier layer is also provided between the first metal line, the metal pad and the insulating layer.

3. The method for manufacturing a MIM capacitor according to claim 2, characterized in that: The steps of forming the groove include: forming a first mask to cover the surface of the insulating layer, wherein the first mask has a plurality of openings; Performing a first etching process on the insulating layer and the dielectric barrier layer to form the trenches using the openings, wherein at least one of the trenches exposes the first metal line; The first mask is removed.

4. The method for manufacturing a MIM capacitor according to claim 1, characterized in that: The steps of forming the second electrode, the first dielectric layer and the first electrode include: forming a second mask to cover the trench and the second electrode material layer on the surrounding insulating layer; Using the second mask, performing a second etching process to sequentially etch the second electrode material layer, the first dielectric material layer, and the first electrode material layer to form the second electrode, the first dielectric layer, and the first electrode; The second mask is removed.

5. The method for manufacturing a MIM capacitor according to claim 1, characterized in that: The steps of forming the second electrode, the first dielectric layer and the first electrode include: forming a second mask to cover the trench and the second electrode material layer on the surrounding insulating layer, and exposing a portion of the second electrode material layer between the trenches; Using the second mask, performing a second etching process to sequentially etch the second electrode material layer, the first dielectric material layer, and the first electrode material layer to form a plurality of second electrodes, a plurality of first dielectric layers, and a plurality of first electrodes to form a plurality of trench capacitors connected in parallel to the first metal line; The second mask is removed.

6. The method for manufacturing a MIM capacitor according to claim 1, wherein: The step of forming the first opening comprises: forming a third mask to cover the surface of the second dielectric layer and expose at least a portion of the second dielectric layer between the grooves; Performing a third etching process using the third mask to etch the exposed second dielectric layer to expose a surface of the second electrode; The third mask is removed.

7. The method for manufacturing a MIM capacitor according to claim 1 or 6, characterized in that: The step of forming the second opening comprises: forming a fourth mask to cover the surface of the second dielectric layer and expose at least a portion of the second dielectric layer above the metal pad; Performing a fourth etching process using the fourth mask to sequentially etch the second dielectric layer and the insulating layer to expose the surface of the metal pad; The fourth mask is removed.

8. The method for manufacturing a MIM capacitor according to claim 1, characterized in that: The step of forming the second metal line includes: forming a metal material layer to cover the surface of the second dielectric layer, the first opening and the inner wall of the second opening; forming a fifth mask to cover the first opening, the second opening and the metal material layer on the second dielectric layer therebetween; A fifth etching process is performed using the fifth mask to remove the exposed metal material layer, and the remaining metal material layer serves as the second metal line.

9. The method for manufacturing a MIM capacitor according to claim 1, characterized in that: After forming the second metal line, a third dielectric layer is formed to cover the second metal line and the second dielectric layer.

10. A MIM capacitor, characterized in that: include: A substrate having a device region and a peripheral region; A first metal line and a metal pad, wherein the first metal line is disposed in the device region, and the metal pad and the first metal line are arranged in the peripheral region in the same layer; an insulating layer, covering the first metal line and the metal pad, wherein a groove is formed in the insulating layer to expose the first metal line; The MIM capacitor comprises a first electrode, a first dielectric layer and a second electrode which sequentially conformally cover the groove and the surrounding insulating layer, wherein the first electrode is electrically connected to the first metal line via the groove; a second dielectric layer covering the surfaces of the insulating layer and the second electrode and filling the grooves, wherein the second dielectric layer between the grooves is provided with a first opening to expose the second electrode, and the second dielectric layer and the insulating layer on the metal pad are provided with a second opening to expose the metal pad; The second metal wire covers the surface of the second dielectric layer, the first opening and the inner wall of the second opening to electrically connect the second electrode and the metal pad.

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