Metal-insulator-metal capacitor and manufacturing method thereof

By forming trenches and through holes in the insulating layer, and forming electrodes and dielectric layers in sequence around the trench, the problem of cumbersome preparation process of metal-insulator-metal capacitors in the prior art is solved, and simple and efficient Process flow and cost reduction.

CN119451562APending Publication Date: 2025-02-14SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO LTD
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Patent Information

Application Number
CN202310948111.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2023-07-31
Publication Date
2025-02-14

AI Technical Summary

Technical Problem

The preparation process of existing metal-insulator-metal capacitors is complicated, the production efficiency is low, and the number of photomask layers is large, the process is complicated, and the cost is high.

Method used

Trenches and through holes are formed simultaneously in the insulating layer, metal wires are exposed by the trench, metal pads are exposed by the through holes, and first electrodes and first dielectrics are formed in sequence on the insulating layer around the trench and its surroundings in order to conformally form the first electrodes and first dielectrics in sequence on the insulating layer of the trench and its surroundings. The layer and the second electrode to form a trench capacitance and extend the second electrode from the device region to the peripheral region for electrical connection with the metal pad.

Benefits of technology

The capacitor formation, extraction and electrical connection processes are simplified, and can be completed in only four lithography processes, reducing costs, saving electrode materials and reducing process difficulty.

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Abstract

The invention provides a metal-insulator-metal capacitor and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate which comprises a device region and a peripheral region, the device region is provided with a metal wire, the peripheral region is provided with a metal bonding pad which is arranged on the same layer as the metal wire, and an insulating layer covers the metal wire and the metal bonding pad; a groove and a through hole are formed in the insulating layer, the metal wire is exposed by the groove, and the metal bonding pad is exposed by the through hole; a first electrode and a first dielectric layer are sequentially formed on the groove and the insulating layer around the groove in a conformal mode, and the first electrode is electrically connected with the metal wire through the groove; forming a second electrode to cover the first dielectric layer, and extending to cover the inner wall of the through hole so as to be electrically connected with the metal bonding pad; and forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode, and filling the groove and the through hole. According to the invention, the leading-out and electric connection of the first electrode and the second electrode of the single-layer capacitor are completed while the single-layer capacitor is formed, so that the forming, leading-out and electric connection processes of the single-layer capacitor are optimized.
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Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a metal-insulator-metal capacitor and a manufacturing method thereof. Background Art

[0002] With the continuous development of semiconductor technology, the application of metal-insulator-metal capacitors (Metal-Insulator-Meta, referred to as MIM) integrated between back-end metal layers is becoming more and more widespread. The application of metal-insulator-metal capacitor structures can reduce the volume of semiconductor devices, making the functions of semiconductor devices more abundant. However, the preparation process of semiconductor devices with metal-insulator-metal capacitor structures is cumbersome, which makes the production efficiency of semiconductor devices with metal-insulator-metal capacitor structures low.

[0003] Metal-insulator-metal capacitors (MIMCs) planar capacitors require a large area to obtain large capacitance, which sacrifices design area. For this reason, metal-insulator-metal capacitors (MIMCs) trench capacitors become the best choice for large capacitance.

[0004] In the related art, taking the formation of a metal-insulator-metal capacitor trench capacitor as an example, a trench capacitor (for example, including an upper electrode and a lower electrode) is usually formed in a dielectric layer, and then the dielectric layer is opened multiple times (multiple photolithography etchings) to form a number of openings to expose the upper electrode and the lower electrode of the trench capacitor, and the metal wires or metal pads corresponding to the trench capacitor, and then metal aluminum is deposited to form aluminum wires to connect the upper electrode and the lower electrode of the trench capacitor and the corresponding metal wires and metal pads. It is not difficult to see that the process of forming a metal-insulator-metal capacitor trench capacitor in the related art has a large number of mask layers (number of photolithography times), the process is complicated, and the cost is high. Summary of the invention

[0005] The object of the present invention is to provide a metal-insulator-metal capacitor and a manufacturing method thereof, so as to optimize the formation, lead-out and electrical connection process of the trench capacitor.

[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a metal-insulator-metal capacitor, comprising:

[0007] Providing a substrate, comprising a device area and a peripheral area, wherein the device area has a metal wire, the peripheral area has a metal pad arranged in the same layer as the metal wire, and an insulating layer covers the metal wire and the metal pad;

[0008] forming a groove and a through hole in the insulating layer, wherein the groove exposes the metal line and the through hole exposes the metal pad;

[0009] Conformally forming a first electrode and a first dielectric layer on the trench and the insulating layer around it, wherein the first electrode is electrically connected to the metal wire via the trench;

[0010] forming a second electrode to cover the first dielectric layer and extend to cover the inner wall of the through hole so as to be electrically connected to the metal pad;

[0011] A second dielectric layer is formed to cover the surfaces of the insulating layer and the second electrode and to fill the trench and the through hole.

[0012] Optionally, a dielectric barrier layer is further provided between the metal wire and the metal pad and the insulating layer.

[0013] Optionally, the step of forming the first groove and the through hole includes:

[0014] Forming a first mask to cover the surface of the insulating layer, wherein the first mask has a first opening and a second opening;

[0015] Performing a first etching process on the insulating layer and the dielectric barrier layer, forming the trench using the first opening, and simultaneously forming the through hole using the second opening, wherein the through hole is located above the metal pad, and at least one of the trenches is located above the metal line;

[0016] The first mask is removed.

[0017] Optionally, the step of forming the first electrode includes:

[0018] forming a first electrode material layer to cover the surface of the insulating layer, the groove and the inner wall of the through hole;

[0019] The second mask covers the trench, the through hole and the first electrode material layer on the surrounding insulating layer of the trench and the through hole;

[0020] Performing a second etching process on the first electrode material layer, using the first electrode material layer on the trench and the insulating layer around it as the first electrode, and retaining the first electrode material layer covering the inner wall of the through hole and the insulating layer around it;

[0021] The second mask is removed.

[0022] Optionally, the step of forming the first dielectric layer includes:

[0023] forming a first dielectric material layer to cover the insulating layer, the first electrode and the through hole;

[0024] forming a third mask to cover the first electrode and the insulating layer around it;

[0025] Performing a third etching process on the first dielectric material layer, using the first dielectric material layer on the first electrode and the surrounding insulating layer as the first dielectric layer, and at least exposing the first electrode material layer on the bottom wall of the through hole;

[0026] The third mask is removed.

[0027] Optionally, the step of forming the first electrode includes:

[0028] forming a first electrode material layer to cover the surface of the insulating layer, the groove and the inner wall of the through hole;

[0029] forming a second mask to cover the first electrode material layer on the trench and the surrounding insulating layer;

[0030] Performing a second etching process on the first electrode material layer, using the first electrode material layer on the insulating layer around the trench and the first electrode material layer as the first electrode, and at least partially exposing the metal pad on the bottom wall of the through hole;

[0031] The second mask is removed.

[0032] Optionally, the step of forming the first dielectric layer includes:

[0033] forming a first dielectric material layer to cover the insulating layer, the first electrode and the through hole;

[0034] forming a third mask to cover the first electrode and the insulating layer around it;

[0035] Performing a third etching process on the first dielectric material layer, using the first dielectric material layer on the first electrode and the surrounding insulating layer as the first dielectric layer, and at least partially exposing the metal pad on the bottom wall of the through hole;

[0036] The third mask is removed.

[0037] Optionally, the step of forming the second electrode includes:

[0038] forming a second electrode material layer to cover the insulating layer, the first dielectric layer and the through hole;

[0039] forming a fourth mask to cover the first dielectric layer, the through hole, and the second electrode material layer on the insulating layer from the trench to the through hole;

[0040] Performing a fourth etching process on the second electrode material layer, using the first dielectric layer, the inner wall of the through hole, and the second electrode material layer on the insulating layer from the trench to the through hole as the second electrode;

[0041] The fourth mask is removed.

[0042] Optionally, the material of the first electrode material layer and the second electrode material layer includes one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

[0043] According to another aspect of the present invention, there is also provided a metal-insulator-metal capacitor, comprising:

[0044] A substrate having a device region and a peripheral region;

[0045] A metal wire and a metal pad, wherein the metal wire is arranged in the device area, and the metal pad and the metal wire are arranged in the peripheral area in the same layer;

[0046] An insulating layer covering the metal line and the metal pad, wherein a groove is formed in the insulating layer to expose the metal line, and a through hole is formed to expose the metal pad;

[0047] A capacitor, comprising a first electrode, a first dielectric layer and a second electrode, which sequentially conformally cover the groove and the surrounding insulating layer, wherein the first electrode is electrically connected to the metal wire by using the groove, and the second electrode extends from the groove to cover the inner wall of the through hole to be electrically connected to the metal pad;

[0048] The second dielectric layer covers the surfaces of the insulating layer and the second electrode and fills the groove and the through hole.

[0049] In summary, the present invention forms a groove and a through hole in the insulating layer at the same time, uses the groove to expose the metal wire, uses the through hole to expose the metal pad, and then conformally forms the first electrode, the first dielectric layer and the second electrode on the insulating layer around the groove and the surrounding area to form a groove capacitor, and the second electrode is extended from the device area to the peripheral area, that is, the groove capacitor is extended to cover the inner wall of the through hole, so that the second electrode is electrically connected to the metal pad, thereby completing the lead-out and electrical connection of the first electrode and the second electrode of the capacitor while forming the capacitor. That is, when forming the first electrode, the metal wire exposed at the bottom of the groove is used to complete the lead-out of the first electrode of the capacitor and the electrical connection with the metal wire, and when forming the second electrode, the second electrode is extended from the groove to the through hole to realize the lead-out of the second electrode and the electrical connection with the metal pad, so that the present embodiment only needs four photolithography processes (four masks) to complete the formation, lead-out and electrical connection of the capacitor with the metal wire and the metal pad, so that it has a simple and efficient process flow, which is conducive to reducing costs. Compared with the related art that uses metal materials (such as aluminum) to fill the gaps in the trench capacitors for lead-out, the present invention uses a second dielectric layer to fill the gaps in the trenches, which is not only beneficial for saving electrode materials, but also beneficial for reducing the corresponding process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0051] Figure 1 is a flow chart of a method for manufacturing a metal-insulator-metal capacitor provided in Example 1;

[0052] Figure 2a to Figure 2f A schematic structural diagram corresponding to corresponding steps of the method for manufacturing a metal-insulator-metal capacitor provided in Example 1;

[0053] Figure 3a to Figure 3c This is a schematic structural diagram corresponding to the corresponding steps of the method for manufacturing a metal-insulator-metal capacitor provided in Example 2.

[0054] In the attached figure:

[0055] 10-substrate; 11-metal wire; 12-metal pad; AA-device area; BB-peripheral area; 21-dielectric barrier layer; 22-insulating layer; 23-groove; 24-through hole; 31-first electrode; 32-first electrode material layer; 33-first dielectric layer; 34-first dielectric material layer; 35-second electrode; 36-second dielectric layer; 37-gap. DETAILED DESCRIPTION

[0056] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0057] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0058] Embodiment 1

[0059] Embodiment 1 provides a method for manufacturing a metal-insulator-metal capacitor.

[0060] Figure 1 It is a flow chart of the method for manufacturing a metal-insulator-metal capacitor provided in the first embodiment.

[0061] like Figure 1 As shown, the manufacturing method of the metal-insulator-metal capacitor provided in this embodiment includes:

[0062] S01: providing a substrate, comprising a device region and a peripheral region, wherein the device region has a metal wire, the peripheral region has a metal pad arranged in the same layer as the metal wire, and an insulating layer covers the metal wire and the metal pad;

[0063] S02: forming a groove and a through hole in the insulating layer, wherein the groove exposes the metal line, and the through hole exposes the metal pad;

[0064] S03: conformally forming a first electrode and a first dielectric layer on the trench and the insulating layer around it, wherein the first electrode is electrically connected to the metal wire via the trench;

[0065] S04: forming a second electrode to cover the first dielectric layer and extend to cover the inner wall of the through hole to be electrically connected to the metal pad;

[0066] S05: forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode, and to fill the trench and the through hole.

[0067] Figure 2a to Figure 2f The structural schematic diagram corresponding to the corresponding steps of the method for manufacturing the metal-insulator-metal capacitor provided in this embodiment, and then Figure 2a to Figure 2f A method for manufacturing the metal-insulator-metal capacitor is described in detail.

[0068] First, please refer to Figure 2a , perform step S01, provide a substrate 10, including a device area AA and a peripheral area BB, the device area AA has a metal line 11, the peripheral area BB has a metal pad 12 arranged in the same layer as the metal line 11, and the insulating layer 22 covers the metal line 11 and the metal pad 12.

[0069] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator, and germanium on insulator, etc. In this embodiment, the material of the substrate 10 is described by taking silicon (silicon substrate) as an example.

[0070] The substrate 10 may include a device area AA and a peripheral area BB, wherein the device area AA is used to form a semiconductor device, and the peripheral area BB is used to form a peripheral circuit, and an interconnection layer is formed on both the semiconductor device and the peripheral circuit. Among them, the metal line 11 may be a metal wiring of the Nth layer (N is greater than or equal to 1) in the interconnection layer of the device area AA, which can be used to connect to the lower electrode of the trench capacitor, and the metal pad 12 may be a metal wiring arranged in the same layer as the metal line 11 in the interconnection layer of the peripheral area BB, which is used to connect to the upper electrode of the trench capacitor. In one example, the metal pad 12 may be, for example, a common ground terminal (VSS).

[0071] A dielectric barrier layer 21 and an insulating layer 22 are sequentially covered on the metal line 11 and the metal pad 12. The material of the dielectric barrier layer 21 is different from that of the insulating layer 22. The material of the dielectric barrier layer 21 can be used to block the escape of metal ions and serve as an etching stop layer during etching. The material of the dielectric barrier layer 21 can include, for example, silicon nitride or silicon carbonitride. In this embodiment, the metal line 11 and the metal pad 12 can be top-layer metal wiring, the material of which can include copper, the material of the dielectric barrier layer 21 can include silicon nitride or silicon oxynitride, and the material of the insulating layer 22 can include silicon oxide.

[0072] In addition, in other examples of this embodiment, as needed, multiple (at least two) metal wires 11 and multiple metal pads 12 can be set to form multiple trench capacitors connected in parallel to one or at least two metal pads 12, and each trench capacitor can also include one or at least two metal wires 11.

[0073] Next, please refer to Figure 2b , step S02 is performed to form a groove 23 and a through hole 24 in the insulating layer 22 , wherein the groove 23 exposes the metal line 11 and the through hole 24 exposes the metal pad 12 .

[0074] Specifically, a first mask may be formed to cover the surface of the insulating layer 22, wherein the first mask has a plurality of first openings and a plurality of second openings; a first etching process may be performed on the insulating layer 22 and the dielectric barrier layer 21 using the first mask, and a plurality of grooves 23 may be formed through the insulating layer 22 and the dielectric barrier layer 21 using the first openings to expose the surface of the metal wire 11, and a plurality of through holes 24 may be formed through the insulating layer 22 and the dielectric barrier layer 21 using the second openings to expose the surface of the metal pad 12; and then the first mask may be removed. Among them, at least one groove 23 (or a part of it) is located above the metal wire 11 to expose the surface of the metal wire 11, and a part of the grooves 23 may also be located in the insulating layer 22 around the metal wire 11, and the through holes 24 are all located above the metal pad 12.

[0075] Next, step S03 is performed to conformally form a first electrode 31 and a first dielectric layer 33 on the trench 23 and the insulating layer 22 around it. The first electrode 31 is electrically connected to the metal line 11 via the trench 23 .

[0076] For details, please refer to Figure 2c , forming the first electrode 31, the specific steps include: forming a first electrode material layer 32 to cover the surface of the insulating layer 22, the groove 23 and the inner wall of the through hole 24. Any suitable process can be used to form a thin film conductive layer as the first electrode material layer 32, which may include one or more thin film conductive layers, and its material may include one or more of titanium, titanium nitride, tantalum or tantalum nitride, for example, and its formation process may include physical vapor deposition, chemical vapor deposition or atomic layer deposition, and the thickness of the first electrode material layer 32 may be, for example, 100 angstroms to 400 angstroms. Next, a second mask is formed to cover the first electrode material layer 32 on the groove 23, the through hole 24 and the insulating layer 22 around them. Next, a second etching process is performed on the first electrode material layer 32 using a second mask to remove the exposed first electrode material layer 32, and then the second mask is removed, so that the first electrode material layer 32 on the groove 23 and the insulating layer 22 around it serves as the first electrode 31, and the first electrode material layer 32 is retained to cover the inner wall of the through hole 24 and the surrounding insulating layer 22 to be electrically connected to the metal pad 12.

[0077] Next, please refer to Figure 2d , forming a first dielectric layer 33 on the first electrode 31, the specific steps of which include: forming a first dielectric material layer to cover the surface of the substrate 10, that is, the insulating layer 22, the surface of the first electrode 31 and the inner wall of the through hole 24. The material of the first dielectric material layer can be a dielectric material with a relatively high dielectric constant, and its dielectric constant can be, for example, greater than or equal to 3.9, and its material can be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide or rhodium oxide. Then, a third mask is formed to cover the first electrode 31 and the insulating layer 22 around it, exposing the first dielectric material layer around the through hole 24. Then, using the third mask, a third etching process is performed on the first dielectric material layer to remove the exposed first dielectric material layer, and then the third mask is removed, so that the remaining first dielectric material layer on the first electrode 31 and the insulating layer 22 around it is used as the first dielectric layer 33, and at least the first electrode material layer 32 on the bottom wall of the through hole 24 is exposed. The formed first dielectric layer 33 covers the first electrode 31 and extends to cover the insulating layer 22 around the first electrode 31 to completely enclose the first electrode 31 to form better electrical isolation.

[0078] In a preferred example, the cross-sectional shape of the through hole 24 may be in an inverted trapezoidal shape, and the inner wall of the through hole 24 is covered with a first electrode material layer 32 as a protective layer and the etching intensity (e.g., etching time) of the first dielectric material layer 34 is appropriately increased, so that when removing the first dielectric material layer 34 exposed on the insulating layer 22, the first dielectric material layer 34 on the bottom wall and the side wall of the through hole 24 is removed simultaneously, so as to expose the first electrode material layer 32 on the inner wall of the through hole 24 as much as possible, thereby facilitating the reduction of contact resistance. Of course, in practice, part of the first dielectric material layer 34 may also be retained on the side wall of the through hole 24.

[0079] Next, please refer to Figure 2e , step S04 is performed to form a second electrode 35 to cover the first dielectric layer 33 and extend to cover the inner wall of the through hole 24 to be electrically connected to the metal pad 12 .

[0080] Specifically, a second electrode 35 material layer may be first formed to cover the surface of the substrate 10, that is, the surface of the insulating layer 22, the surface of the first dielectric layer 33, and the inner wall of the through hole 24. The material of the second electrode 35 material layer may be similar to that of the first electrode material layer 32. Next, a fourth mask is formed to cover the first dielectric layer 33, the through hole 24, and the second electrode 35 material layer on the insulating layer 22 from the groove 23 to the through hole 24. Next, a fourth etching process is performed on the second electrode 35 material layer to remove the exposed second electrode 35 material layer, and then the fourth mask is removed, and the remaining second electrode 35 material layer on the first dielectric layer 33, the inner wall of the through hole 24, and the insulating layer 22 from the groove 23 to the through hole 24 is used as the second electrode 35. The second electrode 35 extends from above the groove 23 to above the through hole 24, and is electrically connected to the metal pad 12 using the first electrode material layer 32 in the through hole 24.

[0081] Thus, a trench capacitor consisting of a first electrode 31, a first dielectric layer 33 and a second electrode 35 is formed in the trench 23 and on the insulating layer 22 around the trench 23. The metal line 11 is exposed at the bottom of the trench 23 to complete the lead-out and electrical connection between the first electrode 31 of the trench capacitor and the metal line 11. After the through hole 24 is formed to expose the first electrode material layer 32 (i.e., the metal pad 12), the second electrode 35 extending from the trench 23 to the through hole 24 is formed to simultaneously form the lead-out of the second electrode 35 of the trench capacitor and the electrical connection with the metal pad 12. Moreover, the above-mentioned trench 23 and the through hole 24 are formed in the same photolithography process (first mask), so that the present embodiment only needs four etching processes (four masks) to complete the formation, lead-out and electrical connection of the trench capacitor with the metal line 11 and the metal pad 12, thereby having a simple and efficient process flow, which is conducive to reducing costs.

[0082] Next, please refer to Figure 2f, step S05 is performed to form a second dielectric layer 36 to cover the surfaces of the insulating layer 22 and the second electrode 35 , and to fill the trench 23 and the through hole 24 .

[0083] The material of the second dielectric layer 36 can be any suitable passivation layer material, such as silicon oxide and / or silicon nitride. The second dielectric layer 36 can also fill the groove 23 and the through hole 24 until it is substantially flush with the surface of the surrounding second dielectric layer 36. Compared with the use of metal materials (such as aluminum) in the related art to fill the gap 37 in the trench capacitor for extraction, the second dielectric layer 36 is used to fill the gap 37 in the trench 23 in this embodiment, which is not only conducive to saving electrode materials, but also conducive to reducing the difficulty of the corresponding process (such as aluminum filling). It should be understood that since metal aluminum is usually formed by sputtering process, it has higher requirements for aluminum sputtering process when filling the gap 37 (relatively long and narrow space), and the trench capacitor in this embodiment does not lead the electrode out of the trench 23, so it is not necessary to use metal materials to fill the gap 37 in the trench 23, that is, the gap 37 is allowed to exist in the trench capacitor in this embodiment (the second dielectric layer 36 is used to fill the gap 37).

[0084] Embodiment 2

[0085] Embodiment 2 provides a method for manufacturing a metal-insulator-metal capacitor.

[0086] Figure 1 It is a flow chart of the method for manufacturing a metal-insulator-metal capacitor provided in the second embodiment.

[0087] like Figure 1 As shown, the manufacturing method of the metal-insulator-metal capacitor provided in this embodiment includes:

[0088] S01: providing a substrate, comprising a device region and a peripheral region, wherein the device region has a metal wire, the peripheral region has a metal pad arranged in the same layer as the metal wire, and an insulating layer covers the metal wire and the metal pad;

[0089] S02: forming a groove and a through hole in the insulating layer, wherein the groove exposes the metal line, and the through hole exposes the metal pad;

[0090] S03: conformally forming a first electrode and a first dielectric layer on the trench and the insulating layer around it, wherein the first electrode is electrically connected to the metal wire via the trench;

[0091] S04: forming a second electrode to cover the first dielectric layer and extend to cover the inner wall of the through hole to be electrically connected to the metal pad;

[0092] S05: forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode, and to fill the trench and the through hole.

[0093] The method for manufacturing a metal-insulator-metal capacitor provided in the second embodiment is similar to the method provided in the first embodiment, and the difference lies mainly in the step of forming the first electrode in step S03 of the second embodiment. Figure 3a to Figure 3c The schematic diagram of the structure corresponding to the corresponding steps of forming the metal-insulator-metal capacitor provided in the second embodiment. Next, Figure 3a to Figure 3c A method for manufacturing the metal-insulator-metal capacitor is described in detail.

[0094] Please refer to Figure 3a , forming the first electrode 31, the specific steps include: forming a first electrode material layer 32 to cover the surface of the insulating layer 22, the groove 23 and the inner wall of the through hole 24. Then, a second mask is formed to cover the first electrode material layer 32 on the insulating layer 22 in the groove 23 and its periphery. Different from the second mask in the first embodiment, the second mask in this embodiment also exposes the first electrode material layer 32 in the through hole 24 and its periphery. Then, using the second mask, a second etching process is performed on the first electrode material layer 32 to remove the exposed first electrode material layer 32, and then the second mask is removed, so that the first electrode material layer 32 on the insulating layer 22 in the groove 23 and its periphery is used as the first electrode 31. Among them, since the first electrode material layer 32 in the through hole 24 and its periphery is not protected by the mask, the first electrode material layer 32 on the bottom wall of the through hole 24 can be removed to expose the surface of the metal pad 12, and the first electrode material layer 32 on the side wall of the through hole 24 can be retained. Of course, it is also feasible that part of the first electrode material layer 32 is still retained on the bottom wall of the through hole 24 (only part of the surface of the metal pad 12 is exposed).

[0095] Please refer to Figure 3b, forming the first dielectric layer 33, the specific steps of which include: forming a first dielectric material layer 34 to cover the surface of the substrate 10, that is, the surface of the insulating layer 22, the first electrode 31 and the inner wall of the through hole 24. Then, forming a third mask to cover the first electrode 31 and the insulating layer 22 around it, exposing the first dielectric material layer 34 around the through hole 24. Then, using the third mask, performing a third etching process on the first dielectric material layer 34 to remove the exposed first dielectric material layer 34, and then removing the third mask, using the remaining first electrode 31 and the first dielectric material layer 34 on the insulating layer 22 around it as the first dielectric layer 33, and at least partially exposing the metal pad 12 and / or the first electrode material layer 32 on the bottom wall of the through hole 24 (if the first electrode material layer 32 is still retained on the surface of the metal pad 12). Part of the first dielectric material layer 34 may also be retained on the side wall of the through hole 24. The formed first dielectric layer 33 covers the first electrode 31 and extends to cover the insulating layer 22 around the first electrode 31 to completely enclose the first electrode 31 to form better electrical isolation.

[0096] Please refer to Figure 3c , and sequentially form a second electrode 35 and a second dielectric layer 36.

[0097] Embodiment 3

[0098] Embodiment 3 provides a metal-insulator-metal capacitor.

[0099] The metal-insulator-metal capacitor provided in this embodiment can be formed by the method provided in the first embodiment or the second embodiment. Figure 2f or Figure 3cAs shown, the metal-insulator-metal capacitor provided in this embodiment may include a substrate 10, a metal line 11, a metal pad 12, an insulating layer 22, a trench capacitor and a second dielectric layer 36. The substrate 10 has a device area AA and a peripheral area BB, the device area AA is used to form a semiconductor device, and the peripheral area BB is used to form a peripheral circuit. The metal line 11 is arranged in the device area AA of the substrate 10, and the metal pad 12 is arranged in the same layer as the metal line 11 in the peripheral area BB of the substrate 10. The insulating layer 22 covers the device area AA and the peripheral area BB of the substrate 10, that is, covers the surface of the metal line 11 and the metal pad 12, and a plurality of grooves 23 are formed in the insulating layer 22 on the metal line 11 to expose the metal line 11, and a plurality of through holes 24 are formed in the insulating layer 22 on the metal pad 12 to expose the metal pad 12. The trench capacitor is formed on the trench 23 and the insulating layer 22 around it, and includes a first electrode 31, a first dielectric layer 33 and a second electrode 35 formed in sequence conformally. The first electrode 31 is electrically connected to the metal line 11 using the bottom of the trench 23. The second electrode 35 covers the surface of the first dielectric layer 33 and extends from the trench 23 to the inner wall of the through hole 24 (i.e., from the device area AA to the peripheral area BB) to be electrically connected to the metal pad 12. The second dielectric layer 36 covers the surface of the insulating layer 22 and the second electrode 35, and fills the trench 23 and the through hole 24.

[0100] In summary, the present invention forms a groove and a through hole in the insulating layer at the same time, uses the groove to expose the metal wire, uses the through hole to expose the metal pad, and then conformally forms the first electrode, the first dielectric layer and the second electrode on the insulating layer around the groove and the surrounding area to form a groove capacitor, and the second electrode is extended from the device area to the peripheral area, that is, the groove capacitor is extended to cover the inner wall of the through hole, so that the second electrode is electrically connected to the metal pad, thereby completing the lead-out and electrical connection of the first electrode and the second electrode of the capacitor while forming the capacitor. That is, when forming the first electrode, the metal wire exposed at the bottom of the groove is used to complete the lead-out of the first electrode of the groove capacitor and the electrical connection with the metal wire, and when forming the second electrode, the second electrode is extended from the groove to the through hole to realize the lead-out of the second electrode and the electrical connection with the metal pad, so that the present embodiment only needs four photolithography processes (four masks) to complete the formation, lead-out and electrical connection of the capacitor with the metal wire and the metal pad, so that it has a simple and efficient process flow, which is conducive to reducing costs. Compared with the related art that uses metal materials (such as aluminum) to fill the gaps in the trench capacitors for lead-out, the present invention uses a second dielectric layer to fill the gaps in the trenches, which is not only beneficial for saving electrode materials, but also beneficial for reducing the corresponding process difficulty.

[0101] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a metal-insulator-metal capacitor, characterized in that: include: Providing a substrate, comprising a device area and a peripheral area, wherein the device area has a metal wire, the peripheral area has a metal pad arranged in the same layer as the metal wire, and an insulating layer covers the metal wire and the metal pad; forming a groove and a through hole in the insulating layer, wherein the groove exposes the metal line and the through hole exposes the metal pad; Conformally forming a first electrode and a first dielectric layer on the trench and the insulating layer around it, wherein the first electrode is electrically connected to the metal wire via the trench; forming a second electrode to cover the first dielectric layer and extend to cover the inner wall of the through hole so as to be electrically connected to the metal pad; A second dielectric layer is formed to cover the surfaces of the insulating layer and the second electrode and to fill the trench and the through hole.

2. The method for manufacturing a metal-insulator-metal capacitor according to claim 1, wherein: A dielectric barrier layer is also provided between the metal wire, the metal pad and the insulating layer.

3. The method for manufacturing a metal-insulator-metal capacitor according to claim 2, wherein: The steps of forming the first groove and the through hole include: Forming a first mask to cover the surface of the insulating layer, wherein the first mask has a first opening and a second opening; Performing a first etching process on the insulating layer and the dielectric barrier layer, forming the trench using the first opening, and simultaneously forming the through hole using the second opening, wherein the through hole is located above the metal pad, and at least one of the trenches is located above the metal line; The first mask is removed.

4. The method for manufacturing a metal-insulator-metal capacitor according to claim 3, characterized in that: The step of forming the first electrode comprises: forming a first electrode material layer to cover the surface of the insulating layer, the groove and the inner wall of the through hole; The second mask covers the trench, the through hole and the first electrode material layer on the surrounding insulating layer of the trench and the through hole; Performing a second etching process on the first electrode material layer, using the first electrode material layer on the trench and the insulating layer around it as the first electrode, and retaining the first electrode material layer covering the inner wall of the through hole and the insulating layer around it; The second mask is removed.

5. The method for manufacturing a metal-insulator-metal capacitor according to claim 4, characterized in that: The step of forming the first dielectric layer comprises: forming a first dielectric material layer to cover the insulating layer, the first electrode and the through hole; forming a third mask to cover the first electrode and the insulating layer around it; Performing a third etching process on the first dielectric material layer, using the first dielectric material layer on the first electrode and the surrounding insulating layer as the first dielectric layer, and at least exposing the first electrode material layer on the bottom wall of the through hole; The third mask is removed.

6. The method for manufacturing a metal-insulator-metal capacitor according to claim 3, characterized in that: The step of forming the first electrode comprises: forming a first electrode material layer to cover the surface of the insulating layer, the groove and the inner wall of the through hole; forming a second mask to cover the first electrode material layer on the trench and the surrounding insulating layer; Performing a second etching process on the first electrode material layer, using the first electrode material layer on the insulating layer around the trench and the first electrode material layer as the first electrode, and at least partially exposing the metal pad on the bottom wall of the through hole; The second mask is removed.

7. The method for manufacturing a metal-insulator-metal capacitor according to claim 6, characterized in that: The step of forming the first dielectric layer comprises: forming a first dielectric material layer to cover the insulating layer, the first electrode and the through hole; forming a third mask to cover the first electrode and the insulating layer around it; Performing a third etching process on the first dielectric material layer, using the first dielectric material layer on the first electrode and the surrounding insulating layer as the first dielectric layer, and at least partially exposing the metal pad on the bottom wall of the through hole; The third mask is removed.

8. The method for manufacturing a metal-insulator-metal capacitor according to any one of claims 1, 5 or 7, characterized in that: The step of forming the second electrode comprises: forming a second electrode material layer to cover the insulating layer, the first dielectric layer and the through hole; forming a fourth mask to cover the first dielectric layer, the through hole, and the second electrode material layer on the insulating layer from the trench to the through hole; Performing a fourth etching process on the second electrode material layer, using the first dielectric layer, the inner wall of the through hole, and the second electrode material layer on the insulating layer from the trench to the through hole as the second electrode; The fourth mask is removed.

9. The method for manufacturing a metal-insulator-metal capacitor according to claim 1, wherein: The materials of the first electrode material layer and the second electrode material layer include one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

10. A metal-insulator-metal capacitor, characterized in that: include: A substrate having a device region and a peripheral region; A metal wire and a metal pad, wherein the metal wire is arranged in the device area, and the metal pad and the metal wire are arranged in the peripheral area in the same layer; An insulating layer covering the metal line and the metal pad, wherein a groove is formed in the insulating layer to expose the metal line, and a through hole is formed to expose the metal pad; A capacitor, comprising a first electrode, a first dielectric layer and a second electrode, which sequentially conformally cover the groove and the surrounding insulating layer, wherein the first electrode is electrically connected to the metal wire by using the groove, and the second electrode extends from the groove to cover the inner wall of the through hole to be electrically connected to the metal pad; The second dielectric layer covers the surfaces of the insulating layer and the second electrode and fills the groove and the through hole.