Detection circuit and detection method for product of resistor and capacitor in chip

Abstract

The invention relates to a detection circuit and a detection method for a resistor-capacitor product in a chip. The detection circuit comprises a resistor Rt to be detected, a capacitor Ct to be detected, a resistor R1, a current source, four switches S1, S2, S3 and S4, an amplifier circuit, a comparator circuit and a digital counter circuit. According to the invention, the capacitance value of the micro resistor can be accurately measured without being influenced by factors such as process variation, temperature variation, power supply fluctuation and the like.

Description

Technical Field

[0001] The invention belongs to the technical field of resistance and capacitance measurement, and relates to a resistance-capacitance product detection circuit and a detection method, in particular to a resistance-capacitance product detection circuit and a detection method in a chip. Background Art

[0002] In the semiconductor manufacturing process, resistors and capacitors are basic components in integrated circuits, and they have a direct impact on the performance of the circuit. For example, resistors are used to control the size of the current in the chip and the size of the voltage division in the chip, while capacitors are used for signal coupling, filtering, and energy storage. Therefore, accurately measuring the resistance and capacitance values ​​is crucial to ensure the correctness of the circuit design and improve product reliability.

[0003] Traditional resistance and capacitance measurement methods, such as external measurement using a multimeter, may not accurately reflect the working status within the chip. This is because the resistance and capacitance inside the chip may be affected by process variation, temperature changes, power supply fluctuations, etc. In addition, traditional methods have difficulty in achieving accurate measurement of tiny resistance and capacitance values.

[0004] Moreover, as electronic devices develop towards high integration, miniaturization and high performance, the requirements for the measurement accuracy of resistance and capacitance are getting higher and higher, especially in sensor development and precision instruments. Traditional capacitance measurement methods rely on complex analog circuit design, such as capacitance bridge and frequency measurement principle, which not only increases the complexity of design, but also limits the measurement range. At the same time, the measurement of resistance and capacitance is easily affected by environmental factors (such as temperature changes), circuit noise and circuit parasitics, resulting in reduced measurement accuracy and stability.

[0005] After searching, no public documents of the prior art identical or similar to the present invention were found. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and to propose a resistance-capacitance product detection circuit and detection method within a chip, which can achieve accurate measurement of tiny resistance and capacitance values ​​and is not affected by factors such as process variation, temperature change, and power supply fluctuation.

[0007] The present invention solves the practical problem by adopting the following technical solutions:

[0008] A resistance-capacitance product detection circuit in a chip includes: a resistance Rt to be measured, a capacitance Ct to be measured, a resistor R1, a current source, four switches S1, S2, S3 and S4, an amplifier circuit, a comparator circuit and a digital counter circuit;

[0009] The two ends of the resistor Rt to be measured are recorded as nodes VA and VB, and the two ends of the capacitor Ct to be measured are recorded as nodes VC and VD;

[0010] The positive input of the amplifier circuit is recorded as node VE, the negative input of the amplifier circuit is connected to node VD, and the output of the amplifier circuit is connected to node VC;

[0011] The positive input of the comparator circuit is connected to the node VC, the negative input of the comparator circuit is recorded as the node VF, and the output of the comparator circuit is recorded as the node VG;

[0012] The node VA is connected to a power source through a resistor R1, and the node VA is connected to a node VF through a fourth switch S4;

[0013] The node VB and the node VD are respectively connected to the selection end of the second single-pole double-throw switch S2, and the other end of the second switch S2 is connected to the ground through a current source; meanwhile, the node VB is connected to the node VE through the third switch S3.

[0014] The node VC and the node VD are connected through a first switch S1, the node VC is connected to the output end of the amplifier circuit, the node VC is connected to the positive input of the comparator circuit, and the node VD is connected to the negative input of the amplifier circuit.

[0015] Wherein, the amplifier circuit has a positive input to the node VE, a negative input to the node VD, and an output connected to the node VC;

[0016] Wherein, the comparator circuit has a positive input as node VC, a negative input as node VF, an output node as node VG, and node VG is connected to the RESET terminal of the digital counter. When the positive voltage value is greater than the negative voltage value, the comparator circuit outputs a high level, and when the positive voltage value is less than the negative voltage value, the comparator circuit outputs a low level.

[0017] The RESET terminal of the digital counter is connected to the output of the comparator, the SET terminal is connected to a pulse input signal, the CLK terminal is connected to a reference clock signal with a known frequency, and the output of the digital counter is the number of reference clocks within a certain period of time.

[0018] The first switch S1 , the second switch S2 , the third switch S3 and the fourth switch S4 can be designed according to actual process requirements and can be implemented using MOS switches or bootstrap boost switches without affecting signal integrity.

[0019] The SET terminal of the digital counter can be triggered by a rising edge or a falling edge, and similarly, the RESET terminal can also be triggered by a corresponding rising edge or a falling edge.

[0020] A detection method for a resistance-capacitance product detection circuit in a chip comprises the following steps:

[0021] Step 1, close the first switch S1, the third switch S3, and the fourth switch S4, and connect the second switch S2 to the node VB;

[0022] Step 2: Input a rising edge pulse signal to the SET terminal of the digital counter, and at the same time, start inputting a reference clock signal with a known frequency to the CLK terminal of the digital counter. The frequency of the reference clock signal is recorded as 1 / T, and the period is recorded as T. The digital counter starts counting.

[0023] Step 3: When a rising edge pulse signal is input to the SET terminal of the digital counter, the first switch S1, the third switch S3, and the fourth switch S4 are turned on, and the second switch S2 is connected to the node VD.

[0024] Step 4: Wait for the RESET terminal of the digital counter to jump from low to high.

[0025] Step 5: When the RESET terminal of the digital counter jumps from low to high, the digital counter stops counting, and the number of counts of the digital counter at this time is read, which is recorded as N. Then the product of the measured resistance Rt and the measured capacitance Ct can be expressed as T*N.

[0026] Advantages and beneficial effects of the present invention:

[0027] 1. The present invention proposes a resistance-capacitance product detection circuit and detection method in a chip. By converting the analog quantity of the resistance-capacitance product into the count number of a digital counter through corresponding conversion, when the frequency of the reference clock is fast enough, the measurement accuracy of the resistance-capacitance product of the present invention is very high.

[0028] 2. The resistance-capacitance product value measured by the present invention is not affected by process variation, temperature change, power supply fluctuation and other factors. In addition to the resistance to be measured and the capacitance to be measured, the circuit structure of the present invention only includes a resistor, a current source, four switches, an amplifier circuit, a comparator circuit and a digital counter circuit. The circuit structure is simple and easy to operate.

[0029] 3. The circuit structure of the present invention only includes one current source, and does not involve the problem of current mirror matching used in other resistance-capacitance product detection circuits. The resistance-capacitance product expression of the present invention is only related to the reference clock frequency and the number of readings of the digital counter, so the resistance value caused by process deviation, temperature change, the current value of the current source and other parameter changes and power supply voltage fluctuations do not affect the resistance-capacitance product detection result of the present invention. At the same time, since the present invention only uses one current source, the resistance-capacitance product expression of the present invention can be realized without including the proportional term of the current mirror, so the problem of current mirror matching in conventional circuits is omitted.

[0030] 4. The present invention can accurately measure the product value of the tiny resistance and capacitance in the chip, and can effectively solve the corresponding problems mentioned in the background technology. The reference clock frequency of the present invention is generally tens of MHz, which is equivalent to the resistance and capacitance product to be detected in tens of ns. That is, the resistance value that can be detected is on the order of several kohm to hundreds of kohm, and the capacitance value is on the order of tens of fF to several pF. Therefore, the present invention can accurately measure the product value of the tiny resistance and capacitance in the chip, and effectively solve the corresponding problems mentioned in the background technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a structural diagram of a resistance-capacitance product detection circuit of the present invention;

[0032] Figure 2 It is a waveform diagram of key nodes when the resistance-capacitance product detection circuit of the present invention is working. DETAILED DESCRIPTION

[0033] The embodiments of the present invention are further described in detail below with reference to the accompanying drawings:

[0034] A resistance-capacitance product detection circuit in a chip, such as Figure 1 As shown, it includes: a resistance Rt to be measured, a capacitance Ct to be measured, a resistor R1, a current source, four switches S1, S2, S3 and S4, an amplifier circuit, a comparator circuit and a digital counter circuit;

[0035] The two ends of the resistor Rt to be measured are recorded as nodes VA and VB, and the two ends of the capacitor Ct to be measured are recorded as nodes VC and VD;

[0036] The positive input of the amplifier circuit is recorded as node VE, the negative input of the amplifier circuit is connected to node VD, and the output of the amplifier circuit is connected to node VC;

[0037] The positive input of the comparator circuit is connected to the node VC, the negative input of the comparator circuit is recorded as the node VF, and the output of the comparator circuit is recorded as the node VG;

[0038] The node VA is connected to a power source through a resistor R1, and the node VA is connected to a node VF through a fourth switch S4;

[0039] The node VB and the node VD are respectively connected to the selection end of the second single-pole double-throw switch S2, and the other end of the second switch S2 is connected to the ground through a current source; meanwhile, the node VB is connected to the node VE through the third switch S3.

[0040] The node VC and the node VD are connected through a first switch S1, the node VC is connected to the output end of the amplifier circuit, the node VC is connected to the positive input of the comparator circuit, and the node VD is connected to the negative input of the amplifier circuit.

[0041] Wherein, the amplifier circuit has a positive input to the node VE, a negative input to the node VD, and an output connected to the node VC;

[0042] Wherein, the comparator circuit has a positive input as node VC, a negative input as node VF, an output node as node VG, and node VG is connected to the RESET terminal of the digital counter. When the positive voltage value is greater than the negative voltage value, the comparator circuit outputs a high level, and when the positive voltage value is less than the negative voltage value, the comparator circuit outputs a low level.

[0043] The RESET terminal of the digital counter is connected to the output of the comparator, the SET terminal is connected to a pulse input signal, the CLK terminal is connected to a reference clock signal with a known frequency, and the output of the digital counter is the number of reference clocks within a certain period of time.

[0044] The first switch S1 , the second switch S2 , the third switch S3 and the fourth switch S4 can be designed according to actual process requirements and can be implemented using MOS switches or bootstrap boost switches without affecting signal integrity.

[0045] The SET terminal of the digital counter can be triggered by a rising edge or a falling edge, and similarly, the RESET terminal can also be triggered by a corresponding rising edge or a falling edge.

[0046] In this embodiment, the resistance-capacitance product detection circuit in the chip of the present invention can accurately detect the size of the resistance-capacitance product. Figure 1: This is the circuit structure of the present embodiment, which includes a resistor, a current source, four switches, an amplifier circuit, a comparator circuit and a digital counter circuit in addition to the resistance Rt to be measured and the capacitance Ct to be measured. Rt and Ct are the resistance to be measured and the capacitance to be measured respectively, and the two ends of the resistance Rt to be measured are recorded as nodes VA and VB, and the two ends of the capacitance Ct to be measured are recorded as nodes VC and VD. Node VA is connected to the power supply through a resistor R1, and node VA is connected to node VF through a fourth switch S4. Node VB and node VD are connected to the selection end of a single-pole double-throw second switch S2, and the other end of the second switch S2 is connected to the ground through a current source, and node VB is connected to node VE through a third switch S3. Node VC and node VD are connected through a first switch S1, node VC is connected to the output end of the amplifier circuit, and node VC is connected to the positive input of the comparator circuit, and node VD is connected to the negative input of the amplifier circuit. The amplifier circuit has a positive input of node VE, a negative input of VD, and an output connected to node VC. The comparator circuit has a positive input node VC, a negative input node VF, and an output node denoted as node VG. Node VG is connected to the RESET terminal of the digital counter. When the positive voltage value is greater than the negative voltage value, the comparator circuit outputs a high level, and when the positive voltage value is less than the negative voltage value, the comparator circuit outputs a low level. The RESET terminal of the digital counter is connected to the output of the comparator, the SET terminal is connected to a pulse input signal, and the CLK terminal is connected to a reference clock signal with a known frequency. The output of the digital counter is the number of reference clocks within a certain period of time.

[0047] A detection method for a resistance-capacitance product detection circuit in a chip, such as Figure 2 As shown, the following steps are included:

[0048] Step 1, close the first switch S1, the third switch S3, and the fourth switch S4, and connect the second switch S2 to the node VB;

[0049] Step 2: Input a rising edge pulse signal to the SET terminal of the digital counter, and at the same time, start inputting a reference clock signal with a known frequency to the CLK terminal of the digital counter. The frequency of the reference clock signal is recorded as 1 / T, and the period is recorded as T. The digital counter starts counting.

[0050] Step 3: When a rising edge pulse signal is input to the SET terminal of the digital counter, the first switch S1, the third switch S3, and the fourth switch S4 are turned on, and the second switch S2 is connected to the node VD.

[0051] Step 4: Wait for the RESET terminal of the digital counter to jump from low to high.

[0052] Step 5: When the RESET terminal of the digital counter jumps from low to high, the digital counter stops counting, and the number of counts of the digital counter at this time is read, which is recorded as N. Then the product of the measured resistance Rt and the measured capacitance Ct can be expressed as T*N.

[0053] The working principle of the present invention is:

[0054] The working principle of the resistance-capacitance product detection circuit in the chip of the present invention is as follows: Figure 2 As shown, the SET of the digital counter is a rising edge trigger signal, RESET is a rising edge trigger signal, and SET is connected to the pulse input. At the same time, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are also controlled by this pulse signal. When the pulse signal is a logic low level, the first switch S1, the third switch S3, and the fourth switch S4 are all closed, and the second switch S2 is connected to the node VB; when the pulse signal is a logic high level, the first switch S1, the third switch S3, and the fourth switch S4 are all opened, and the second switch S2 is connected to the node VD. After a rising edge pulse signal is input to the SET end of the digital counter, the CLK end of the digital counter starts to input a reference clock signal with a known frequency. The frequency of the reference clock signal is recorded as 1 / T, and the period is recorded as T.

[0055] When the pulse signal is at a logic low level, the current provided by the current source is recorded as I, and the detection circuit state of the present invention is: the first switch S1, the third switch S3, and the fourth switch S4 are all closed, the second switch S2 is connected to the node VB, and the two ends of the measured capacitor Ct are short-circuited by the first switch S1, that is, the node VC and the node VD are connected together. Since the amplifier is connected to a unit gain negative feedback mode at this time, the node voltage VC=VD=VE. At this time, the node voltage VA=VF=VDD-I*R1, the node voltage VB=VC=VD=VE=VDD-I*R1-I*Rt, and since the voltage of the node VC is less than the voltage value of the node VF, the output of the comparator Comp is a logic low level.

[0056] When SET_PULSE is at a logic high level, the detection circuit state of the present invention is: the first switch S1, the third switch S3, and the fourth switch S4 are all open, the second switch S2 is connected to the node VD, and the measured capacitor Ct is connected to the circuit. According to the working principle of the amplifier, the node voltage VD=VE=VDD-I*R1-I*Rt. Since the third switch S3 is open, the node VE=VDD-I*R1-I*Rt; since the fourth switch S4 is open, the node VF=VDD-I*R1. Since the node VD is connected to the current source through the second switch S2, in order to continuously and stably provide current, the voltage of the node VC will rise to charge the upper plate of the measured capacitor Ct, and the voltage change of the node VC and the charging time t need to satisfy I*t=Ct*ΔVC. As the voltage of the node VC continues to rise, when the voltage of the node VC rises to exceed the voltage of the node VF, the output of the comparator circuit changes from a logic low level to a logic high level.

[0057] The charging time at this time can be expressed as:

[0058] t=Ct*ΔVC / I=Ct*(VF-VD) / I=Ct*(VDD-I*R1-VDD+I*R1+I*Rt) / I=Ct*Rt.

[0059] When the input of the digital counter SET terminal switches from a logic low level to a logic high level, the digital counter starts counting, and when the input of the digital counter RESET terminal switches from a logic low level to a logic high level, the digital counter stops counting. Since the charging time t of the above-mentioned measured capacitor is equal to the counting time of the digital counter, the number of counts of the digital counter within this time t can be read, which is recorded as N. Since the frequency 1 / T and the period T of the reference clock signal are known, the product of the measured resistance Rt and the measured capacitance Ct can be expressed as Ct*Rt=t=T*N, that is, the product of the measured resistance and capacitance can be calculated by detecting the count value of the digital counter.

[0060] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0061] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0062] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0063] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

Claims

1. A resistance-capacitance product detection circuit in a chip, characterized in that: include: A resistance to be measured Rt, a capacitance to be measured Ct, a resistor R1, a current source, four switches S1, S2, S3 and S4, an amplifier circuit, a comparator circuit and a digital counter circuit; The two ends of the resistor Rt to be measured are recorded as nodes VA and VB, and the two ends of the capacitor Ct to be measured are recorded as nodes VC and VD; The positive input of the amplifier circuit is recorded as node VE, the negative input of the amplifier circuit is connected to node VD, and the output of the amplifier circuit is connected to node VC; The positive input of the comparator circuit is connected to the node VC, the negative input of the comparator circuit is recorded as the node VF, and the output of the comparator circuit is recorded as the node VG; The node VA is connected to a power source through a resistor R1, and the node VA is connected to a node VF through a fourth switch S4; The node VB and the node VD are respectively connected to the selection end of the second single-pole double-throw switch S2, and the other end of the second switch S2 is connected to the ground through a current source; meanwhile, the node VB is connected to the node VE through the third switch S3. The node VC and the node VD are connected through a first switch S1, the node VC is connected to the output end of the amplifier circuit, the node VC is connected to the positive input of the comparator circuit, and the node VD is connected to the negative input of the amplifier circuit. Wherein, the amplifier circuit has a positive input to the node VE, a negative input to the node VD, and an output connected to the node VC; Wherein, the comparator circuit has a positive input as node VC, a negative input as node VF, an output node as node VG, and node VG is connected to the RESET terminal of the digital counter. When the positive voltage value is greater than the negative voltage value, the comparator circuit outputs a high level, and when the positive voltage value is less than the negative voltage value, the comparator circuit outputs a low level. The RESET terminal of the digital counter is connected to the output of the comparator, the SET terminal is connected to a pulse input signal, the CLK terminal is connected to a reference clock signal with a known frequency, and the output of the digital counter is the number of reference clocks within a certain period of time. The first switch S1 , the second switch S2 , the third switch S3 and the fourth switch S4 can be designed according to actual process requirements and can be implemented using MOS switches or bootstrap boost switches without affecting signal integrity. The SET terminal of the digital counter can be triggered by a rising edge or a falling edge, and similarly, the RESET terminal can also be triggered by a corresponding rising edge or a falling edge.

2. A detection method for a resistance-capacitance product detection circuit in a chip, characterized in that: The following steps are involved: Step 1, close the first switch S1, the third switch S3, and the fourth switch S4, and connect the second switch S2 to the node VB; Step 2: Input a rising edge pulse signal to the SET terminal of the digital counter, and at the same time, start inputting a reference clock signal with a known frequency to the CLK terminal of the digital counter. The frequency of the reference clock signal is recorded as 1 / T, and the period is recorded as T. The digital counter starts counting. Step 3: When a rising edge pulse signal is input to the SET terminal of the digital counter, the first switch S1, the third switch S3, and the fourth switch S4 are turned on, and the second switch S2 is connected to the node VD. Step 4: Wait for the RESET terminal of the digital counter to jump from low to high. Step 5: When the RESET terminal of the digital counter jumps from low to high, the digital counter stops counting, and the number of counts of the digital counter at this time is read, which is recorded as N. Then the product of the measured resistance Rt and the measured capacitance Ct can be expressed as T*N.

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