Novel system Beidou signal rapid capture IP circuit design based on FPGA in high dynamic scene

Abstract

The invention discloses a high-dynamic scene new system Beidou signal rapid capture IP circuit design based on an FPGA, and the design comprises a single-channel PMF-FFT capture algorithm module, a capture judgment logic module, and a high-dynamic B1C signal parallel capture IP circuit design. The single-channel PMF-FFT capture algorithm module comprises a short-time matched filter operation module, an FFT state control module, an FFTIP operation module and a coherent integration module, and the capture judgment logic module comprises a capture judgment threshold generation module, a peak value detection module and comparison logic. The advantages are realized by adopting the FPGA chip: algorithm upgrading is facilitated, parallel design can be realized, and the capture speed is improved; the data utilization rate is increased; the improved matched filter coefficient is convenient for FPGA internal implementation, and B1C signal capture can be carried out; the PMF-FFT capture algorithm meets the capture bandwidth in a high dynamic environment; incoherent integration and noise estimation design: increasing the gain of the incoherent integration; and line processing: the capture time and the data utilization efficiency are improved.

Description

Technical Field

[0001] The present invention relates to the field of satellite signal technology, and in particular to a new system Beidou signal fast capture IP circuit design based on FPGA in high dynamic scenarios. Background Art

[0002] The BeiDou-3 satellite navigation system completed its networking in July 2020, using a code division multiple access (CDMA) system. The BeiDou B1C signal is a new satellite navigation signal added to the BeiDou satellite-3 system, using the modern navigation signal MBOC modulation method to implement CDMA. This new modulation method is intended to solve the problem of signal congestion in high-quality frequency points, but the new modulation method is quite different from the traditional modulation method. Its power spectrum bandwidth becomes larger, and the autocorrelation function has a larger secondary peak, which can easily lead to capture ambiguity problems, all of which will affect the capture effect. In addition, in high-dynamic scenarios, the rapid change in the relative distance between the satellite and the receiver brings about the Doppler effect, which increases the difficulty of capturing satellite signals. When the satellite navigation signal receiver is running at a speed of less than or equal to 8000m / s and an acceleration of less than or equal to 50g (g is the acceleration of gravity), the Doppler frequency deviation of the satellite navigation signal carrier is close to ±50kHz in value, and its frequency change rate is also close to ±2500Hz / s, resulting in the introduction of large Doppler frequency shift and frequency shift change rate to the received satellite signal carrier frequency, which in turn causes pseudo code phase delay. This high-dynamic signal change has higher requirements for the receiver's capture speed and performance. At present, the capture algorithm combining short-time matched filter and FFT (PMF-FFT capture algorithm) can realize satellite navigation signal capture in a high-dynamic environment, but there are problems such as capture ambiguity caused by B1C signal modulation, increased sampling data, and the selection of matched filter coefficients in the PMF-FFT algorithm.

[0003] With the rapid development and application of software radio technology, and since my country officially announced the start of trial operation of the Beidou satellite navigation system (Beidou-2) in December 2012, China's Beidou satellite navigation receivers have also developed a variety of application solutions. The general-purpose processor (GPP) chip can be programmed through the operating system to implement software radio, which is widely applicable and has many open source programs; however, its speed is easily limited, power consumption and price are high, and the multiplication and addition unit (MAC) is mostly serial operation, which affects the algorithm speed, and the programming program is carried out sequentially, and parallelization cannot be achieved. DSP is a microprocessor chip specially used to implement signal processing algorithms. It can be regarded as an optimized general-purpose processor chip. Although a dedicated parallel MAC unit is introduced, the processing speed is still limited by the clock frequency, and the programming language is relatively complex. The programming program is still carried out sequentially, and parallelization cannot be achieved. With the continuous development and progress of my country's Beidou satellite navigation business, in order to reduce production costs, the application-specific integrated circuit (ASIC) chip of Beidou satellite navigation baseband has developed rapidly. ASIC chips for signal processing have the characteristics of strong specialization, low power consumption, fast computing speed, and low cost in mass production. However, the cost of ASIC chip tape-out is high, the development cycle is long, and each upgrade of the baseband algorithm requires the redesign of ASIC chips. ASIC chips are more suitable for scenarios that do not require frequent replacement, which is in conflict with the continuous upgrading of Beidou baseband chips to improve performance. In order to meet the continuous upgrading of Beidou baseband chips, programmable devices can be used instead of application-specific integrated circuits (ASICs), thereby effectively solving the above problems. Currently, the widely used programmable devices are mainly field programmable gate arrays (FPGAs). The design of Beidou ASIC baseband chips can be realized by writing hardware description languages, and the improved algorithms can be quickly implemented and verified to meet the continuous upgrading needs of Beidou baseband chips. In addition, FPGAs can also process digital signals in parallel, support debugging using online logic analyzers, and have strong device compatibility, making them very suitable as core devices for satellite signal reception and processing.

[0004] Therefore, studying and designing the Beidou B1C signal capture algorithm in a high dynamic environment, and then realizing the capture algorithm circuit design and implementation based on FPGA devices will help promote the application development of the Beidou satellite navigation system and have certain research significance and engineering application value.

[0005] In order to solve the above problems, we have made improvements and proposed a new FPGA-based Beidou signal fast capture IP circuit design for high dynamic scenarios. Summary of the invention

[0006] The purpose of the present invention is to provide a new system Beidou signal fast capture IP circuit design based on FPGA in high dynamic scenarios to solve the problems raised in the above background technology.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] The new FPGA-based Beidou signal fast capture IP circuit design for high dynamic scenarios includes a single-channel PMF-FFT capture algorithm module, a capture decision logic module and a high dynamic B1C signal parallel capture IP circuit design. The single-channel PMF-FFT capture algorithm module includes a short-time matched filter operation module, an FFT state control module, an FFTIP operation module and a coherent integration module. The capture decision logic module includes a capture decision threshold generation module, a peak detection module and a comparison logic. The capture decision threshold generation module includes a noise estimation module. The high dynamic B1C signal parallel capture IP circuit design includes a digital down-conversion and filtering module, a data pipelining module and a parallel PMF-FFT capture algorithm module.

[0009] As a further solution of the present invention: the short-time matching filter operation module includes an in-phase parallel circuit design, which includes an autocorrelation calculation module, a short-time matching filter module and a RAM; the short-time matching filter operation module also includes an orthogonal path parallel circuit design, which includes an autocorrelation calculation module, a short-time matching filter module and a RAM.

[0010] As a further solution of the present invention: the digital down-conversion and filtering module includes a DDS signal generating module (COS signal), a filtering truncation module and a (sin signal) DDS signal generating module.

[0011] As a further solution of the present invention: the data pipeline processing module includes an N-level pipeline state machine control module, and the N-level pipeline state machine control module is connected to the parallel PMF-FFT capture algorithm module.

[0012] As a further solution of the present invention: the parallel PMF-FFT capture algorithm module includes PMF-FFT capture algorithm module channels 1, 2 and 3, the parallel PMF-FFT capture algorithm module also includes PMF-FFT capture algorithm module channel N, the PMF-FFT capture algorithm module channel N is connected to the capture detection module n, and the PMF-FFT capture algorithm module channels 1, 2 and 3 are connected to the capture detection modules 1, 2 and 3.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] The present invention adopts FPGA chip to achieve advantages: it is convenient for algorithm upgrading and can be designed in parallel, thereby improving the capture speed; it adopts pipeline design to increase data utilization; the improved matched filter coefficient is convenient for internal implementation of FPGA, and B1C signal capture can be performed; the PMF-FFT capture algorithm meets the capture bandwidth in a high dynamic environment; the incoherent integration and noise estimation design improves the incoherent integration gain; and the row processing improves the capture time and data utilization efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the design of a new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0016] Figure 2 Data flow control diagram in the design of IP circuit for rapid capture of Beidou signals based on FPGA for high dynamic scenarios;

[0017] Figure 3 Generate a matched filter coefficient module diagram in the design of a new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0018] Figure 4 Single-channel PMF-FFT capture algorithm and capture detection module diagram in the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0019] Figure 5 Schematic diagram of single-shot multi-channel parallel capture in the design of a new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0020] Figure 6 Schematic diagram of single multi-channel parallel capture decision in the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0021] Figure 7 High dynamic Beidou B1C signal spectrum simulation diagram in the design of new Beidou signal fast capture IP circuit based on FPGA for high dynamic scenarios;

[0022] Figure 8 Capture signal-to-noise ratio diagram in the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0023] Fig. 9 The Matlab capture effect diagram of the quantized signal in the design of the new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0024] Fig.10 The logic analyzer capture circuit diagram in the design of IP circuit for fast capture of Beidou signals based on FPGA for high dynamic scenarios;

[0025] Fig.11 Circuit performance index diagram in the design of IP circuit for rapid capture of Beidou signals based on new FPGA for high dynamic scenarios;

[0026] Fig.12 Establishing timing margin diagram in the design of new FPGA-based BeiDou signal fast capture IP circuit for high dynamic scenarios;

[0027] Fig.13 The hold time margin diagram in the design of the new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0028] Fig.14 Resource utilization diagram in the design of IP circuits for rapid capture of BeiDou signals based on new FPGA for high dynamic scenarios;

[0029] Fig.15 Design of the intermediate frequency data down-conversion module for the new FPGA-based Beidou signal fast capture IP circuit design for high dynamic scenarios;

[0030] Fig.16 The multiplier IP configuration diagram in the design of the new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0031] Fig.17 Generate digital filter coefficient diagrams in Matlab in the design of IP circuits for rapid Beidou signal capture based on FPGA for high dynamic scenarios;

[0032] Fig.18 Filter IP configuration diagram in the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0033] Fig.19 Simulation diagram of down-conversion data in the design of IP circuit for rapid capture of Beidou signals based on FPGA for high dynamic scenarios;

[0034] Fig. 20 Simulation diagram of down-conversion and spectrum analysis of the in-phase branch in the design of IP circuit for fast capture of Beidou signals based on FPGA for high dynamic scenarios;

[0035] Fig.21 Schematic diagram of five-level data pipeline in the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0036] Fig. 22 Design of a five-stage pipeline state machine diagram for down-converted data in a new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0037] Fig.23 RAM IP configuration diagram in the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0038] Fig.24 Simulation verification diagram of digital down-conversion data pipeline processing module in the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0039] Fig.25 Schematic diagram of the matched filter coefficient generation module in the design of the new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0040] Fig.26 Simulation diagram of the matching filter coefficient generation module in the design of the new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0041] Fig. 27 Schematic diagram of single PMF-FFT capture and decision module in the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0042] Fig.28 Matched filter calculation graph in the design of IP circuit for rapid capture of Beidou signals based on FPGA for high dynamic scenarios;

[0043] Fig.29 FFT IP configuration diagram in the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0044] Fig.30 Simulation diagram of FFT IP core in the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0045] Fig.31 The non-coherent integration schematic diagram in the design of the new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0046] Fig.32 Schematic diagram of the capture and judgment module in the design of the new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0047] Fig.33 Generate data capture simulation diagrams in Matlab for the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0048] Fig.34 The effect diagram of the data capture of the intermediate frequency data down-conversion in the design of the new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0049] Fig.35 Schematic diagram of multi-channel parallel PMF-FFT capture algorithm in the design of new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios;

[0050] Fig.36 The comprehensive netlist diagram of the multi-channel parallel PMF-FFT capture algorithm circuit in the design of the new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.

[0052] Embodiment 1

[0053] See also Figure 1-6 , the new FPGA-based Beidou signal fast capture IP circuit design for high dynamic scenarios includes a single-channel PMF-FFT capture algorithm module, a capture decision logic module and a high dynamic B1C signal parallel capture IP circuit design. The single-channel PMF-FFT capture algorithm module includes a short-time matched filter operation module, an FFT state control module, an FFTIP operation module and a coherent integration module. The capture decision logic module includes a capture decision threshold generation module, a peak detection module and a comparison logic. The capture decision threshold generation module includes a noise estimation module. The high dynamic B1C signal parallel capture IP circuit design includes a digital down-conversion and filtering module, a data pipelining module and a parallel PMF-FFT capture algorithm module.

[0054] Specifically, the short-time matching filter operation module includes an in-phase parallel circuit design, which includes an autocorrelation calculation module, a short-time matching filter module and a RAM. The short-time matching filter operation module also includes an orthogonal path parallel circuit design, which includes an autocorrelation calculation module, a short-time matching filter module and a RAM.

[0055] Specifically, the digital down-conversion and filtering module includes a DDS signal generation module (COS signal), a filtering and truncation module and a (sin signal) DDS signal generation module.

[0056] Specifically, the data pipeline processing module includes an N-level pipeline state machine control module, and the N-level pipeline state machine control module is connected to the parallel PMF-FFT capture algorithm module.

[0057] Specifically, the parallel PMF-FFT capture algorithm module includes PMF-FFT capture algorithm module channels 1, 2 and 3, and the parallel PMF-FFT capture algorithm module also includes PMF-FFT capture algorithm module channel N. PMF-FFT capture algorithm module channel N is connected to capture detection module n, and PMF-FFT capture algorithm module channels 1, 2 and 3 are connected to capture detection modules 1, 2 and 3.

[0058] The specific implementation of the present invention is:

[0059] In order to more efficiently develop programs and debug and verify algorithms, the circuit design of the capture circuit adopts a top-down design method. First, the overall module design and sub-module division design of the high-dynamic Beidou B1C signal capture algorithm are carried out, and then each sub-module is designed and functionally simulated and verified, and finally the program is compiled. In order to adapt to the acquisition data of various ADC chip types, it mainly includes an intermediate frequency data down-conversion module, a down-conversion data pipeline processing module, a matched filter coefficient generation module, and a parallel multi-channel PMF-FFT capture algorithm module. The parallel multi-channel PMF-FFT capture algorithm module consists of multiple single-channel PMF-FFT capture algorithms and capture detection modules. The circuit operation steps are as follows:

[0060] 1. Digital down-conversion and filtering module: This module completes the functions of digital orthogonal down-conversion, truncation processing, filtering processing, etc. of the sampled intermediate frequency digital signal.

[0061] (1) Sampling the intermediate frequency digital signal and digital orthogonal down-conversion

[0062] Assuming that the bandwidth of the new Beidou signal is, the intermediate frequency digital signal frequency sampled by ADC is, the Doppler frequency deviation is, and the sampling frequency is, the digital sine signal with frequency and sampling frequency are respectively multiplied with the cosine signal to obtain the orthogonal path signal and the in-phase path down-converted signal respectively.

[0063] (2) Low-pass filter processing

[0064] Since digital down-conversion will introduce high-frequency components, a low-pass filter is required to remove the high-frequency components. After low-pass filtering, the data becomes a baseband signal with a data carrier frequency of . The filtering bandwidth of the low-pass filter needs to be greater than MHz, and the out-of-band amplitude suppression is 60dB.

[0065] (3) Data truncation processing

[0066] Both down-conversion and low-pass filtering need to be multiplied. In digital circuits, the bit width will be continuously expanded, resulting in a waste of resources. Therefore, bit truncation is used. The bit truncation rules are as follows:

[0067] (a) For fixed-point data whose position is unknown, generally speaking, the low-order data is directly removed and the required high-order data is retained;

[0068] (b) For fixed-point data with known positions, some signed numbers need to be processed and the middle digits need to be removed, that is, the low-order data is retained and the high-order data is removed, because the high-order data is basically the same as the sign bit.

[0069] 2. Data pipeline processing module: This module completes the data pipeline processing and time division multiplexing

[0070] Assuming that the ranging code period is and the number of pipeline stages is, the single-stage pipeline duration is, and a state machine can be used for pipeline control.

[0071] 3. Generate matching filter coefficient module

[0072] The module for generating matched filter coefficients is used to generate matched filter coefficients of different phases for autocorrelation matching operation. The module for generating matched filter coefficients mainly includes Legendre sequence storage module, XOR calculation and arithmetic logic conversion module, such as Figure 3 As shown in the figure, since the down-conversion filter data needs to be operated with a sign, the data used to generate the matched filter coefficient module is not a logical value but an arithmetic value, that is, a ±1 value.

[0073] 4. Parallel multi-channel PMF-FFT capture algorithm module

[0074] (1) Single-channel PMF-FFT capture algorithm and capture detection module: The single-shot capture and decision module is composed of short-time matched filter, FFT IP core operation, FFT IP core state control, and coherent integration. Figure 4 shown.

[0075] a. Single channel PMF-FFT acquisition algorithm

[0076] First, the first-level pipeline data of the multi-level pipeline data is multiplied by the matched filter data pipeline, and then short-time matched filtering is performed. The short-time matched filtering length is L, and the pipeline is added cyclically; the single-level pipeline outputs a total of M data, which are padded with zeros to the power of 2, and the number of FFT data points is F; RAM is used to save the timing; the data is generated through FFT IP control to match the data timing of the FFT IP core, and then FFT IP operation is performed, and the spectrum position is output.

[0077] b. Incoherent integration module

[0078] Used to complete the modulo operation of the in-phase component and the orthogonal component.

[0079] c. Capture test module

[0080] The functions that need to be implemented in the capture detection module are mainly as follows:

[0081] 1. The spectrum peak and peak position detection module needs to compare the spectrum data after incoherent integration one by one to detect the maximum value and maximum position of the incoherent integrated spectrum.

[0082] 2. The noise estimation module is used to estimate signal noise and set the capture threshold.

[0083] 3. Output capture parameters. The satellite navigation signal capture output parameters mainly include satellite number, Doppler frequency shift, and code phase delay.

[0084] (2) Multi-channel parallel capture

[0085] The biggest advantage of the FPGA platform over other platforms in implementing the capture algorithm is its parallel execution capability, which allows for multi-channel parallel capture to increase the capture speed. c / P, if only one sampling code phase point is searched, it is very wasteful, and the single-channel capture algorithm cannot give full play to the advantages of FPGA and often cannot meet the capture requirements. Assuming that the capture time of a single satellite is T1, and there are a total of PRN satellite numbers in the BeiDou-3 satellite, the time to search the entire satellite constellation is T PRN .

[0086]

[0087] T PRN =PRN·T1

[0088] Where T sys is the system working clock, T c is the ranging code period, E is the number of parallel operations, P is the number of pipeline stages, C offset is the mobile code phase point, and PRN is the number of satellite numbers. Therefore, T PRN The number of channels should be selected based on the capture time and circuit resources required.

[0089] The ranging code data of the fused subcarrier is selected as the matched filter coefficient of the PMF-FFT acquisition algorithm.

[0090] 1. Ensure that the system is always running in a loop to capture signals.

[0091] 2. Implement cyclic control of satellite number PRN increment, each time After each stage of pipeline operation, the PRN number is incremented by one.

[0092] 3. The realization of code phase includes parallel code phase control and serial code phase control.

[0093] Parallel control: realize parallel E-point code phase control (control the reading start address)

[0094] Serial control: Serial control is implemented for each P-stage pipeline, that is, each pipeline is controlled by adding point E (after each five-stage pipeline)

[0095] In order to verify the capture performance of the proposed algorithm, a high-dynamic Beidou B1C signal data model is established as shown in Table 1. The Doppler frequency deviation caused by high dynamics is +10KHz, and the code phase delay is about 7 chips.

[0096] Table 1 High dynamic B1C signal simulation parameters

[0097]

[0098] In the simulation verification phase, since the effective bandwidth of the B1C signal is 16.328MHz, this experiment uses a low-pass filter of order 5, a filter bandwidth of 18MHz, and an out-of-band amplitude attenuation of 60dB. The signal noise power can be calculated to be approximately -132dBW. Therefore, for a high dynamic environment, the received navigation signal model is:

[0099]

[0100] Where, i = 0, 1, 2, ..., N-1; P s is the signal power; T s is the sampling time interval; f if is the intermediate frequency of the signal; f d is the Doppler frequency deviation; Φ0 is the initial phase of the carrier; N(t) is the noise during signal transmission. The Beidou B1C signal model in a high dynamic environment is simulated.

[0101] According to the high-dynamic data model in Chapter 3, the 16-bit quantized capture circuit data is output through the Matlab signal simulator. The data of the high-dynamic capture algorithm used in this chapter is to capture the high-dynamic satellite signal with a Doppler frequency of 10000Hz and a code phase delay of 7 chips. The baseband signal input signal-to-noise ratio is -30dB. The experimental test tests the PRN1, PRN10, PRN30, and PRN63 satellite navigation signals. Since the spectrum output by the FFT IP core is a positive frequency spectrum, there is no need to move the spectrum when simulating and capturing the quantized data.

[0102] Adding a logic analyzer to the capture circuit for analysis, it can be seen that the circuit can successfully capture B1C and the peak is prominent. The spectrum position is 26, the output Doppler shift is 10140Hz, and the code phase delay is 7 chips. When the signal is captured, it meets the analysis of the capture output parameters in 3.4.1.

[0103] 2.3.2 Circuit performance analysis (timing, resource utilization, power consumption)

[0104] When designing the capture algorithm circuit, the circuit running clock is 64M, and the circuit reset adopts a low-level effective reset; the satellite signal data is processed by fixed-point quantization, the quantization bit width is a 16-bit signed number, the high bit is the sign bit, and the signed number is represented by the complement code; if there is no special prompt, the data calculation method is all signed processing, and the signed data definition needs to be declared using the signed keyword; in order to prevent the data multiplication and addition calculation from causing the data bit width to expand infinitely, the data after the multiplication and addition calculation needs to be truncated. The truncation principles of this article are as follows:

[0105] 1. For data with known bit width, retain the valid digits and truncate the high-order data.

[0106] 2. For data whose fixed-point data width is unknown, the method of truncating low-order data is adopted.

[0107] This chapter gives a specific capture circuit design parameter as a reference. The capture circuit design parameters are shown in Table 4.1.

[0108] Tab.4.1Capture circuit design parameters

[0109]

[0110] According to the parameters in Table 4.1 and the performance indicators of the high dynamic Beidou B1C signal capture algorithm design in Chapter 3, the expected performance indicators of the high dynamic Beidou B1C signal capture circuit FPGA implementation based on the PMF-FFT capture algorithm are as follows:

[0111] Input signal-to-noise ratio tolerance: -30dB;

[0112] Cold capture time: 90s;

[0113] False alarm probability: 10-5;

[0114] Detection probability: >90%.

[0115] 2.4.1 Data Processing Principles

[0116] 1. Data Quantification

[0117] Quantization is 2^the number of quantization bits. Since the ADC sampling data width is 16 bits, the data in this article uses 16-bit fixed-point quantization.

[0118] 2. Signed processing:

[0119] In FPGA, the default digital signal is an unsigned number, but the satellite navigation signal processing requires signed number calculation, so the signed keyword needs to be added for signed operations.

[0120] 4. To ensure better timing requirements, you can use the phase-locked loop PLL IP core.

[0121] 2.4.2 Design and verification of IF data down-conversion module

[0122] The BLAD16Q125 ADC chip is used for IF satellite signal data acquisition. The ADC sampling signal IF frequency is 16MHz, the sampling frequency is 64MHz, and the output data width is 16 bits.

[0123] The function of the intermediate frequency data down-conversion module is to realize the down-conversion of satellite navigation signals and filter out the introduced high-frequency components. In order to improve the precision control, this part is developed and designed using Block Design based on Xilinx's Vivado18.3 kit.

[0124] Call the DDS IP core to generate the sine function and cosine function for the down-conversion of the intermediate frequency data. The DDS IP core can realize the function of the numerically controlled oscillator (NCO). Set the output frequency of the DDS IP core to 16MHz and the sampling frequency to 64MHz. Since the effective data bit width of the DDS IP core output is a multiple of 8, the actual output effective data is the lower 3 bits. Use the Slice IP core to truncate and retain the lower 3 bits.

[0125] The multiplier IP core is used for multiplication calculation of intermediate frequency down-conversion, and the input data is 16-bit satellite navigation signal and 3-bit data of sine and cosine signal.

[0126] Then use Matlab to output as a .coe file for configuring the FIR IP core parameters, and Matlab generates digital filter coefficients; after passing through a low-pass filter, 24-bit data is output, and method 2 is used to truncate the output data to 16 bits for capture algorithm processing.

[0127] 2.4.3 Design and verification of digital down-conversion data pipeline processing module

[0128] A five-stage pipeline is used for signal acquisition processing. Each pipeline caches 2ms of data, that is, each pipeline caches 128k of data. Five RAM IP cores (simple dual-port RAM) are used as data buffers, and data reading and writing are controlled through a five-stage data pipeline control module.

[0129] There are 7 states in the state machine control: IDLE state, WRAM1 state, WRAM2_RRAM1 state, WRAM3_RRAM2 state, WRAM4_RRAM3 state, WRAM4_RRAM5 state, WRAM5_RRAM1 state. When the data filtering is completed and the data valid flag is set to 1, the state machine starts to enter the WRAM1 state and write data to the register RAM1; when the RAM1 write address is full, it enters the WRAM2_RRAM1 state, starts to read RAM1 data for processing, and writes the new filtered data to RAM2. The RAM3, RAM4|, and RAM5 memory state control are the same. In order to ensure good timing, since the RAM writes and reads data on the rising edge, the read and write control signals are set to 1 on the falling edge of the clock when designing to maintain the best timing requirements.

[0130] Note: There is a difference of two clocks between the setting of the output enable signal of RAM data and the data output.

[0131] 2.4.4 Design and verification of local ranging code coefficient generation module

[0132] Note: The output of the RAM needs to be delayed by two clocks.

[0133] The generated Legendre sequence is placed in RAM, and the data of two different interception points and phase points are read by the read addresses of two control RAMs, and then XOR is performed to generate the ranging code sequence. From formula 3.9, it can be seen that two Legendre sequences need to be generated. Substitute the parameters of formula 3.11 into formula 3.9, and optimization is required when reading data. For the first Legendre sequence, when the sum of the interception point plus the number of generated bits (ranging code) minus one is greater than 10243, the SDRAM0 memory read data address outputs formula (1), otherwise it outputs formula (2).

[0134] addra0<=intercept_pot_p+WeilCodelength_K-1-legendrelength (1)

[0135] addra0<=legendrelength-intercept_pot_p-WeilCodelength_K+1 (2)

[0136] For the first Legendre sequence, when the sum of the intercept point plus the phase difference plus the number of generated bits (ranging code) minus one is greater than 10243, the SDRAM1 memory read data address outputs formula (3), otherwise it outputs (4).

[0137] addra1<=intercept_pot_p+phase_diff_p+WeilCodelength_K-1-legendrelength (3)

[0138] addra1<=legendrelength-intercept_pot_p-WeilCodelength_K-phase_diff_p+1 (4)

[0139] The data input to the autocorrelation calculation of the matched filter coefficient generation module should be an arithmetic value. The subcarrier is essentially a symbol function. When the function is greater than 0, the subcarrier arithmetic number is 1 and the logical value is regarded as 1; when the subcarrier arithmetic value is -1, the logical value is regarded as 0; the case where the symbol function is equal to 0 is currently ignored. Under the sampling clock of 64M, only the sampling value at time 0 is 0. From the above design, it can be seen that in the design process, the local ranging code is generated as a logical value, which needs to be converted into an arithmetic operation value when doing related calculation input. The conversion of logical values ​​into arithmetic values ​​is shown in Table 4.2.

[0140] Table 4.2 Ranging code logic operation converted to arithmetic value table

[0141] Tab.4.4Conversion of distance code logical operation to arithmeticvalue table

[0142]

[0143] 2.4.5 Single-channel PMF-FFT capture algorithm and capture decision module design and verification

[0144] The single-channel PMF-FFT capture algorithm is used to realize high-dynamic Beidou B1C signal capture. The capture decision module is used to detect module results. The single capture and decision module is mainly composed of short-time matched filter, FFT operation, FFT state control, coherent integration, and capture decision modules.

[0145] (1) Short-term matched filter generation (PMF)

[0146] Data matching and multiplication use multiplier IP. In order to meet the FFT calculation requirements, 56 zeros need to be padded. Data addition and multiplication will increase the data bit width. In order to ensure the output bit width, each output is set to 32-bit data. Using RAM as a cache can better meet the serial timing of FFT. Since the output of RAM will be delayed by two clocks, the signal enabling the FFT IP core must also be delayed by two clocks.

[0147] (2) FFT operation and control module

[0148] The FFT IP core is used for FFT operation to output the captured spectrum, including the output captured data in the spectrum position, spectrum amplitude, etc. Therefore, the FFT IP core needs to be configured to add the XK_INDEX signal for outputting the spectrum position. It should be noted that for data orthogonal demodulation, the orthogonal branch data needs to be a negative number. In order to ensure the spectrum position, the orthogonal branch data and the in-phase branch data can be exchanged. Otherwise, the input data of the orthogonal path needs to be transformed in sign.

[0149] Through the analysis of the simulation diagram, it can be seen that the data needs to be delayed for 6 clocks before the data valid bit starts to be valid and the capture result can be seen. In addition, the two clock signal delays introduced by the RAM, the data valid bit start and the valid data should differ by 8 clocks. The shift register can be used to delay the data and enable flag bit.

[0150] (3) Incoherent integration

[0151] The incoherent integration is realized by data modulo calculation. In addition, it is also necessary to retain the function of the data spectrum position after FFT calculation.

[0152] Note: The internal multiplier uses unsigned numbers for calculation and the multiplier output needs to be delayed by two clocks.

[0153] The steps for calculating the incoherent integral are as follows:

[0154] Step 1: Determine whether the real part and imaginary part of the complex number are negative. If they are negative, they need to be negated and added with 1 to become positive.

[0155] Step 2: Compare the absolute values ​​of the real part and the imaginary part of the complex number, set the smaller absolute value as data_min, and the larger absolute value as data_max; then set data_X = 7*data_max; data_Y = 3*data_min;

[0156] Step 3: If data_max>data_Y, then output formula (5); otherwise, output formula (6).

[0157]

[0158] Note: Here, the 32-bit signed number is converted into an unsigned number for judgment, and the data becomes 35-bit data after calculation with the 3-bit unsigned data 3 and 7. Therefore, the capture judgment module judges the spectrum data after incoherent integration.

[0159] (4) Capture decision module

[0160] The functions that need to be implemented in the capture judgment module are mainly as follows:

[0161] 1. The spectrum peak and peak position detection module needs to compare the spectrum data after incoherent integration one by one to detect the maximum value and maximum position of the incoherent integrated spectrum.

[0162] 2. The noise estimation module is used to estimate the signal noise and set the capture threshold. Based on the analysis in 3.3, this paper selects the mean of all the spectrum data captured this time as the noise estimate; since the false alarm probability needs to be lower than 10-5, the formula Calculation shows that the noise coefficient needs to be greater than or equal to 4.76. Since floating-point operations cannot be performed inside the FPGA, a noise coefficient of 5 is selected to meet the false alarm probability.

[0163] 3. Output capture parameters. The satellite navigation signal capture output parameters mainly include satellite number, Doppler frequency shift, and code phase delay. If the spectrum peak is greater than the capture threshold (the value of noise coefficient multiplied by noise), since floating-point operations cannot be performed inside the FPGA, the spectrum position accuracy is set to 390Hz, and the error is approximately spectrum position*0.625Hz. The code phase delay output parameter is set to 159*code phase step value / 100, with two decimal places.

[0164] 2.4.6 Design and verification of multi-channel parallel PMF-FFT acquisition algorithm module

[0165] Considering the internal resources of FPGA, this paper chooses to use 200 channels for parallel capture. Within 2ms, 200 channels can detect the code phase delay of 1600 sampling points, so the capture time of a single satellite is 0.8s, and the capture time of searching the entire satellite constellation is 63×0.8s=50.4s, which meets the circuit requirement of cold capture time less than 90s.

[0166] The capture control logic module is the core to ensure the operation of the capture algorithm. The capture algorithm designed in this paper is based on multi-channel parallel capture under cold capture conditions. Therefore, the main tasks of the capture control logic module design system are as follows:

[0167] 1. Ensure that the system is always running in a loop to capture signals.

[0168] 2. Implement cyclic control of satellite number PRN increment, and add 1 to PRN number after every 80 five-level pipelines.

[0169] 3. The realization of code phase includes parallel code phase control and serial code phase control.

[0170] A circuit synthesis netlist (register transfer level synthesis netlist) can be obtained.

[0171] What has been described above are only preferred specific implementations of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, can make equivalent replacements or changes based on the technical solutions and novel inventive concepts of the present invention, which should be covered by the protection scope of the present invention.

Claims

1. Design of a new FPGA-based Beidou signal fast capture IP circuit for high dynamic scenarios, including a single-channel PMF-FFT capture algorithm module, a capture decision logic module, and a high dynamic B1C signal parallel capture IP circuit design, characterized by: The single-channel PMF-FFT capture algorithm module includes a short-time matched filter operation module, an FFT state control module, an FFTIP operation module and a coherent integration module; the capture decision logic module includes a capture decision threshold generation module, a peak detection module and a comparison logic; the capture decision threshold generation module includes a noise estimation module; the high dynamic B1C signal parallel capture IP circuit design includes a digital down-conversion and filtering module, a data pipelining module and a parallel PMF-FFT capture algorithm module.

2. According to the high dynamic scene FPGA-based new system Beidou signal fast capture IP circuit design of claim 1, it is characterized by: The short-time matching filter operation module includes an in-phase parallel circuit design, which includes an autocorrelation calculation module, a short-time matching filter module and a RAM. The short-time matching filter operation module also includes an orthogonal path parallel circuit design, which includes an autocorrelation calculation module, a short-time matching filter module and a RAM.

3. According to the high dynamic scene FPGA-based new system Beidou signal fast capture IP circuit design of claim 1, it is characterized by: The digital down-conversion and filtering module includes a DDS signal generation module (COS signal), a filtering and truncation module and a (sin signal) DDS signal generation module.

4. According to the high dynamic scene FPGA-based new system Beidou signal fast capture IP circuit design of claim 1, it is characterized by: The data pipeline processing module includes an N-level pipeline state machine control module, and the N-level pipeline state machine control module is connected to the parallel PMF-FFT capture algorithm module.

5. According to the high dynamic scene FPGA-based new system Beidou signal fast capture IP circuit design of claim 1, it is characterized by: The parallel PMF-FFT capture algorithm module includes PMF-FFT capture algorithm module channels 1, 2 and 3, and the parallel PMF-FFT capture algorithm module also includes PMF-FFT capture algorithm module channel N. The PMF-FFT capture algorithm module channel N is connected to a capture detection module n, and the PMF-FFT capture algorithm module channels 1, 2 and 3 are connected to capture detection modules 1, 2 and 3.

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