Loop parameter compensation method of digital power supply chip and related product

Abstract

The invention provides a loop parameter compensation method, device and system for a digital power supply chip and a readable storage medium, and the method comprises the steps: responding to excitation signals generated by an excitation signal generation module at different moments based on a frequency test algorithm in a sampling process; calculating amplitude-frequency response data corresponding to a preset test frequency interval of the digital power supply chip; based on the amplitude-frequency response data, determining a direct-current gain of the digital power supply chip and a zero point and a pole point corresponding to a power level circuit in a sampling process; calculating compensation parameters of the digital power supply chip by combining the direct-current gain, the zero point and the pole point; and updating the compensation parameter into the digital filter so as to regulate and control the output voltage of the digital power supply chip. Through the implementation of the scheme of the invention, the application scene of the digital power supply chip is greatly expanded, and the optimal control of the output voltage of the digital power supply chip can still be realized under the condition that the power level parameters are changed.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a loop parameter compensation method, device, system and readable storage medium for a digital power chip. Background Art

[0002] With the development of new energy vehicles, 5G communications, artificial intelligence, computers and other electronic consumer products, the application scenarios of power management chips are becoming more and more abundant. As an important part of power management chips, digital power chips (such as DCDC chips) play a key role in these fields due to their high efficiency, stability and adjustable characteristics. DCDC chips can accurately adjust the output voltage through a negative feedback loop. When designing a negative feedback loop, the loop needs to be compensated to ensure its stability; appropriate compensation parameters can improve the load transient response speed of the DCDC chip. However, in the related art, it is necessary to set corresponding parameters for compensation according to different application scenarios. The process of determining the compensation parameters is relatively difficult, and the stability of the output voltage control of the digital power chip is difficult to guarantee. Summary of the invention

[0003] The embodiments of the present application provide a loop parameter compensation method, device, system and readable storage medium for a digital power chip, which can at least solve the problem of difficulty in updating loop compensation parameters in different application scenarios in related technologies.

[0004] In a first aspect, an embodiment of the present application provides a loop parameter compensation method for a digital power chip, which is applied to a digital power chip control system. The digital power chip control system includes a digital power chip, a power stage circuit and an excitation signal generating module electrically connected to the digital power chip, respectively, and the digital power chip includes a digital filter; including:

[0005] In response to the excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process, the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip is calculated; wherein the test frequencies corresponding to all the excitation signals belong to the preset test frequency interval;

[0006] Based on the amplitude-frequency response data, determine the DC gain of the digital power chip during the sampling process and the corresponding zeros and poles of the power stage circuit;

[0007] Calculate the compensation parameters of digital power chips by combining DC gain, zeros and poles;

[0008] The compensation parameters are updated to the digital filter to regulate the output voltage of the digital power chip.

[0009] A second aspect of the embodiment of the present application provides a loop parameter compensation device for a digital power chip, which is applied to a digital power chip control system. The digital power chip control system includes a digital power chip, a power stage circuit and an excitation signal generation module electrically connected to the digital power chip, respectively, and the digital power chip includes a digital filter; the device includes:

[0010] A first calculation module is used to calculate the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip in response to the excitation signals respectively generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process; wherein the test frequencies corresponding to all the excitation signals belong to the preset test frequency interval;

[0011] A determination module, used for determining the DC gain of the digital power chip and the zero points and poles corresponding to the power stage circuit during the sampling process based on the amplitude-frequency response data;

[0012] A second calculation module is used to calculate the compensation parameters of the digital power chip by combining the DC gain, zero point and pole;

[0013] The update module is used to update the compensation parameters into the digital filter to regulate the output voltage of the digital power chip.

[0014] The third aspect of the embodiment of the present application provides a digital power chip control system, including: an excitation signal generation module, a digital power chip, a power stage circuit, a memory and a processor, wherein the digital power chip is electrically connected to the excitation signal generation module; the excitation signal generation module is used to generate an excitation signal; the power stage circuit is electrically connected to the digital power chip, for realizing energy conversion and voltage regulation; the digital power chip includes a digital filter for performing loop compensation on the digital power chip according to compensation parameters; the processor is used to execute a computer program stored in the memory, and when the processor executes the computer program, it implements each step in the loop parameter compensation method of the digital power chip provided in the first aspect of the embodiment of the present application.

[0015] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, each step of the loop parameter compensation method for a digital power chip provided in the first aspect of the embodiment of the present application is implemented.

[0016] As can be seen from the above, according to the loop parameter compensation method, device, system and readable storage medium of the digital power chip provided by the scheme of the present application, in response to the excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process, the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip is calculated; wherein, the test frequencies corresponding to all excitation signals belong to the preset test frequency interval; based on the amplitude-frequency response data, the DC gain of the digital power chip and the zeros and poles corresponding to the power stage circuit during the sampling process are determined; the compensation parameters of the digital power chip are calculated by combining the DC gain, zeros and poles; the compensation parameters are updated to the digital filter to regulate the output voltage of the digital power chip. Through the implementation of the scheme of the present application, the compensation parameters are obtained by using the self-tuning algorithm of the on-chip loop, and the optimal control of the output voltage of the digital power chip can be achieved when the power stage parameters change; that is, flexible adjustment of the compensation parameters and optimal voltage output control under different loads and voltage requirements can be achieved to meet the needs of different application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the structure of a digital power chip control system provided in the first embodiment of the present application;

[0018] Figure 2 A basic flow chart of a loop parameter compensation method for a digital power chip provided in the first embodiment of the present application;

[0019] Figure 3 A flow chart of generating a sinusoidal excitation signal provided in the first embodiment of the present application;

[0020] Figure 4 A schematic diagram of the structure of an amplitude-frequency response calculation module provided in the first embodiment of the present application;

[0021] Figure 5 An amplitude-frequency response curve diagram provided for the first embodiment of the present application;

[0022] Figure 6 A schematic diagram of loop compensation of an IIR digital filter provided in the first embodiment of the present application;

[0023] Figure 7 A schematic diagram of a program module of a loop parameter compensation device for a digital power chip provided in the second embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0025] In the description of the embodiments of the present application, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0027] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0028] In order to solve the problem of difficulty in updating loop compensation parameters in different application scenarios in related technologies, the first embodiment of the present application provides a loop parameter compensation method for a digital power chip, which is applied to a digital power chip control system. The digital power chip control system includes a digital power chip, a power stage circuit and an excitation signal generating module electrically connected to the digital power chip, and the digital power chip includes a digital filter.

[0029] Furthermore, if Figure 1As shown, in one implementation of this embodiment, the digital power chip control system includes a loop of a digital power chip, a power stage circuit, and an excitation signal generation module, an amplitude-frequency response calculation module, a zero-pole detection module, and a loop compensation and self-tuning module for implementing the above-mentioned loop parameter compensation method; the power stage circuit is an external circuit and is the control object of the digital power chip; the digital filter is a part of the loop of the digital power chip; in addition, a PWM switch controller is also provided in the loop of the digital power chip: K PWM , voltage division ratio: K DIV , DAC gain: K DAC , Analog sampling pre-stage gain: K AFE , Error ADC quantization gain: K EADC , Voltage compensator: G COMP And the delay chain: G DELAY ; K PWM Respectively with the power stage circuit, G DELAY , the excitation signal generation module is connected to realize the adjustment of the PWM signal; K DIV Connected to the power stage circuit, it can be used to divide the input voltage to meet the chip's input voltage range requirements (input voltage requirement 0-1.6V) so as to synchronize with a specific power rail; K DAC It can be used to convert digital control signals into analog signals to control the switching action of power supply equipment; K DIV and K DAC The signal is used to add through the adder and then output to K AFE Middle; K AFE It can be used as the gain coefficient of the analog sampling pre-stage to amplify the input signal to adapt to different working conditions and load changes, thereby maintaining the stability and reliability of the power supply output; K EADC It can be used to compare the difference between the actual output voltage Vout and the reference output voltage Vref, obtain the first voltage input signal vsin, and adjust the parameters of the power supply control loop according to the comparison result to reduce the error between Vout and Vref; DELAY It can be used to control the voltage drop (dv / dt) within the allowable range by adjusting G DELAY The number of stages in the circuit can accurately control the rate of change of the voltage.

[0030] In some implementations of this embodiment, an excitation signal generation module, an amplitude-frequency response calculation module, a zero-pole detection module, and a loop compensation and self-tuning module are provided to implement a loop parameter compensation method for a digital power chip. Figure 2 The basic flow chart of the loop parameter compensation method of the digital power chip provided in this embodiment is as follows. The loop parameter compensation method of the digital power chip includes the following steps:

[0031] Step 201 : In response to the excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process, the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip is calculated.

[0032] Specifically, one excitation signal generates an excitation signal corresponding to one excitation signal; the test frequencies corresponding to all excitation signals belong to the preset test frequency range. The digital power chip of this embodiment may refer to a DCDC chip. After the voltage anomaly, current anomaly, temperature anomaly and other faults disappear, the DCDC chip has a variety of fault monitoring and protection functions such as automatic restart, which can ensure the stable operation of electronic equipment under various working conditions and improve the reliability and service life of the equipment. In addition, the DCDC chip also has functions such as adjustable output voltage and current. The amplitude-frequency response calculation module can perform input / output signal detection for each excitation signal received, and calculate the gain and phase of the input / output signal at the frequency. Combined with the gain and phase corresponding to multiple test frequencies, the amplitude-frequency response of the entire preset test frequency range is finally determined.

[0033] Step 202: Determine the DC gain of the digital power chip and the zeros and poles corresponding to the power stage circuit during the sampling process based on the amplitude-frequency response data.

[0034] Specifically, the zero-pole detection module can perform zero-pole matching based on a preset zero-pole matching rule, thereby ensuring the stability of the digital power chip loop and optimal control of the output voltage.

[0035] Step 203: Calculate compensation parameters of the digital power chip by combining the DC gain, zero point and pole.

[0036] Specifically, the loop compensation and self-tuning module can perform discretization mapping according to the above parameters such as DC gain, zero point and pole, and then obtain the required compensation parameters.

[0037] Step 204: Update the compensation parameters into the digital filter to regulate the output voltage of the digital power chip.

[0038] Specifically, the digital filter of this embodiment may refer to an IIR digital filter. By writing the calculated compensation parameters into the compensation parameter register (compensator) of the IIR digital filter, the loop compensation can be completed to achieve the expected loop gain and phase margin.

[0039] In one implementation of the present embodiment, before the step of calculating the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip in response to the multiple excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process, it also includes: for the generation of a single target excitation signal, the excitation signal generation module calculates the number of cycles and the cycle length reference value of the target excitation signal based on the frequency test algorithm; wherein the cycle reference value represents the number of clocks corresponding to one cycle of the target excitation signal; obtains the target voltage amplitude of the target excitation signal; combines the number of cycles, the cycle length reference value and the target voltage amplitude, performs PWM modulation on the loop of the digital power chip, and outputs the target excitation signal; wherein the power stage circuit is part of the loop.

[0040] Specifically, Figure 3 As shown, the excitation signal may refer to a white noise signal, a pulse signal, a sine signal, etc. Preferably, the excitation signal generated by the excitation signal generating module of this embodiment may be a sine signal. More specifically, the excitation signal may be generated based on the following rules: ①, according to the maximum value of the test frequency F meas_max Determine the sampling frequency F s , F s ≥ 2F meas_max ;②, according to the test frequency F meas Determine the test time t p , t p is an integer multiple of the test waveform, that is, t p =m*F meas (m), in some specific implementations, m can be agreed to be 20; ③, to avoid spectrum leakage, ensure that the number of sampling points N obtained by the frequency correction algorithm of the excitation signal generation module is an integer; ④, since the sinusoidal signal generates a clock F g Due to the limitations of meas signal, so it is necessary to meas After some correction, the excitation signal generation module can be based on the preset frequency test algorithm (for example: Rife algorithm) to F meas Corrected, the corrected F meas_modified , and calculate the reference value of the sine cycle length number_n and the number of cycles number_N. ⑤. Determine the duty cycle duty_dc when the loop is switched from closed loop to open loop, and obtain the sine signal amplitude duty_offset to be modulated and output according to the pre-set sine amplitude rule (that is, obtain the above-mentioned target voltage amplitude); ⑥. Perform PWM modulation based on the number_n, number_N and sine signal amplitude duty_offset calculated above, output the sinusoidal function for testing, and generate the target excitation signal.

[0041] In one implementation of the present embodiment, the above-mentioned step of calculating the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip in response to the multiple excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process includes: in response to the multiple excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process, respectively obtaining input signals corresponding to each excitation signal; wherein the input signal corresponding to a single excitation signal includes a first voltage input signal and a second voltage input signal; based on each input signal, respectively calculating the gain and phase corresponding to each test frequency, and determining all gains and phases as the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip.

[0042] Specifically, Figure 4 The structure diagram of an amplitude-frequency response calculation module provided by the present embodiment is shown. When receiving the excitation signal from the excitation signal generation module, the amplitude-frequency response calculation module can simultaneously detect the second voltage input signal isin and the first voltage input signal vsin, and then calculate the gain and phase of the input / output at the frequency. Based on the excitation signals corresponding to different test frequencies at different times, the gain and phase of the input / output at different frequencies can be calculated.

[0043] More specifically, the PWM modulation process can make the signal duty cycle show periodic changes according to the sin signal, so that the Vout obtained at the output end will also show a sine shape. The phase and gain can be obtained by Fourier transforming the first voltage input signal (that is, the above-mentioned error signal vsin) and the second voltage input signal (that is, the duty cycle sinusoidal signal isin: the reference excitation signal voltage amplitude given to the amplitude-frequency response calculation module); when modulating the duty cycle, isin is normalized with an amplitude of 0.1V according to the peak value of the modulated output voltage, and the DFT calculation result of the error signal vsin is the amplitude-frequency response data of the desired control target.

[0044] Furthermore, in one implementation of the present embodiment, the above-mentioned step of calculating the gain and phase corresponding to each test frequency based on each input signal includes: based on the Fourier transform law, calculating the reference amplitude of each excitation signal according to each input signal; wherein the reference amplitude includes the amplitude related to the real part and the amplitude related to the imaginary part; based on each reference amplitude, calculating the gain and phase corresponding to each test frequency.

[0045] Specifically, the calculation process of the reference amplitude can be implemented based on the following calculation formula:

[0046]

[0047] Among them, F s Indicates the sampling frequency, Fg Indicates the frequency of the sinusoidal signal, F meas Indicates the test frequency, n represents a cycle of T meas T required for a sine wave g Number, N represents the number of DFT points, k represents the relative value of the test frequency and the sampling frequency in the frequency domain, and the sampling frequency is determined based on the maximum value of the test frequency in the preset test frequency interval. p represents the sampling time, X(k) represents the data after DFT transformation, x(n) represents the sampled analog signal, real(k) represents the amplitude of the real part, and imag(k) represents the amplitude of the imaginary part. The products of different x(n) with cos and sin are summed respectively, and then accumulated under different k, and the obtained vsin_sum and vcos_sum are the final results of DFT transformation.

[0048] Furthermore, in one implementation of this embodiment, the above-mentioned step of respectively calculating the gain and phase corresponding to each test frequency based on each reference amplitude includes: respectively calculating the gain corresponding to each test frequency based on a first calculation formula; wherein the first calculation formula is expressed as:

[0049]

[0050] Based on the second calculation formula, the phase corresponding to each test frequency is calculated respectively; wherein the second calculation formula is expressed as:

[0051]

[0052] Here, |z| represents the gain and θ represents the phase.

[0053] In one implementation of the present embodiment, the above-mentioned step of determining the DC gain of the digital power chip and the zeros and poles corresponding to the power stage circuit during the sampling process based on the amplitude-frequency response data includes: generating a corresponding amplitude-frequency response curve graph based on the amplitude-frequency response data, and determining the gain corresponding to the preset frequency in the amplitude-frequency response curve graph as the DC gain of the digital power chip during the sampling process; based on a preset zero-pole matching rule, determining the zeros and poles corresponding to the power stage circuit from the amplitude-frequency response curve graph.

[0054] Specifically, based on the gain and phase calculation results of each test frequency point, the amplitude-frequency response curve of the tested target can be drawn, such as Figure 5As shown. It should be noted that the zero point refers to the point in the frequency response of the system where the transfer function is zero, and the pole is the point in the denominator where the transfer function is zero; the position of the pole determines the cutoff frequency and roll-off rate of the filter. By selecting the appropriate zero point position, it is possible to enhance or suppress a specific frequency band, thereby achieving the specific function of the filter. By adjusting the position of the zero point and the pole, the gain or attenuation of the filter at different frequencies can be controlled.

[0055] In a specific implementation, the working process of the zero-pole detection module can be performed as follows: ①, find the frequency point where the test frequency is near the low frequency in the amplitude-frequency response curve (for example, 100 Hz), and determine the data corresponding to the frequency as the DC gain K of the amplitude-frequency response. DC ②. Obtain K in the amplitude-frequency response curve DC The result of the DC gain of the amplitude-frequency response at -3dB is used to determine the corresponding frequency point as the double-pole frequency point W of the power stage circuit. P12_PT ③. Based on the switching frequency F configured inside the digital power chip switch , calculate the loop working bandwidth F B :F B =10%*F switch ; Loop working bandwidth F B It refers to the highest frequency that the controller can effectively respond to while maintaining stable performance, through the loop working bandwidth F B The setting can ensure that the system can maintain a stable and fast response when the load changes quickly and the input voltage fluctuates. ④. Pole placement: Place a pole WP1 at low frequency to increase the loop low-frequency gain. ⑤. The double-pole frequency W monitored by the power stage zero-pole monitoring module P12_PT Place a pair of zero points WZ1 and WZ2 at the first 90% position. ⑥ At 1 / 5*F s The second pole WP2 is placed at the input to suppress high frequency noise.

[0056] In one implementation of the present embodiment, before the step of calculating the compensation parameters of the digital power chip in combination with the DC gain, zero point and pole, the step further includes: constructing a loop compensation model of the digital power chip based on the power stage circuit, and determining the transfer function corresponding to the loop compensation model; mapping the transfer function from the s domain to the z domain to obtain the target transfer function; thereby, the step of calculating the compensation parameters of the digital power chip in combination with the DC gain, zero point and pole includes: calculating the compensation parameters of the digital power chip based on the target transfer function in combination with the DC gain, zero point and pole.

[0057] Specifically, the digital filter of this embodiment may be an IIR digital filter. Figure 6The following is a schematic diagram of loop compensation for an IIR digital filter. DC , WP1, WZ1, WZ2, WP2; map it from the S domain to the Z domain, extract the compensation parameters of the compensator according to the structure of the IIR digital filter: b0, b1, b2, a1, a2, write the compensation parameters into the compensation parameter register of the IIR digital filter, and the loop compensation can be completed to achieve the expected loop gain and phase margin. More specifically, the process of mapping the transfer function from the s domain to the z domain, that is, the process of converting the PID compensator from a continuous-time system design to a discrete-time system; can be achieved using bilinear transformation (Bilinear transformation) or other mapping methods, which can maintain the key frequency response characteristics between continuous-time and discrete-time systems, and ensure that the stability, response speed and noise resistance of the compensator can be reliably retained during the conversion process.

[0058] In one implementation of this embodiment, for a second-order system, the following is adopted: Figure 5 The IIR digital filter shown in the figure is used for compensation. Taking the BUCK circuit as an example, the loop compensation model is modeled according to the power stage circuit, and the second-order transfer function of the circuit structure is calculated based on the average state space method. It has a pair of resonant poles and a zero point formed by the output capacitor and its parasitic resistance; the transfer function expression is as follows:

[0059]

[0060] Where: d represents the duty cycle of the PWM signal, R S Represents the sum of the on-resistance of the MOSFET and the parasitic resistance of the inductor, R C Represents the parasitic resistance of the output capacitor, R L represents output impedance, L represents inductance, C represents output capacitance, s represents an imaginary variable in the S domain, C S represents the load capacitance of the power stage, V in Indicates the input voltage.

[0061] The corresponding K is calculated by loop compensation and self-tuning module. DC, WP1, WZ1, WZ2, WP2 compensation parameters b0, b1, b2, a1, a2, write b0, b1, b2, a1, a2 into the PID compensator, and the desired loop compensation can be achieved. The above-mentioned entire calculation process is completely implemented on-chip, and it takes about 1 minute to complete an adaptive loop compensation for load switching without manually changing the chip configuration. It should be noted that in the above-mentioned implementation mode, the specific placement positions of the two zeros and two poles used for compensation have been illustrated in the above-mentioned step of "determining the zeros and poles corresponding to the power stage circuit from the amplitude-frequency response curve diagram", which will not be repeated here; one of the redundant poles is placed at 1 / 5 of the switching frequency, which is much higher than the loop bandwidth, and can suppress high-frequency noise.

[0062] Based on the technical solution of the embodiment of the present application described above, in response to the excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process, the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip is calculated; wherein, the test frequencies corresponding to all excitation signals belong to the preset test frequency interval; based on the amplitude-frequency response data, the DC gain of the digital power chip during the sampling process and the zeros and poles corresponding to the power stage circuit are determined; the compensation parameters of the digital power chip are calculated in combination with the DC gain, zeros and poles; the compensation parameters are updated to the digital filter to regulate the output voltage of the digital power chip. Through the implementation of the solution of the present application, it can be ensured that the DCDC chip has the optimal output voltage under different loads, which greatly simplifies the circuit design under different power application scenarios, and greatly expands the application scenarios of the chip. For different loads, different output voltages, different switching frequencies, etc., the optimal control of the power supply output voltage can be achieved.

[0063] Figure 7 A loop parameter compensation device for a digital power chip is provided in the second embodiment of the present application; it is applied to a digital power chip control system, the digital power chip control system includes a digital power chip, a power stage circuit and an excitation signal generation module electrically connected to the digital power chip, and the digital power chip includes a digital filter. The loop parameter compensation device for a digital power chip can be applied to the loop parameter compensation method of the aforementioned digital power chip. Figure 7 As shown, the loop parameter compensation device of the digital power chip mainly includes:

[0064] The first calculation module 701 is used to calculate the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip in response to the excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process; wherein the test frequencies corresponding to all the excitation signals belong to the preset test frequency interval;

[0065] A determination module 702 is used to determine the DC gain of the digital power chip and the zeros and poles corresponding to the power stage circuit during the sampling process based on the amplitude-frequency response data;

[0066] The second calculation module 703 is used to calculate the compensation parameters of the digital power chip by combining the DC gain, zero point and pole;

[0067] The updating module 704 is used to update the compensation parameters into the digital filter to adjust the output voltage of the digital power chip.

[0068] In some implementations of the present embodiment, an excitation signal generating module is further included, and the excitation signal generating module is specifically used to: calculate the number of cycles and the reference value of the cycle length of the target excitation signal based on the frequency test algorithm; wherein the cycle reference value represents the number of clocks corresponding to one cycle of the target excitation signal; obtain the target voltage amplitude of the target excitation signal; combine the number of cycles, the reference value of the cycle length and the target voltage amplitude, perform PWM modulation on the loop of the digital power chip, and output the target excitation signal; wherein the power stage circuit is part of the loop.

[0069] In some implementations of this embodiment, when the first calculation module performs the above-mentioned function of calculating the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip in response to the multiple excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process, it is specifically used to: in response to the multiple excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process, respectively obtain the input signal corresponding to each excitation signal; wherein the input signal corresponding to a single excitation signal includes a first voltage input signal and a second voltage input signal;

[0070] Based on each input signal, the gain and phase corresponding to each test frequency are calculated respectively, and all gains and phases are determined as amplitude-frequency response data corresponding to a preset test frequency interval of the digital power chip.

[0071] Further, in some implementations of the present embodiment, when the first calculation module executes the above-mentioned function of respectively calculating the gain and phase corresponding to each test frequency based on each input signal, it is specifically used to: based on the Fourier transform law, respectively calculate the reference amplitude of each excitation signal according to each input signal; wherein the reference amplitude includes the amplitude related to the real part and the amplitude related to the imaginary part; based on each reference amplitude, respectively calculate the gain and phase corresponding to each test frequency.

[0072] Furthermore, in some implementations of this embodiment, when the first calculation module performs the above-mentioned function of calculating the gain and phase corresponding to each test frequency based on each reference amplitude, it is specifically used to: calculate the gain corresponding to each test frequency based on the first calculation formula; wherein the first calculation formula is expressed as:

[0073]

[0074] Based on the second calculation formula, the phase corresponding to each test frequency is calculated respectively; wherein the second calculation formula is expressed as:

[0075]

[0076] Among them, |z| represents gain, real(k) represents the amplitude of the real part, imag(k) represents the amplitude of the imaginary part, k represents the relative value of the test frequency and the sampling frequency in the frequency domain, the sampling frequency is determined based on the maximum value of the test frequency in the preset test frequency interval, and θ represents the phase.

[0077] In some implementations of this embodiment, the determination module is specifically used to: generate a corresponding amplitude-frequency response curve diagram based on the amplitude-frequency response data, and determine the gain corresponding to the preset frequency in the amplitude-frequency response curve diagram as the DC gain of the digital power chip during the sampling process; based on a preset zero-pole matching rule, determine the zero points and poles corresponding to the power stage circuit from the amplitude-frequency response curve diagram.

[0078] In some implementations of this embodiment, a construction module is further included, and the construction module is used to: construct a loop compensation model of the digital power chip based on the power stage circuit, and determine the transfer function corresponding to the loop compensation model; map the transfer function from the s domain to the z domain to obtain the target transfer function; When the second calculation module performs the above-mentioned function of calculating the compensation parameters of the digital power chip in combination with the DC gain, zero point and pole, it is specifically used to: calculate the compensation parameters of the digital power chip based on the target transfer function in combination with the DC gain, zero point and pole.

[0079] According to the loop parameter compensation device of the digital power chip provided in this embodiment, in response to the excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process, the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip is calculated; wherein, the test frequencies corresponding to all excitation signals belong to the preset test frequency interval; based on the amplitude-frequency response data, the DC gain of the digital power chip during the sampling process and the zeros and poles corresponding to the power stage circuit are determined; the compensation parameters of the digital power chip are calculated in combination with the DC gain, zeros and poles; the compensation parameters are updated to the digital filter to regulate the output voltage of the digital power chip. Through the implementation of the scheme of this application, it can be ensured that the DCDC chip has the optimal output voltage under different loads, which greatly simplifies the circuit design under different power application scenarios, and greatly expands the application scenarios of the chip. For different loads, different output voltages, different switching frequencies, etc., the optimal control of the power supply output voltage can be achieved.

[0080] The third embodiment of the present application provides a digital power chip control system. The digital power chip control system can be used to implement the loop parameter compensation method of the digital power chip in the aforementioned embodiment, and mainly includes: a digital power chip, a power stage circuit, a memory, a processor, and a computer program stored in the memory and executable on the processor. The memory and the processor are connected by communication. When the processor executes the computer program, the method in the aforementioned embodiment 1 is implemented. The number of processors may be one or more, which are used to execute the corresponding computer program to implement the functions corresponding to the above-mentioned excitation signal generation module, the amplitude-frequency response calculation module, the zero-pole detection module, and the loop compensation and self-tuning module. Specifically, the digital power chip is electrically connected to the excitation signal generation module, and the excitation signal generation module is used to generate an excitation signal; the power stage circuit is electrically connected to the digital power chip, and is used to realize energy conversion and voltage regulation; the digital power chip includes a digital filter for loop compensation of the digital power chip according to the compensation parameters.

[0081] The memory may be a high-speed random access memory (RAM) memory or a non-volatile memory, such as a disk memory. The memory is used to store executable program codes, and the processor is coupled to the memory.

[0082] Furthermore, an embodiment of the present application also provides a computer-readable storage medium, which may be arranged in the above-mentioned digital power chip control system, and the computer-readable storage medium may be the memory in the aforementioned embodiment.

[0083] The computer readable storage medium stores a computer program, and when the program is executed by the processor, the loop parameter compensation method of the digital power chip in the aforementioned embodiment is implemented. Furthermore, the computer storable medium can also be a U disk, a mobile hard disk, a read-only memory (ROM), a RAM, a magnetic disk or an optical disk, and other media that can store program codes.

[0084] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely exemplary. For example, the division of modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0085] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0086] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0087] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a readable storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned readable storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0088] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0089] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0090] The above is a description of the loop parameter compensation method, device, system and readable storage medium of the digital power chip provided in the present application. For technicians in this field, according to the ideas of the embodiments of the present application, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A loop parameter compensation method for a digital power chip, applied to a digital power chip control system, wherein the digital power chip control system comprises a digital power chip, a power stage circuit and an excitation signal generating module respectively electrically connected to the digital power chip, and the digital power chip comprises a digital filter; characterized in that: The loop parameter compensation method comprises: In response to the excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process, the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip is calculated; wherein the test frequencies corresponding to all the excitation signals belong to the preset test frequency interval; Based on the amplitude-frequency response data, determining the DC gain of the digital power chip and the zero points and poles corresponding to the power stage circuit during the sampling process; Calculate compensation parameters of the digital power chip by combining the DC gain, the zero point and the pole; The compensation parameter is updated to the digital filter to regulate the output voltage of the digital power chip.

2. The loop parameter compensation method of the digital power chip according to claim 1, characterized in that: Before calculating the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip in response to the multiple excitation signals generated by the excitation signal generation module at different times based on the frequency test algorithm of the digital power chip during the sampling process, the method further includes: For the generation of a single target excitation signal, the excitation signal generation module calculates the number of cycles and the reference value of the cycle length of the target excitation signal based on the frequency test algorithm; wherein the reference value of the cycle represents the number of clocks corresponding to one cycle of the target excitation signal; Acquiring a target voltage amplitude of the target excitation signal; In combination with the number of cycles, the reference value of the cycle length and the target voltage amplitude, PWM modulation is performed on the loop of the digital power chip to output the target excitation signal; wherein the power stage circuit is a part of the loop.

3. The loop parameter compensation method of the digital power chip according to claim 1, characterized in that: The step of calculating the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip in response to the multiple excitation signals generated by the excitation signal generation module based on the frequency test algorithm at different times during the sampling process includes: In response to a plurality of excitation signals generated by the excitation signal generation module based on the frequency test algorithm at different times during the sampling process, input signals corresponding to the excitation signals are respectively acquired; wherein the input signal corresponding to a single excitation signal includes a first voltage input signal and a second voltage input signal; Based on each of the input signals, the gain and phase corresponding to each of the test frequencies are calculated respectively, and all of the gains and phases are determined as amplitude-frequency response data corresponding to a preset test frequency interval of the digital power chip.

4. The loop parameter compensation method of the digital power chip according to claim 3, characterized in that: The step of calculating the gain and phase corresponding to each of the test frequencies based on each of the input signals comprises: Based on the Fourier transform rule, the reference amplitude of each of the excitation signals is calculated according to each of the input signals; wherein the reference amplitude includes an amplitude related to the real part and an amplitude related to the imaginary part; Based on the reference amplitudes, the gain and phase corresponding to the test frequencies are calculated respectively.

5. The loop parameter compensation method of the digital power chip according to claim 4, characterized in that: The step of calculating the gain and phase corresponding to each of the test frequencies based on each of the reference amplitudes comprises: Based on the first calculation formula, the gains corresponding to the test frequencies are calculated respectively; wherein the first calculation formula is expressed as: Based on the second calculation formula, the phase corresponding to each of the test frequencies is calculated respectively; wherein the second calculation formula is expressed as: Among them, |z| represents the gain, real(k) represents the amplitude related to the real part, imag(k) represents the amplitude related to the imaginary part, k represents the relative value of the test frequency and the sampling frequency in the frequency domain, the sampling frequency is determined based on the maximum value of the test frequency in the preset test frequency interval, and θ represents the phase.

6. The loop parameter compensation method of a digital power chip according to any one of claims 1 to 5, characterized in that: The determining, based on the amplitude-frequency response data, the DC gain of the digital power chip and the zero points and poles corresponding to the power stage circuit during the sampling process includes: Generate a corresponding amplitude-frequency response curve graph based on the amplitude-frequency response data, and determine the gain corresponding to the preset frequency in the amplitude-frequency response curve graph as the DC gain of the digital power chip during the sampling process; Based on a preset zero-pole matching rule, the zeros and poles corresponding to the power stage circuit are determined from the amplitude-frequency response curve diagram.

7. The loop parameter compensation method of a digital power chip according to any one of claims 1 to 5, characterized in that: Before calculating the compensation parameters of the digital power chip by combining the DC gain, the zero point and the pole, the method further includes: Constructing a loop compensation model of the digital power chip based on the power stage circuit, and determining a transfer function corresponding to the loop compensation model; Mapping the transfer function from the s domain to the z domain to obtain a target transfer function; The step of calculating the compensation parameters of the digital power chip by combining the DC gain, the zero point and the pole includes: Based on the target transfer function, in combination with the DC gain, the zero point and the pole, the compensation parameters of the digital power chip are calculated.

8. A loop parameter compensation device for a digital power chip, applied to a digital power chip control system, the digital power chip control system comprising a digital power chip, a power stage circuit and an excitation signal generating module respectively electrically connected to the digital power chip, the digital power chip comprising a digital filter; characterized in that: The loop parameter compensation device comprises: A first calculation module, configured to calculate the amplitude-frequency response data corresponding to the preset test frequency interval of the digital power chip in response to the excitation signals respectively generated by the excitation signal generation module at different times based on the frequency test algorithm during the sampling process; wherein the test frequencies corresponding to all the excitation signals belong to the preset test frequency interval; A determination module, used to determine the DC gain of the digital power chip and the zero points and poles corresponding to the power stage circuit during the sampling process based on the amplitude-frequency response data; A second calculation module, used to calculate the compensation parameters of the digital power chip by combining the DC gain, the zero point and the pole; An updating module is used to update the compensation parameter into the digital filter to regulate the output voltage of the digital power chip.

9. A digital power chip control system, characterized in that: It includes an excitation signal generation module, a digital power chip, a power stage circuit, a memory and a processor, wherein: The digital power chip is electrically connected to the excitation signal generating module; the excitation signal generating module is used to generate an excitation signal; the power stage circuit is electrically connected to the digital power chip, and is used to realize energy conversion and voltage regulation; the digital power chip includes a digital filter for loop compensation of the digital power chip according to compensation parameters; The processor is used to execute the computer program stored in the memory; When the processor executes the computer program, the steps in the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the method according to any one of claims 1 to 7 are implemented.

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