Branch prediction method, branch predictor and related equipment

Abstract

The embodiment of the invention provides a branch prediction method, a branch predictor and related equipment. The method comprises the following steps: acquiring address information and first identification information of a to-be-predicted instruction; based on the address information, a pre-stored target address of a target instruction corresponding to the instruction to be predicted and redundant information of the target address are obtained, and the redundant information comprises second identification information and permission information; if the to-be-predicted instruction is a user mode instruction, judging whether the first identification information is consistent with the second identification information or not, and if the first identification information is consistent with the second identification information, allowing to execute access of the target address; if the to-be-predicted instruction is a kernel mode instruction, judging whether the permission information is a privilege level identifier or not; and if yes and the first identification information is consistent or inconsistent with the second identification information, allowing to execute access of the target address. According to the embodiment, the instruction processing efficiency can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of processor technology, and in particular to a branch prediction method, a branch predictor, and related devices. Background Art

[0002] In modern processors, instructions need to go through the processes of instruction fetch, decoding, execution and write back; among them, instruction fetch is used to obtain the instructions to be executed, decoding is used to parse and translate the fetched instructions to obtain the micro-instructions (micro-op, Uop) corresponding to the instructions, execution is used to perform the corresponding instruction operations based on the micro-instructions obtained by decoding, and write back is used to write the results of the instruction operation back to the preset address.

[0003] However, the existing instruction processing flow and instruction processing efficiency need to be improved. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a branch prediction method, a branch predictor, and related devices to improve instruction processing efficiency.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a branch prediction method, comprising:

[0007] Acquire address information and first identification information of an instruction to be predicted, where the first identification information is used to indicate a source of the instruction to be predicted;

[0008] Based on the address information, obtaining a pre-stored target address of a target instruction corresponding to the instruction to be predicted and redundant information of the target address, the redundant information including second identification information and permission information, the second identification information being used to indicate a source of a historical instruction from which the target instruction was obtained, and the permission information being used to indicate whether the historical instruction from which the target instruction was obtained was a privileged instruction;

[0009] If the instruction to be predicted is a user-mode instruction, determining whether the first identification information and the second identification information are consistent; if the first identification information and the second identification information are consistent, allowing execution of access to the target address;

[0010] If the instruction to be predicted is a kernel-mode instruction, determine whether the permission information is a privilege level identifier; if so, and the first identification information and the second identification information are consistent or inconsistent, allow access to the target address.

[0011] Optionally, if the instruction to be predicted is a kernel-mode instruction, determining whether the permission information is a privilege level identifier; if so, and the first identification information and the second identification information are consistent or inconsistent, executing access to the target address, specifically:

[0012] If the instruction to be predicted is a kernel-mode instruction, determining whether the permission information is a privileged level identifier; if so, skipping the step of determining whether the first identification information and the second identification information are consistent, and executing access to the target address;

[0013] or,

[0014] If the instruction to be predicted is a kernel-mode instruction, determine whether the permission information is a privileged level identifier, and determine whether the first identification information and the second identification information are consistent. If the permission information is a privileged level identifier, and the first identification information and the second identification information are consistent or inconsistent, execute access to the target address.

[0015] Optionally, the redundant information further includes a valid identifier for marking whether the target address is valid, and the method further includes:

[0016] Receive a valid identification refresh instruction;

[0017] Based on the valid flag refresh instruction, executing a process of updating the valid flag of the target address stored in the branch target buffer;

[0018] Among them, the update process includes: determining whether the permission information of the target address is a privileged level identifier; if not, updating the valid identifier of the target address to a first value, the first value being used to mark the target address as invalid; if so, skipping the item where the target address is located.

[0019] Optionally, after obtaining, based on the address information, a pre-stored target address of a target instruction corresponding to the instruction to be predicted and redundant information of the target address, and before accessing the target address, the method further includes:

[0020] Based on the valid identifier, determining whether the target address is valid;

[0021] If not, access to the target address is prohibited.

[0022] Optionally, the first identification information is the processor core identification or the logical core identification that initiates the instruction to be predicted, and the second identification information is the processor core identification or the logical core identification that initiates the historical instruction.

[0023] Optionally, in a virtualization scenario, the kernel-state instruction is a kernel-state instruction of the host.

[0024] In a second aspect, an embodiment of the present application provides a branch predictor, comprising:

[0025] Instruction information acquisition logic, used to acquire address information and first identification information of the instruction to be predicted, where the first identification information is used to indicate a source of the instruction to be predicted;

[0026] Prediction information acquisition logic, configured to acquire, based on the address information, a pre-stored target address of a target instruction corresponding to the instruction to be predicted and redundant information of the target address, the redundant information including second identification information and permission information, the second identification information being used to indicate a source of a historical instruction from which the target instruction was obtained, and the permission information being used to indicate whether the historical instruction from which the target instruction was obtained was a privileged instruction;

[0027] Access determination logic is used to determine whether the first identification information and the second identification information are consistent if the instruction to be predicted is a user-state instruction, and if so, allow execution of access to the target address; if the instruction to be predicted is a kernel-state instruction, determine whether the permission information is a privileged level identification; if so, and if the first identification information and the second identification information are consistent or inconsistent, allow execution of access to the target address.

[0028] Optionally, the access determination logic is configured to, if the instruction to be predicted is a kernel-mode instruction, determine whether the permission information is a privilege level identifier; if so, and the first identification information and the second identification information are consistent or inconsistent, execute access to the target address, specifically:

[0029] If the instruction to be predicted is a kernel-mode instruction, determining whether the permission information is a privileged level identifier; if so, skipping the step of determining whether the first identification information and the second identification information are consistent, and executing access to the target address;

[0030] or,

[0031] If the instruction to be predicted is a kernel-mode instruction, determine whether the permission information is a privileged level identifier, and determine whether the first identification information and the second identification information are consistent. If the permission information is a privileged level identifier, and the first identification information and the second identification information are consistent or inconsistent, execute access to the target address.

[0032] Optionally, the redundant information further includes a valid flag for marking whether the target address is valid, and the branch predictor further includes:

[0033] Redundant information refresh logic, configured to receive a valid flag refresh instruction; and execute a process of updating the valid flag of the target address stored in the branch target buffer based on the valid flag refresh instruction;

[0034] Among them, the update process includes: determining whether the permission information of the target address is a privileged level identifier; if not, updating the valid identifier of the target address to a first value, the first value being used to mark the target address as invalid; if so, skipping the item where the target address is located.

[0035] Optionally, the access determination logic is further used to determine whether the target address is valid based on the valid identifier; if not, prohibiting access to the target address.

[0036] Optionally, the first identification information is the processor core identification or the logical core identification that initiates the instruction to be predicted, and the second identification information is the processor core identification or the logical core identification that initiates the historical instruction.

[0037] Optionally, in a virtualization scenario, the kernel-state instruction is a kernel-state instruction of the host.

[0038] In a third aspect, an embodiment of the present application further provides a processor, comprising the branch predictor described in the second aspect.

[0039] In a fourth aspect, an embodiment of the present application further provides a chip, comprising the processor provided in the third aspect of the embodiment of the present application.

[0040] In a fifth aspect, an embodiment of the present application further provides an electronic device, comprising the chip provided in the fourth aspect of the embodiment of the present application.

[0041] In a sixth aspect, an embodiment of the present application further provides a storage medium, wherein the storage medium stores one or more computer-executable instructions, and the one or more computer-executable instructions are used to execute the branch prediction method as described in the first aspect.

[0042] In a seventh aspect, an embodiment of the present application further provides a computer program product comprising one or more computer executable instructions, which, when executed, implement the branch prediction method as described in the first aspect.

[0043] The branch prediction method, branch predictor and related equipment provided by the embodiments of the present application include: obtaining address information and first identification information of an instruction to be predicted, wherein the first identification information is used to indicate the source of the instruction to be predicted; based on the address information, obtaining a pre-stored target address of a target instruction corresponding to the instruction to be predicted and redundant information of the target address, wherein the redundant information includes second identification information and permission information, wherein the second identification information is used to indicate the source of a historical instruction from which the target instruction was obtained, and the permission information is used to indicate whether the historical instruction from which the target instruction was obtained is a privileged instruction; if the instruction to be predicted is a user-mode instruction, determining whether the first identification information and the second identification information are consistent; if the first identification information and the second identification information are consistent, allowing execution of access to the target address; if the instruction to be predicted is a kernel-mode instruction, determining whether the permission information is a privileged-level identification; if so, and the first identification information and the second identification information are consistent or inconsistent, allowing execution of access to the target address.

[0044] It can be seen that in the branch prediction process of the embodiment of the present application, when the instruction to be predicted is a user-state instruction, the identification information is judged based on the normal process, that is, whether the first identification information and the second identification information are consistent is judged. When the first identification information and the second identification information are consistent, the access to the target address is allowed to be executed; and when the instruction to be predicted is a kernel-state instruction, whether the permission information is a privileged level identification is judged. When the permission information is a privileged level identification, the access to the target address can be executed regardless of whether the corresponding identification information is consistent, so that the kernel-state instruction can be accessed across sources, thereby improving the instruction processing efficiency while ensuring the original security effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0046] Figure 1 An optional diagram of the instruction processing flow.

[0047] Figure 2 A schematic diagram of instruction processing timing in an instruction pipeline.

[0048] Figure 3 An optional flow diagram for branch instruction prediction.

[0049] Figure 4 A schematic diagram of a predictive controlled process.

[0050] Figure 5 This is a schematic diagram of an optional structure of a BTB item.

[0051] Figure 6 An alternative diagram of the branch prediction process.

[0052] Figure 7 This is a schematic diagram of an optional structure of a BTB item.

[0053] Figure 8 A schematic diagram of BTB item access under the IBRS mechanism.

[0054] Figure 9 A schematic diagram of BTB entry access.

[0055] Figure 10 A schematic diagram of an optional flow chart of a branch prediction method provided in an embodiment of the present application.

[0056] Figure 11 A schematic diagram of an optional structure of a BTB item provided in an embodiment of the present application.

[0057] Figure 12 A schematic diagram of a prediction information refresh process in a branch prediction method provided in an embodiment of the present application.

[0058] Figure 13 An optional flowchart of a branch prediction method provided in an embodiment of the present application.

[0059] Figure 14 This is an optional structural diagram of a branch predictor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0061] In the general instruction processing flow, refer to Figure 1The following is an optional diagram of the instruction processing flow. Instructions typically go through the following processes: instruction fetch, decode, execute, and write back. Instruction fetch is the process of fetching the instruction corresponding to the program from the processor's cache or main memory; decoding is the process of decoding the fetched instruction to determine the instruction's opcode and / or address; execution is the process of executing the instruction based on the obtained opcode and / or address to execute the program. Write back is the process of writing the result of executing the program to a register with a preset address.

[0062] Processors typically use instruction pipelining to improve instruction processing efficiency. In this technique, different hardware modules are configured for different processing steps. In the processor's pipeline operation, multiple instructions at different processing steps can be processed and transferred sequentially within the corresponding hardware modules.

[0063] refer to Figure 2 A schematic diagram of instruction processing timing in an instruction pipeline is shown, as shown in FIG. Figure 2 As shown in the figure, the processor can fetch instruction 2 in advance when instruction 1 enters the decoding stage. When instruction 1 enters the execution stage, it can decode instruction 2 and fetch instruction 3 in parallel. When instruction 1 enters the write-back stage, the processor can execute instruction 2, decode instruction 3, and fetch instruction 4. When instruction 1 is submitted, the processor can write back instruction 2, execute instruction 3, decode instruction 4, and fetch instruction 5, and so on, thereby achieving parallel execution of multiple instructions. It can be seen that within two clock cycles t1 and t2, the instruction pipeline technology can complete five instructions. Compared with the serial execution instruction process that can only complete one instruction per clock cycle, the instruction processing efficiency is greatly improved.

[0064] However, when processing branch instructions (a type of instruction), a branch prediction mechanism is needed to reduce instruction latency. It can be understood that a branch instruction is an instruction that can change the direction of the program flow. In a specific program flow, a branch instruction can execute different instruction sequences (i.e., enter different branch flows) based on different instruction results. Figure 3The figure shows an alternative flow diagram for branch instruction prediction. Branch instruction N needs to enter different branch processes, namely branch N1 and branch N2, based on the result of instruction M. At this time, if the instructions are executed according to normal logic, branch instruction N needs to wait for the result of instruction M, such as result M1 or result M2. However, in the processor's pipeline operation, multiple instructions at different processing stages are processed simultaneously within different hardware logic. The delay of one instruction can block the processing of multiple other instructions in the subsequent pipeline, causing pipeline delays.

[0065] In order to reduce the pipeline delay caused by the processor waiting for the instruction result of the branch instruction to determine the next instruction to be fetched, the branch prediction mechanism of the instruction can be used to predict which instruction to execute next (such as Figure 3 The branches Ni shown, where i can be 1 or 2, reduce the waiting time of the processor when executing the branch instruction.

[0066] In an optional prediction mechanism, a corresponding prediction can be made based on the target address of the branch instruction. Specifically, the address information of the historical branch instruction and the target address corresponding to the historical branch instruction are stored in an entry of the BTB (BranchTarget Buffer). When a branch instruction with the same address information subsequently appears, the target address corresponding to the historical branch instruction is used as the address of the predicted target instruction, thereby achieving prediction of the branch instruction. The information stored in the entry can be called the prediction information of the BTB.

[0067] However, this prediction mechanism has security risks. In a specific scenario, such as Spectre Variant 2, an attacker can control the branch predictor's prediction target through training, leading the victim to speculatively execute certain malicious code and access confidential data. Figure 4 As shown in the schematic diagram of the predictive controlled flow, an attacker can use the branch instruction at the PC1 address to train a BTB entry in the attacker's address space. For example, the attacker can control the branch instruction at PC1 to jump to a target address PC4, so that the target address corresponding to the branch instruction stored in the BTB entry is the victim address PC4 that meets the attacker's intention. The attacker can control the address information (such as the HASH value of the address) recorded in the entry of the branch instruction of PC1 to be equal to the address information (such as the HASH value of the address) of the branch instruction at the victim PC2.

[0068] When the victim executes the branch instruction at PC2, because the address information of the branch instruction at PC2 (such as the address's HASH value) collides with the address information of the branch instruction at PC1 (such as the address's HASH value), the branch predictor will index the branch instruction at PC2 to the BTB entry trained by the attacker. At this time, the victim's branch instruction at PC2 is architecturally supposed to jump to the instruction at PC3, but based on the prediction information of this record in the BTB, the target address is predicted to be PC4. Based on this prediction, the instruction at PC4 will be used as the target instruction, thus executing the instruction at the malicious branch PC4 trained by the attacker. Afterwards, the instruction at PC4 executed based on the prediction will access confidential information and leave traces in the cache, which can be recovered by side-channel technology, resulting in the leakage of confidential information.

[0069] Accordingly, in some implementations, hardware defense mechanisms such as STIBP (Single Thread Indirect Branch Prediction) and IBRS (Indirect Branch Restricted Speculation) can eliminate this risk.

[0070] Specifically, under the STIBP mechanism, in addition to recording the target address of the target instruction, the BTB entry can also record the identification information of the historical branch instruction that obtained the target instruction. Figure 5 A schematic diagram of an optional structure of a BTB item is shown, wherein the identification information can be recorded as redundant information (also called a tag) in the item corresponding to the target address to indicate the source of the instruction. The identification information can be, for example, a logical core identifier. Accordingly, the identification information of the historical branch instruction can be the logical core identifier of the historical branch instruction, and the identification information of the current branch instruction can be the logical core identifier of the current branch instruction.

[0071] Accordingly, reference Figure 6An optional schematic diagram of a branch prediction process is shown. In the branch prediction process under the STIBP mechanism, the attacker's identification information (such as the logical core identification) can be, for example, TID1, and the victim's identification information (such as the logical core identification) can be, for example, TID2. When the attacker trains the predicted target of the control branch predictor, the identification information TID1 of the branch instruction of PC1 used for training will be recorded in the BTB. During the branch prediction process of the branch instruction of the victim PC2, since the identification information TID2 of the branch instruction of PC2 is different from the identification information TID1 recorded in the corresponding item, that is, the identification information TID2 of the branch instruction is different from the identification information of the historical branch instruction TID1 used to obtain the target instruction, the branch instruction of PC2 cannot access the target instruction corresponding to the target address PC4 of the item, and thus needs to execute the instruction at PC3 based on the architecture jump.

[0072] Under the IBRS mechanism, reference Figure 7 A schematic diagram of an optional structure of a BTB entry is shown. In the BTB entry, in addition to recording the target address of the target instruction and the identification information of the historical branch instructions obtained for the target instruction, the permission information of the historical branch instructions (hereinafter referred to as historical instructions) obtained for the target instruction is also recorded. The permission information can be recorded as redundant information (also called a tag) in the item corresponding to the target address, which is used to indicate whether the instruction is a privileged instruction, so as to distinguish whether the instruction is a kernel-state instruction (in a virtualization scenario, it can be understood as a kernel-state instruction of the host, i.e., a HOST instruction) or a user-state instruction.

[0073] It is understood that kernel-mode instructions are privileged instructions, while user-mode instructions are non-privileged instructions. Kernel-mode instructions can be understood as instructions executed in kernel mode, and user-mode instructions can be understood as instructions executed in user mode. In the branch prediction process under the IBRS mechanism, a branch instruction cannot access a target instruction whose identification information differs from that of the branch instruction. Furthermore, a branch instruction cannot access a target instruction that does not comply with the permission access rules.

[0074] Specifically, the permission access rule may be, for example: user-mode branch instructions allow the target address whose access permission information is marked as a privileged level identifier, and the privileged level identifier indicates that the historical instruction for obtaining the target instruction is a privileged level instruction; kernel-mode branch instructions prohibit the target address whose access permission information is marked as a non-privileged level identifier, and the non-privileged level identifier indicates that the historical instruction for obtaining the target instruction is a non-privileged level instruction; that is, user-mode branch instructions allow the target address whose access permission information is both a privileged level identifier and a non-privileged level identifier, and kernel-mode branch instructions only allow the target address whose access permission information is a privileged level identifier.

[0075] Correspondingly, under the IBRS mechanism, it is first determined whether the identification information of the branch instruction is the same as the identification information corresponding to the target address. If they are the same, it is further determined whether the permissions of the branch instruction and the permission information of the target address corresponding to the BTB record comply with the permission access rules, and based on the result of the permission access rules, it is determined whether to execute access to the target address.

[0076] refer to Figure 8 A schematic diagram of BTB item access under the IBRS mechanism is shown. A branch instruction with identification information TID0 and permission information of privileged level CPL0 can only access the target address indicated in the BTB item with identification information TID0 and permission information CPL0; a branch instruction with identification information TID1 and permission information of non-privileged level CPL3 is allowed to access the target address indicated in the BTB item with identification information TID1 and permission information of CPL3 and CPL0.

[0077] The inventors believe that instruction processing efficiency needs to be improved under the aforementioned hardware defense mechanism. After analysis, they believe the main reason is that some instructions require cross-source sharing (e.g., cross-core sharing). However, both STIBP and IBRS prohibit cross-source access for all instructions, resulting in instructions requiring cross-source sharing being unable to achieve cross-core access. In other words, the prediction mechanism with hardware defense mechanisms sacrifices instruction processing efficiency while ensuring security.

[0078] The inventors consider that they can try to distinguish the instructions that need to be shared across sources, and allow some instructions that need to be shared across sources to be shared across sources. Under this premise, the original security effect should also be guaranteed. After research, the inventors believe that they can divide instructions from the perspective of kernel state and user state (that is, the perspective of instruction permission judgment) under the premise of combining permission judgment, so as to distinguish the instructions that need to be shared across sources, and allow these instructions to share the corresponding prediction data (that is, the data in the BTB) across sources under the premise of complying with the permission access rules. In other words, referring to Figure 9 A schematic diagram of BTB item access is shown. A branch instruction with identification information TID0 and permission information CPL0 can not only access the target address indicated in the item with identification information TID0 and permission information CPL0 in the BTB, but also access the target address indicated in the item with identification information TID1 and permission information CPL0 in the BTB.

[0079] This is because, among instructions that require cross-source sharing, kernel-mode instructions, as a system-level management and control instruction, have greater cross-source sharing requirements. At the same time, based on permission access rules, kernel-mode instructions have high permissions and correspondingly low security risks. The corresponding cross-source access has little impact on the original security protection effect.

[0080] Specifically, if an attacker attacks a high-privilege kernel-mode instruction in low-privilege mode, they need to train a high-privilege target address while complying with permission access rules. In this case, the attacker can only train through system calls, using branch instructions within the system call. In this scenario, the attacker's training process is significantly limited. First, the branch instruction address used in the attacker's training is restricted by the address of the system call in the kernel, making it difficult to construct a training address that collides with the victim's HASH. Second, the target address used in the attacker's training is determined by the target address of the branch instruction in the system call, which is beyond the attacker's control, making it difficult to construct a target address that meets the attacker's intentions. Therefore, the risk of carrying out an attack in this attack scenario is almost impossible.

[0081] If an attacker wishes to attack high-privilege kernel-mode instructions in high-privilege mode, they must first breach the privilege level boundary, subject to the permission access rules. However, if the attacker has already breached the privilege level boundary, the corresponding security risk is a more direct leakage of confidential data, while the information leakage through the speculative execution mechanism is unnecessary. In other words, this scenario is meaningless.

[0082] Obviously, under the premise of combining permission judgment, instructions are divided from the perspective of kernel state and user state (that is, the perspective of instruction priority), so as to distinguish instructions that have cross-source sharing requirements, and allow these instructions to be shared across sources under the premise of complying with permission access rules. This can improve instruction processing efficiency while ensuring the original security effect.

[0083] In view of this, an embodiment of the present application provides a branch prediction method, a branch predictor and related equipment, the method comprising: obtaining address information and first identification information of an instruction to be predicted, the first identification information being used to indicate the source of the instruction to be predicted; based on the address information, obtaining a pre-stored target address of a target instruction corresponding to the instruction to be predicted and redundant information of the target address, the redundant information comprising second identification information and permission information, the second identification information being used to indicate the source of a historical instruction from which the target instruction was obtained, and the permission information being used to indicate whether the historical instruction from which the target instruction was obtained is a privileged instruction; if the instruction to be predicted is a user-state instruction, determining whether the first identification information and the second identification information are consistent, and if the first identification information and the second identification information are consistent, allowing execution of access to the target address; if the instruction to be predicted is a kernel-state instruction, determining whether the permission information is a privileged-level identification; if so, and the first identification information and the second identification information are consistent or inconsistent, allowing execution of access to the target address.

[0084] It can be seen that in the branch prediction process of the embodiment of the present application, when the instruction to be predicted is a user-state instruction, the identification information is judged based on the normal process, that is, whether the first identification information and the second identification information are consistent is judged. When the first identification information and the second identification information are consistent, the access to the target address is allowed to be executed; and when the instruction to be predicted is a kernel-state instruction, whether the permission information is a privileged level identification is judged. When the permission information is a privileged level identification, the access to the target address can be executed regardless of whether the corresponding identification information is consistent, so that the kernel-state instruction can be accessed across sources, thereby improving the instruction processing efficiency while ensuring the original security effect.

[0085] The following is a detailed introduction to the branch prediction solution provided in the embodiments of the present application.

[0086] Figure 10 This is an optional flow chart of a branch prediction method provided in an embodiment of the present application, refer to Figure 10 , the branch prediction process includes:

[0087] Step S100: Acquire address information and first identification information of an instruction to be predicted, where the first identification information is used to indicate a source of the instruction to be predicted;

[0088] The instruction to be predicted is a branch instruction of a branch to be predicted, and the address information is used to identify the address of the instruction to be predicted. The address information can be, for example, a HASH value of the address. The identification information is used to indicate the source of the instruction, and the source is used to indicate the initiator of the instruction, for example, the processor core that initiates the instruction. When there is a logical core, the source can also be the logical core. Accordingly, the identification information can be the processor core identifier or the logical core identifier of the instruction initiating the instruction; the first identification information is used to indicate the source of the instruction to be predicted described in this embodiment, for example, the first identification information is the processor core identifier or the logical core identifier that initiates the instruction to be predicted, so as to perform access control on the target address indicated in the branch target buffer BTB based on the source. Wherein, when the identification information is the logical core identifier that initiates the instruction, the method can be applied within a processor core to implement cross-logical core access to prediction data within a processor core.

[0089] It is understandable that the processor usually records instruction information of the instruction, and the instruction information includes source information of the instruction (ie, identification information). Accordingly, the first identification information can be obtained from the instruction information recorded by the processor.

[0090] Step S110: Based on the address information, obtaining a pre-stored target address of a target instruction corresponding to the instruction to be predicted and redundant information of the target address;

[0091] It is understood that the prediction information pre-stored in the BTB is obtained based on the processing flow of historical instructions. This prediction information may include the address of the target instruction predicted for the historical instruction, i.e., the target address. The target instruction can be understood as the result of the BTB prediction, i.e., the next instruction predicted for the instruction to be predicted. Based on the address information of the historical instruction and the address information of the instruction to be predicted, the target address of the corresponding target instruction can be determined.

[0092] The redundant information includes second identification information and permission information, wherein the second identification information is used to indicate a source of a historical instruction from which the target instruction is obtained, and the permission information is used to indicate whether the historical instruction from which the target instruction is obtained is a privileged instruction;

[0093] In the stored prediction information, the second identification information in the redundant information is used to indicate the source of the historical instructions for obtaining the target instruction. For example, the second identification information may be the processor core identification or the logic core identification that initiated the historical instruction, etc., so as to confirm whether the source of the instruction to be predicted is consistent with the source of the historical instructions for obtaining the target instruction based on the second identification information. If they are consistent, it indicates that the source of the instruction to be predicted is the same as that of the historical instructions, and the access to the corresponding target address can be understood as a safe access; if they are inconsistent, the source of the instruction to be predicted is not the same as that of the historical instructions, and the access to the corresponding target address may be a security risk.

[0094] The permission information in the redundant information is used to indicate whether the historical instruction from which the target instruction was derived was a privileged instruction; wherein the privileged instruction can be understood as a kernel-mode instruction, i.e., an instruction executed in kernel mode, and the non-privileged instruction can be understood as a user-mode instruction, i.e., an instruction executed in user mode. Based on the marking of the permission information, access to the target address can be controlled and implemented only under the premise of complying with the permission access rules, i.e., a privileged instruction accesses a target address obtained when the historical instruction was a privileged instruction, and a non-privileged instruction accesses a target address obtained when the historical instruction was a privileged instruction or a non-privileged instruction.

[0095] It can be understood that the instruction information of the instruction to be predicted usually records information such as the attributes and source of the instruction. Therefore, based on the instruction information of the instruction to be predicted, it can be determined whether the instruction to be predicted is a kernel-state instruction. If so, step S120 is executed to determine whether access to the target address is allowed based only on the judgment of the permission information. If not, it indicates that the instruction to be predicted is a user-state instruction, and step S130 is executed. Based on the result of step S130, it is determined whether access to the target address is allowed.

[0096] Specifically, step S120 and step S130 are described as follows:

[0097] Step S120: determining whether the permission information is a privilege level identifier;

[0098] By judging whether the permission information is a privileged level identifier, it is determined whether the historical instruction is a privileged level instruction, thereby allowing the corresponding access to be executed based on the permission access rule.

[0099] When the instruction to be predicted is a kernel-mode instruction, whether the source condition allows access to the target address is no longer considered. That is, when the instruction to be predicted is a kernel-mode instruction, if the permission information is a privileged level identifier, indicating that the historical instruction is a privileged level instruction, access to the target address is permitted regardless of whether the first identifier and the second identifier are consistent or inconsistent. This enables cross-source access of the kernel-mode instruction to the predicted data, thereby improving instruction processing efficiency while maintaining the original security effect.

[0100] In an optional example, when there are two judgments of permission conditions and source conditions, when the judgment result of this step is yes, step S130 can be skipped, or step S130 can be executed, but regardless of the result (such as the result of step S130 is yes or no), step S200 is allowed to be executed to achieve access to the target address, so that the instructions to be predicted can share the prediction information in the BTB across sources.

[0101] It should be noted that when the instruction to be predicted is a user-mode instruction, access can be performed for a target address whose permission information is a privileged level identifier or a non-privileged level identifier. Accordingly, when the instruction to be predicted is a user-mode instruction, there is no need to determine the permission information in this step, that is, this step can be skipped. Alternatively, this step can be performed, but regardless of the result (such as yes or no), whether step S200 is allowed to access the target address is determined based on the judgment result in step S130.

[0102] Step S130: determining whether the first identification information and the second identification information are consistent;

[0103] By judging whether the identification information (i.e., the first identification information of the instruction to be predicted and the second identification information of the historical instruction) are consistent, it is determined whether the instruction to be predicted and the historical instruction are from the same source, and then based on the result, it is determined whether to execute access to the corresponding target address.

[0104] It is understood that, in the embodiment of the present application, this step is performed when the instruction to be predicted is a user-mode instruction. If the judgment result is yes, it indicates that the instruction to be predicted and the historical instruction are from the same source, and thus the access to the target address in step S200 can be allowed. If the judgment result is no, it indicates that the instruction to be predicted and the historical instruction are from different sources, and the execution of step S200 is prohibited.

[0105] When the instruction to be predicted is a kernel-mode instruction, in order to realize the sharing of prediction information from different sources, step S130 can be skipped, or, when the result of step S120 is yes, step S130 can be executed again, and regardless of the result of step S130 (that is, when the judgment result is yes or no), step S200 is allowed to access the target address.

[0106] It should be noted that when both step S120 and step S130 need to be executed, step S120 and step S130 can be executed simultaneously or sequentially, and then corresponding processing flows can be executed based on corresponding results.

[0107] Step S200: Execute access to the target address;

[0108] Based on the above results, access to the target address may be performed to implement branch prediction for the instruction to be predicted.

[0109] It can be seen that in the embodiment of the present application, when the instruction to be predicted is a user-state instruction, the identification information is judged based on the normal process, and when the instruction to be predicted is a kernel-state instruction, the judgment is based on whether the permission information is a privileged level identification, and the identification information indicating the source of the prediction data is no longer judged, so that the kernel-state instruction can be accessed across sources, thereby improving the instruction processing efficiency while ensuring the original security effect.

[0110] In a further example, refer to Figure 11 A schematic diagram of an optional structure of a BTB entry is shown, in which the redundant information also includes a valid flag for marking whether the target address is valid. This valid flag can invalidate historical prediction information (i.e., existing prediction information) in the BTB at a preset time, thereby preventing the impact of historical prediction information on subsequent instructions and eliminating potential security risks. The preset time may be, for example, when the device switches modes or switches users.

[0111] Among them, in view of the above analysis, it can be seen that sharing the prediction information of historical instructions of the privileged level does not increase the security risk. On the contrary, it can improve the instruction processing efficiency while ensuring the original security effect. Therefore, in order to further improve the instruction processing efficiency, the embodiment of the present application further adjusts the refresh process of the valid identifier, and keeps the valid identifier of the prediction information that meets the permission conditions at the original value (that is, the invalidation process for the prediction information that meets the permission conditions is not executed), so that kernel state instructions can share historical prediction information.

[0112] refer to Figure 12 FIG. 1 is a schematic diagram of a prediction information refresh process in a branch prediction method, wherein the refresh process includes:

[0113] Step S300: receiving a valid identification refresh command;

[0114] The valid flag refresh command is used to invalidate the historical prediction information in the BTB, thereby preventing the historical prediction information from affecting subsequent instructions. It is understood that at a preset time (such as when the device switches modes or switches users), the device will issue a valid flag refresh command, thereby invalidating the existing prediction information based on the valid flag refresh command, thereby preventing the historical prediction information from affecting subsequent instructions.

[0115] It should be noted that the refresh of historical prediction information in the embodiment of the present application can skip the items of prediction information that meet the permission conditions (i.e., prediction information), so that kernel-mode instructions can access the target address obtained based on historical instructions as privileged instructions, thereby improving instruction processing efficiency.

[0116] Step S310: executing a process of updating the valid flag of the target address stored in the branch target buffer based on the valid flag refresh command;

[0117] Among them, the update process includes: determining whether the permission information of the target address is a privileged level identifier; if not, updating the valid identifier of the target address to a first value, and the first value is used to mark the target address as invalid; if so, skipping the item where the target address is located, so that the valid identifier of the target address remains at the original value.

[0118] Among them, the first value can be, for example, "0" to mark the corresponding target address as invalid. In an optional example, the valid identifier can also be a second value, and the second value can be, for example, "1" to mark the corresponding target address as valid. In an embodiment of the present application, if the valid identifier corresponding to the target address has not been invalidated, that is, the valid identifier corresponding to the target address is the second value, by skipping the item where the target address is located, the valid identifier corresponding to the target address can be kept at the original value (that is, the second value), so that the kernel state instruction can access the target address obtained as a privileged instruction based on the historical instruction, thereby improving the instruction processing efficiency.

[0119] Accordingly, in an optional implementation of the embodiment of the present application, the embodiment of the present application further provides a branch prediction process based on the effective identification execution. Figure 13 An optional flow chart of a branch prediction method is shown. After executing step S110 and before executing step S200, the branch prediction method further includes:

[0120] S140: Based on the validity identifier, determine whether the target address is valid;

[0121] It is understandable that based on the valid flag, the historical prediction information in the BTB can be invalidated at a preset time, and by judging whether the target address is valid, the prediction information corresponding to the non-privileged instructions in the BTB before and after the preset time can be avoided from being confused and shared.

[0122] Specifically, if yes, it indicates that the target address (which can also be understood as the prediction information where the target address is located) is valid, and step S200 is allowed to access the target address. If no, it indicates that the target address (which can also be understood as the prediction information where the target address is located) is invalid, and step S200 is prohibited.

[0123] It should be noted that, in the example where there is a valid identifier, no matter the instruction to be predicted is a kernel-mode instruction or a user-mode instruction, step S140 needs to be executed to determine the validity of the prediction information.

[0124] The execution order of the above steps S120, S130 and S140 is not limited, and they can be executed simultaneously or sequentially. This application does not make any specific restrictions here. Figure 13 In the example, step S140 is executed later. However, when the result of any step indicates that step S200 is prohibited, step S200 is not executed. In an optional example, different steps can be selected for execution for instructions with different permission levels. For example, when the instruction to be predicted is a kernel-mode instruction, step S120 and step S140 are selected for execution, step S130 is skipped, and step S200 is executed when both steps indicate that step S200 is allowed to be executed; and when the instruction to be predicted is a user-mode instruction, step S130 and step S140 are selected for execution, and step S200 is executed when both steps indicate that step S200 is allowed to be executed.

[0125] It can be seen that in the embodiment of the present application, corresponding access control is performed through further configured valid identification to avoid the impact of prediction information obtained from non-privileged historical instructions on subsequent instructions, thereby eliminating possible security risks.

[0126] In an alternative implementation, reference Figure 14 An optional structural diagram of a branch predictor provided in an embodiment of the present application is shown. The branch predictor may be an optional hardware structure for implementing the above-mentioned branch prediction method. The branch predictor includes:

[0127] Instruction information acquisition logic 400, used to acquire address information and first identification information of the instruction to be predicted, where the first identification information is used to indicate the source of the instruction to be predicted;

[0128] Prediction information acquisition logic 410 is configured to acquire, based on the address information, a pre-stored target address of a target instruction corresponding to the instruction to be predicted and redundant information about the target address, the redundant information including second identification information and permission information, the second identification information being used to indicate a source of a historical instruction from which the target instruction was derived, and the permission information being used to indicate whether the historical instruction from which the target instruction was derived was a privileged instruction;

[0129] The access determination logic 420 is used to determine whether the first identification information and the second identification information are consistent if the instruction to be predicted is a user-mode instruction; if the first identification information and the second identification information are consistent, allow execution of access to the target address; if the instruction to be predicted is a kernel-mode instruction, determine whether the permission information is a privileged level identification; if so, and if the first identification information and the second identification information are consistent or inconsistent, allow execution of access to the target address.

[0130] Optionally, the access determination logic 420 is configured to, if the instruction to be predicted is a kernel-mode instruction, determine whether the permission information is a privilege level identifier; if so, and the first identification information and the second identification information are consistent or inconsistent, execute access to the target address, specifically:

[0131] If the instruction to be predicted is a kernel-mode instruction, determining whether the permission information is a privileged level identifier; if so, skipping the step of determining whether the first identification information and the second identification information are consistent, and executing access to the target address;

[0132] or,

[0133] If the instruction to be predicted is a kernel-mode instruction, determine whether the permission information is a privileged level identifier, and determine whether the first identification information and the second identification information are consistent. If the permission information is a privileged level identifier, and the first identification information and the second identification information are consistent or inconsistent, execute access to the target address.

[0134] Optionally, the redundant information further includes a valid flag for marking whether the target address is valid, and the branch predictor further includes:

[0135] Redundancy information refresh logic 430 is configured to receive a valid flag refresh instruction; and based on the valid flag refresh instruction, execute a process of updating the valid flag of the target address stored in the branch target buffer;

[0136] Among them, the update process includes: determining whether the permission information of the target address is a privileged level identifier; if not, updating the valid identifier of the target address to a first value, the first value being used to mark the target address as invalid; if so, skipping the item where the target address is located.

[0137] Optionally, the access determination logic 420 is further configured to determine whether the target address is valid based on the valid identifier; if not, prohibiting access to the target address.

[0138] Optionally, the first identification information is the processor core identification or the logical core identification that initiates the instruction to be predicted, and the second identification information is the processor core identification or the logical core identification that initiates the historical instruction.

[0139] Optionally, in a virtualization scenario, the kernel-state instruction is a kernel-state instruction of the host.

[0140] It can be understood that the solution provided in the embodiment of the present application, when the instruction to be predicted is a user-state instruction, judges the permission information and identification information based on the normal process, that is, judges whether the permission information is a privileged level identification; if not, judges whether to execute access to the target address based on the first identification information and the second identification information; and when the instruction to be predicted is a kernel-state instruction, the judgment of whether the permission information is a privileged level identification is the basis. When the permission information is a privileged level identification, the access to the target address can be executed regardless of whether the corresponding identification information is consistent, so that the kernel-state instruction can be accessed across sources, thereby improving the instruction processing efficiency while ensuring the original security effect.

[0141] An embodiment of the present application further provides a processor, which may include the above-mentioned branch predictor.

[0142] A chip is also provided in an embodiment of the present application, and the chip may include the above-mentioned processor.

[0143] An embodiment of the present application also provides an electronic device, which may include the above-mentioned chip.

[0144] An embodiment of the present application further provides a storage medium, wherein the storage medium stores one or more computer-executable instructions, and the one or more computer-executable instructions are used to execute the branch prediction method as described above.

[0145] An embodiment of the present application further provides a computer program product, characterized in that it includes one or more computer-executable instructions, and when the one or more computer-executable instructions are executed, they can implement the branch prediction method as described above.

[0146] The above describes multiple embodiment schemes provided by the embodiments of the present application. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present application.

[0147] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A branch prediction method, characterized in that: include: Acquire address information and first identification information of the instruction to be predicted, where the first identification information is used to indicate a source of the instruction to be predicted; Based on the address information, obtaining a pre-stored target address of a target instruction corresponding to the instruction to be predicted and redundant information of the target address, wherein the redundant information includes second identification information and permission information, wherein the second identification information is used to indicate a source of a historical instruction from which the target instruction is obtained, and the permission information is used to indicate whether the historical instruction from which the target instruction is obtained is a privileged instruction; If the instruction to be predicted is a user-mode instruction, determining whether the first identification information is consistent with the second identification information, and if the first identification information is consistent with the second identification information, allowing execution of access to the target address; If the instruction to be predicted is a kernel state instruction, determining whether the permission information is a privilege level identifier; If so, and the first identification information is consistent with or inconsistent with the second identification information, access to the target address is allowed.

2. The branch prediction method according to claim 1, characterized in that: If the instruction to be predicted is a kernel-mode instruction, determine whether the permission information is a privilege level identifier; if so, and the first identifier information is consistent with the second identifier information or inconsistent, perform access to the target address, specifically: If the instruction to be predicted is a kernel-mode instruction, determining whether the permission information is a privileged level identifier; if so, skipping the step of determining whether the first identifier information and the second identifier information are consistent, and executing access to the target address; or, If the instruction to be predicted is a kernel-mode instruction, determine whether the permission information is a privileged level identifier, and determine whether the first identification information and the second identification information are consistent; if the permission information is a privileged level identifier, and the first identification information and the second identification information are consistent or inconsistent, execute access to the target address.

3. The branch prediction method according to claim 1 or 2, characterized in that: The redundant information also includes a valid identifier for marking whether the target address is valid, and the method further includes: Receive a valid identification refresh instruction; Based on the valid flag refresh instruction, executing a process of updating the valid flag of the target address stored in the branch target buffer; Among them, the update process includes: determining whether the permission information of the target address is a privileged level identifier; if not, updating the valid identifier of the target address to a first value, wherein the first value is used to mark the target address as invalid; if so, skipping the item where the target address is located.

4. The branch prediction method according to claim 3, characterized in that: After acquiring the pre-stored target address of the target instruction corresponding to the instruction to be predicted and the redundant information of the target address based on the address information, and before executing the access to the target address, the method further includes: Based on the valid identifier, determining whether the target address is valid; If not, access to the target address is prohibited.

5. The branch prediction method according to claim 1, characterized in that: The first identification information is the processor core identification or the logic core identification that initiates the instruction to be predicted, and the second identification information is the processor core identification or the logic core identification that initiates the historical instruction.

6. The branch prediction method according to claim 1, characterized in that: In a virtualization scenario, the kernel state instruction is a kernel state instruction of the host.

7. A branch predictor, characterized in that: include: Instruction information acquisition logic, used to acquire address information and first identification information of the instruction to be predicted, where the first identification information is used to indicate the source of the instruction to be predicted; Prediction information acquisition logic, used to acquire, based on the address information, a pre-stored target address of a target instruction corresponding to the instruction to be predicted and redundant information of the target address, wherein the redundant information includes second identification information and permission information, wherein the second identification information is used to indicate a source of a historical instruction from which the target instruction is obtained, and the permission information is used to indicate whether the historical instruction from which the target instruction is obtained is a privileged instruction; an access determination logic, for determining, if the instruction to be predicted is a user-mode instruction, whether the first identification information and the second identification information are consistent, and allowing execution of access to the target address if the first identification information and the second identification information are consistent; If the instruction to be predicted is a kernel-mode instruction, determine whether the permission information is a privileged level identifier; if so, and the first identifier information and the second identifier information are consistent or inconsistent, access to the target address is allowed.

8. The branch predictor according to claim 7, characterized in that: The access determination logic is used to determine whether the permission information is a privileged level identifier if the instruction to be predicted is a kernel state instruction; if so, and the first identification information and the second identification information are consistent or inconsistent, perform access to the target address, specifically: If the instruction to be predicted is a kernel-mode instruction, determining whether the permission information is a privileged level identifier; if so, skipping the step of determining whether the first identifier information and the second identifier information are consistent, and executing access to the target address; or, If the instruction to be predicted is a kernel-mode instruction, determine whether the permission information is a privileged level identifier, and determine whether the first identification information and the second identification information are consistent; if the permission information is a privileged level identifier, and the first identification information and the second identification information are consistent or inconsistent, execute access to the target address.

9. The branch predictor according to claim 7 or 8, characterized in that: The redundant information further includes a valid flag for marking whether the target address is valid, and the branch predictor further includes: The redundant information refresh logic is used to receive a valid identification refresh instruction; based on the valid identification refresh instruction, execute an update process of the valid identification of the target address stored in the branch target buffer; Among them, the update process includes: determining whether the permission information of the target address is a privileged level identifier; if not, updating the valid identifier of the target address to a first value, wherein the first value is used to mark the target address as invalid; if so, skipping the item where the target address is located.

10. The branch predictor according to claim 9, characterized in that: The access determination logic is further used to determine whether the target address is valid based on the valid identifier; if not, access to the target address is prohibited.

11. The branch predictor according to claim 7, characterized in that: The first identification information is the processor core identification or the logic core identification that initiates the instruction to be predicted, and the second identification information is the processor core identification or the logic core identification that initiates the historical instruction.

12. The branch predictor according to claim 7, characterized in that: In a virtualization scenario, the kernel state instruction is a kernel state instruction of the host.

13. A processor, characterized in that: The processor comprises the branch predictor according to any one of claims 7 to 12.

14. A chip, characterized in that: Comprising a processor as claimed in claim 13.

15. An electronic device, characterized in that: Comprising the chip as claimed in claim 14.

16. A storage medium, characterized in that: The storage medium stores one or more computer executable instructions, and the one or more computer executable instructions are used to execute the branch prediction method according to any one of claims 1 to 6.

17. A computer program product, characterized in that The method comprises one or more computer executable instructions, and when the one or more computer executable instructions are executed, the branch prediction method according to any one of claims 1 to 6 is implemented.

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