Multi-core data transmission system

Abstract

The invention discloses a multi-core data transmission system, and relates to the technical field of data communication, the system comprises an upper computer and a lower computer, the lower computer comprises a multi-core processor with a first core and a second core; the first core and the second core are connected through a plurality of inter-core channels; the first kernel is used for acquiring first operation data and sending the first operation data to the upper computer; the second kernel is used for acquiring second operation data and performing data processing on the second operation data based on preset business logic to obtain third operation data; generating a third message representing an acquisition mode of the third job data, and sending the third message to the first kernel through a plurality of inter-kernel channels; and the first kernel is also used for acquiring the third job data based on the third message and sending the third job data to the upper computer. According to the scheme, the real-time performance of data transmission can be improved.

Description

Technical Field

[0001] The present invention relates to the field of data communication technology, and in particular to a multi-core data transmission system. Background Art

[0002] In data transmission scenarios where the data flow of oil and gas logging equipment such as directional probes is large and the data types are diverse, it is difficult to ensure the real-time transmission of the operating data obtained in the detection. In related technologies, multi-core processors can be used for data transmission.

[0003] Based on the heterogeneous multi-core processor of AMP (asymmetric multi-processing) mode, multiple cores can run different operating systems. Each core is isolated from each other and can run different operating systems (OS) or bare metal applications, giving full play to the hardware performance of specific application scenarios. The AMP architecture also needs to use some synchronization and communication mechanisms, such as message passing and shared memory, to achieve communication and collaboration between processor cores, thereby providing better real-time performance. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, one object of the present invention is to provide a multi-core data transmission system to improve the real-time performance of data transmission.

[0005] According to a first aspect of an embodiment of the present invention, a multi-core data transmission system is provided, the system comprising an upper computer and a lower computer, the lower computer comprising a multi-core processor having a first core and a second core; the first core and the second core are connected via a plurality of inter-core channels;

[0006] The first kernel is used to obtain first operation data and send the first operation data to the host computer;

[0007] The second kernel is used to obtain second operation data, and perform data processing on the second operation data based on a preset business logic to obtain third operation data; generate a third message indicating a method for obtaining the third operation data, and send the third message to the first kernel through multiple inter-core channels;

[0008] The first kernel is further configured to obtain the third operation data based on the third message, and send the third operation data to the host computer.

[0009] Optionally, the inter-core channel is a remote processor message transmission rpmsg channel; the rpmsg channel is formed in the following manner:

[0010] The first kernel loads a plurality of rpmsg drivers, generates a device node corresponding to each rpmsg driver, and sets a channel identifier for each device node;

[0011] The second kernel creates a virtual device corresponding to each channel identifier;

[0012] An rpmsg channel is established between each device node and each virtual device based on the set channel identifier.

[0013] Optionally, when there are multiple third messages, the second kernel sends the third message to the first kernel through multiple inter-core channels, including:

[0014] Grouping the third message according to a preset priority level, and allocating an inter-core channel to each group;

[0015] The third message in each group is sent to the first core through the allocated inter-core channel.

[0016] Optionally, grouping the third messages according to a preset priority includes:

[0017] Selecting a preset number of types of third messages with the same priority, and when the selected third messages meet a preset grouping condition, determining the selected third messages as the same group;

[0018] The grouping condition includes: the group containing the third message with a higher priority has fewer types of third messages.

[0019] Optionally, the grouping condition further includes: in the group where the third message with a higher priority belongs, the sum of the expected sending frequencies of the third messages of different categories is smaller.

[0020] Optionally, the expected sending frequency of the third message is set based on a minimum delay duration corresponding to the third message.

[0021] Optionally, the multi-core processor is a heterogeneous multi-core processor based on an asymmetric multi-processing AMP mode.

[0022] Optionally, the first kernel is a master kernel with a Linux system installed, and the second kernel is a slave kernel with a real-time operating system or a bare metal application installed.

[0023] Optionally, the multi-core processor is a ZYNQ processor, and the ZYNQ processor includes the first core, the second core and a first FPGA chip;

[0024] The lower computer also includes a storage unit and a second FPGA chip;

[0025] The second FPGA chip is used to obtain the first job data and the second job data, and store the first job data and the second job data in the storage unit, generate a first message, the first message including: the storage location and data type of the first job data, the storage location and data type of the second job data; send the first message to the first FPGA chip;

[0026] The first FPGA chip is used to generate second messages for the first job data and the second job data respectively according to the data type in the first message, and send the second message for the first job data to the first core so that the first core obtains the first job data from the storage unit according to the received second message for the first job data; and send the second message for the second job data to the second core so that the second core obtains the second job data from the storage unit according to the received second message for the second job data.

[0027] Optionally, if the third message includes instruction information, the second core is further configured to send the third message to the first core via a dedicated inter-core channel preset for the instruction information.

[0028] In the solution provided by the embodiment of the present invention, a lower computer is used to perform data processing, data communication and data transmission to an upper computer. In order to improve the real-time performance of data received by the upper computer, the operation data is divided into second operation data that needs to be processed according to the business logic and first operation data that does not need to be processed; the first operation data that does not need to be processed by the business logic is directly sent to the upper computer through the first kernel; the data that needs to be processed by the business logic is processed by the second kernel, which does not affect the data transmission of the first kernel, thereby improving the real-time performance of data transmission.

[0029] In addition, multiple inter-core channels are set between the first core and the second core, so that the third message can be sent to the first core more quickly without preemption between the third messages during sending, so that the first core can obtain the processed third job data according to the third message and transmit it more quickly, further improving the real-time performance.

[0030] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic structural diagram of a first multi-core data transmission system provided by an embodiment of the present invention;

[0032] Figure 2is a schematic diagram of the structure of a first multi-core processor provided by an embodiment of the present invention;

[0033] Figure 3 is a structural schematic diagram of a second multi-core data transmission system provided by an embodiment of the present invention;

[0034] Figure 4 It is a schematic diagram of the structure of a second multi-core processor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0036] In one embodiment of the present invention, see Figure 1 , provides a multi-core data transmission system, including an upper computer and a lower computer, the lower computer including a multi-core processor having a first core and a second core; the first core and the second core are connected via a plurality of inter-core channels;

[0037] A first kernel is used to obtain first operation data and send the first operation data to a host computer;

[0038] The second kernel is used to obtain the second operation data, and perform data processing on the second operation data based on the preset business logic to obtain the third operation data; generate a third message indicating the method for obtaining the third operation data, and send the third message to the first kernel through multiple inter-core channels;

[0039] The first kernel is further configured to obtain third operation data based on the third message, and send the third operation data to the host computer.

[0040] In the above system, the host computer usually refers to a computer system with powerful computing and data processing capabilities. It is responsible for monitoring the entire control system, issuing instructions, data collection, processing and analysis, and user interaction. The slave device refers to the device or controller directly connected to the hardware such as sensors and actuators in the control system.

[0041] The first core and the second core can be an independently running CPU (Central Processing Unit) respectively. There can be more than two cores in a multi-core processor, for example, there are multiple second cores, all of which are connected to the first core in the above manner and transmit data in the above manner. In this way, each second core can process different second job data respectively.

[0042] In the solution provided by the embodiment of the present invention, a lower computer is used to perform data processing, data communication and data transmission to an upper computer. In order to improve the real-time performance of data received by the upper computer, the operation data is divided into second operation data that needs to be processed according to the business logic and first operation data that does not need to be processed; the first operation data that does not need to be processed by the business logic is directly sent to the upper computer through the first kernel; the data that needs to be processed by the business logic is processed by the second kernel, which does not affect the data transmission of the first kernel, thereby improving the real-time performance of data transmission.

[0043] In addition, multiple inter-core channels are set between the first core and the second core, so that the third message can be sent to the first core more quickly without preemption between the third messages during sending, so that the first core can obtain the processed third job data according to the third message and transmit it more quickly, further improving the real-time performance.

[0044] In one embodiment of the present invention, the inter-core channel is an rpmsg (Remote Processor Messaging) channel; the rpmsg channel is formed in the following manner:

[0045] The first kernel loads multiple rpmsg drivers, generates a device node corresponding to each rpmsg driver, and sets a channel identifier for each device node; the second kernel creates a virtual device corresponding to each channel identifier; and establishes an rpmsg channel between each device node and each virtual device based on the set channel identifier.

[0046] See also Figure 2 , CPU0 is the first core, and CPU1 is the second core. In this embodiment, the multi-core processor is a heterogeneous multi-core processor based on an asymmetric multi-processing AMP mode, and specifically can adopt an OpenAMP framework, which is applicable to most hardware platforms, easy to transplant, and high in development efficiency.

[0047] The first kernel is a master kernel installed with a Linux system, and the second kernel is a slave kernel installed with a real-time operating system (RTOS) or a bare-metal application program.

[0048] CPU0 is divided into Linux user space and Linux kernel space, and the rpmsg driver is loaded in the Linux kernel space. In CPU0 and CPU1, virtio is a standardized device virtualization technology that provides a set of simplified device driver interfaces. The rpmsg driver uses the interface provided by virtio to transmit data. The main function of rproc (Remote Processor Framework) in CPU0 is to manage the life cycle of the remote processor, that is, to start and stop the remote processor.

[0049] Device nodes are created in the / dev directory and are the hub connecting the Linux kernel space and the Linux user space. In Linux, all devices are stored in the / dev directory in the form of files and are accessed through files. Device nodes are the Linux kernel's abstraction of devices, and a device node is a file. Applications access device nodes through a set of standardized calls that are independent of any specific driver. The driver is responsible for mapping these standard calls to actual hardware devices.

[0050] exist Figure 2 In the embodiment, CPU0 loads 16 rpmsg drivers, rpmsg0 to rpmsg15. Corresponding device nodes / dev / rpmsg0 to / dev / rpmsg15 are generated in the device folder, and the corresponding device channel IDs are ch1 to ch16. The channel ID is the channel identifier.

[0051] Create rpmsg virtual devices 0 to 15 in CPU1, corresponding to channel IDs: ch1-ch16;

[0052] The application of CPU0 sends and receives data of CPU1 by reading and writing rpmsg0~rpmsg15 nodes, so as to receive the third message. Conversely, CPU1 can also send and receive data of CPU0 by reading and writing virtual device 0~virtual device 15.

[0053] Virtual devices are implemented through CPU virtualization, which enables one or more virtual devices to run on a single physical CPU. Specifically, virtual devices can be created through virtualization platforms such as KVM and VMware that support rpmsg drivers.

[0054] Application in CPU0 and CPU1 represents an interaction module, which is used to transmit data and instruction information. For example, after CPU0 obtains the third message through the rpmsg channel, the interaction module receives the third message and uses the read / write channels 0-15 to obtain the third job data from the preset storage unit according to the data address indicated by the third message. The functions of the read / write channels 0-15 and the Application interaction module in CPU1 are similar.

[0055] In one embodiment, the init_rpmsg_channel function in C language may be used to initialize the channel, thereby establishing the rpmsg channel.

[0056] In this way, by using multi-core processors and assigning different cores to process different types of job data, it is possible to take into account the complexity and real-time nature of data transmission, and give full play to the advantages of the AMP mode of heterogeneous multi-core processors to adapt to data transmission scenarios with large data flows and multiple data types.

[0057] In one embodiment of the present invention, when there are multiple third messages, the second kernel sends the third message to the first kernel through multiple inter-core channels, including:

[0058] The third message is grouped according to a preset priority, and an inter-core channel is allocated to each group; and the third message in each group is sent to the first core through the allocated inter-core channel.

[0059] The priority can be set according to the type of the third message. Since the third message indicates the method of obtaining the third job data, the type of the third message can be set according to the data type of the third job data.

[0060] For example, the third operation data can be divided into core function data and auxiliary function data. The core function data is such as drawing coordinate data, including frequency information, voltage information, time information, etc.; the auxiliary function data is such as drawing coordinate verification or correction data, including but not limited to actual state parameter information such as PID, oscillator, filter, etc.

[0061] Correspondingly, the types of the third message can be divided into types corresponding to core function data and types corresponding to auxiliary function data.

[0062] In this way, the priority of the third message indicating the method for acquiring core function data may be set higher than the priority of the third message indicating the method for acquiring auxiliary function data.

[0063] Alternatively, the priorities may also be differentiated based on different real-time requirements of different third job data.

[0064] Specifically, the priority can be represented by a numerical sequence of 1, 2, 3, ... n. In the embodiment of the present application, the smaller the numerical sequence, the higher the priority. In other embodiments, the larger the numerical sequence, the higher the priority, which is not limited in the embodiment of the present invention.

[0065] In this way, when there is a priority, a dedicated inter-core channel can be allocated for the third message corresponding to one or several third job data with a high priority, which will not be affected by low-priority messages during transmission and can adapt to the transmission requirements of high-real-time messages.

[0066] In one embodiment of the present invention, grouping the third message according to a preset priority level includes:

[0067] Selecting a preset number of types of third messages with the same priority, and when the selected third messages meet a preset grouping condition, determining the selected third messages as the same group;

[0068] The grouping condition includes: the group containing the third message with a higher priority has fewer types of third messages.

[0069] For example, according to the real-time requirements, the priorities of multiple third messages are determined to be 1, 2, 3...n, respectively. A third message with a priority of 1 occupies one inter-core channel for every N1 types; a third message with a priority of 2 occupies one inter-core channel for every N2 types; a third message with a priority of 3 occupies one inter-core channel for every N3 types; a third message with a priority of n occupies one inter-core channel for every Nn types; wherein: Nn>…>N3>N2>N1.

[0070] In one embodiment of the present invention, the grouping condition further includes: in the group where the third message with a higher priority belongs, the sum of the expected sending frequencies of the third messages of different categories is smaller.

[0071] Continuing with the above embodiment, every N1 third messages with a priority level of 1 occupy an inter-core channel, and the sum of the expected sending frequencies f of the N1 third messages is f1; similarly, every N2 third messages with a priority level of 2 occupy an inter-core channel, and the sum of the expected sending frequencies f is f2; similarly, every N3 third messages with a priority level of 3 occupy an inter-core channel, and the sum of the expected sending frequencies f is f3; similarly, the sum of the expected sending frequencies f of every Nn third messages with a priority level of n is fn; the sum of the above frequencies meets the following requirements: fn>…>f3>f2>f1.

[0072] The expected sending frequency of the above data can be set manually, indicating the expected value of the sending frequency.

[0073] In one embodiment of the present invention, the expected sending frequency of the third message is set based on the minimum delay duration corresponding to the third message. The following formula can be used as a reference: t·fm≤Cm. Wherein, m is the type of the third message, fm is the expected sending frequency of the mth third message, Cm is the minimum delay duration of the mth third message, and the time required for the inter-core channel to send and receive a message is t.

[0074] In one embodiment of the present invention, the multi-core processor is a ZYNQ processor, and the ZYNQ processor includes a first core, a second core, and a first FPGA chip;

[0075] The lower computer also includes a storage unit and a second FPGA chip;

[0076] The second FPGA chip is used to obtain the first operation data and the second operation data, and store the first operation data and the second operation data in a storage unit, generate a first message, the first message includes: a storage location and a data type of the first operation data, a storage location and a data type of the second operation data; and send the first message to the first FPGA chip;

[0077] The first FPGA chip is used to generate second messages of the first job data and the second job data respectively according to the data type in the first message, and send the second message of the first job data to the first kernel so that the first kernel obtains the first job data from the storage unit according to the received second message of the first job data; and send the second message of the second job data to the second kernel so that the second kernel obtains the second job data from the storage unit according to the received second message of the second job data.

[0078] See also Figure 3 , PC (Personal Computer) is the host computer, which is a terminal computer operated by the client, used to obtain information from the lower computer and send instructions to the lower computer. In other embodiments, the host computer can also be a server or a mobile terminal, which is not limited in the embodiments of the present invention.

[0079] The ZYNQ processor in the lower computer includes a first core CPU0, a second core CPU1 and a first FPGA chip FPGA1. FPGA1 is a component of the ZYNQ processor, and FPGA1 exchanges data with CPU1 through a high-speed interface.

[0080] The lower computer also includes a storage unit DDR (Double Data Rate SDRAM) for storing data and a second FPGA chip FPGA2. FPGA2 refers to a chip external to the ZYNQ processor, and data is exchanged between FPGA2 and FPGA1 via a channel interface protocol or a universal system bus; FPGA1 and FPGA2 mainly write data to DDR, wherein FPGA2 writes the first job data and the second job data to DDR, CPU0 mainly reads data from DDR, and CPU1 exchanges data with DDR, including both reading and writing.

[0081] like Figure 3 As shown, the storage location of the job data in the first message can be represented by the data address and the data length.

[0082] Based on the data type classification, FPGA1 divides the job data corresponding to the first message into data that requires CPU1 to perform business logic processing and data that does not need to be processed by CPU1 according to the received first message, and generates a second message. During this period, FPGA1 can adjust the address or address list of the data in DDR.

[0083] CPU1 determines the second operation data to be processed according to the received second message, and processes the second operation data based on the preset business logic, for example, processing the frequency data to select a frequency point that meets the preset requirements, obtaining the start time and the end time by calculation, etc. During data processing, CPU1 can read data from DDR and write the third operation data of the processing result into DDR.

[0084] For the first operation data that does not need to be processed, FPGA1 sends a second message to CPU0, and then CPU0 takes it out from DDR and sends it to PC.

[0085] The data type of the first job data is different from the data type of the second job data. For example, they can be represented by different codes. After the second FPGA chip obtains the job data, it divides the job data into data that requires CPU1 to perform business logic processing and data that does not require CPU1 to process, forming second job data and second job data respectively.

[0086] In addition, the data type of the operation data may be provided with more detailed sub-categories to represent frequency information, voltage information, time information, and the like.

[0087] The second FPGA chip can be connected to the measurement sensor to obtain operation data.

[0088] In one embodiment of the present invention, if the third message includes instruction information, the second core is further configured to send the third message to the first core via a dedicated inter-core channel preset for the instruction information.

[0089] The instruction information can be used to indicate the sampling frequency of the CPU to coordinate the rate of data transmission and reception between the first core and the second core. In addition, different dedicated inter-core channels can be set for instruction information with different real-time characteristics, such as Figure 4 The inter-core channel between CPU0 and CPU1 is set. The instruction information includes real-time instruction information and delayed instruction information, and both the real-time instruction information and the delayed instruction information are transmitted through a dedicated inter-core channel, which is separate from the inter-core channel for transmitting the core function data address and the auxiliary function data address of the third message.

[0090] In addition, the transmission of instruction information is bidirectional. Through the third message, the second core can transmit instruction information to the first core. Conversely, the first core can also transmit instruction information to the second core through the same dedicated inter-core channel.

[0091] From the above, the AMP multi-channel inter-core communication solution can improve the real-time performance of data transmission in scenarios with many data types, large data volumes, and high data transmission message frequencies compared to the single-channel inter-core communication solution. It can take into account both complex applications and real-time requirements, and is compatible with multiple data streams and multiple instruction interactions. It is suitable for AMP multi-core communication scenarios with high real-time requirements and multiple data streams at the same time.

[0092] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0093] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0094] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0095] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0096] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0097] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0098] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0099] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A multi-core data transmission system, characterized in that: The system includes an upper computer and a lower computer, wherein the lower computer includes a multi-core processor having a first core and a second core; the first core and the second core are connected via a plurality of inter-core channels; The first kernel is used to obtain first operation data and send the first operation data to the host computer; The second kernel is used to obtain second operation data, and perform data processing on the second operation data based on a preset business logic to obtain third operation data; generate a third message indicating a method for obtaining the third operation data, and send the third message to the first kernel through multiple inter-core channels; The first kernel is further configured to obtain the third operation data based on the third message, and send the third operation data to the host computer.

2. The system according to claim 1, characterized in that The inter-core channel is a remote processor message transmission rpmsg channel; the rpmsg channel is formed in the following manner: The first kernel loads a plurality of rpmsg drivers, generates a device node corresponding to each rpmsg driver, and sets a channel identifier for each device node; The second kernel creates a virtual device corresponding to each channel identifier; An rpmsg channel is established between each device node and each virtual device based on the set channel identifier.

3. The system according to claim 1, characterized in that In the case where there are multiple third messages, the second kernel sends the third message to the first kernel through multiple inter-core channels, including: Grouping the third message according to a preset priority level, and allocating an inter-core channel to each group; The third message in each group is sent to the first core through the allocated inter-core channel.

4. The system according to claim 3, characterized in that The grouping the third messages according to a preset priority level includes: Selecting a preset number of types of third messages with the same priority, and when the selected third messages meet a preset grouping condition, determining the selected third messages as the same group; The grouping condition includes: the group containing the third message with a higher priority has fewer types of third messages.

5. The system according to claim 4, characterized in that The grouping condition also includes: in the group where the third message with a higher priority belongs, the sum of the expected sending frequencies of the third messages of different categories is smaller.

6. The system according to claim 5, characterized in that The expected sending frequency of the third message is set based on the minimum delay duration corresponding to the third message.

7. The system according to claim 1, characterized in that The multi-core processor is a heterogeneous multi-core processor based on an asymmetric multi-processing AMP mode.

8. The system according to claim 7, characterized in that The first kernel is a master kernel with a Linux system installed, and the second kernel is a slave kernel with a real-time operating system or a bare metal application installed.

9. The system according to claim 1, characterized in that The multi-core processor is a ZYNQ processor, and the ZYNQ processor includes the first core, the second core and a first FPGA chip; The lower computer also includes a storage unit and a second FPGA chip; The second FPGA chip is used to obtain the first job data and the second job data, and store the first job data and the second job data in the storage unit, generate a first message, the first message including: the storage location and data type of the first job data, the storage location and data type of the second job data; send the first message to the first FPGA chip; The first FPGA chip is used to generate second messages for the first job data and the second job data respectively according to the data type in the first message, and send the second message for the first job data to the first core so that the first core obtains the first job data from the storage unit according to the received second message for the first job data; and send the second message for the second job data to the second core so that the second core obtains the second job data from the storage unit according to the received second message for the second job data.

10. The system according to claim 1, characterized in that If the third message includes instruction information, the second core is further configured to send the third message to the first core via a dedicated inter-core channel preset for the instruction information.

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