Remote dynamic reconfigurable system and method based on FPGA

Abstract

The invention belongs to the technical field of FPGA (Field Programmable Gate Array) reconfiguration, and discloses a remote dynamic reconfigurable system based on an FPGA and a reconfiguration method. According to the system, a RapidIO high-speed serial bus technology and a reconfigurable technology are fused, a DSP + FPGA + RapidIO-based framework is reconfigured and designed, non-remote dynamic reconfiguration and remote dynamic reconfiguration are realized, and the system specifically comprises a host, a DSP, an FPGA, a slave and a FLASH memory. According to the invention, the dynamic reconfigurable carrier board with a DSP + FPGA + RapidIO architecture is designed as the main control board, so that functional boards with different functional requirements can be hung, and high stability, high expansibility and high universality are achieved. The transmission bandwidth of the RapidIO bus can reach 6.5 Gbytes, and the realization of the remote dynamic reconfigurable system based on the SRIO bus provides a guarantee for realizing remote and rapid switching of complex algorithms by using a high-speed dynamic reconstruction technology.

Description

Technical Field

[0001] The invention belongs to the field of FPGA reconfigurable technology, and in particular relates to a remote dynamic reconfigurable system based on FPGA and a reconfiguration method. Background Art

[0002] Reconfigurable technology was proposed as early as the 1960s, but it was not promoted due to the limitations of technical conditions at the time. In the 1980s, Xilinx invented the world's first FPGA, providing a general hardware platform for reconfigurable technology, and reconfigurable technology has gradually been promoted and applied. FPGA-based dynamic reconfigurable technology can reconfigure all or part of its internal logical functions while the FPGA is powered on and running normally, greatly improving the flexibility of FPGA system design and having important application value in improving resource utilization, reducing system power consumption, and enhancing system reliability.

[0003] Although FPGA reconfigurable technology can achieve seamless switching between different communication protocols and different algorithms, and improve the real-time, versatility, flexibility and scalability of industrial controllers. However, its reconstruction speed and reconstruction distance directly determine the performance of the system and hardware boards. With the continuous development of digital signal processing technology, the requirements for the transmission speed and complexity of high-performance equipment are gradually increasing, and data transmission bandwidth and transmission distance have become bottlenecks in the development of equipment. The current method of increasing data bandwidth is to increase the data throughput between devices by increasing the width of the parallel bus, but this method has problems with signal delay and clock phase offset. Traditional parallel transmission technology has been difficult to meet the current data transmission requirements. However, high-speed serial interface technology has the advantages of high bandwidth, low latency, strong anti-interference ability, and fewer pins, and has begun to lead the development of a new generation of high-speed transmission technology. Summary of the invention

[0004] In order to overcome the problems existing in the related technologies, the disclosed embodiments of the present invention provide a remote dynamic reconfigurable system and a reconfiguration method based on FPGA, and specifically relate to a remote dynamic reconfigurable technology implementation method based on FPGAUltraScale series RapidIO high-speed serial bus. The purpose of the present invention is to integrate RapidIO high-speed serial bus technology with reconfigurable technology, and design a dynamic reconfigurable system based on DSP+FPGA+RapidIO framework, which can solve the problems of reconfigurable system reconstruction speed and reconstruction distance.

[0005] The technical solution is as follows: a remote dynamic reconfigurable system based on FPGA, which integrates RapidIO high-speed serial bus technology with reconfigurable technology, reconfigures and designs a DSP+FPGA+RapidIO framework, realizes non-remote dynamic reconfiguration and remote dynamic reconfiguration, and specifically includes a host, DSP, FPGA, slave and FLASH memory;

[0006] The host is responsible for transmitting the remote configuration file to FPGA-KU115 through the RapidIO high-speed interface;

[0007] The DSP is responsible for the management of the reconstruction configuration file and transmits the configuration file to the slave A7 through the EMIF bus according to user requirements;

[0008] The FPGA adopts FPGA-KU115, which is used to configure the initial configuration file and the local configuration file;

[0009] The slave A7 is responsible for loading the received configuration data into FPGA-KU115 through the SelectMAP configuration interface;

[0010] The FLASH memory stores the initial configuration file and the local configuration file of FPGA-KU115.

[0011] Furthermore, the DSP is also used to read the remote configuration file received by FPGA-KU115 through the EMIF bus and store it in the DSP peripheral mounted FLASH memory.

[0012] The DSP processor of the DSP has an internal integrated EMIF bus interface, and the EMIF bus interface has multiple chip select spaces to connect different types of memories and processors; wherein the slave A7 is mounted to the CE1 space of the EMIF bus interface of the DSP processor; and the FPGA-KU115 is mounted to the CE2 space of the EMIF bus interface of the processor.

[0013] The slave A7 is also responsible for sending reset, work enable, and reconstructed waveform number information to the FPGA-KU115.

[0014] The FPGA-based remote dynamic reconfigurable system further includes: an EMIF interface between the DSP and the FPGA-KU115, an EMIF bus interface between the DSP and the A7, and a RapidIO interface between the FPGA-KU115 and the host.

[0015] Another object of the present invention is to provide a remote dynamic reconfiguration method based on FPGA, the method comprising: integrating RapidIO high-speed serial bus technology with reconfiguration technology, designing a hardware circuit design based on DSP+FPGA+RapidIO framework, performing dynamic reconfiguration of the carrier board, realizing high-speed dynamic switching of multiple complex algorithms, and realizing non-remote dynamic reconfiguration and remote dynamic reconfiguration.

[0016] Furthermore, the hardware circuit design of the dynamically reconfigurable carrier board includes:

[0017] The RapidIO bus circuit is designed and implemented. The RapidIO bus circuit is an interconnection architecture based on point-to-point message exchange technology. The RapidIO bus circuit supports 1x, 2x and 4x channel widths through SRIOGen2.0 endpoints, and the rate of each channel supports 1.25G, 2.5G, 3.125G, 5.0G and 6.25G.

[0018] The hardware circuit design for dynamically reconfiguring the carrier board also includes: designing and implementing the circuit for mounting FLASH on the periphery of FPGA-KU115. When performing global reconstruction, the global bitstream configuration file is loaded into FPGA-KU115, all the logic of FPGA-KU115 before reconstruction is completely changed, and the state indication and the intermediate results of the calculation are saved in the storage area before reconstruction; the FLASH memory in the FLASH circuit is used to store the state and intermediate results of FPGA-KU115 before reconstruction configuration, for data backup of multiple reconstruction tasks, and for redundant upgrade of the system.

[0019] The hardware circuit design for dynamically reconfiguring the carrier board also includes:

[0020] Design and implement the circuit of mounting FLASH on DSP peripherals. In the dynamic reconfiguration setting, a non-volatile memory is mounted on the DSP peripherals to store the configuration files.

[0021] Design and implement the peripheral storage circuit of slave A7. Mount a PROM on the peripheral of slave A7 to store the card's storage program and cascade multiple bitstream files.

[0022] The hardware circuit design for dynamically reconfiguring the carrier board also includes:

[0023] Design and implement the SelectMAP configuration circuit, which is used by slave A7 to configure FPGA-KU115 with the received configuration data through the SlaveSelectMAP interface.

[0024] In combination with all the above technical solutions, the beneficial effects of the present invention are as follows:

[0025] In order to solve the problems of reconstruction speed and reconstruction distance in the reconfigurable system and realize high reliability, high scalability and high flexibility of the overall project, the present invention integrates RapidIO high-speed serial bus technology with reconfigurable technology, reconstructs and designs a DSP+FPGA+RapidIO framework, realizes non-remote dynamic reconstruction and remote dynamic reconstruction, and calls corresponding configuration files according to different requirements based on the DSP+FPGA+RapidIO framework to realize the function of switching the internal logic of FPGA.

[0026] The present invention designs a dynamically reconfigurable system based on the "DSP+FPGA+RapidIO" framework, and selects DSP, XCKU115, and A7 as the three main processors of the reconstruction system. The hardware circuit design of the dynamically reconfigurable carrier board is carried out according to the overall design scheme of the system, wherein the carrier board communication circuit includes the design and implementation of the EMIF bus interface circuit and the design and implementation of the RapidIO interface circuit. The configuration circuit includes the design and implementation of the SelectMAP configuration circuit. The universal memory interface circuit includes the design and implementation of the FPGA-KU11 mounting FLASH circuit, the design and implementation of the DSP mounting FLASH memory circuit, and the design and implementation of the A7 mounting PROM circuit.

[0027] The dynamic reconfigurable system can store multiple configuration files, realize high-speed dynamic switching of multiple complex algorithms, and realize local dynamic reconstruction and remote dynamic reconstruction. In the present invention, A7 is used as a coprocessor of the reconstruction system, which is more flexible than other MCUs that directly configure the reconstruction device.

[0028] The present invention designs a dynamically reconfigurable carrier board of a "DSP+FPGA+RapidIO" architecture as a main control board, which can be connected with functional boards with different functional requirements and has high stability, high scalability and high versatility.

[0029] The transmission bandwidth of the RapidIO bus in the present invention can reach 6.5 Gbytes, and the realization of the remote dynamic reconfigurable system based on the SRIO bus provides a guarantee for the use of high-speed dynamic reconfiguration technology to achieve remote and rapid switching of complex algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure;

[0031] Figure 1 Schematic diagram of a remote dynamic reconfigurable system based on FPGA provided by an embodiment of the present invention;

[0032] Figure 2This is a diagram of a remote dynamically reconfigurable system based on FPGA provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below.

[0034] Embodiment 1, the remote dynamic reconfigurable system based on FPGA provided by the embodiment of the present invention calls the corresponding configuration file according to different requirements to switch the internal logic function of FPGA. The system mainly consists of five parts: host, DSP, FPGA, slave and FLASH memory. Figure 1 As shown;

[0035] The non-remote dynamic reconfiguration scenarios include:

[0036] (1) FPGA-KU115 calls the initial configuration file and local configuration file stored in the FLASH memory and reconstructs them to obtain the local reconstructed configuration file;

[0037] (2) FPGA-KU115 transmits the above local reconstruction configuration file to DSP through EMIF bus. DSP is responsible for the management of local reconstruction configuration file, resetting, enabling and configuring reconstruction waveform number of local reconstruction configuration file. After successful configuration, the configuration information is transmitted to slave A7 through EMIF bus according to user requirements.

[0038] (3) Slave A7 loads the received configuration data into FPGA-KU115 through the SelectMAP configuration interface; completes sending a work enable command to FPGA-KU115, and finally realizes non-remote dynamic reconstruction;

[0039] Exemplarily, the local configuration file is a local configuration BIT file;

[0040] The local configuration BIT file is produced from the program which BitGen is used to generate the bitstream required by the Xilinx Field Programmable Gate Array (FPGA). It is stored in a binary format and contains information used to upload data for configuration to the FPGA tool;

[0041] The initial configuration file usually includes .bash_profile environment variable settings, bashrc bash personal configuration, or directly using the system default configuration. Personal users do not need anything.

[0042] In the remote dynamic reconstruction scheme, including:

[0043] 1) The host uses Xilinx's KC705 development board to transmit the remote configuration file to FPGA-KU115 through the RapidIO high-speed interface;

[0044] 2) FPGA-KU115 calls the initial configuration file and the local configuration file stored in the FLASH memory, and reconstructs them to obtain the remote reconstructed configuration file;

[0045] 3) DSP reads the remote reconstruction configuration file reconstructed by FPGA-KU115 through the EMIF bus. DSP is responsible for the management of the remote reconstruction configuration file, and performs the reset, work enable, and reconstruction waveform number configuration of the remote reconstruction configuration file. After the configuration is successful, one path is stored in the DSP peripheral mounted FLASH memory; the other path transmits the configuration information to the slave A7 through the EMIF bus according to user needs;

[0046] 4) Slave A7 is responsible for loading the received configuration data into FPGA-KU115 through the SelectMAP configuration interface. In addition, it sends reset, work enable, reconstruction waveform number and other information to FPGA-KU115; completes sending the work enable command to FPGA-KU115, and finally realizes remote dynamic reconstruction.

[0047] Embodiment 2, in order to realize the communication between the processors of each component in the reconstruction system, the communication interface between each processor is designed, mainly including the EMIF interface between the DSP and the FPGA-KU115, the EMIF bus interface between the DSP and the A7, and the RapidIO interface between the FPGA-KU115 and the host XilinxKC705;

[0048] Furthermore, the EMIF bus circuit design and implementation are carried out;

[0049] The DSP processor integrates an EMIF bus interface, which has 8 chip select spaces (CE0-CE7) that can connect different types of memories and processors. In order to facilitate communication between DSP and FPGA, the present invention mounts slave A7 to the CE1 space of the DSP chip EMIF bus interface. Mount the FPGA-KU115 chip to the CE2 space of the DSP chip EMIF bus interface;

[0050] Furthermore, the RapidIO bus circuit is designed and implemented. The RapidIO bus technology is an interconnection architecture based on point-to-point message exchange technology, which has the advantages of high bandwidth, low latency, strong anti-interference ability, and fewer pins.

[0051] Xilinx has designed the SRIOGen2.0EndPoint solution in the Ultrascale series FPGA. The IP core solution provides sample design code in the form of a netlist. The SRIOGen2.0 endpoint supports 1x, 2x and 4x channel widths. The rate of each channel supports 1.25G, 2.5G, 3.125G, 5.0G and 6.25G;

[0052] Furthermore, the circuit design and implementation of the FLASH mounted on the periphery of FPGA-KU115 are carried out. When global reconstruction is required during the operation of the reconstruction system, the global bitstream configuration file is loaded into the FPGA-KU115. All the logic of FPGA-KU115 before reconstruction is changed. Therefore, some status indications and intermediate results of calculations must be saved in a certain storage area before reconstruction.

[0053] Therefore, a dedicated FLASH memory is designed in the present invention to store the state and intermediate results of FPGA-KU115 before the reconfiguration. As a backup memory for system reconfiguration, a memory with large capacity is selected as much as possible to facilitate the system to perform data backup for multiple reconfiguration tasks and facilitate the system to perform redundant upgrades.

[0054] Furthermore, the circuit design and implementation of DSP peripheral mounting FLASH are carried out. In the dynamically reconfigurable design scheme, a non-volatile memory is required to be mounted on the DSP peripheral to store the configuration file. Due to the high reliability of BPIFLASH, it is often used to store code and key data. In the present invention, BPIFLASH is selected as the non-volatile memory mounted on the DSP peripheral.

[0055] Furthermore, the design and implementation of the slave A7 peripheral curing storage circuit is carried out. A PROM is mounted on the slave A7 peripheral to store the board's curing program. XCF32P is an online programmable PROM for configuring Xilinx FPGA, which can cascade and store multiple bitstream files. The maximum configuration rate of the FPGA configuration interface can reach 66MHz. It has a built-in data decompressor, which is compatible with Xilinx advanced compression technology.

[0056] Furthermore, the SelectMAP configuration circuit is designed and implemented. In the present invention, DSP serves as the main controller of the dynamic reconstruction system, determines the content and initiation time of the reconstruction, and transmits the configuration data to the slave A7 through the EMIF bus. The slave A7 configures the FPGA-KU115 with the received configuration data through the SlaveSelectMAP interface.

[0057] Embodiment 3, as Figure 2 The present invention provides a remote dynamic reconfigurable method based on FPGA, the method comprising:

[0058] S1, integrates RapidIO high-speed serial bus technology with reconfigurable technology to design a DSP+FPGA+RapidIO framework;

[0059] S2, conducts hardware circuit design of dynamic reconstruction carrier board, realizes high-speed dynamic switching of multiple complex algorithms, and realizes non-remote dynamic reconstruction and remote dynamic reconstruction.

[0060] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0061] Since the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present invention, their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0062] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment.

[0063] An embodiment of the present invention further provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps in any of the above-mentioned method embodiments when executing the computer program.

[0064] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0065] An embodiment of the present invention further provides an information data processing terminal, which, when executed on an electronic device, provides a user input interface to implement the steps in the above method embodiments. The information data processing terminal is not limited to mobile phones, computers, and switches.

[0066] An embodiment of the present invention further provides a server, which is used to provide a user input interface to implement the steps in the above method embodiments when executed on an electronic device.

[0067] An embodiment of the present invention provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0068] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a disk or an optical disk.

[0069] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered by the protection scope of the present invention.

Claims

1. A remote dynamically reconfigurable system based on FPGA, characterized in that: The system integrates RapidIO high-speed serial bus technology with reconfigurable technology, and reconfigures the design based on DSP+FPGA+RapidIO framework to achieve non-remote dynamic reconstruction and remote dynamic reconstruction, specifically including the host, DSP, FPGA, slave and FLASH memory; The host is responsible for transmitting the remote configuration file to FPGA-KU115 through the RapidIO high-speed interface; The DSP is responsible for the management of the reconstruction configuration file and transmits the configuration file to the slave A7 through the EMIF bus according to user requirements; The FPGA adopts FPGA-KU115, which is used to configure the initial configuration file and the local configuration file; The slave A7 is responsible for loading the received configuration data into FPGA-KU115 through the SelectMAP configuration interface; The FLASH memory stores the initial configuration file and the local configuration file of FPGA-KU115.

2. The remote dynamically reconfigurable system based on FPGA according to claim 1, characterized in that: The DSP is also used to read the remote configuration file received by FPGA-KU115 through the EMIF bus and store it in the DSP peripheral mounted FLASH memory.

3. The remote dynamically reconfigurable system based on FPGA according to claim 1, characterized in that: The DSP processor of the DSP has an internal integrated EMIF bus interface, and the EMIF bus interface has multiple chip select spaces to connect different types of memories and processors; wherein the slave A7 is mounted to the CE1 space of the EMIF bus interface of the DSP processor; and the FPGA-KU115 is mounted to the CE2 space of the EMIF bus interface of the processor.

4. The remote dynamically reconfigurable system based on FPGA according to claim 1, characterized in that: The slave A7 is also responsible for sending reset, work enable, and reconstructed waveform number information to the FPGA-KU115.

5. The remote dynamically reconfigurable system based on FPGA according to claim 1, characterized in that: The system further includes: an EMIF interface between the DSP and the FPGA-KU115, an EMIF bus interface between the DSP and the A7, and a RapidIO interface between the FPGA-KU115 and the host.

6. A remote dynamic reconfigurable method based on FPGA, characterized in that: The method is applied to the FPGA-based remote dynamic reconfigurable system according to any one of claims 1 to 5, and the method comprises: S1. Integrate RapidIO high-speed serial bus technology with reconfigurable technology to design a DSP+FPGA+RapidIO framework. S2. Perform hardware circuit design of the dynamic reconstruction carrier board to achieve high-speed dynamic switching of multiple complex algorithms, as well as non-remote dynamic reconstruction and remote dynamic reconstruction.

7. The remote dynamic reconfigurable method based on FPGA according to claim 6, characterized in that: The hardware circuit design for dynamically reconfiguring the carrier board includes: The RapidIO bus circuit is designed and implemented. The RapidIO bus circuit is an interconnection architecture based on point-to-point message exchange technology. The RapidIO bus circuit supports 1x, 2x and 4x channel widths through SRIOGen2.0 endpoints, and the rate of each channel supports 1.25G, 2.5G, 3.125G, 5.0G and 6.25G.

8. The remote dynamic reconfigurable method based on FPGA according to claim 6, characterized in that: The hardware circuit design for dynamically reconfiguring the carrier board also includes: designing and implementing the circuit for mounting FLASH on the periphery of FPGA-KU115. When performing global reconstruction, the global bitstream configuration file is loaded into FPGA-KU115, all the logic of FPGA-KU115 before reconstruction is completely changed, and the state indication and the intermediate results of the calculation are saved in the storage area before reconstruction; the FLASH memory in the FLASH circuit is used to store the state and intermediate results of FPGA-KU115 before reconstruction configuration, for data backup of multiple reconstruction tasks, and for redundant upgrade of the system.

9. The remote dynamic reconfigurable method based on FPGA according to claim 6, characterized in that: The hardware circuit design for dynamically reconfiguring the carrier board also includes: Design and implement the circuit of mounting FLASH on DSP peripherals. In the dynamic reconfiguration setting, a non-volatile memory is mounted on the DSP peripherals to store the configuration files. Design and implement the peripheral storage circuit of slave A7. Mount a PROM on the peripheral of slave A7 to store the card's storage program and cascade multiple bitstream files.

10. The remote dynamic reconfigurable method based on FPGA according to claim 6, characterized in that: The hardware circuit design for dynamically reconfiguring the carrier board also includes: Design and implement the SelectMAP configuration circuit, which is used by slave A7 to configure FPGA-KU115 with the received configuration data through the SlaveSelectMAP interface.

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