Implication logic synthesis and optimization method based on memristor circuit

Abstract

The invention discloses a memristor circuit-based implication logic synthesis and optimization method, which comprises the following steps of: acquiring a gate-level netlist for representing a Boolean function by using an ABC and a simulated annealing algorithm based on a node sensing cost function, and converting a circuit topology connection relationship in the gate-level netlist into an IMG; calculating the optimal IIG of all the four-input NPN Boolean functions by using an SAT-based precise synthesis algorithm and NPN equivalent classification, establishing an IMG off-line database by using IMG logic to represent an inverter in the IIG, and converting an input circuit into an IMG structure by using a logic rewriting algorithm and the IMG off-line database; based on a heuristic algorithm of logic reconstruction, all structures with a fan-out problem in an IMG structure are solved, and an implication network without the fan-out problem and with the number of memristors and the number of pulses reduced is obtained. According to the method, the number of operation pulses in the memristor circuit is reduced, the number of memristors is reduced, and the design cost is reduced.

Description

Technical Field

[0001] The present invention relates to an electronic design automation method for a storage-computation integrated circuit, and in particular to an implicit logic synthesis and optimization method based on a memristor circuit. Background Art

[0002] In recent years, as Moore's Law approaches its limits, the von Neumann architecture faces a "memory wall" bottleneck, which hinders processor performance and leads to increased energy consumption. This challenge has prompted extensive research on alternative computing paradigms, including quantum computing, optical computing, and in-memory computing using non-volatile memory. Among them, in-memory computing has attracted widespread attention due to its ability to achieve energy-efficient computing and overcome the limitations of the von Neumann architecture. Prominent non-volatile memory technologies in this field include phase-change memory (PCM) and memristor-based resistive random-access memory (RRAM). In-memory computing can be applied to both analog and digital computing paradigms. Analog methods are often used for matrix-vector multiplication (MVM) in neural network implementations, where multiplication and accumulation (MAC) are performed based on inherent physical properties (such as Kirchhoff's laws). It shows superior energy and latency performance compared to traditional CMOS-based computing platforms. However, the accuracy of analog in-memory computing is limited, so it is not suitable for high-precision, high-demand scientific computing. In contrast, digital in-memory computing is able to achieve precise logic calculations, making it very suitable for scientific simulation. Several logic design styles have been developed using memristors, including material implication (Implication, IMPLY), memristor-aided logic (Memristor-aided Logic, MAGIC), etc. It is worth noting that the IMPLY paradigm is particularly attractive for its efficient and compact design, because memristive switches can perform "stateful" logic operations, integrating logic and memory functions in the same device.

[0003] To achieve large-scale design of implied logic circuits, logic synthesis and design automation are crucial as they facilitate efficient and scalable development of these advanced circuits. For standard digital logic, various synthesis tools have been developed over time. One effective tool is the logic synthesis open source tool ABC, which performs process-independent optimization of Boolean functions followed by process mapping. However, for implied logic circuits, the storage characteristics of memristors reduce data movement during calculations, but when there are multiple fan-outs, the original input values ​​are overwritten by the stored values, which brings challenges in the order of calculations. Traditional logic synthesis tools are not designed to address these issues, so the results generated by these tools must be analyzed for the aforementioned fan-out issues. Different from traditional CMOS circuits, memristors have their specific area and delay constraints, where area is defined as the total number of input and working memristors and delay is defined as the total number of pulses required for implied and FALSE operations. Therefore, it is crucial to study and develop synthesis methods specifically for memristor circuits and implied logic.

[0004] The current implicit logic synthesis method used for memristor-based circuits uses repeated generation of correct fan-out logic or temporary copying of the result to another memristor to solve the fan-out problem structure, and then further searches for a better sub-circuit without fan-out problem. However, this method only focuses on optimizing the nodes within the structure used to solve the fan-out problem, that is, the optimization of the circuit structure. Other aspects of logic synthesis are not considered, which makes the number of circuit operation pulses and the number of memristors not the optimal result after solving the circuit fan-out problem. Summary of the invention

[0005] The technical problem to be solved by the present invention is to propose an implicit logic synthesis and optimization method based on a memristor circuit in view of the shortcomings of the prior art. The method solves this challenge from the perspective of logic synthesis, which not only reduces the number of operating pulses in the memristor circuit, but also reduces the number of memristors, thereby reducing the design cost.

[0006] The technical solution adopted by the present invention to solve the above technical problems is: an implicit logic synthesis and optimization method based on a memristor circuit, comprising the following steps: S1. Use the open source logic synthesis tool ABC and the simulated annealing algorithm based on the node-aware cost function to obtain the gate-level netlist used to represent the Boolean function, and convert the circuit topology connection relationship in the gate-level netlist into a directed acyclic graph IMG (IMPLY Graph, IMG); S2. Calculate the optimal imply-inverter graph IIG (IMPLY-Inverter Graph, IIG) of all four-input NPN Boolean functions by using the exact synthesis algorithm based on Boolean Satisfiability SAT (Satisfiability, SAT) and NPN (Negation-Permutation-Negation, NPN) equivalence classification, and use the directed acyclic graph IMG to logically represent the inverters in the optimal imply-inverter graph IIG, establish an IMG offline database, and convert the input circuit into an IMG structure through the logic rewriting algorithm and the IMG offline database; S3. A heuristic algorithm based on logic reconstruction is used to solve all structures with fan-out problems in the IMG structure, and an implied network with no fan-out problem and a reduced number of memristors and pulses is obtained.

[0007] In a specific implementation manner, the specific process of step S1 is: S1.1. Use the open source logic synthesis tool ABC to read the Boolean function described in blif or pla format and the process library in genlib format containing IMP, INV, ZERO, ONE, and BUF gates, where IMP represents a two-input implication gate, INV represents an inverter whose second input represented by IMP is 0 (i.e., the non-negative input is 0), ZERO represents a constant gate zero, ONE represents a constant gate one, and BUF represents a buffer; The optimization operators rewrite, rewrite -z, refactor, refactor -z, resub, resub-z, balance and dc2 are selected and applied iteratively. The simulated annealing algorithm is used to iteratively reshape and reduce the AIG representation of the Boolean function. A node-aware cost function C is introduced to predict the total number of nodes in the Boolean function after solving the fan-out problem, so as to evaluate and determine the operator sequence with the minimum cost. The AIG representation of the Boolean function is logically optimized through the operator sequence with the minimum cost. The node-aware cost function C is defined as: ; In formula (1), N represents the Boolean function, n represents the number of original nodes in the Boolean function, S i represents the fan-out cost of the i-th node in the original node; S1.2, use the process mapping command map in ABC, use the input process library, process map the AIG representation of the Boolean function after logic optimization, and obtain the gate-level netlist in Verilog format; S1.3. The circuit topology connection relationship in the gate-level netlist is converted into a directed acyclic graph IMG through a netlist parser, wherein the nodes in IMG include two types: IMP and INV represented by IMP, and the edges in IMG represent the connection relationship between logic gates.

[0008] In a specific implementation manner, the specific process of step S2 is: S2.1. Define four Boolean variables: x it , g hi , S ijk , P ci ,in: x it Indicates the circuit i Logic Gates x i In the truth table of the logic function t The value of the bit; g hi Represents a logic gate x i Is the output of the circuit the original output? If the logic gate x i The output of the circuit is h Raw output g hi , then the Boolean variable g hi The value is true, otherwise it is false; S ijk Represents a logic gate x i The two input x j , x k The connection relationship between the two inputs and whether the two inputs perform implicit logic. If the logic gate x i The two input x j and x k If the implied logic is executed, the Boolean variable S ijk The value is true, otherwise it is false, where j , k The value range is: 1≤ j < i , 1≤ k < i , j ≠ k ; Pci Represents a logic gate x i The two input x j , x k The polarity of P ci The value range is: 0≤ P ci ≤1, where c =1,2; S2.2. The logic circuit consisting of implied logic and negation logic is used as the logic function. In addition to the original input and original output, each logic gate performs the implied logic operation. The negation logic is represented by the dotted line connecting the edges in the circuit. The main constraints in the implied logic are: ; In formula (2), the symbol “ " represents the essence of the logical operation, the symbol " " indicates strict equivalence; Formula (2) indicates that if the logic gate x i The two inputs are x j , x k ,and x j , x k Perform the implied logic operation, i.e. , then the logic gate x i The value of x it Expressed as ; Applying the Tseytin transformation method, the implied logic gates in the circuit are converted into the description form of the CNF formula, and the CNF paradigm of the implied logic gates is obtained: ; in" ” represents the AND gate; use , where the symbol " " represents logical OR, and the constraints of CNF paradigm are obtained, which can be further simplified to: ; For the logical expression contained in formula (4) , define a Boolean variable , then formula (4) becomes: ; Using Tseytin transformation method, the logical expression Converted into CNF form, we get: ; In summary, the main CNF constraint formulas of implication logic are summarized as follows: ; In addition, if the logic gate x i is the original output of the circuit, then x i The logic function truth table must be equal to the original output of the circuit g h So we add the constraint: ; in yes t The binary code of " ” stands for logical exclusive OR; To ensure the original output of the circuit g h Must be a logic gate x i Output of adding constraints: ; To ensure that each logic gate in the circuit has two legal inputs, add the constraints: ; S2.3. Based on the constraints obtained above, the number of implied logic gates required is first set to 0, and a CNF constraint file is obtained by encoding. The obtained CNF constraint file is then transmitted to a Boolean satisfiability solver, i.e., a SAT solver. The SAT solver assigns values ​​to the Boolean variables in the received CNF constraint file, and searches for a set of Boolean variable assignments whose values ​​satisfy equations (7) to (10) and are all true. If the SAT solver finds such a set of Boolean variable assignments, the result returned is SAT, indicating that the optimal solution has been found; otherwise, the required number of implied logic gates is increased by 1, and the code and solution are re-performed until the result returned by the SAT solver is SAT and the result representing the optimal solution is returned; S2.4, according to the result representing the optimal solution returned by the SAT solver, the optimal implication-inverter graph IIG of all four-input NPN Boolean functions is calculated by using NPN equivalence classification, and the inverters in the optimal implication-inverter graph IIG are represented by using the directed acyclic graph IMG logic to establish an IMG offline database; S2.5, for the directed acyclic graph IMG of the input circuit, first use the cut enumeration algorithm to find the four-input cuts for each node of IMG; S2.6, apply NPN equivalent classification to normalize each cut and obtain the Boolean function of the cut; S2.7, match the IMG offline database established in step S2.4 with the Boolean function of the cut; if the Boolean expression in the IMG offline database is better than the four-input cut of IMG, then replace it, that is, obtain the optimized IMG structure through the logic rewriting algorithm.

[0009] In a specific implementation manner, the specific process of step S3 is: S3.1. First, define different structural types of fan-out problems, and determine the structures without fan-out problems after logical reconstruction that match the structural types of different fan-out problems. S3.2, for the IMG structure obtained in step S2, first traverse the nodes in the IMG structure in topological order, and then for each node, determine whether the IMG structure has a structure with a fan-out problem through the connection relationship between the node and the nodes of the next level. If there is a structure with a fan-out problem, determine the structure type of the fan-out problem and perform logical reconstruction, that is, replace the structure with a fan-out problem with a structure without a fan-out problem after logical reconstruction that matches the structure type of the fan-out problem; S3.3. Repeat step S3.2 to solve all structures with fan-out problems in the IMG structure, and obtain an implied network with no fan-out problem and a reduced number of memristors and pulses.

[0010] Compared with the prior art, the present invention has the following advantages: (1) The implied logic synthesis and optimization method based on memristor circuit proposed in the present invention uses the open source logic synthesis tool ABC and a simulated annealing algorithm based on the node-aware cost function to obtain a gate-level netlist, which has better results and a higher degree of automation. Specifically, the method of the present invention can accurately calculate the cost value required for each node in the circuit to complete the ABC process mapping according to the specific fan-out type information of the circuit; compared with the traditional method, the present invention not only has a more accurate cost function, but also can obtain a higher quality mapping netlist; through practical verification, the number of nodes in the gate-level netlist obtained by the method of the present invention after ABC process mapping is greatly reduced; (2) The proposed method for the implication logic synthesis and optimization based on memristor circuits uses an exact synthesis algorithm based on SAT and NPN equivalence classification to calculate the optimal implication-inverter graph IIG of all four-input NPN Boolean functions. By using IMG logic to represent the inverters in the IIG, an IMG offline database is established. The input circuit is converted into an IMG structure through a logic rewriting algorithm and an IMG offline database. Through examples, it is verified that this method reduces or maintains the total number of circuit nodes while ensuring that the local cut network is optimal or fan-out-free. (3) The heuristic algorithm based on logic reconstruction adopted by the present invention can solve various types of fan-out problem structures in IMG structures. Compared with the methods in existing work, this method obtains a better structure without fan-out problem to integrate memristor-based logic circuits, minimize the operation pulses, and reduce the design cost. The evaluation of the benchmark circuit shows that when there is an improved structure, the method of the present invention reduces the increase in the number of nodes after solving the fan-out problem. In addition, the method of the present invention can solve the fan-out problem of single-output and multi-output Boolean functions. Specifically, the optimization results on ISCAS'85 and a group of MCNC test sets show that the method of the present invention reduces the use of memristors by 7% and 22%, respectively, and reduces the number of operation pulses by 4% and 21%, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The structure of the implicit logic circuit composed of memristors and resistors and its logic gate symbols; Figure 2 is the truth table of the logic function of the implicit logic circuit composed of memristors; Figure 3 To solve the fan-out problem in implied logic; Figure 4 It is a process library in genlib format that contains IMP, INV, ZERO, ONE, and BUF gates; Figure 5 It is the flowchart of simulated annealing algorithm; Figure 6 for two fan-out problem circuit substructures with the same number of nodes and their fan-out-free structure; Figure 7 This is the netlist IMG representation of circuit exam3_d after ABC process mapping; Figure 8 A circuit substructure for fan-out problem and a solution thereof; Fig. 9 Compare two substructures for solving the fan-out problem; Fig.10 Restructuring and replacement processes for fan-out problem structures; Fig.11 The figure is an overall flow chart of the method of the present invention. DETAILED DESCRIPTION

[0012] The present invention is further described in detail below with reference to the accompanying drawings.

[0013] Figure 1 The structure of the logic circuit composed of memristors and resistors and its logic gate symbol, Figure 2is the logic function truth table of the implicit logic circuit composed of memristors. From this truth table, we can derive the implicit logic Logically equivalent to A memristor is a two-terminal device with an internal resistance state, which can be a low resistance state (LRS) or a high resistance state (HRS), representing the binary values ​​0 and 1, respectively. By applying positive or negative voltages, the resistance state of these devices can be changed, thereby performing digital logic operations. Figure 1 In the structure of the two memristors as digital switches, the initial resistance state is the logic input, and the voltage is applied to each V COND and V SET Perform an implied logic operation , can be executed and the result stored in the memristor Q The result of the operation is Q The final resistance value.

[0014] However, this storage-computation-in-one feature will cause the implicit logic circuit to produce Figure 3 The fan-out problem in the implied logic is shown. Figure 3 middle, M 1 Represents a memristor, when it contains a logic gate G 0 The output (assuming the output value is v 1 , saved in M 1 Middle) are connected to two implied logic gates G 1 and G 2 When the non-negative input terminal is given G 1 When the voltage pulse is aligned, after the implicit logic operation, the memristor M 1 The logical value of v 1 becomes v 2 , then the previous logical value v 1 It disappears. At the same time, for the implied gate G 2 For example, its non-negative input should be v 1 , but at this time G 2 The input value of the non-negative input terminal is v2 , so G 2 The logic result is wrong. The method of the present invention aims to solve the fan-out problem of the implied logic circuit, synthesize the circuit, and simultaneously use the logic synthesis method to optimize the implied network.

[0015] Taking the exam3_d circuit in the international benchmark test circuit example MCNC as an example, the method of the present invention is used to perform implicit logic synthesis and optimization, and the steps are as follows: S1. Logic synthesis Use the open source logic synthesis tool ABC to read the exam3_d circuit described in blif or pla format and the genlib format containing IMP, INV, ZERO, ONE, and BUF gates. Figure 4 The process library shown, where IMP represents a two-input implication gate, INV represents an inverter with the second input 0 represented by IMP, ZERO represents a constant gate zero, ONE represents a constant gate one, and BUF represents a buffer.

[0016] Different from using ABC's built-in fixed-order optimization operators rewrite, refactor and balance to perform logical optimization on the AIG representation of Boolean functions, the present invention iteratively applies operators to optimize a given Boolean function, replacing the fixed operator sequence and using the number of nodes of legal implied logic circuits as the node-aware cost function.

[0017] The present invention selects the optimization operators rewrite, rewrite -z, refactor, refactor -z, resub, resub -z, balance and dc2, and applies these optimization operators iteratively, using Figure 5 The simulated annealing algorithm shown iteratively reshapes and reduces the AIG representation of the Boolean function, and, in order to evaluate the operator selection in the simulated annealing algorithm, the traditional typical method is to use the number of network nodes as a performance indicator. However, since the main goal of the method of the present invention is to optimize the implied network after solving the fan-out problem, and the fan-out problem often increases the number of nodes in the mapping netlist, the present invention introduces a node-aware cost function C to predict the total number of nodes in the Boolean function after solving the fan-out problem, so as to evaluate and determine the operator sequence with the minimum cost, and the AIG representation of the Boolean function is logically optimized through the operator sequence with the minimum cost, wherein the node-aware cost function C is defined as: ; In formula (1), N represents the Boolean function, n represents the number of original nodes in the Boolean function, S i represents the fan-out cost of the i-th node in the original node.

[0018] After solving the fan-out problem, the netlist is scored based on the final number of nodes in the Boolean function (i.e., the network) using the node-aware cost function described above. The total number of nodes in the Boolean function after solving the fan-out problem, predicted by the node-aware cost function, is used as a criterion for selecting optimization operators in the simulated annealing algorithm, ensuring that the network is optimized while minimizing the overhead caused by solving the fan-out problem.

[0019] The node-aware cost function defined in the simulated annealing algorithm makes it a node-aware simulated annealing algorithm. When optimizing a network using a randomly selected ABC optimizer through simulated annealing, the synthesis tool ALSO reads the network and checks its fan-out structure. This process determines whether there is a fan-out problem for each node, determines the fan-out type, and calculates the number of fan-outs, assigns a corresponding score to each node, and returns the evaluated score result to the simulated annealing algorithm as a selection criterion. The algorithm selects the circuit structure with the lowest total cost. For example, if a circuit appears like Figure 6 The circuit shown, Figure 6 (a) and Figure 6 The two structures have the same number of nodes, but belong to different fan-out types: fp_fn and fp_1. After solving the fan-out problem, the resulting structures are as follows: Figure 6 (b) and Figure 6 This shows that, despite the equal number of initial nodes, the final structure differs depending on the fan-out type. For example, in Figure 6 In (a), node a has multiple fan-outs and is classified as fp_1. Then the number of fan-outs of node a is returned. num , Figure 6 (b) in the figure shows the structure after solving the fan-out problem. The fan-out evaluation score for this type is defined as S a = num Given num = 2, Figure 6 The fan-out score of the structure in (a) is 2. In contrast, for Figure 6 In the structure of (c), node a is classified as fp_fn. The fan-out number of node a is returned as num , the score of this type is defined as S a = num -1, so Figure 6 The fan-out score of the structure in (c) is 1.

[0020] therefore, Figure 6 The final cost of (a) is 5, while Figure 6The final cost of (c) in is 4. Assuming that the optimization operator sequence is rewrite, refactor, and resub, we get Figure 6 In the structure (a), selecting the optimization operators refactor, resub, and rewrite will yield Figure 6 In the structure (c), the node-aware simulated annealing algorithm selects the operator sequence with the lowest cost: refactor, resub, rewrite, thus obtaining a more optimized network. After the simulated annealing algorithm based on the node-aware cost function evaluates and selects the optimized operator sequence, the process mapping command map in ABC is used to process map the AIG representation of the Boolean function after logic optimization using the input process library to obtain a gate-level netlist in Verilog format.

[0021] When read, the IMPLY netlist of the original exam3_d circuit contains 14 gates. Then, following the previous process, the simulated annealing algorithm is used in conjunction with ABC to adjust the optimization operator sequence, resulting in a mapped IMPLY netlist with 10 gates. For this optimized 10-gate IMPLY netlist, a netlist parser is used to input it into the synthesis tool ALSO to construct a DAG consisting only of IMPLY gates: IMG, as shown in Figure 7 As shown. Figure 7 In the figure, node 0 represents constant node 0, nodes 1, 2, 3 and 4 represent the PI of the circuit, Po0 represents the PO of the circuit, and other nodes represent intermediate gate nodes. The circuit topology connection relationship in the gate-level netlist is converted into a directed acyclic graph IMG through a netlist parser. There are two types of nodes in IMG: IMP and INV (non-negative input is 0) represented by IMP. The edges in IMG represent the connection relationship between logic gates.

[0022] S2. Calculate the optimal implication-inverter graph IIG of all four-input NPN Boolean functions using the exact synthesis algorithm based on Boolean satisfiability SAT and NPN equivalent classification. Use the directed acyclic graph IMG to logically represent the inverters in the optimal implication-inverter graph IIG, establish an IMG offline database, and convert the input circuit into an IMG structure through the logic rewriting algorithm and the IMG offline database. The specific steps are as follows: Step 1: Define Boolean variables Define four Boolean variables: x it , g hi , S ijk , P ci ,in: x it Indicates the circuit iLogic Gates x i In the truth table of the logic function t The value of the bit; g hi Represents a logic gate x i Is the output of the circuit the original output? If the logic gate x i The output of the circuit is h Raw output g hi , then the Boolean variable g hi The value is true, otherwise it is false; S ijk Represents a logic gate x i The two input x j , x k The connection relationship between the two inputs and whether the two inputs perform implicit logic. If the logic gate x i The two input x j and x k If the implied logic is executed, the Boolean variable S ijk The value is true, otherwise it is false, where j , k The value range is: 1≤ j < i , 1≤ k < i , j ≠ k ; P ci Represents a logic gate x i The two input x j , x k The polarity of P ci The value range is: 0≤ P ci ≤1, where c =1,2; Step ②: Convert the constraint problem in the implication logic into a conjunctive normal form formula, i.e., a CNF formula, and obtain the constraint condition formula for the implication logic: ; Based on the constraints obtained above, the number of implied logic gates required is first set to 0, and a CNF constraint file is obtained by encoding; the obtained CNF constraint file is then transmitted to a Boolean satisfiability solver, i.e., a SAT solver; the SAT solver assigns values ​​to the Boolean variables in the received CNF constraint file, and searches for a set of Boolean variable assignments whose values ​​are all true and satisfy the above constraints; If the SAT solver finds such a set of Boolean variable assignments, the result returned is SAT, indicating that the optimal solution has been found; otherwise, the required number of implied logic gates is increased by 1, and the code and solution are re-performed until the result returned by the SAT solver is SAT and the result representing the optimal solution is returned; According to the results representing the optimal solution returned by the SAT solver, the optimal implication-inverter graph IIG (i.e., digital circuit logic functions, a total of 222 functions) of all four-input NPN Boolean functions is calculated using NPN equivalent classification. By using IMG logic to represent the inverters in the IIG, the optimal IIG of the circuit logic function is obtained, and the optimal IMG offline database is established accordingly.

[0023] For the directed acyclic graph IMG of the input circuit, the four-input cut of each node of IMG is first found using the cut enumeration algorithm; each cut is normalized by applying NPN equivalence classification to obtain the Boolean function of the cut; the Boolean function of the cut is matched with the IMG offline database; if the Boolean expression in the IMG offline database is better than the four-input cut of IMG, it is replaced, that is, the optimized IMG structure is obtained through the logic rewriting algorithm.

[0024] S3. Based on the heuristic algorithm of logic reconstruction, all structures with fan-out problems in the IMG structure are solved to obtain the implied network without fan-out problems and with reduced number of memristors and pulses. The specific steps are as follows: First, define different fan-out problem structure types, and determine the structure without fan-out problem after logical reconstruction that matches the structure type of fan-out problem. Figure 8 As shown, it involves logic refactoring by adding two INV gates to preserve logic functionality while solving the fan-out problem. The fan-out problem can be solved by adding two INV gates in parallel or in series. Figure 8 In the added door G 3 and G 4 Based on the implied INV gate (non-negative input value is 0), the value of the negative input can be inverted. In addition, the original value (otherwise it will be overwritten) can be stored in the working memristor of the added INV gate, thus solving the fan-out problem. On this basis, a better fan-out-free structure is proposed, such as Fig. 9 As shown, it is possible to both solve the fan-out problem and optimize the circuit.

[0025] Give an example to explain how to solve the fan-out problem. Figure 7 ,First, the heuristic algorithm traverses each node in the network n through the topological structure. For node 1, first obtain its fan-out information, the red edge represents the working memristor end, and the black edge represents the input memristor end. Node 1 has two fan-out nodes, which serve as inputs to nodes 6 and 11 respectively. Node 1 is not used as the input to the working memristor port of any other node, so node 1 is stored as a normal node, and its fan-out node set (including only the node itself and the working memristor port) is: 1, 11. Similar processing is performed on other nodes.

[0026] After determining that the type of node 3 is a fan-out structure, and its fan-out node set is: '3', '7', '6', '8', the corresponding type of structure in the heuristic algorithm is used to solve the fan-out problem. The main method involves logical reconstruction. The specific process is as follows Fig.10 As shown, first, an edge is generated for node 3: "signal_1", and then "signal_1" is reversed to create a new INV node "g 1 ", the output is "f 1 ". Perform the same operation on node 6 to create a new INV node 'g 2 ', the output is 'f 2 '. Then, use 'f 1 'as the input memristor terminal,'f 2 'As a working memristor end to reconstruct an implication gate 7', it replaces the original node 7. This process of replacing the original structure to form a new network is called logic reconstruction.

[0027] Similarly, the obtained IMG structure is first topologically traversed through the nodes in the IMG structure, and then for each node, the connection relationship between the node and the nodes of the next level is used to determine whether the IMG structure has a structure with a fan-out problem. If there is a structure with a fan-out problem, the structure type of the fan-out problem is determined and logical reconstruction is performed, that is, the structure with the fan-out problem is replaced with a structure without a fan-out problem after logical reconstruction corresponding to the structure type of the fan-out problem; repeat the above operation to solve all structures with fan-out problems in the IMG structure, and obtain an implied network with no fan-out problem and a reduced number of memristors and pulses.

[0028] The overall flow chart of the method of the present invention is shown in Fig.11 The performance comparison of the implied logic synthesis and optimization method based on memristor circuit proposed in the present invention with the best work of such research results is as follows.

[0029] Table 1 shows the performance comparison of the number of gates (“#gates”) implied in the network obtained after ABC mapping between the simulated annealing algorithm based on the node-aware cost function proposed in the present invention and the best previous work.

[0030] The results on a set of MCNC test sets are shown in Table 1. The number of implication gate nodes in the mapping network is reduced by 22% on average.

[0031] Table 1

[0032] The proposed method for implied logic synthesis and optimization based on memristor circuits first applies the cut-rewrite optimization to the network, and then uses a heuristic algorithm based on logic reconstruction to solve the fan-out problem. To prove its scalability and independently evaluate its performance, the results on a set of ISCAS'85 test sets obtained by direct mapping without ABC optimization are shown in Table 2 ("#Gates" indicates the number of implied gates in the network obtained after ABC mapping). The method of the present invention achieves an average reduction of nearly 4% in operation pulses and an average reduction of 7% in the number of memristors.

[0033] Table 2

[0034] Tables 1 and 2 above independently evaluate the performance of the present invention in creating the initial implied logic network using the simulated annealing algorithm, as well as the performance of the implied logic network optimization. In order to evaluate the performance of the overall logic synthesis framework, the results on a set of MCNC test sets are shown in Table 3. The results show that compared with the best work, the present invention method reduces the number of operation pulses by 21% and the number of memristors by 22% on average.

[0035] Table 3

[0036] In summary, the implicit logic synthesis and optimization method based on memristor circuit proposed in the present invention not only reduces the number of memristors, but also reduces the number of operation pulses of the logic function synthesized on the memristor circuit. The implicit logic synthesis and optimization method based on memristor circuit proposed in the present invention improves the current related work methods, can reduce the cost of memristor circuit design, and enriches the research methods of implicit logic in logic synthesis.

Claims

1. A method for implied logic synthesis and optimization based on memristor circuits, characterized in that: The following steps are involved: S1. Use the open source logic synthesis tool ABC and the simulated annealing algorithm based on the node-aware cost function to obtain the gate-level netlist used to represent the Boolean function, and convert the circuit topology connection relationship in the gate-level netlist into a directed acyclic graph IMG; S2. Calculate the optimal implication-inverter graph IIG of all four-input NPN Boolean functions using the exact synthesis algorithm based on Boolean satisfiability SAT and NPN equivalence classification, use the directed acyclic graph IMG to logically represent the inverters in the optimal implication-inverter graph IIG, establish an IMG offline database, and convert the input circuit into an IMG structure through the logic rewriting algorithm and the IMG offline database; S3. A heuristic algorithm based on logic reconstruction is used to solve all structures with fan-out problems in the IMG structure, and an implied network with no fan-out problem and a reduced number of memristors and pulses is obtained.

2. The method for implied logic synthesis and optimization based on memristor circuit according to claim 1, characterized in that: The specific process of step S1 is: S1.

1. Use the open source logic synthesis tool ABC to read the Boolean function described in blif or pla format and the process library in genlib format containing IMP, INV, ZERO, ONE, and BUF gates, where IMP represents a two-input implication gate, INV represents an inverter whose second input is 0 represented by IMP, ZERO represents a constant gate zero, ONE represents a constant gate one, and BUF represents a buffer; The optimization operators rewrite, rewrite -z, refactor, refactor -z, resub, resub -z, balance and dc2 are selected and applied iteratively. The simulated annealing algorithm is used to iteratively reshape and reduce the AIG representation of the Boolean function. The node-aware cost function C is introduced to predict the total number of nodes in the Boolean function after solving the fan-out problem, so as to evaluate and determine the operator sequence with the minimum cost. The AIG representation of the Boolean function is logically optimized through the operator sequence with the minimum cost. The node-aware cost function C is defined as: ； In formula (1), N represents the Boolean function, n represents the number of original nodes in the Boolean function, S i represents the fan-out cost of the i-th node in the original node; S1.2, use the process mapping command map in ABC, use the input process library, process map the AIG representation of the Boolean function after logic optimization, and obtain the gate-level netlist in Verilog format; S1.

3. The circuit topology connection relationship in the gate-level netlist is converted into a directed acyclic graph IMG through a netlist parser, wherein the nodes in IMG include two types: IMP and INV represented by IMP, and the edges in IMG represent the connection relationship between logic gates.

3. The method for implied logic synthesis and optimization based on memristor circuit according to claim 1, characterized in that: The specific process of step S2 is: S2.

1. Define four Boolean variables: x it , g hi , S ijk , P ci ,in: x it Indicates the circuit i Logic Gates x i In the truth table of the logic function t The value of the bit; g hi Represents a logic gate x i Is the output of the circuit the original output? If the logic gate x i The output of the circuit is h Raw output g hi , then the Boolean variable g hi The value is true, otherwise it is false; S ijk Represents a logic gate x i The two input x j , x k The connection relationship between the two inputs and whether the two inputs perform implicit logic. If the logic gate x i The two input x j and x k If the implied logic is executed, the Boolean variable S ijk The value is true, otherwise it is false, where j , k The value range is: 1≤ j < i , 1≤ k < i , j ≠ k ; P ci Represents a logic gate x i The two input x j , x k The polarity of P ci The value range is: 0≤ P ci ≤1, where c =1,2; S2.

2. The logic circuit consisting of implied logic and negation logic is used as the logic function. In addition to the original input and original output, each logic gate performs the implied logic operation. The negation logic is represented by the dotted line connecting the edges in the circuit. The main constraints in the implied logic are: ； In formula (2), the symbol " "Represents the essence of the logical operation, symbol" " indicates strict equivalence; Formula (2) indicates that if the logic gate x i The two inputs are x j , x k ,and x j , x k Perform the implied logic operation, i.e. , then the logic gate x i The value of x it Expressed as ; Applying the Tseytin transformation method, the implied logic gates in the circuit are converted into the description form of the CNF formula, and the CNF paradigm of the implied logic gates is obtained: ； in" ” represents the AND gate; use , where the symbol " " represents logical OR, and the constraints of CNF paradigm are obtained, which can be further simplified to: ； For the logical expression contained in formula (4) , define a Boolean variable , then formula (4) becomes: ； Using Tseytin transformation method, the logical expression Converted into CNF form, we get: ； In summary, the main CNF constraint formulas of implication logic are summarized as follows: ； In addition, if the logic gate x i is the original output of the circuit, then x i The logic function truth table must be equal to the original output of the circuit g h So we add the constraint: ； in yes t The binary encoding of " ” stands for logical exclusive OR; To ensure the original output of the circuit g h Must be a logic gate x i Output of , adding constraints: ； To ensure that each logic gate in the circuit has two legal inputs, add the constraints: ； S2.

3. Based on the constraints obtained above, the number of implied logic gates required is first set to 0, and a CNF constraint file is obtained by encoding. The obtained CNF constraint file is then transmitted to a Boolean satisfiability solver, i.e., a SAT solver. The SAT solver assigns values ​​to the Boolean variables in the received CNF constraint file, and searches for a set of Boolean variable assignments whose values ​​satisfy equations (7) to (10) and are all true. If the SAT solver finds such a set of Boolean variable assignments, the result returned is SAT, indicating that the optimal solution has been found; otherwise, the required number of implied logic gates is increased by 1, and the code and solution are re-performed until the result returned by the SAT solver is SAT and the result representing the optimal solution is returned; S2.4, according to the result representing the optimal solution returned by the SAT solver, the optimal implication-inverter graph IIG of all four-input NPN Boolean functions is calculated by using NPN equivalence classification, and the inverters in the optimal implication-inverter graph IIG are represented by using the directed acyclic graph IMG logic to establish an IMG offline database; S2.5, for the directed acyclic graph IMG of the input circuit, first use the cut enumeration algorithm to find the four-input cuts for each node of IMG; S2.6, apply NPN equivalent classification to normalize each cut and obtain the Boolean function of the cut; S2.7, match the IMG offline database established in step S2.4 with the Boolean function of the cut; if the Boolean expression in the IMG offline database is better than the four-input cut of IMG, then replace it, that is, obtain the optimized IMG structure through the logic rewriting algorithm.

4. The method for implied logic synthesis and optimization based on memristor circuit according to claim 1, characterized in that: The specific process of step S3 is: S3.

1. First, define different structural types of fan-out problems, and determine the structures without fan-out problems after logical reconstruction that match the structural types of different fan-out problems. S3.2, for the IMG structure obtained in step S2, first traverse the nodes in the IMG structure in topological order, and then for each node, determine whether the IMG structure has a structure with a fan-out problem through the connection relationship between the node and the nodes of the next level. If there is a structure with a fan-out problem, determine the structure type of the fan-out problem and perform logical reconstruction, that is, replace the structure with a fan-out problem with a structure without a fan-out problem after logical reconstruction that matches the structure type of the fan-out problem; S3.

3. Repeat step S3.2 to solve all structures with fan-out problems in the IMG structure, and obtain an implied network with no fan-out problem and a reduced number of memristors and pulses.

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