Configuration method and providing method of IO IP core with adjustable output current capability and electrostatic discharge protection grade, device and chip

Abstract

The invention relates to the technical field of chip IP cores and EDA, in particular to a configuration method and providing method of an IOIP core with adjustable output current capacity and electrostatic discharge protection level, a device and a chip. An existing IO IP core is generally an integral module, can only provide output current capacity and electrostatic discharge protection capacity of limited gears, and cannot be conveniently changed according to chip requirements. A special EDA tool is researched and developed, meanwhile, the circuit module and the layout of the IO IP core are subjected to customized design, and the configurable IO IP core comprising the IO core circuit module and the output current and electrostatic discharge protection level adjustable module is reconstructed, so that user requirements are obtained by customizing the EDA tool, and the modules in the configurable IO core are configured; and flexible configuration is realized.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip IP core and EDA (Electronic Design Automation), and in particular to a configuration method and providing method, device and chip of an IO IP core with adjustable output current capability and electrostatic discharge protection level. Background Art

[0002] As the chip size is reduced and the circuit complexity increases, the input / output (I / O) unit is no longer limited to simple signal receiving and sending functions. In order to meet the requirements of high speed and high current driving, it is also required to have stronger output driving capability.

[0003] However, the output drive currents of the IO IP cores provided by most of the existing mainstream process factories are also limited to a few values. For example, Huahong HHGRACE only provides three output drive currents, such as 4mA, 8mA, and 16mA; TSMC mainly provides four output drive currents, such as 2mA, 4mA, 8mA, and 12mA; SMIC mainly provides six output drive currents, such as 2mA, 4mA, 8mA, 12mA, 16mA, and 24mA. However, in actual industrial chip design, the output drive currents of the IO IP cores required are also different. Some only require uA-level output current capabilities, such as 100uA, 500uA, etc., while others require output current capabilities greater than 24mA.

[0004] At the same time, most chips need to operate stably 24 / 7 in high / low temperature, high humidity, strong electromagnetic and other environments, and their lifespan needs to reach more than 15 years. This poses a huge challenge to the reliability of chip pins that are susceptible to environmental interference, and the ESD (Electro-Static discharge) protection capability of the chip's I / O pins is an important indicator of its resistance to external environmental interference. Most of the IO IP cores provided by mainstream process factories can only resist 2kV electrostatic discharge. However, many chips such as power drivers need to resist 4kV and 5kV electrostatic discharge, and some interface chips even need to resist electrostatic discharge of more than 10kV.

[0005] In summary, the IO IP cores provided by most of the current mainstream process factories can only have fixed ESD protection capabilities and a limited number of output current capabilities. As a result, the output current capability and ESD protection capabilities provided by the IO IP cores currently provided by the process factories cannot meet the chip design requirements for key industrial application scenarios such as electromagnetic heat, electricity, rail transportation, and automobiles. Summary of the invention

[0006] In order to solve the problems in the related art, the embodiments of the present disclosure provide a configuration method of an IO IP core with adjustable output current capability and electrostatic discharge protection level, and a providing method, device and chip.

[0007] In a first aspect, an embodiment of the present disclosure provides a method for configuring an IO IP core with adjustable output current capability and electrostatic discharge protection level, the method being implemented based on a customized EDA tool, and the method comprising:

[0008] Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO basic circuit module, an output current and an electrostatic discharge protection level adjustable module, the IO basic circuit module includes an IO core circuit module, and the output current and electrostatic discharge protection level adjustable module includes a PMOS module group and an NMOS module group;

[0009] Get the high-level output source current, low-level output sink current, and electrostatic discharge protection level of the specified pin module input by the user for the customized IO IP core;

[0010] According to the high-level output pull current, the low-level output sink current and the electrostatic discharge protection level, the output current and electrostatic discharge protection level adjustable module is configured, including: determining a first number of PMOS modules from the PMOS module group according to the high-level output pull current, determining a second number of NMOS modules from the NMOS module group according to the low-level output sink current, determining a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic discharge protection level, selecting the maximum value of the first number and the third number as the number of selected PMOS modules, selecting the maximum value of the second number and the third number as the number of selected NMOS modules, connecting the selected PMOS module and the selected NMOS module, and generating a configured output current and electrostatic discharge protection level adjustable module, wherein the configured output current and electrostatic discharge protection level adjustable module is used to provide a specified electrostatic discharge protection capability corresponding to the electrostatic discharge protection level and provide a specified output current capability under the control of the control signal of the IO core circuit module;

[0011] Connecting the IO core circuit module and the configured output current and electrostatic release protection level adjustable module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: a power supply voltage port, a ground port, an IO signal input port, and a control signal output port, and the configured output current and electrostatic release protection level adjustable module includes: a power supply voltage port, a ground port, and a control signal input port;

[0012] The power supply voltage ports of the IO core circuit module and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the grounding ports are all grounded;

[0013] The control signal output port of the IO core circuit module is connected to the control signal input port of the configured output current and electrostatic discharge protection level adjustable module, and is used to output the control signal to the configured output current and electrostatic discharge protection level adjustable module based on the IO input signal obtained from the IO signal input port;

[0014] The control signal input port of the configured output current and electrostatic discharge protection level adjustable module is connected to the first number of PMOS modules and the second number of NMOS modules.

[0015] According to an embodiment of the present disclosure, it includes:

[0016] Based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

[0017] According to an embodiment of the present disclosure, it also includes:

[0018] A bottom module is obtained, and the bottom of the designated pin module of the customized IO IP core is sealed by using the bottom module to generate a designated pin module with a sealed bottom.

[0019] According to an embodiment of the present disclosure, it also includes:

[0020] Based on the bottom-enclosed designated pin module, a second designated pin circuit layout of the customized IO IP core is generated.

[0021] According to an embodiment of the present disclosure, it also includes:

[0022] Acquire at least one filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module being connected to a power supply voltage, and the ground port of the filling module being grounded;

[0023] Generate multiple pin modules of the customized IO IP core;

[0024] Splicing the plurality of pin modules to obtain a spliced ​​pin module;

[0025] The at least one filling module is used to fill the empty space in the splicing tube foot module to obtain a filled splicing tube foot module.

[0026] According to an embodiment of the present disclosure, it also includes:

[0027] Based on the filled spliced ​​pin module, a multi-pin circuit layout of the customized IO IP core is generated.

[0028] According to an embodiment of the present disclosure, the configured output current and electrostatic release protection level adjustable module includes a plurality of unit output current and electrostatic release protection level adjustable modules, the unit output current and electrostatic release protection level adjustable module includes a plurality of PMOS modules and a plurality of NMOS modules, and the PMOS modules and NMOS modules included in the plurality of unit output current and electrostatic release protection level adjustable modules respectively constitute the PMOS module group and the NMOS module group;

[0029] The unit output current and electrostatic release protection level adjustable module includes a power supply voltage port, a ground port and a control signal input port. The power supply voltage port of the unit output current adjustable module is connected to the power supply voltage, and the ground port of the unit output current adjustable module is grounded.

[0030] According to an embodiment of the present disclosure, in the unit output current and electrostatic discharge protection level adjustable module:

[0031] All PMOS modules and all NMOS modules are connected to the control signal input port of the unit output current and electrostatic discharge protection level adjustable module, and all connected PMOS modules and all NMOS modules provide unit electrostatic discharge protection capability and unit output current capability at the same time;

[0032] Alternatively, some PMOS modules and / or some NMOS modules are connected to the control signal input port of the unit output current and electrostatic release protection level adjustable module, and some of the connected PMOS modules and / or some of the NMOS modules simultaneously provide partial unit electrostatic release protection capability and partial unit output current capability, and the remaining PMOS modules and / or the remaining NMOS modules simultaneously provide the remaining unit electrostatic release protection capability;

[0033] Alternatively, all PMOS modules and all NMOS modules are disconnected from the control signal input port of the unit output current and electrostatic discharge protection level adjustable module, and all disconnected PMOS modules and all NMOS modules provide unit electrostatic discharge protection capability at the same time.

[0034] According to an embodiment of the present disclosure, when the part of the PMOS modules and / or the part of the NMOS modules are connected to the control signal input port of the unit output current and electrostatic discharge protection level adjustable module, in the remaining PMOS modules and / or the remaining NMOS modules of the unit output current and electrostatic discharge protection level adjustable module: the gates of a part of the PMOS modules and the NMOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of the other part of the PMOS modules and the NMOS modules are grounded through the ground port;

[0035] When all the PMOS modules and all the NMOS modules are disconnected from the control signal input port of the unit output current and electrostatic release protection level adjustable module, among all the PMOS modules and all the NMOS modules of the unit output current and electrostatic release protection level adjustable module: the gates of some of the PMOS modules and NMOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other parts of the PMOS modules and NMOS modules are grounded through the ground port.

[0036] According to an embodiment of the present disclosure, the gates of a part of the PMOS modules and the NMOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of another part of the PMOS modules and the NMOS modules are grounded through the ground port, including:

[0037] The gates and sources of a part of the PMOS modules and the NMOS modules are short-circuited and then connected to the power supply voltage through the power supply voltage port, and the gates and sources of another part of the PMOS modules and the NMOS modules are short-circuited and then grounded through the ground port.

[0038] According to an embodiment of the present disclosure, when the part of the PMOS modules and / or the part of the NMOS modules are connected to the control signal input port of the unit output current and electrostatic discharge protection level adjustable module, in the remaining PMOS modules and / or the remaining NMOS modules of the unit output current and electrostatic discharge protection level adjustable module: the gates of a part of the PMOS modules and the NMOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of the other part of the PMOS modules and the NMOS modules are grounded through the resistance module and the grounding port;

[0039] When all the PMOS modules and all the NMOS modules are disconnected from the control signal input port of the unit output current and electrostatic release protection level adjustable module, among all the PMOS modules and all the NMOS modules of the unit output current and electrostatic release protection level adjustable module: the gates of some PMOS modules and NMOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other part of the PMOS modules and NMOS modules are grounded through the resistance module and the grounding port.

[0040] According to an embodiment of the present disclosure, the customized EDA tool provides a graphical user interface GUI, and the GUI interface includes a plurality of customized input boxes;

[0041] The multiple customized input boxes include: an expected high-level output source current input box, an expected low-level output sink current input box, and an expected electrostatic release protection level input box, so as to obtain the high-level output source current, low-level output sink current, and electrostatic release protection level input by the user for the specified pin module of the customized IO IP core.

[0042] According to an embodiment of the present disclosure, when a corresponding plurality of module layouts are generated based on the IO core circuit module, the configured output current, and the electrostatic discharge protection level adjustable module, the widths of the plurality of module layouts are consistent.

[0043] In a second aspect, the present disclosure provides a method for providing a configurable IO IP core, comprising:

[0044] Providing an IO core circuit module, the IO core circuit module comprising a power supply voltage port, a ground port, an IO signal input port and a control signal output port, for processing an IO input signal obtained from the IO signal input port and outputting a control signal;

[0045] A module with adjustable output current and electrostatic discharge protection level is provided, wherein the module includes a PMOS module group, an NMOS module group, a power supply voltage port, a ground port and a control signal input port, wherein a customized EDA tool determines a first number of PMOS modules from the PMOS module group according to a high-level output pull current, determines a second number of NMOS modules from the NMOS module group according to a low-level output sink current, determines a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic discharge protection level, selects a maximum value between the first number and the third number as the number of selected PMOS modules, selects a maximum value between the second number and the third number as the number of selected NMOS modules, and connects the selected PMOS module and the selected NMOS module.

[0046] According to an embodiment of the present disclosure, it also includes: providing at least one filling module, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules, and the filling module includes: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded.

[0047] According to an embodiment of the present disclosure, it also includes:

[0048] At least one bottom module is provided, and the bottom module is used to seal the bottom of the one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

[0049] In a third aspect, the present disclosure provides a configuration device for an IO IP core with adjustable output current capability and electrostatic discharge protection level, the device being implemented based on a customized EDA tool, comprising:

[0050] A first acquisition module is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO basic circuit module, an output current and an electrostatic discharge protection level adjustable module, the IO basic circuit module includes an IO core circuit module, and the output current and electrostatic discharge protection level adjustable module includes a PMOS module group and an NMOS module group;

[0051] The second acquisition module is configured to obtain the high-level output source current, low-level output sink current, and electrostatic discharge protection level input by the user for the specified pin module of the customized IO IP core;

[0052] The current and electrostatic discharge protection configuration module is configured to configure the output current and electrostatic discharge protection level adjustable module according to the high-level output pull current, the low-level output sink current and the electrostatic discharge protection level, including: determining a first number of PMOS modules from the PMOS module group according to the high-level output pull current, determining a second number of NMOS modules from the NMOS module group according to the low-level output sink current, determining a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic discharge protection level, selecting the maximum value of the first number and the third number as the number of selected PMOS modules, selecting the maximum value of the second number and the third number as the number of selected NMOS modules, connecting the selected PMOS module and the selected NMOS module, and generating a configured output current and electrostatic discharge protection level adjustable module, wherein the configured output current and electrostatic discharge protection level adjustable module is used to provide a specified electrostatic discharge protection capability corresponding to the electrostatic discharge protection level and provide a specified output current capability under the control of the control signal of the IO core circuit module;

[0053] A first generating module is configured to connect the IO core circuit module and the configured output current and electrostatic release protection level adjustable module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: a power supply voltage port, a ground port, an IO signal input port, and a control signal output port, and the configured output current and electrostatic release protection level adjustable module includes: a power supply voltage port, a ground port, and a control signal input port;

[0054] The power supply voltage ports of the IO core circuit module and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the grounding ports are all grounded;

[0055] The control signal output port of the IO core circuit module is connected to the control signal input port of the configured output current and electrostatic discharge protection level adjustable module, and is used to output the control signal to the configured output current and electrostatic discharge protection level adjustable module based on the IO input signal obtained from the IO signal input port;

[0056] The control signal input port of the configured output current and electrostatic discharge protection level adjustable module is connected to the first number of PMOS modules and the second number of NMOS modules.

[0057] According to an embodiment of the present disclosure, a third acquisition module is further included, which is configured to acquire a bottom module, wherein the bottom module is used to close the bottom of the designated pin module of the custom IO IP core to generate a designated pin module with a closed bottom.

[0058] According to an embodiment of the present disclosure, a second generation module is further included, which is configured to generate a second designated pin circuit layout of the customized IO IP core based on the bottom-enclosed designated pin module.

[0059] According to an embodiment of the present disclosure, a fourth acquisition module is also included, which is configured to acquire at least one filling module, wherein the filling module includes: a power supply voltage port and a ground port, wherein the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; the filling module is used to fill the vacancies in the splicing pin module of the custom IO IP core to obtain the filled splicing pin module, wherein the splicing pin module is obtained by splicing multiple pin modules of the custom IOIP core.

[0060] According to an embodiment of the present disclosure, a third generation module is further included, which is configured to generate a multi-pin circuit layout of the customized IO IP core based on the filled splicing pin module.

[0061] In a fourth aspect, the present disclosure provides an apparatus for providing a configurable IO IP core, comprising:

[0062] A first providing module is configured to provide an IO core circuit module, wherein the IO core circuit module includes a power supply voltage port, a ground port, an IO signal input port, and a control signal output port, and is used to process an IO input signal obtained from the IO signal input port and output a control signal;

[0063] The second providing module is configured to provide an output current and electrostatic discharge protection level adjustable module, wherein the output current and electrostatic discharge protection level adjustable module includes a PMOS module group, an NMOS module group, a power supply voltage port, a ground port and a control signal input port, the customized EDA tool determines a first number of PMOS modules from the PMOS module group according to a high-level output pull current, determines a second number of NMOS modules from the NMOS module group according to a low-level output sink current, determines a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic discharge protection level, selects the maximum value of the first number and the third number as the number of the selected PMOS modules, selects the maximum value of the second number and the third number as the number of the selected NMOS modules, and connects the selected PMOS module and the selected NMOS module.

[0064] According to an embodiment of the present disclosure, it also includes:

[0065] A third providing module is configured to provide at least one filling module, which is used to fill the empty positions in the spliced ​​pin module of the customized IO IP core when generating multiple pin modules of the customized IO IP core based on the provided configurable IOIP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules, and the filling module includes: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded.

[0066] According to an embodiment of the present disclosure, it also includes:

[0067] The fourth providing module is configured to provide at least one bottom module, wherein the bottom module is used to seal the bottom of one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

[0068] In a fifth aspect, an embodiment of the present disclosure provides a chip, comprising: a custom IO IP core manufactured using the method generated according to any one of the methods described in the first aspect, or a custom IO IP core manufactured using the configurable IO IP core provided by the method described in the second aspect.

[0069] In a sixth aspect, an embodiment of the present disclosure provides an electronic device, comprising the chip as described in the fifth aspect.

[0070] In a seventh aspect, an embodiment of the present disclosure provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the method as described in any one of the first aspect or the second aspect.

[0071] In an eighth aspect, an embodiment of the present disclosure provides a computer program product, comprising computer instructions, which, when executed by a processor, implement the method as described in any one of the first aspect or the second aspect.

[0072] According to the technical solution provided by the embodiment of the present disclosure, user requirements (high-level output pull current, low-level output sink current, and electrostatic discharge protection level for the designated pin module input of the customized IOIP core) are obtained through a customized EDA tool, and a configurable IO IP core including an IO core circuit module and an output current and electrostatic discharge protection level adjustable module is configured, a first number of PMOS modules are determined from a PMOS module group according to the high-level output pull current, a second number of NMOS modules are determined from an NMOS module group according to the low-level output sink current, a third number of PMOS modules and a third number of NMOS modules are determined from the PMOS module group and the NMOS module group respectively according to the electrostatic discharge protection level, a maximum value between the first number and the third number is selected as the number of the selected PMOS modules, a maximum value between the second number and the third number is selected as the number of the selected NMOS modules, the selected PMOS module and the selected NMOS module are connected, and a configured output current and electrostatic discharge protection level adjustable module is generated; the IO core circuit module and the configured output current and electrostatic discharge protection level adjustable module are connected to generate the designated pin module of the customized IO IP core.

[0073] The present invention discloses the development of a special customized EDA tool, and at the same time customizes the circuit module and layout of the IO IP core, and reconstructs it into a configurable IOIP core including an IO core circuit module and an output current and electrostatic release protection level adjustable module, which can be adjusted according to the design needs of the actual chip, so that the output current and electrostatic release protection level adjustable module can be used to simultaneously realize the flexible configuration of the output current capability and the electrostatic release protection capability, so that the customized IO IP core generated by the customized EDA tool and the configurable IO IP core can meet the design requirements of complex industrial chips such as different output current capabilities and electrostatic release protection capabilities.

[0074] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0076] Figure 1 A flow chart showing a configuration method of an IOIP core with adjustable output current capability and electrostatic discharge protection level according to an embodiment of the present disclosure;

[0077] Figure 2 A schematic diagram showing an IO basic circuit module according to an embodiment of the present disclosure is shown;

[0078] Figure 3 A schematic diagram showing a unit output current and electrostatic discharge protection level adjustable module according to an embodiment of the present disclosure;

[0079] Figure 4 A schematic diagram showing another unit output current and electrostatic discharge protection level adjustable module according to an embodiment of the present disclosure;

[0080] Figure 5 A schematic diagram showing another module with adjustable unit output current and electrostatic discharge protection level according to an embodiment of the present disclosure

[0081] Figure 6 A schematic diagram showing a configuration method of an IO IP core according to an embodiment of the present disclosure, connecting an IO core circuit module, a configured output current, and an electrostatic discharge protection level adjustable module;

[0082] Figure 7 A schematic diagram showing splicing of pin modules in a configuration method of an IO IP core according to an embodiment of the present disclosure is shown;

[0083] Figure 8A flowchart showing a method for providing a configurable IO IP core according to an embodiment of the present disclosure is shown;

[0084] Fig. 9 A schematic diagram showing a configuration device of an IO IP core according to an embodiment of the present disclosure;

[0085] Fig.10 A schematic diagram showing an apparatus for providing a configurable IO IP core according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0086] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0087] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0088] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0089] In the present disclosure, if it involves operations of obtaining user information or user data or displaying user information or user data to others, the operations are all authorized and confirmed by the user, or actively selected by the user.

[0090] As mentioned above, the output current capabilities (high-level output pull current IOH and low-level output sink current IOL) of the IO IP cores provided by most of the existing mainstream process plants or IP manufacturers are mostly limited in number, and can only provide a fixed electrostatic discharge protection capability (for example, it can only resist 2kV of electrostatic discharge). As a result, the output current capability and electrostatic discharge protection capability provided by the IO IP cores manufactured by current process plants or IP manufacturers cannot meet the design requirements of chip designs in complex industrial application scenarios such as electromagnetic heating, industrial control, and aerospace.

[0091] After research, the inventors found that the reason why the existing IO IP core can only provide fixed electrostatic discharge protection capability and a limited number of output current capabilities is that the IO IP core is designed as an integral module, integrating multiple functions such as signal reception and transmission and providing output drive current and electrostatic discharge protection capabilities. As an integral module, the IO IP core cannot be easily changed according to chip requirements, resulting in the IO IP core being able to provide only a limited number of output current capabilities and fixed electrostatic discharge protection capabilities, which brings a lot of inconvenience to chip design in complex industrial application scenarios and increases the difficulty of chip design.

[0092] The present disclosure provides a configuration method for an IO IP core with adjustable output current capability and electrostatic release protection level. The method is implemented based on a customized EDA tool. The method includes: obtaining a configurable IO IP core, wherein the configurable IO IP core includes an IO basic circuit module, an output current and an electrostatic release protection level adjustable module, wherein the IO basic circuit module includes an IO core circuit module, and the output current and an electrostatic release protection level adjustable module includes a PMOS module group and an NMOS module group; obtaining a high-level output pull current, a low-level output sink current, and an electrostatic release protection level input by a user for a specified pin module of the customized IO IP core; configuring the output current and an electrostatic release protection level adjustable module according to the high-level output pull current, the low-level output sink current, and the electrostatic release protection level, including: determining a first number of PMOS modules from the PMOS module group according to the high-level output pull current, determining a second number of NMOS modules from the NMOS module group according to the low-level output sink current, determining a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group according to the electrostatic release protection level, selecting the first number of PMOS modules and the third number of NMOS modules from the PMOS module group and the NMOS module group, respectively, and selecting the first number of PMOS modules and the third number of NMOS modules from the PMOS module group and the NMOS module group, respectively. The maximum value of the second quantity and the third quantity is used as the number of the selected PMOS modules, the maximum value of the second quantity and the third quantity is selected as the number of the selected NMOS modules, the selected PMOS module and the selected NMOS module are connected to generate a configured output current and electrostatic discharge protection level adjustable module, the configured output current and electrostatic discharge protection level adjustable module is used to provide a specified electrostatic discharge protection capability corresponding to the electrostatic discharge protection level and provide a specified output current capability under the control of the control signal of the IO core circuit module; the IO core circuit module and the configured output current and electrostatic discharge protection level adjustable module are connected to generate a specified pin module of the customized IO IP core.

[0093] Among them, the IO core circuit module includes: a power supply voltage port, a ground port, an IO signal input port, and a control signal output port, and the configured output current and electrostatic release protection level adjustable module includes: a power supply voltage port, a ground port and a control signal input port; the power supply voltage ports of the IO core circuit module and the configured output current and electrostatic release protection level adjustable module are both connected to the power supply voltage, and the ground ports are both grounded; the control signal output port of the IO core circuit module is connected to the control signal input port of the configured output current and electrostatic release protection level adjustable module, and is used to output the control signal to the configured output current and electrostatic release protection level adjustable module based on the IO input signal obtained from the IO signal input port; the control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to the first number of PMOS modules and the second number of NMOS modules.

[0094] The present disclosure splits the existing overall module into an IO core circuit module and an output current and electrostatic discharge protection level adjustable module to obtain a configurable IO IP core. At the same time, since the existing EDA tools are all configured for the IO IP core as a whole module, it is impossible to use the existing EDA tools to configure the configurable IO IP core of the module obtained after the splitting. Therefore, the present disclosure develops a special EDA tool, and at the same time customizes the circuit module and layout of the IO IP core to reconstruct it into a configurable IO IP core including the IO core circuit module and the output current and electrostatic discharge protection level adjustable module, so that the configurable IO IP core is configured by using the customized EDA tool, and the output current capability and electrostatic discharge protection level requirements input from the customized EDA tool are adjusted according to the needs of the actual chip, so as to realize flexible configuration of the output current capability and electrostatic discharge protection capability, so that the customized IO IP core generated by using the customized EDA tool and the configurable IO IP core can meet the design requirements of complex industrial chips with different output current capabilities and electrostatic discharge protection levels.

[0095] Figure 1 A flow chart showing a configuration method of an IOIP core with adjustable output current capability and electrostatic discharge protection level according to an embodiment of the present disclosure is shown. The method is implemented based on a custom EDA tool, such as Figure 1 As shown, the method includes the following steps S101 to S104:

[0096] In the present disclosure, since the configurable IO IP core is obtained by splitting and reconstructing the existing IO IP core, it cannot be directly configured using the existing EDA tools. Therefore, it is necessary to customize the EDA tools so as to configure the configurable IO IP core using the customized EDA tools.

[0097] In the step S101, a configurable IO IP core is obtained, wherein the configurable IO IP core includes an IO basic circuit module, an output current and an electrostatic discharge protection level adjustable module, the IO basic circuit module includes an IO core circuit module, and the output current and electrostatic discharge protection level adjustable module includes a PMOS module group and an NMOS module group.

[0098] In step S102, the high-level output source current, low-level output sink current, and electrostatic discharge protection level input by the user for the designated pin module of the customized IO IP core are obtained.

[0099] According to an embodiment of the present disclosure, the designated pin module of the customized IO IP core is any pin module to be generated in the customized IO IP core; the high-level output source current, low-level output sink current, and electrostatic release protection level input by the user are the output current capability and electrostatic release protection capability that the designated pin module of the customized IO IP core is expected to be able to achieve.

[0100] According to an embodiment of the present disclosure, the customized EDA tool provides a GUI (graphical user interface), and the GUI interface includes multiple customized input boxes; the multiple customized input boxes include: an expected high-level output source current input box, an expected low-level output sink current input box, and an expected electrostatic release protection level input box, so as to obtain the high-level output source current, low-level output sink current, and electrostatic release protection level input by the user for the specified pin module of the customized IO IP core.

[0101] Specifically, three input boxes are provided on the GUI interface of the customized EDA tool, namely: an "expected high-level output source current IOH" input box, an "expected low-level output sink current IOL" input box, and an "expected electrostatic discharge protection level" input box. The user inputs the output current capability expected to be achieved for the specified pin module of the customized IO IP core and the electrostatic discharge protection capability corresponding to the expected electrostatic discharge protection level from the three input boxes.

[0102] In the present disclosure, the IO IP core is no longer an integral module, but a configurable IO IP core including multiple functional modules such as an IO core circuit module, an output current and an electrostatic discharge protection level adjustable module, etc. Different functional modules implement corresponding functions, and the output current and the electrostatic discharge protection level adjustable module are further refined into a PMOS module group and an NMOS module group, so that the customized EDA tool can perform more customizable and more refined configurations on the output current capability and electrostatic discharge protection capability of the configurable IO IP core.

[0103] Figure 2 A schematic diagram of an IO basic circuit module according to an embodiment of the present disclosure is shown.

[0104] like Figure 2 As shown, the IO basic circuit module includes an IO core circuit module, and the IO core circuit module includes: a power supply voltage port, a ground port, an IO signal input port, and a control signal output port. The power supply voltage port of the IO core circuit module is connected to the power supply voltage to provide the IO core circuit module with an operating voltage, and the ground port of the IO core circuit module is grounded.

[0105] In step S103, the output current and electrostatic release protection level adjustable module is configured according to the high-level output pull current, the low-level output sink current and the electrostatic release protection level, including: determining a first number of PMOS modules from the PMOS module group according to the high-level output pull current, determining a second number of NMOS modules from the NMOS module group according to the low-level output sink current, determining a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic release protection level, selecting the maximum value of the first number and the third number as the number of selected PMOS modules, selecting the maximum value of the second number and the third number as the number of selected NMOS modules, connecting the selected PMOS module and the selected NMOS module, and generating a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level and provide a specified output current capability under the control of the control signal of the IO core circuit module.

[0106] According to an embodiment of the present disclosure, the configured output current and electrostatic discharge protection level adjustable module includes: a power supply voltage port, a ground port and a control signal input port.

[0107] According to an embodiment of the present disclosure, the power supply voltage port of the configured output current and electrostatic release protection level adjustable module is connected to the power supply voltage, which is used to provide working voltage for the configured output current and electrostatic release protection level adjustable module, and the ground port of the configured output current and electrostatic release protection level adjustable module is grounded.

[0108] In step S104, the IO core circuit module and the configured output current and electrostatic discharge protection level adjustable module are connected to generate a designated pin module of the customized IO IP core.

[0109] Among them, the control signal output port of the IO core circuit module is connected to the control signal input port of the configured output current and electrostatic release protection level adjustable module, and is used to output the control signal to the configured output current and electrostatic release protection level adjustable module based on the IO input signal obtained from the IO signal input port.

[0110] The control signal input port of the configured output current and electrostatic discharge protection level adjustable module is connected to the first number of PMOS modules and the second number of NMOS modules.

[0111] According to an embodiment of the present disclosure, the configured output current and electrostatic release protection level adjustable module includes multiple unit output current and electrostatic release protection level adjustable modules, and the unit output current and electrostatic release protection level adjustable module includes multiple PMOS modules and multiple NMOS modules. The PMOS modules and NMOS modules included in the multiple unit output current and electrostatic release protection level adjustable modules constitute the PMOS module group and the NMOS module group respectively.

[0112] Among them, the unit output current and electrostatic release protection level adjustable module includes a power supply voltage port, a ground port and a control signal input port. The power supply voltage port of the unit output current adjustable module is connected to the power supply voltage, and the ground port of the unit output current adjustable module is grounded.

[0113] Among them, each PMOS module or NMOS module corresponds to a PMOS tube or an NMOS tube when the customized IO IP core is implemented as an integrated circuit or a chip, that is, at this time, each unit output current and electrostatic release protection level adjustable module includes multiple PMOS tubes and multiple NMOS tubes.

[0114] In the present disclosure, since the configured output current and electrostatic release protection level adjustable module is further divided into multiple unit output current and electrostatic release protection level adjustable modules, when the desired high-level output source current IOH, the low-level output sink current IOL, and the electrostatic release protection level are input through the GUI interface of the customized EDA tool, one or more unit output current and electrostatic release protection level adjustable modules can be directly selected to provide the desired output current capability and electrostatic release protection capability, further simplifying the complexity of the configuration operation.

[0115] Specifically, the electrostatic release protection capability is divided into levels based on the unit electrostatic release protection capability. For example, assuming that the unit electrostatic release protection capability is 1kV, the electrostatic release protection capability corresponding to the first-level electrostatic release protection level is 1kV, the electrostatic release protection capability corresponding to the second-level electrostatic release protection level is 2kV, the electrostatic release protection capability corresponding to the third-level electrostatic release protection level is 3kV, and so on.

[0116] Since it is expected that the electrostatic discharge protection level can be divided into levels based on the unit electrostatic discharge protection capability, the electrostatic discharge protection level is proportional to the unit output current and the electrostatic discharge protection level adjustable module. The customized EDA tool can map the electrostatic discharge protection level and the unit electrostatic discharge protection module. For example, the first-level electrostatic release protection level corresponds to the unit output current and the electrostatic release protection capability provided by the PMOS module and the NMOS module included in the electrostatic release protection level adjustable module, and the second-level electrostatic release protection level corresponds to the electrostatic release protection capability provided by the PMOS module and the NMOS module included in the two unit output currents and the electrostatic release protection level adjustable module. Then, when the user inputs the electrostatic release protection level through the GUI interface provided by the customized EDA tool, the required unit output current and the number of electrostatic release protection level adjustable modules can be calculated according to the required number of PMOS modules and NMOS modules, so as to realize flexible configuration of the electrostatic release protection capability.

[0117] Reference below Figure 3-Figure 5 , the unit output current and the electrostatic discharge protection level adjustable module in the configured output current and the electrostatic discharge protection level adjustable module are described, and those skilled in the art should understand that, Figure 5-Figure 7 The examples shown are various specific implementations of the unit output current and electrostatic discharge protection level adjustable module. When there are multiple units of output current and electrostatic discharge protection level adjustable modules, the various specific implementations can be combined according to user needs.

[0118] In the first embodiment, in the unit output current and electrostatic discharge protection level adjustable module: all PMOS modules and all NMOS modules are connected to the control signal input port of the unit output current and electrostatic discharge protection level adjustable module, and all connected PMOS modules and all NMOS modules provide unit electrostatic discharge protection capability and unit output current capability at the same time, such as Figure 3 At this time, all MOS modules in the unit output current and electrostatic discharge protection level adjustable module not only provide unit electrostatic discharge protection capability, but also provide unit output current capability.

[0119] In a second embodiment, in the unit output current and electrostatic release protection level adjustable module: some PMOS modules and / or some NMOS modules are connected to the control signal input port of the unit output current and electrostatic release protection level adjustable module, and the connected part of the PMOS modules and / or some of the NMOS modules simultaneously provide part of the unit electrostatic release protection capability and part of the unit output current capability, and the remaining PMOS modules and / or the remaining NMOS modules simultaneously provide the remaining unit electrostatic release protection capability, such as Figure 4 At this time, some MOS modules in the unit output current and electrostatic release protection level adjustable module have both corresponding electrostatic release protection capabilities and output current capabilities, while the remaining MOS modules only have corresponding electrostatic release protection capabilities, and the electrostatic release protection capabilities corresponding to the some MOS modules and the electrostatic release protection capabilities corresponding to the remaining MOS modules together constitute the unit electrostatic release protection capability.

[0120] In a third embodiment, in the unit output current and electrostatic discharge protection level adjustable module: all PMOS modules and all NMOS modules are disconnected from the control signal input port of the unit output current and electrostatic discharge protection level adjustable module, and all disconnected PMOS modules and all NMOS modules provide unit electrostatic discharge protection capability at the same time, such as Figure 5 At this time, the unit output current and ESD protection level adjustable module can only provide unit ESD protection capability, but cannot provide any output current capability.

[0121] As mentioned above Figure 3-Figure 5 As shown, the unit output current and electrostatic release protection level adjustable module includes an output PMOS unit and an output NMOS unit, the output PMOS unit includes a plurality of PMOS modules, and the output NMOS unit includes a plurality of NMOS modules.

[0122] In a specific implementation, assuming that IOH=3mA, IOL=5.1mA, ESD=12kV, the unit output current capability provided by the unit output current and electrostatic discharge protection level adjustable module is 0.5mA, and the unit electrostatic discharge protection capability provided is 1kV. Then, IOH is 3mA / 0.5mA=6, and 6 complete output PMOS units are required to provide a high-level output pull current, and IOL is 5.1mA / 0.5mA=10.2, and 10 complete output NMOS units and an output NMOS unit accounting for 20% are required to provide a low-level output sink current, wherein the output NMOS unit accounting for 20% is: 20% of the number of NMOS modules are used in the multiple NMOS modules included in the output NMOS unit, and ESD=12kV / 1kV=12, and 12 complete output NMOS units and 12 complete output NMOS units are required.

[0123] Therefore, to achieve the above-mentioned assumed conditions, it is necessary to connect 12 unit output current and electrostatic discharge protection level adjustable modules to the IO core circuit module to provide 12kV electrostatic discharge protection capability, and connect 6 complete output PMOS units to the control signal input port to provide high-level output pull current, and select 10 complete output NMOS units and one output NMOS unit accounting for 20% to be connected to the control signal input port to provide low-level output sink current. The output NMOS unit accounting for 20% is: 20% of the NMOS modules are used in the multiple NMOS modules included in the output NMOS unit.

[0124] In the present disclosure, in the unit output current and electrostatic release protection level adjustable module, the control signal of the IO core circuit module is received through the control signal input port to control the PMOS module and the NMOS module connected to the control signal input port in the output PMOS unit and the output NMOS unit respectively, so as to achieve the output current capability expected by the user.

[0125] Furthermore, when the customized IO IP core is implemented as a circuit layout, the layout area of ​​the implemented circuit layout capable of providing electrostatic discharge protection capability needs to be implemented as the layout area of ​​the customized IO IP core.

[0126] The present disclosure divides the output current and electrostatic release protection level adjustable module into multiple unit output current and electrostatic release protection level adjustable modules, which not only improves the setting accuracy of the output current capability and the electrostatic release protection capability, but also further increases the flexibility of the output current capability and the electrostatic release protection capability configuration. Moreover, when the required high-level output pull current IOH or low-level output sink current IOL, and the electrostatic release protection capability ESD are large values, multiple unit output current and electrostatic release protection level adjustable modules can be conveniently and directly selected for splicing, which simplifies the design process of the customized IOIP core and improves the user experience.

[0127] Further, in Figure 4 In the example shown, that is, when some of the PMOS modules and / or some of the NMOS modules are connected to the control signal input port of the unit output current and electrostatic release protection level adjustable module, in the remaining PMOS modules and / or the remaining NMOS modules of the unit output current and electrostatic release protection level adjustable module: the gates of some of the PMOS modules and NMOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other parts of the PMOS modules and NMOS modules are grounded through the ground port.

[0128] Specifically, in the remaining PMOS modules and / or remaining NMOS modules of the unit output current and electrostatic discharge protection level adjustable module: the gate and source of a part of the PMOS modules and NMOS modules are short-circuited and connected to the power supply voltage through the power supply voltage port, and the gate and source of another part of the PMOS modules and NMOS modules are short-circuited and grounded through the ground port. For example, when the configured output current and electrostatic discharge protection level adjustable module is implemented as a chip or an integrated circuit, the PMOS module and the NMOS module correspond to one or more PMOS tubes and one or more NMOS tubes, then it is necessary to short-circuit the gate and source of one or more PMOS tubes corresponding to the remaining PMOS modules and connect the power supply voltage through the power supply voltage port VDD to form a GDPMOS (Gate VDD PMOS) structure, and short-circuit the gate and source of one or more NMOS tubes corresponding to the remaining NMOS modules and ground them through the ground port VSS to form a GGNMOS (Gate Ground NMOS) structure.

[0129] Alternatively, in the remaining PMOS modules and / or remaining NMOS modules of the module with adjustable unit output current and electrostatic release protection level: the gates of some PMOS modules and NMOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other part of the PMOS modules and NMOS modules are grounded through the resistance module and the grounding port.

[0130] Specifically, in the remaining PMOS modules and / or remaining NMOS modules of the unit output current and electrostatic discharge protection level adjustable module: the gate and source of a part of the PMOS modules and the NMOS modules are short-circuited and connected to the power supply voltage through the resistor module and the power supply voltage port, and the gate and source of another part of the PMOS modules and the NMOS modules are short-circuited and grounded through the resistor module and the grounding port. For example, when the configured unit output current and electrostatic discharge protection level adjustable module is implemented as a chip or an integrated circuit, the PMOS module and the NMOS module correspond to one or more PMOS tubes and one or more NMOS tubes, then it is necessary to short-circuit the gate and source of one or more PMOS tubes corresponding to the remaining PMOS modules and connect the power supply voltage through the resistor module and the power supply voltage port VDD to form an RGPMOS (Resistor-Gate PMOS) structure, and short-circuit the gate and source of one or more NMOS tubes corresponding to the remaining NMOS modules and grounded through the resistor module and the grounding port VSS to form an RGNMOS (Resistor-Gate NMOS) structure.

[0131] exist Figure 5 In the example shown, that is, when all the PMOS modules and all the NMOS modules are disconnected from the control signal input port of the unit output current and electrostatic release protection level adjustable module, among all the PMOS modules and all the NMOS modules of the unit output current and electrostatic release protection level adjustable module: the gates of some of the PMOS modules and NMOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other parts of the PMOS modules and NMOS modules are grounded through the ground port.

[0132] Specifically, in all PMOS modules and all NMOS modules of the unit output current and electrostatic discharge protection level adjustable module: the gate and source of a part of the PMOS modules and NMOS modules are short-circuited and connected to the power supply voltage through the power supply voltage port, and the gate and source of another part of the PMOS modules and NMOS modules are short-circuited and grounded through the ground port. For example, when the unit output current and electrostatic discharge protection level adjustable module is implemented as a chip or an integrated circuit, all the PMOS modules and NMOS modules correspond to multiple PMOS tubes and multiple NMOS tubes, then it is necessary to short-circuit the gate and source of the multiple PMOS tubes corresponding to all the PMOS modules and connect the power supply voltage through the power supply voltage port VDD to form a GDPMOS structure, and short-circuit the gate and source of the multiple NMOS tubes corresponding to all the NMOS modules and ground them through the ground port VSS to form a GGNMOS structure.

[0133] Alternatively, among all the PMOS modules and NMOS modules of the module with adjustable unit output current and electrostatic release protection level: the gates of some PMOS modules and NMOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other PMOS modules and NMOS modules are grounded through the resistance module and the grounding port.

[0134] Specifically, in the PMOS module and NMOS module of the adjustable unit output current and electrostatic discharge protection level module: the gates of a part of the PMOS modules and the NMOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of the other part of the PMOS modules and the NMOS modules are grounded through the resistor module and the grounding port. For example, when the adjustable unit output current and electrostatic discharge protection level module is implemented as a chip or an integrated circuit, all the PMOS modules and the NMOS modules correspond to a plurality of PMOS tubes and a plurality of NMOS tubes, then it is necessary to short-circuit the gates and sources of the plurality of PMOS tubes corresponding to the plurality of PMOS modules and connect the power supply voltage through the resistor module and the power supply voltage port VDD to form an RGPMOS structure, and short-circuit the gates and sources of the plurality of NMOS tubes corresponding to the plurality of NMOS modules and connect them to the ground through the resistor module and the grounding port VSS to form a GGNMOS structure.

[0135] The present invention can automatically select the unit output current and electrostatic release level adjustable protection module that needs to be connected and automatically select the PMOS module and NMOS module that need to be connected in the selected unit output current and electrostatic release level adjustable protection module according to the different output current capabilities and electrostatic release protection capability requirements of the actual chip, thereby forming a chip design with output current capability and electrostatic release protection capability that meets the requirements, and at the same time achieving flexible configuration of output current capability and electrostatic release protection capability.

[0136] According to an embodiment of the present disclosure, based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

[0137] Figure 6 A schematic diagram showing the connection of an IO core circuit module, a configured output current, and an electrostatic discharge protection level adjustable module in a configuration method of an IO IP core according to an embodiment of the present disclosure is shown. Figure 6 In the example shown, the configured output current and electrostatic discharge protection level adjustable module includes 2 different unit output current and electrostatic discharge protection level adjustable modules, which are respectively Figure 3 and Figure 5Those skilled in the art should understand that the number of the adjustable modules for unit output current and electrostatic discharge protection level and the type of the adjustable modules for unit output current and electrostatic discharge protection level are set according to user needs, and the number and type of the adjustable modules for unit output current and electrostatic discharge protection level are not used as technical means to limit the scope of protection of the present disclosure.

[0138] like Figure 6 As shown, the customized IO IP core includes: an IO core circuit module, a configured output current and electrostatic release protection level adjustable module, the control signal output port of the IO core circuit module is connected to the control signal input port of the first unit output current and electrostatic release protection level adjustable module and the second unit output current and electrostatic release protection level adjustable module; in the first unit output current and electrostatic release protection level adjustable module, the control signal input port is connected to all PMOS modules and all NMOS modules; in the second unit output current and electrostatic release protection level adjustable module, the control signal input port is disconnected from all PMOS modules and all NMOS modules.

[0139] Among them, the IO core circuit module includes: a power supply voltage port, a ground port, an IO signal input port and a control signal output port; the first unit output current and electrostatic release protection level adjustable module and the second unit output current and electrostatic release protection level adjustable module include: a power supply voltage port, a ground port and a control signal input port.

[0140] The power supply voltage ports of the IO core circuit module, the first unit output current and electrostatic release protection level adjustable module, and the second unit output current and electrostatic release protection level adjustable module are all connected to the power supply voltage, and the grounding ports are all grounded. The IO signal input port of the IO core circuit module receives an external IO input signal, obtains a control signal after processing, and outputs it through the control signal output port, and the selected unit output current and electrostatic release protection level adjustable module obtains the control signal through the control signal input port to control the PMOS module and NOS module connected to the control signal input port of the unit output current and electrostatic release protection level adjustable module to simultaneously provide corresponding electrostatic release protection capabilities and output current capabilities.

[0141] For example, when a pin module of a customized IO IP core needs to have a 5kV electrostatic discharge protection capability, when the configured output current and electrostatic discharge protection level adjustable module is implemented as an integrated circuit or a chip, assuming that the unit electrostatic discharge protection capability that can be provided by a unit output current and electrostatic discharge protection level adjustable module in the configured output current and electrostatic discharge protection level adjustable module is 0.5kV, then under the 0.18um design process, 5kV / 0.5kV=10 unit electrostatic release protection modules need to be connected to the IO core circuit.

[0142] For another example, a pin module of a customized IO IP core needs to have both 4kV electrostatic discharge protection capability and 4mA output current capability. When the configured output current and electrostatic discharge protection level adjustable module is implemented as an integrated circuit or chip, assuming that the unit electrostatic discharge protection capability that can be provided by a unit output current and electrostatic discharge protection level adjustable module in the configured output current and electrostatic discharge protection level adjustable module is 0.5kV, then under the 0.18um design process, when all PMOS tubes and all NMOS tubes in a unit output current and electrostatic discharge protection level adjustable module are used, the unit output current that can be provided is 0.5kV. If the current capacity is 1mA, it is necessary to connect 4kV / 0.5kV=8 unit output current and electrostatic release protection level adjustable modules with 4kV / 0.5kV to the IO core circuit module, wherein all PMOS tubes and all NMOS tubes in the 4mA / 1mA=4 unit output current and electrostatic release protection level adjustable modules need to be connected to the corresponding control signal input ports to provide both unit electrostatic release protection capacity and unit output current capacity, and all PMOS tubes and all NMOS tubes in the remaining 4 unit output current and electrostatic release protection level adjustable modules are disconnected from the corresponding control signal input ports to only provide unit electrostatic release protection capacity.

[0143] According to an embodiment of the present disclosure, a bottom module is obtained, and the bottom of the designated pin module of the customized IO IP core is sealed using the bottom module to generate a designated pin module with a sealed bottom.

[0144] The present disclosure inserts a bottom module at the bottom of the designated pin module to achieve the requirement of closing the overall circuit layout and meet the design rule check. In order to ensure the smoothness and integrity of the wiring in the designated pin module, the wiring requirements in the designated pin circuit layout are met by the bottom module.

[0145] According to an embodiment of the present disclosure, a second designated pin circuit layout of the customized IO IP core is generated based on the bottom-enclosed designated pin module.

[0146] The present disclosure can automatically generate a designated pin circuit layout based on the designated pin module of the designed custom IO IP core, which facilitates the subsequent manufacture of integrated circuits or chips. When manufacturing based on the above circuit layout, it is necessary to manufacture according to the layout border. The layout border defines the physical shape of the circuit board after processing. The chip process manufacturer or manufacturer will cut and process the circuit board according to the layout border to ensure that the size and shape of the circuit board meet the design requirements.

[0147] Figure 7 A schematic diagram showing splicing pin modules in a configuration method of an IO IP core according to an embodiment of the present disclosure is shown.

[0148] like Figure 7 As shown, a bottom module is obtained, and the bottom module is used to seal the bottom of the designated pin module of the customized IO IP core to generate a designated pin module with a sealed bottom.

[0149] According to an embodiment of the present disclosure, a second designated pin circuit layout of the customized IO IP core is generated based on the bottom-enclosed designated pin module.

[0150] According to an embodiment of the present disclosure, at least one filling module is obtained, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; multiple pin modules of the customized IO IP core are generated; the multiple pin modules are spliced ​​to obtain a spliced ​​pin module; and the vacancies in the spliced ​​pin module are filled using the at least one filling module to obtain a filled spliced ​​pin module.

[0151] According to an embodiment of the present disclosure, a multi-pin circuit layout of the customized IO IP core is generated based on the filled spliced ​​pin module.

[0152] In order to meet the design rule check (DRC) of the layout design, the present disclosure also provides a filling module so that the integrated circuit or chip can meet the design requirements during the manufacturing process.

[0153] According to an embodiment of the present disclosure, when corresponding multiple module layouts are generated based on the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic release protection level adjustable module, the widths of the multiple module layouts are consistent.

[0154] According to an embodiment of the present disclosure, when corresponding multiple module layouts are generated based on the IO core circuit module, the configured input threshold adjustable module, the configured output current and electrostatic release protection level adjustable module, the filling module and the bottom module, the widths of the multiple module layouts are consistent.

[0155] In order to save the design area of ​​the circuit layout, the widths of the modules in the designated pin modules are set to be consistent, thereby saving design costs and reducing resource waste.

[0156] Figure 8 FIG. 1 is a flow chart showing a method for providing a configurable IO IP core according to an embodiment of the present disclosure. Figure 8 As shown, the method includes steps S801 to S802.

[0157] In step S801, an IO core circuit module is provided, wherein the IO core circuit module includes a power supply voltage port, a ground port, an IO signal input port and a control signal output port, and is used to process the IO input signal obtained from the IO signal input port and output a control signal.

[0158] In step S803, a module with adjustable output current and electrostatic discharge protection level is provided, and the module with adjustable output current and electrostatic discharge protection level includes a PMOS module group, an NMOS module group, a power supply voltage port, a ground port and a control signal input port. The customized EDA tool determines a first number of PMOS modules from the PMOS module group according to a high-level output pull current, determines a second number of NMOS modules from the NMOS module group according to a low-level output sink current, determines a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic discharge protection level, selects the maximum value of the first number and the third number as the number of selected PMOS modules, selects the maximum value of the second number and the third number as the number of selected NMOS modules, and connects the selected PMOS module and the selected NMOS module.

[0159] The present disclosure can provide a configurable IO IP core for a customized EDA tool, so that the configurable IO IP core can be configured through the customized EDA tool to achieve flexible adjustment of input voltage threshold, output current capability, and electrostatic discharge protection capability.

[0160] According to an embodiment of the present disclosure, it also includes: providing at least one filling module, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules, and the filling module includes: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded.

[0161] According to an embodiment of the present disclosure, it further includes: providing at least one bottom module, wherein the bottom module is used to seal the bottom of one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

[0162] The configurable IO IP core provided by the present disclosure has various forms, which can be an IP soft core designed by hardware description language (HDL), which allows users to flexibly modify and customize according to their needs, and each module in the provided configurable IO IP core can be in the form of a soft core; it can also be an IP solid core provided in the form of a gate-level circuit netlist to provide users with a more specific and optimized circuit design implementation, and each module in the provided configurable IO IP core can be in the form of a solid core; it can also be an IP hard core that provides a verified design circuit layout, and each module in the provided configurable IO IP core can be in the form of a hard core, which ensures the stability and reliability of the chip circuit design, and users can use it directly without further verification.

[0163] In a specific embodiment, the HDL codes for implementing each module in the customized IO IP core may be stored in a code library, so that users can conveniently download and use the code library.

[0164] Fig. 9 A schematic diagram of an IO IP core configuration device 900 according to an embodiment of the present disclosure is shown. The device is implemented based on a customized EDA tool, and the device 900 includes: a first acquisition module 901, a second acquisition module 902, a current and electrostatic discharge protection configuration module 903, and a first generation module 904.

[0165] like Fig. 9 As shown, the first acquisition module 901 is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO basic circuit module, an output current and an electrostatic discharge protection level adjustable module, wherein the IO basic circuit module includes an IO core circuit module, and the output current and electrostatic discharge protection level adjustable module includes a PMOS module group and an NMOS module group.

[0166] The second acquisition module 902 is configured to acquire the high-level output source current, low-level output sink current, and electrostatic discharge protection level input by the user for the designated pin module of the customized IO IP core.

[0167] The current and electrostatic discharge protection configuration module 903 is configured to configure the output current and electrostatic discharge protection level adjustable module according to the high-level output pull current, the low-level output sink current and the electrostatic discharge protection level, including: determining a first number of PMOS modules from the PMOS module group according to the high-level output pull current, determining a second number of NMOS modules from the NMOS module group according to the low-level output sink current, determining a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic discharge protection level, selecting the maximum value of the first number and the third number as the number of selected PMOS modules, selecting the maximum value of the second number and the third number as the number of selected NMOS modules, connecting the selected PMOS module and the selected NMOS module, and generating a configured output current and electrostatic discharge protection level adjustable module, wherein the configured output current and electrostatic discharge protection level adjustable module is used to provide a specified electrostatic discharge protection capability corresponding to the electrostatic discharge protection level and provide a specified output current capability under the control of the control signal of the IO core circuit module.

[0168] The first generating module 904 is configured to connect the IO core circuit module and the configured output current and electrostatic discharge protection level adjustable module to generate a designated pin module of the customized IO IP core.

[0169] Wherein, the IO core circuit module includes: a power supply voltage port, a ground port, an IO signal input port, and a control signal output port, and the configured output current and electrostatic release protection level adjustable module includes: a power supply voltage port, a ground port, and a control signal input port;

[0170] The power supply voltage ports of the IO core circuit module and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the grounding ports are all grounded;

[0171] The control signal output port of the IO core circuit module is connected to the control signal input port of the configured output current and electrostatic discharge protection level adjustable module, and is used to output the control signal to the configured output current and electrostatic discharge protection level adjustable module based on the IO input signal obtained from the IO signal input port;

[0172] The control signal input port of the configured output current and electrostatic discharge protection level adjustable module is connected to the first number of PMOS modules and the second number of NMOS modules.

[0173] The present disclosure can generate a customized IO IP core using a customized EDA tool and a configurable IO IP core according to user needs, so that the customized IO IP core can achieve the output current capability and electrostatic discharge protection capability required by the user, and realizes flexible configuration of the output current capability and electrostatic discharge protection capability.

[0174] According to an embodiment of the present disclosure, a third acquisition module is further included, which is configured to acquire a bottom module, wherein the bottom module is used to close the bottom of the designated pin module of the custom IO IP core to generate a designated pin module with a closed bottom.

[0175] According to an embodiment of the present disclosure, a second generation module is further included, which is configured to generate a second designated pin circuit layout of the customized IO IP core based on the bottom-enclosed designated pin module.

[0176] According to an embodiment of the present disclosure, a fourth acquisition module is also included, which is configured to acquire at least one filling module, wherein the filling module includes: a power supply voltage port and a ground port, wherein the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; the filling module is used to fill the vacancies in the splicing pin module of the custom IO IP core to obtain the filled splicing pin module, wherein the splicing pin module is obtained by splicing multiple pin modules of the custom IOIP core.

[0177] According to an embodiment of the present disclosure, a third generation module is further included, which is configured to generate a multi-pin circuit layout of the customized IO IP core based on the filled splicing pin module.

[0178] Fig.10 A schematic diagram of an apparatus 1000 for providing a configurable IO IP core according to an embodiment of the present disclosure is shown. The apparatus 1000 includes: a first providing module 1001 and a second providing module 1002 .

[0179] like Fig.10 As shown, the first providing module 1001 is configured to provide an IO core circuit module, and the IO core circuit module includes a power supply voltage port, a ground port, an IO signal input port and a control signal output port, which is used to process the IO input signal obtained from the IO signal input port and output a control signal.

[0180] The second providing module 1002 is configured to provide an output current and electrostatic discharge protection level adjustable module, wherein the output current and electrostatic discharge protection level adjustable module includes a PMOS module group, an NMOS module group, a power supply voltage port, a ground port and a control signal input port, the customized EDA tool determines a first number of PMOS modules from the PMOS module group according to a high-level output pull current, determines a second number of NMOS modules from the NMOS module group according to a low-level output sink current, determines a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic release protection level, selects the maximum value between the first number and the third number as the number of the selected PMOS modules, selects the maximum value between the second number and the third number as the number of the selected NMOS modules, and connects the selected PMOS module and the selected NMOS module.

[0181] The present disclosure can provide a configurable IO IP core for a customized EDA tool, so that the customized EDA tool configures the configurable IO IP core to obtain a customized IO IP core that meets the output current capability and electrostatic discharge protection capability required by the user.

[0182] According to an embodiment of the present disclosure, it also includes: a third providing module, configured to provide at least one filling module, which is used to fill the empty positions in the spliced ​​pin module of the custom IOIP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules, and the filling module includes: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded.

[0183] According to an embodiment of the present disclosure, it also includes: a fourth providing module, configured to provide at least one bottom module, wherein the bottom module is used to seal the bottom of one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

[0184] The present disclosure provides a chip, including: a custom IO IP core manufactured according to the method described above, or a custom IO IP core manufactured according to the configurable IO IP core provided by the method described above.

[0185] The present disclosure provides an electronic device, comprising: the chip as described above.

[0186] The present disclosure provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the configuration method of an IO IP core as described in any of the preceding items or the method for providing a configurable IO IP core is implemented.

[0187] The present disclosure provides a computer program product, including computer instructions, which, when executed by a processor, implement the configuration method of an IO IP core as described in any of the preceding items or the method for providing a configurable IO IP core.

[0188] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0189] The units or modules involved in the embodiments described in the present disclosure may be implemented by software or programmable hardware. The units or modules described may also be set in a processor, and the names of these units or modules do not constitute limitations on the units or modules themselves in some cases.

[0190] As another aspect, the present disclosure further provides a computer-readable storage medium, which may be a computer-readable storage medium included in the electronic device or computer system in the above embodiment; or a computer-readable storage medium that exists independently and is not assembled into a device. The computer-readable storage medium stores one or more programs, and the programs are used by one or more processors to execute the method described in the present disclosure.

[0191] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A configuration method for an IO IP core with adjustable output current capability and electrostatic discharge protection level, characterized in that: The method is implemented based on a customized EDA tool, and the method includes: Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO basic circuit module, an output current and an electrostatic discharge protection level adjustable module, the IO basic circuit module includes an IO core circuit module, and the output current and electrostatic discharge protection level adjustable module includes a PMOS module group and an NMOS module group; Get the high-level output source current, low-level output sink current, and electrostatic discharge protection level of the specified pin module input by the user for the customized IO IP core; According to the high-level output pull current, the low-level output sink current and the electrostatic discharge protection level, the output current and electrostatic discharge protection level adjustable module is configured, including: determining a first number of PMOS modules from the PMOS module group according to the high-level output pull current, determining a second number of NMOS modules from the NMOS module group according to the low-level output sink current, determining a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic discharge protection level, selecting the maximum value of the first number and the third number as the number of selected PMOS modules, selecting the maximum value of the second number and the third number as the number of selected NMOS modules, connecting the selected PMOS module and the selected NMOS module, and generating a configured output current and electrostatic discharge protection level adjustable module, wherein the configured output current and electrostatic discharge protection level adjustable module is used to provide a specified electrostatic discharge protection capability corresponding to the electrostatic discharge protection level and provide a specified output current capability under the control of the control signal of the IO core circuit module; Connecting the IO core circuit module and the configured output current and electrostatic release protection level adjustable module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: a power supply voltage port, a ground port, an IO signal input port, and a control signal output port, and the configured output current and electrostatic release protection level adjustable module includes: a power supply voltage port, a ground port, and a control signal input port; The power supply voltage ports of the IO core circuit module and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the grounding ports are all grounded; The control signal output port of the IO core circuit module is connected to the control signal input port of the configured output current and electrostatic discharge protection level adjustable module, and is used to output the control signal to the configured output current and electrostatic discharge protection level adjustable module based on the IO input signal obtained from the IO signal input port; The control signal input port of the configured output current and electrostatic discharge protection level adjustable module is connected to the first number of PMOS modules and the second number of NMOS modules.

2. The method according to claim 1, characterized in that include: Based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

3. The method according to claim 1, characterized in that Also includes: A bottom module is obtained, and the bottom of the designated pin module of the customized IO IP core is sealed by using the bottom module to generate a designated pin module with a sealed bottom.

4. The method according to claim 3, characterized in that Also includes: Based on the bottom-enclosed designated pin module, a second designated pin circuit layout of the customized IO IP core is generated.

5. The method according to claim 1, characterized in that Also includes: Acquire at least one filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module being connected to a power supply voltage, and the ground port of the filling module being grounded; Generate multiple pin modules of the customized IO IP core; Splicing the plurality of pin modules to obtain a spliced ​​pin module; The at least one filling module is used to fill the empty space in the splicing tube foot module to obtain a filled splicing tube foot module.

6. The method according to claim 5, characterized in that Also includes: Based on the filled spliced ​​pin module, a multi-pin circuit layout of the customized IO IP core is generated.

7. The method according to claim 1, characterized in that The configured output current and electrostatic release protection level adjustable module includes a plurality of unit output current and electrostatic release protection level adjustable modules, the unit output current and electrostatic release protection level adjustable module includes a plurality of PMOS modules and a plurality of NMOS modules, and the PMOS modules and NMOS modules included in the plurality of unit output current and electrostatic release protection level adjustable modules respectively constitute the PMOS module group and the NMOS module group; The unit output current and electrostatic release protection level adjustable module includes a power supply voltage port, a ground port and a control signal input port. The power supply voltage port of the unit output current adjustable module is connected to the power supply voltage, and the ground port of the unit output current adjustable module is grounded.

8. The method according to claim 7, characterized in that In the unit output current and electrostatic discharge protection level adjustable module: All PMOS modules and all NMOS modules are connected to the control signal input port of the unit output current and electrostatic discharge protection level adjustable module, and all connected PMOS modules and all NMOS modules provide unit electrostatic discharge protection capability and unit output current capability at the same time; Alternatively, some PMOS modules and / or some NMOS modules are connected to the control signal input port of the unit output current and electrostatic release protection level adjustable module, and some of the connected PMOS modules and / or some of the NMOS modules simultaneously provide partial unit electrostatic release protection capability and partial unit output current capability, and the remaining PMOS modules and / or the remaining NMOS modules simultaneously provide the remaining unit electrostatic release protection capability; Alternatively, all PMOS modules and all NMOS modules are disconnected from the control signal input port of the unit output current and electrostatic release protection level adjustable module, and all disconnected PMOS modules and all NMOS modules provide unit electrostatic release protection capability at the same time.

9. The method according to claim 8, characterized in that: When the part of the PMOS modules and / or the part of the NMOS modules are connected to the control signal input port of the unit output current and electrostatic discharge protection level adjustable module, in the remaining PMOS modules and / or the remaining NMOS modules of the unit output current and electrostatic discharge protection level adjustable module: the gates of a part of the PMOS modules and the NMOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of the other part of the PMOS modules and the NMOS modules are grounded through the ground port; When all the PMOS modules and all the NMOS modules are disconnected from the control signal input port of the unit output current and electrostatic release protection level adjustable module, among all the PMOS modules and all the NMOS modules of the unit output current and electrostatic release protection level adjustable module: the gates of some of the PMOS modules and NMOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other parts of the PMOS modules and NMOS modules are grounded through the ground port.

10. The method according to claim 9, characterized in that The gates of a part of the PMOS modules and the NMOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of another part of the PMOS modules and the NMOS modules are grounded through the ground port, including: The gates and sources of a part of the PMOS modules and the NMOS modules are short-circuited and then connected to the power supply voltage through the power supply voltage port, and the gates and sources of another part of the PMOS modules and the NMOS modules are short-circuited and then grounded through the ground port.

11. The method according to claim 8, characterized in that: When the part of the PMOS modules and / or the part of the NMOS modules are connected to the control signal input port of the unit output current and electrostatic release protection level adjustable module, in the remaining PMOS modules and / or the remaining NMOS modules of the unit output current and electrostatic release protection level adjustable module: the gates of a part of the PMOS modules and the NMOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of the other part of the PMOS modules and the NMOS modules are grounded through the resistance module and the grounding port; When all the PMOS modules and all the NMOS modules are disconnected from the control signal input port of the unit output current and electrostatic release protection level adjustable module, among all the PMOS modules and all the NMOS modules of the unit output current and electrostatic release protection level adjustable module: the gates of some PMOS modules and NMOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other part of the PMOS modules and NMOS modules are grounded through the resistance module and the grounding port.

12. The method according to claim 1, characterized in that The customized EDA tool provides a graphical user interface (GUI), wherein the GUI interface includes a plurality of customized input boxes; The multiple customized input boxes include: an expected high-level output source current input box, an expected low-level output sink current input box, and an expected electrostatic release protection level input box, so as to obtain the high-level output source current, low-level output sink current, and electrostatic release protection level input by the user for the specified pin module of the customized IO IP core.

13. The method according to claim 1, characterized in that When a corresponding plurality of module layouts are generated based on the IO core circuit module, the configured output current and the electrostatic discharge protection level adjustable module, the widths of the plurality of module layouts are consistent.

14. A method for providing a configurable IO IP core, characterized in that: include: Providing an IO core circuit module, the IO core circuit module comprising a power supply voltage port, a ground port, an IO signal input port and a control signal output port, for processing an IO input signal obtained from the IO signal input port and outputting a control signal; A module with adjustable output current and electrostatic discharge protection level is provided, wherein the module includes a PMOS module group, an NMOS module group, a power supply voltage port, a ground port and a control signal input port, wherein a customized EDA tool determines a first number of PMOS modules from the PMOS module group according to a high-level output pull current, determines a second number of NMOS modules from the NMOS module group according to a low-level output sink current, determines a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic discharge protection level, selects a maximum value between the first number and the third number as the number of selected PMOS modules, selects a maximum value between the second number and the third number as the number of selected NMOS modules, and connects the selected PMOS module and the selected NMOS module.

15. The method according to claim 14, characterized in that Also includes: At least one filling module is provided, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules, and the filling module includes: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded.

16. The method according to claim 14, characterized in that Also includes: At least one bottom module is provided, and the bottom module is used to seal the bottom of the one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

17. A configuration device for an IO IP core with adjustable output current capability and electrostatic discharge protection level, characterized in that: The device is implemented based on a customized EDA tool, including: A first acquisition module is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO basic circuit module, an output current and an electrostatic discharge protection level adjustable module, the IO basic circuit module includes an IO core circuit module, and the output current and electrostatic discharge protection level adjustable module includes a PMOS module group and an NMOS module group; The second acquisition module is configured to obtain the high-level output source current, low-level output sink current, and electrostatic discharge protection level input by the user for the specified pin module of the customized IO IP core; The current and electrostatic discharge protection configuration module is configured to configure the output current and electrostatic discharge protection level adjustable module according to the high-level output pull current, the low-level output sink current and the electrostatic discharge protection level, including: determining a first number of PMOS modules from the PMOS module group according to the high-level output pull current, determining a second number of NMOS modules from the NMOS module group according to the low-level output sink current, determining a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic discharge protection level, selecting the maximum value of the first number and the third number as the number of selected PMOS modules, selecting the maximum value of the second number and the third number as the number of selected NMOS modules, connecting the selected PMOS module and the selected NMOS module, and generating a configured output current and electrostatic discharge protection level adjustable module, wherein the configured output current and electrostatic discharge protection level adjustable module is used to provide a specified electrostatic discharge protection capability corresponding to the electrostatic discharge protection level and provide a specified output current capability under the control of the control signal of the IO core circuit module; A first generating module is configured to connect the IO core circuit module and the configured output current and electrostatic release protection level adjustable module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: a power supply voltage port, a ground port, an IO signal input port, and a control signal output port, and the configured output current and electrostatic release protection level adjustable module includes: a power supply voltage port, a ground port, and a control signal input port; The power supply voltage ports of the IO core circuit module and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the grounding ports are all grounded; The control signal output port of the IO core circuit module is connected to the control signal input port of the configured output current and electrostatic discharge protection level adjustable module, and is used to output the control signal to the configured output current and electrostatic discharge protection level adjustable module based on the IO input signal obtained from the IO signal input port; The control signal input port of the configured output current and electrostatic discharge protection level adjustable module is connected to the first number of PMOS modules and the second number of NMOS modules.

18. The device according to claim 17, characterized in that The system further comprises a third acquisition module configured to acquire a bottom module, wherein the bottom module is used to seal the bottom of the designated pin module of the custom IO IP core to generate a designated pin module with a sealed bottom.

19. The device according to claim 18, characterized in that It also includes a second generation module configured to generate a second designated pin circuit layout of the customized IO IP core based on the bottom-enclosed designated pin module.

20. The device according to claim 17, characterized in that It also includes a fourth acquisition module, which is configured to acquire at least one filling module, wherein the filling module includes: a power supply voltage port and a ground port, wherein the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; the filling module is used to fill the vacancies in the splicing pin module of the custom IO IP core to obtain the filled splicing pin module, wherein the splicing pin module is obtained by splicing multiple pin modules of the custom IO IP core.

21. The device according to claim 20, characterized in that It also includes a third generation module configured to generate a multi-pin circuit layout of the customized IO IP core based on the filled splicing pin module.

22. A device for providing a configurable IO IP core, characterized in that: include: A first providing module is configured to provide an IO core circuit module, wherein the IO core circuit module includes a power supply voltage port, a ground port, an IO signal input port, and a control signal output port, and is used to process an IO input signal obtained from the IO signal input port and output a control signal; The second providing module is configured to provide an output current and electrostatic discharge protection level adjustable module, wherein the output current and electrostatic discharge protection level adjustable module includes a PMOS module group, an NMOS module group, a power supply voltage port, a ground port and a control signal input port, the customized EDA tool determines a first number of PMOS modules from the PMOS module group according to a high-level output pull current, determines a second number of NMOS modules from the NMOS module group according to a low-level output sink current, determines a third number of PMOS modules and a third number of NMOS modules from the PMOS module group and the NMOS module group respectively according to the electrostatic discharge protection level, selects the maximum value of the first number and the third number as the number of the selected PMOS modules, selects the maximum value of the second number and the third number as the number of the selected NMOS modules, and connects the selected PMOS module and the selected NMOS module.

23. The device according to claim 22, characterized in that Also includes: A third providing module is configured to provide at least one filling module, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules, and the filling module includes: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded.

24. The device according to claim 22, characterized in that Also includes: The fourth providing module is configured to provide at least one bottom module, wherein the bottom module is used to seal the bottom of one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

25. A chip, characterized in that: The method comprises manufacturing a customized IO IP core generated by the method according to any one of claims 1 to 13, or manufacturing a customized IO IP core generated by the configurable IO IP core provided by the method according to any one of claims 14 to 16.

26. An electronic device, characterized in that: Comprising a chip according to claim 25.

27. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 1 to 16 is implemented.

28. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the method according to any one of claims 1 to 16.

Images